1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2 /* 3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. 4 */ 5 6 #ifndef ATH11K_WMI_H 7 #define ATH11K_WMI_H 8 9 #include <net/mac80211.h> 10 #include "htc.h" 11 12 struct ath11k_base; 13 struct ath11k; 14 struct ath11k_fw_stats; 15 struct ath11k_fw_dbglog; 16 struct ath11k_vif; 17 18 #define PSOC_HOST_MAX_NUM_SS (8) 19 20 /* defines to set Packet extension values which can be 0 us, 8 usec or 16 usec */ 21 #define MAX_HE_NSS 8 22 #define MAX_HE_MODULATION 8 23 #define MAX_HE_RU 4 24 #define HE_MODULATION_NONE 7 25 #define HE_PET_0_USEC 0 26 #define HE_PET_8_USEC 1 27 #define HE_PET_16_USEC 2 28 29 #define WMI_MAX_CHAINS 8 30 31 #define WMI_MAX_NUM_SS MAX_HE_NSS 32 #define WMI_MAX_NUM_RU MAX_HE_RU 33 34 #define WMI_TLV_CMD(grp_id) (((grp_id) << 12) | 0x1) 35 #define WMI_TLV_EV(grp_id) (((grp_id) << 12) | 0x1) 36 #define WMI_TLV_CMD_UNSUPPORTED 0 37 #define WMI_TLV_PDEV_PARAM_UNSUPPORTED 0 38 #define WMI_TLV_VDEV_PARAM_UNSUPPORTED 0 39 40 struct wmi_cmd_hdr { 41 u32 cmd_id; 42 } __packed; 43 44 struct wmi_tlv { 45 u32 header; 46 u8 value[]; 47 } __packed; 48 49 #define WMI_TLV_LEN GENMASK(15, 0) 50 #define WMI_TLV_TAG GENMASK(31, 16) 51 #define TLV_HDR_SIZE sizeof_field(struct wmi_tlv, header) 52 53 #define WMI_CMD_HDR_CMD_ID GENMASK(23, 0) 54 #define WMI_MAX_MEM_REQS 32 55 #define ATH11K_MAX_HW_LISTEN_INTERVAL 5 56 57 #define WLAN_SCAN_MAX_HINT_S_SSID 10 58 #define WLAN_SCAN_MAX_HINT_BSSID 10 59 #define MAX_RNR_BSS 5 60 61 #define WLAN_SCAN_MAX_HINT_S_SSID 10 62 #define WLAN_SCAN_MAX_HINT_BSSID 10 63 #define MAX_RNR_BSS 5 64 65 #define WLAN_SCAN_PARAMS_MAX_SSID 16 66 #define WLAN_SCAN_PARAMS_MAX_BSSID 4 67 #define WLAN_SCAN_PARAMS_MAX_IE_LEN 256 68 69 #define WMI_APPEND_TO_EXISTING_CHAN_LIST_FLAG 1 70 71 #define WMI_BA_MODE_BUFFER_SIZE_256 3 72 /* 73 * HW mode config type replicated from FW header 74 * @WMI_HOST_HW_MODE_SINGLE: Only one PHY is active. 75 * @WMI_HOST_HW_MODE_DBS: Both PHYs are active in different bands, 76 * one in 2G and another in 5G. 77 * @WMI_HOST_HW_MODE_SBS_PASSIVE: Both PHYs are in passive mode (only rx) in 78 * same band; no tx allowed. 79 * @WMI_HOST_HW_MODE_SBS: Both PHYs are active in the same band. 80 * Support for both PHYs within one band is planned 81 * for 5G only(as indicated in WMI_MAC_PHY_CAPABILITIES), 82 * but could be extended to other bands in the future. 83 * The separation of the band between the two PHYs needs 84 * to be communicated separately. 85 * @WMI_HOST_HW_MODE_DBS_SBS: 3 PHYs, with 2 on the same band doing SBS 86 * as in WMI_HW_MODE_SBS, and 3rd on the other band 87 * @WMI_HOST_HW_MODE_DBS_OR_SBS: Two PHY with one PHY capabale of both 2G and 88 * 5G. It can support SBS (5G + 5G) OR DBS (5G + 2G). 89 * @WMI_HOST_HW_MODE_MAX: Max hw_mode_id. Used to indicate invalid mode. 90 */ 91 enum wmi_host_hw_mode_config_type { 92 WMI_HOST_HW_MODE_SINGLE = 0, 93 WMI_HOST_HW_MODE_DBS = 1, 94 WMI_HOST_HW_MODE_SBS_PASSIVE = 2, 95 WMI_HOST_HW_MODE_SBS = 3, 96 WMI_HOST_HW_MODE_DBS_SBS = 4, 97 WMI_HOST_HW_MODE_DBS_OR_SBS = 5, 98 99 /* keep last */ 100 WMI_HOST_HW_MODE_MAX 101 }; 102 103 /* HW mode priority values used to detect the preferred HW mode 104 * on the available modes. 105 */ 106 enum wmi_host_hw_mode_priority { 107 WMI_HOST_HW_MODE_DBS_SBS_PRI, 108 WMI_HOST_HW_MODE_DBS_PRI, 109 WMI_HOST_HW_MODE_DBS_OR_SBS_PRI, 110 WMI_HOST_HW_MODE_SBS_PRI, 111 WMI_HOST_HW_MODE_SBS_PASSIVE_PRI, 112 WMI_HOST_HW_MODE_SINGLE_PRI, 113 114 /* keep last the lowest priority */ 115 WMI_HOST_HW_MODE_MAX_PRI 116 }; 117 118 enum WMI_HOST_WLAN_BAND { 119 WMI_HOST_WLAN_2G_CAP = 0x1, 120 WMI_HOST_WLAN_5G_CAP = 0x2, 121 WMI_HOST_WLAN_2G_5G_CAP = WMI_HOST_WLAN_2G_CAP | WMI_HOST_WLAN_5G_CAP, 122 }; 123 124 /* Parameters used for WMI_VDEV_PARAM_AUTORATE_MISC_CFG command. 125 * Used only for HE auto rate mode. 126 */ 127 enum { 128 /* HE LTF related configuration */ 129 WMI_HE_AUTORATE_LTF_1X = BIT(0), 130 WMI_HE_AUTORATE_LTF_2X = BIT(1), 131 WMI_HE_AUTORATE_LTF_4X = BIT(2), 132 133 /* HE GI related configuration */ 134 WMI_AUTORATE_400NS_GI = BIT(8), 135 WMI_AUTORATE_800NS_GI = BIT(9), 136 WMI_AUTORATE_1600NS_GI = BIT(10), 137 WMI_AUTORATE_3200NS_GI = BIT(11), 138 }; 139 140 enum { 141 WMI_HOST_VDEV_FLAGS_NON_MBSSID_AP = 0x00000001, 142 WMI_HOST_VDEV_FLAGS_TRANSMIT_AP = 0x00000002, 143 WMI_HOST_VDEV_FLAGS_NON_TRANSMIT_AP = 0x00000004, 144 WMI_HOST_VDEV_FLAGS_EMA_MODE = 0x00000008, 145 WMI_HOST_VDEV_FLAGS_SCAN_MODE_VAP = 0x00000010, 146 }; 147 148 /* 149 * wmi command groups. 150 */ 151 enum wmi_cmd_group { 152 /* 0 to 2 are reserved */ 153 WMI_GRP_START = 0x3, 154 WMI_GRP_SCAN = WMI_GRP_START, 155 WMI_GRP_PDEV = 0x4, 156 WMI_GRP_VDEV = 0x5, 157 WMI_GRP_PEER = 0x6, 158 WMI_GRP_MGMT = 0x7, 159 WMI_GRP_BA_NEG = 0x8, 160 WMI_GRP_STA_PS = 0x9, 161 WMI_GRP_DFS = 0xa, 162 WMI_GRP_ROAM = 0xb, 163 WMI_GRP_OFL_SCAN = 0xc, 164 WMI_GRP_P2P = 0xd, 165 WMI_GRP_AP_PS = 0xe, 166 WMI_GRP_RATE_CTRL = 0xf, 167 WMI_GRP_PROFILE = 0x10, 168 WMI_GRP_SUSPEND = 0x11, 169 WMI_GRP_BCN_FILTER = 0x12, 170 WMI_GRP_WOW = 0x13, 171 WMI_GRP_RTT = 0x14, 172 WMI_GRP_SPECTRAL = 0x15, 173 WMI_GRP_STATS = 0x16, 174 WMI_GRP_ARP_NS_OFL = 0x17, 175 WMI_GRP_NLO_OFL = 0x18, 176 WMI_GRP_GTK_OFL = 0x19, 177 WMI_GRP_CSA_OFL = 0x1a, 178 WMI_GRP_CHATTER = 0x1b, 179 WMI_GRP_TID_ADDBA = 0x1c, 180 WMI_GRP_MISC = 0x1d, 181 WMI_GRP_GPIO = 0x1e, 182 WMI_GRP_FWTEST = 0x1f, 183 WMI_GRP_TDLS = 0x20, 184 WMI_GRP_RESMGR = 0x21, 185 WMI_GRP_STA_SMPS = 0x22, 186 WMI_GRP_WLAN_HB = 0x23, 187 WMI_GRP_RMC = 0x24, 188 WMI_GRP_MHF_OFL = 0x25, 189 WMI_GRP_LOCATION_SCAN = 0x26, 190 WMI_GRP_OEM = 0x27, 191 WMI_GRP_NAN = 0x28, 192 WMI_GRP_COEX = 0x29, 193 WMI_GRP_OBSS_OFL = 0x2a, 194 WMI_GRP_LPI = 0x2b, 195 WMI_GRP_EXTSCAN = 0x2c, 196 WMI_GRP_DHCP_OFL = 0x2d, 197 WMI_GRP_IPA = 0x2e, 198 WMI_GRP_MDNS_OFL = 0x2f, 199 WMI_GRP_SAP_OFL = 0x30, 200 WMI_GRP_OCB = 0x31, 201 WMI_GRP_SOC = 0x32, 202 WMI_GRP_PKT_FILTER = 0x33, 203 WMI_GRP_MAWC = 0x34, 204 WMI_GRP_PMF_OFFLOAD = 0x35, 205 WMI_GRP_BPF_OFFLOAD = 0x36, 206 WMI_GRP_NAN_DATA = 0x37, 207 WMI_GRP_PROTOTYPE = 0x38, 208 WMI_GRP_MONITOR = 0x39, 209 WMI_GRP_REGULATORY = 0x3a, 210 WMI_GRP_HW_DATA_FILTER = 0x3b, 211 WMI_GRP_WLM = 0x3c, 212 WMI_GRP_11K_OFFLOAD = 0x3d, 213 WMI_GRP_TWT = 0x3e, 214 WMI_GRP_MOTION_DET = 0x3f, 215 WMI_GRP_SPATIAL_REUSE = 0x40, 216 }; 217 218 #define WMI_CMD_GRP(grp_id) (((grp_id) << 12) | 0x1) 219 #define WMI_EVT_GRP_START_ID(grp_id) (((grp_id) << 12) | 0x1) 220 221 #define WMI_CMD_UNSUPPORTED 0 222 223 enum wmi_tlv_cmd_id { 224 WMI_INIT_CMDID = 0x1, 225 WMI_START_SCAN_CMDID = WMI_TLV_CMD(WMI_GRP_SCAN), 226 WMI_STOP_SCAN_CMDID, 227 WMI_SCAN_CHAN_LIST_CMDID, 228 WMI_SCAN_SCH_PRIO_TBL_CMDID, 229 WMI_SCAN_UPDATE_REQUEST_CMDID, 230 WMI_SCAN_PROB_REQ_OUI_CMDID, 231 WMI_SCAN_ADAPTIVE_DWELL_CONFIG_CMDID, 232 WMI_PDEV_SET_REGDOMAIN_CMDID = WMI_TLV_CMD(WMI_GRP_PDEV), 233 WMI_PDEV_SET_CHANNEL_CMDID, 234 WMI_PDEV_SET_PARAM_CMDID, 235 WMI_PDEV_PKTLOG_ENABLE_CMDID, 236 WMI_PDEV_PKTLOG_DISABLE_CMDID, 237 WMI_PDEV_SET_WMM_PARAMS_CMDID, 238 WMI_PDEV_SET_HT_CAP_IE_CMDID, 239 WMI_PDEV_SET_VHT_CAP_IE_CMDID, 240 WMI_PDEV_SET_DSCP_TID_MAP_CMDID, 241 WMI_PDEV_SET_QUIET_MODE_CMDID, 242 WMI_PDEV_GREEN_AP_PS_ENABLE_CMDID, 243 WMI_PDEV_GET_TPC_CONFIG_CMDID, 244 WMI_PDEV_SET_BASE_MACADDR_CMDID, 245 WMI_PDEV_DUMP_CMDID, 246 WMI_PDEV_SET_LED_CONFIG_CMDID, 247 WMI_PDEV_GET_TEMPERATURE_CMDID, 248 WMI_PDEV_SET_LED_FLASHING_CMDID, 249 WMI_PDEV_SMART_ANT_ENABLE_CMDID, 250 WMI_PDEV_SMART_ANT_SET_RX_ANTENNA_CMDID, 251 WMI_PDEV_SET_ANTENNA_SWITCH_TABLE_CMDID, 252 WMI_PDEV_SET_CTL_TABLE_CMDID, 253 WMI_PDEV_SET_MIMOGAIN_TABLE_CMDID, 254 WMI_PDEV_FIPS_CMDID, 255 WMI_PDEV_GET_ANI_CCK_CONFIG_CMDID, 256 WMI_PDEV_GET_ANI_OFDM_CONFIG_CMDID, 257 WMI_PDEV_GET_NFCAL_POWER_CMDID, 258 WMI_PDEV_GET_TPC_CMDID, 259 WMI_MIB_STATS_ENABLE_CMDID, 260 WMI_PDEV_SET_PCL_CMDID, 261 WMI_PDEV_SET_HW_MODE_CMDID, 262 WMI_PDEV_SET_MAC_CONFIG_CMDID, 263 WMI_PDEV_SET_ANTENNA_MODE_CMDID, 264 WMI_SET_PERIODIC_CHANNEL_STATS_CONFIG_CMDID, 265 WMI_PDEV_WAL_POWER_DEBUG_CMDID, 266 WMI_PDEV_SET_REORDER_TIMEOUT_VAL_CMDID, 267 WMI_PDEV_SET_WAKEUP_CONFIG_CMDID, 268 WMI_PDEV_GET_ANTDIV_STATUS_CMDID, 269 WMI_PDEV_GET_CHIP_POWER_STATS_CMDID, 270 WMI_PDEV_SET_STATS_THRESHOLD_CMDID, 271 WMI_PDEV_MULTIPLE_VDEV_RESTART_REQUEST_CMDID, 272 WMI_PDEV_UPDATE_PKT_ROUTING_CMDID, 273 WMI_PDEV_CHECK_CAL_VERSION_CMDID, 274 WMI_PDEV_SET_DIVERSITY_GAIN_CMDID, 275 WMI_PDEV_DIV_GET_RSSI_ANTID_CMDID, 276 WMI_PDEV_BSS_CHAN_INFO_REQUEST_CMDID, 277 WMI_PDEV_UPDATE_PMK_CACHE_CMDID, 278 WMI_PDEV_UPDATE_FILS_HLP_PKT_CMDID, 279 WMI_PDEV_UPDATE_CTLTABLE_REQUEST_CMDID, 280 WMI_PDEV_CONFIG_VENDOR_OUI_ACTION_CMDID, 281 WMI_PDEV_SET_AC_TX_QUEUE_OPTIMIZED_CMDID, 282 WMI_PDEV_SET_RX_FILTER_PROMISCUOUS_CMDID, 283 WMI_PDEV_DMA_RING_CFG_REQ_CMDID, 284 WMI_PDEV_HE_TB_ACTION_FRM_CMDID, 285 WMI_PDEV_PKTLOG_FILTER_CMDID, 286 WMI_PDEV_SET_RAP_CONFIG_CMDID, 287 WMI_PDEV_DSM_FILTER_CMDID, 288 WMI_PDEV_FRAME_INJECT_CMDID, 289 WMI_PDEV_TBTT_OFFSET_SYNC_CMDID, 290 WMI_PDEV_SET_SRG_BSS_COLOR_BITMAP_CMDID, 291 WMI_PDEV_SET_SRG_PARTIAL_BSSID_BITMAP_CMDID, 292 WMI_PDEV_SET_SRG_OBSS_COLOR_ENABLE_BITMAP_CMDID, 293 WMI_PDEV_SET_SRG_OBSS_BSSID_ENABLE_BITMAP_CMDID, 294 WMI_PDEV_SET_NON_SRG_OBSS_COLOR_ENABLE_BITMAP_CMDID, 295 WMI_PDEV_SET_NON_SRG_OBSS_BSSID_ENABLE_BITMAP_CMDID, 296 WMI_PDEV_GET_TPC_STATS_CMDID, 297 WMI_PDEV_ENABLE_DURATION_BASED_TX_MODE_SELECTION_CMDID, 298 WMI_PDEV_GET_DPD_STATUS_CMDID, 299 WMI_PDEV_SET_BIOS_SAR_TABLE_CMDID, 300 WMI_PDEV_SET_BIOS_GEO_TABLE_CMDID, 301 WMI_VDEV_CREATE_CMDID = WMI_TLV_CMD(WMI_GRP_VDEV), 302 WMI_VDEV_DELETE_CMDID, 303 WMI_VDEV_START_REQUEST_CMDID, 304 WMI_VDEV_RESTART_REQUEST_CMDID, 305 WMI_VDEV_UP_CMDID, 306 WMI_VDEV_STOP_CMDID, 307 WMI_VDEV_DOWN_CMDID, 308 WMI_VDEV_SET_PARAM_CMDID, 309 WMI_VDEV_INSTALL_KEY_CMDID, 310 WMI_VDEV_WNM_SLEEPMODE_CMDID, 311 WMI_VDEV_WMM_ADDTS_CMDID, 312 WMI_VDEV_WMM_DELTS_CMDID, 313 WMI_VDEV_SET_WMM_PARAMS_CMDID, 314 WMI_VDEV_SET_GTX_PARAMS_CMDID, 315 WMI_VDEV_IPSEC_NATKEEPALIVE_FILTER_CMDID, 316 WMI_VDEV_PLMREQ_START_CMDID, 317 WMI_VDEV_PLMREQ_STOP_CMDID, 318 WMI_VDEV_TSF_TSTAMP_ACTION_CMDID, 319 WMI_VDEV_SET_IE_CMDID, 320 WMI_VDEV_RATEMASK_CMDID, 321 WMI_VDEV_ATF_REQUEST_CMDID, 322 WMI_VDEV_SET_DSCP_TID_MAP_CMDID, 323 WMI_VDEV_FILTER_NEIGHBOR_RX_PACKETS_CMDID, 324 WMI_VDEV_SET_QUIET_MODE_CMDID, 325 WMI_VDEV_SET_CUSTOM_AGGR_SIZE_CMDID, 326 WMI_VDEV_ENCRYPT_DECRYPT_DATA_REQ_CMDID, 327 WMI_VDEV_ADD_MAC_ADDR_TO_RX_FILTER_CMDID, 328 WMI_PEER_CREATE_CMDID = WMI_TLV_CMD(WMI_GRP_PEER), 329 WMI_PEER_DELETE_CMDID, 330 WMI_PEER_FLUSH_TIDS_CMDID, 331 WMI_PEER_SET_PARAM_CMDID, 332 WMI_PEER_ASSOC_CMDID, 333 WMI_PEER_ADD_WDS_ENTRY_CMDID, 334 WMI_PEER_REMOVE_WDS_ENTRY_CMDID, 335 WMI_PEER_MCAST_GROUP_CMDID, 336 WMI_PEER_INFO_REQ_CMDID, 337 WMI_PEER_GET_ESTIMATED_LINKSPEED_CMDID, 338 WMI_PEER_SET_RATE_REPORT_CONDITION_CMDID, 339 WMI_PEER_UPDATE_WDS_ENTRY_CMDID, 340 WMI_PEER_ADD_PROXY_STA_ENTRY_CMDID, 341 WMI_PEER_SMART_ANT_SET_TX_ANTENNA_CMDID, 342 WMI_PEER_SMART_ANT_SET_TRAIN_INFO_CMDID, 343 WMI_PEER_SMART_ANT_SET_NODE_CONFIG_OPS_CMDID, 344 WMI_PEER_ATF_REQUEST_CMDID, 345 WMI_PEER_BWF_REQUEST_CMDID, 346 WMI_PEER_REORDER_QUEUE_SETUP_CMDID, 347 WMI_PEER_REORDER_QUEUE_REMOVE_CMDID, 348 WMI_PEER_SET_RX_BLOCKSIZE_CMDID, 349 WMI_PEER_ANTDIV_INFO_REQ_CMDID, 350 WMI_BCN_TX_CMDID = WMI_TLV_CMD(WMI_GRP_MGMT), 351 WMI_PDEV_SEND_BCN_CMDID, 352 WMI_BCN_TMPL_CMDID, 353 WMI_BCN_FILTER_RX_CMDID, 354 WMI_PRB_REQ_FILTER_RX_CMDID, 355 WMI_MGMT_TX_CMDID, 356 WMI_PRB_TMPL_CMDID, 357 WMI_MGMT_TX_SEND_CMDID, 358 WMI_OFFCHAN_DATA_TX_SEND_CMDID, 359 WMI_PDEV_SEND_FD_CMDID, 360 WMI_BCN_OFFLOAD_CTRL_CMDID, 361 WMI_BSS_COLOR_CHANGE_ENABLE_CMDID, 362 WMI_VDEV_BCN_OFFLOAD_QUIET_CONFIG_CMDID, 363 WMI_FILS_DISCOVERY_TMPL_CMDID, 364 WMI_ADDBA_CLEAR_RESP_CMDID = WMI_TLV_CMD(WMI_GRP_BA_NEG), 365 WMI_ADDBA_SEND_CMDID, 366 WMI_ADDBA_STATUS_CMDID, 367 WMI_DELBA_SEND_CMDID, 368 WMI_ADDBA_SET_RESP_CMDID, 369 WMI_SEND_SINGLEAMSDU_CMDID, 370 WMI_STA_POWERSAVE_MODE_CMDID = WMI_TLV_CMD(WMI_GRP_STA_PS), 371 WMI_STA_POWERSAVE_PARAM_CMDID, 372 WMI_STA_MIMO_PS_MODE_CMDID, 373 WMI_PDEV_DFS_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_DFS), 374 WMI_PDEV_DFS_DISABLE_CMDID, 375 WMI_DFS_PHYERR_FILTER_ENA_CMDID, 376 WMI_DFS_PHYERR_FILTER_DIS_CMDID, 377 WMI_PDEV_DFS_PHYERR_OFFLOAD_ENABLE_CMDID, 378 WMI_PDEV_DFS_PHYERR_OFFLOAD_DISABLE_CMDID, 379 WMI_VDEV_ADFS_CH_CFG_CMDID, 380 WMI_VDEV_ADFS_OCAC_ABORT_CMDID, 381 WMI_ROAM_SCAN_MODE = WMI_TLV_CMD(WMI_GRP_ROAM), 382 WMI_ROAM_SCAN_RSSI_THRESHOLD, 383 WMI_ROAM_SCAN_PERIOD, 384 WMI_ROAM_SCAN_RSSI_CHANGE_THRESHOLD, 385 WMI_ROAM_AP_PROFILE, 386 WMI_ROAM_CHAN_LIST, 387 WMI_ROAM_SCAN_CMD, 388 WMI_ROAM_SYNCH_COMPLETE, 389 WMI_ROAM_SET_RIC_REQUEST_CMDID, 390 WMI_ROAM_INVOKE_CMDID, 391 WMI_ROAM_FILTER_CMDID, 392 WMI_ROAM_SUBNET_CHANGE_CONFIG_CMDID, 393 WMI_ROAM_CONFIGURE_MAWC_CMDID, 394 WMI_ROAM_SET_MBO_PARAM_CMDID, 395 WMI_ROAM_PER_CONFIG_CMDID, 396 WMI_ROAM_BTM_CONFIG_CMDID, 397 WMI_ENABLE_FILS_CMDID, 398 WMI_OFL_SCAN_ADD_AP_PROFILE = WMI_TLV_CMD(WMI_GRP_OFL_SCAN), 399 WMI_OFL_SCAN_REMOVE_AP_PROFILE, 400 WMI_OFL_SCAN_PERIOD, 401 WMI_P2P_DEV_SET_DEVICE_INFO = WMI_TLV_CMD(WMI_GRP_P2P), 402 WMI_P2P_DEV_SET_DISCOVERABILITY, 403 WMI_P2P_GO_SET_BEACON_IE, 404 WMI_P2P_GO_SET_PROBE_RESP_IE, 405 WMI_P2P_SET_VENDOR_IE_DATA_CMDID, 406 WMI_P2P_DISC_OFFLOAD_CONFIG_CMDID, 407 WMI_P2P_DISC_OFFLOAD_APPIE_CMDID, 408 WMI_P2P_DISC_OFFLOAD_PATTERN_CMDID, 409 WMI_P2P_SET_OPPPS_PARAM_CMDID, 410 WMI_P2P_LISTEN_OFFLOAD_START_CMDID, 411 WMI_P2P_LISTEN_OFFLOAD_STOP_CMDID, 412 WMI_AP_PS_PEER_PARAM_CMDID = WMI_TLV_CMD(WMI_GRP_AP_PS), 413 WMI_AP_PS_PEER_UAPSD_COEX_CMDID, 414 WMI_AP_PS_EGAP_PARAM_CMDID, 415 WMI_PEER_RATE_RETRY_SCHED_CMDID = WMI_TLV_CMD(WMI_GRP_RATE_CTRL), 416 WMI_WLAN_PROFILE_TRIGGER_CMDID = WMI_TLV_CMD(WMI_GRP_PROFILE), 417 WMI_WLAN_PROFILE_SET_HIST_INTVL_CMDID, 418 WMI_WLAN_PROFILE_GET_PROFILE_DATA_CMDID, 419 WMI_WLAN_PROFILE_ENABLE_PROFILE_ID_CMDID, 420 WMI_WLAN_PROFILE_LIST_PROFILE_ID_CMDID, 421 WMI_PDEV_SUSPEND_CMDID = WMI_TLV_CMD(WMI_GRP_SUSPEND), 422 WMI_PDEV_RESUME_CMDID, 423 WMI_ADD_BCN_FILTER_CMDID = WMI_TLV_CMD(WMI_GRP_BCN_FILTER), 424 WMI_RMV_BCN_FILTER_CMDID, 425 WMI_WOW_ADD_WAKE_PATTERN_CMDID = WMI_TLV_CMD(WMI_GRP_WOW), 426 WMI_WOW_DEL_WAKE_PATTERN_CMDID, 427 WMI_WOW_ENABLE_DISABLE_WAKE_EVENT_CMDID, 428 WMI_WOW_ENABLE_CMDID, 429 WMI_WOW_HOSTWAKEUP_FROM_SLEEP_CMDID, 430 WMI_WOW_IOAC_ADD_KEEPALIVE_CMDID, 431 WMI_WOW_IOAC_DEL_KEEPALIVE_CMDID, 432 WMI_WOW_IOAC_ADD_WAKE_PATTERN_CMDID, 433 WMI_WOW_IOAC_DEL_WAKE_PATTERN_CMDID, 434 WMI_D0_WOW_ENABLE_DISABLE_CMDID, 435 WMI_EXTWOW_ENABLE_CMDID, 436 WMI_EXTWOW_SET_APP_TYPE1_PARAMS_CMDID, 437 WMI_EXTWOW_SET_APP_TYPE2_PARAMS_CMDID, 438 WMI_WOW_ENABLE_ICMPV6_NA_FLT_CMDID, 439 WMI_WOW_UDP_SVC_OFLD_CMDID, 440 WMI_WOW_HOSTWAKEUP_GPIO_PIN_PATTERN_CONFIG_CMDID, 441 WMI_WOW_SET_ACTION_WAKE_UP_CMDID, 442 WMI_RTT_MEASREQ_CMDID = WMI_TLV_CMD(WMI_GRP_RTT), 443 WMI_RTT_TSF_CMDID, 444 WMI_VDEV_SPECTRAL_SCAN_CONFIGURE_CMDID = WMI_TLV_CMD(WMI_GRP_SPECTRAL), 445 WMI_VDEV_SPECTRAL_SCAN_ENABLE_CMDID, 446 WMI_REQUEST_STATS_CMDID = WMI_TLV_CMD(WMI_GRP_STATS), 447 WMI_MCC_SCHED_TRAFFIC_STATS_CMDID, 448 WMI_REQUEST_STATS_EXT_CMDID, 449 WMI_REQUEST_LINK_STATS_CMDID, 450 WMI_START_LINK_STATS_CMDID, 451 WMI_CLEAR_LINK_STATS_CMDID, 452 WMI_GET_FW_MEM_DUMP_CMDID, 453 WMI_DEBUG_MESG_FLUSH_CMDID, 454 WMI_DIAG_EVENT_LOG_CONFIG_CMDID, 455 WMI_REQUEST_WLAN_STATS_CMDID, 456 WMI_REQUEST_RCPI_CMDID, 457 WMI_REQUEST_PEER_STATS_INFO_CMDID, 458 WMI_REQUEST_RADIO_CHAN_STATS_CMDID, 459 WMI_SET_ARP_NS_OFFLOAD_CMDID = WMI_TLV_CMD(WMI_GRP_ARP_NS_OFL), 460 WMI_ADD_PROACTIVE_ARP_RSP_PATTERN_CMDID, 461 WMI_DEL_PROACTIVE_ARP_RSP_PATTERN_CMDID, 462 WMI_NETWORK_LIST_OFFLOAD_CONFIG_CMDID = WMI_TLV_CMD(WMI_GRP_NLO_OFL), 463 WMI_APFIND_CMDID, 464 WMI_PASSPOINT_LIST_CONFIG_CMDID, 465 WMI_NLO_CONFIGURE_MAWC_CMDID, 466 WMI_GTK_OFFLOAD_CMDID = WMI_TLV_CMD(WMI_GRP_GTK_OFL), 467 WMI_CSA_OFFLOAD_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_CSA_OFL), 468 WMI_CSA_OFFLOAD_CHANSWITCH_CMDID, 469 WMI_CHATTER_SET_MODE_CMDID = WMI_TLV_CMD(WMI_GRP_CHATTER), 470 WMI_CHATTER_ADD_COALESCING_FILTER_CMDID, 471 WMI_CHATTER_DELETE_COALESCING_FILTER_CMDID, 472 WMI_CHATTER_COALESCING_QUERY_CMDID, 473 WMI_PEER_TID_ADDBA_CMDID = WMI_TLV_CMD(WMI_GRP_TID_ADDBA), 474 WMI_PEER_TID_DELBA_CMDID, 475 WMI_STA_DTIM_PS_METHOD_CMDID, 476 WMI_STA_UAPSD_AUTO_TRIG_CMDID, 477 WMI_STA_KEEPALIVE_CMDID, 478 WMI_BA_REQ_SSN_CMDID, 479 WMI_ECHO_CMDID = WMI_TLV_CMD(WMI_GRP_MISC), 480 WMI_PDEV_UTF_CMDID, 481 WMI_DBGLOG_CFG_CMDID, 482 WMI_PDEV_QVIT_CMDID, 483 WMI_PDEV_FTM_INTG_CMDID, 484 WMI_VDEV_SET_KEEPALIVE_CMDID, 485 WMI_VDEV_GET_KEEPALIVE_CMDID, 486 WMI_FORCE_FW_HANG_CMDID, 487 WMI_SET_MCASTBCAST_FILTER_CMDID, 488 WMI_THERMAL_MGMT_CMDID, 489 WMI_HOST_AUTO_SHUTDOWN_CFG_CMDID, 490 WMI_TPC_CHAINMASK_CONFIG_CMDID, 491 WMI_SET_ANTENNA_DIVERSITY_CMDID, 492 WMI_OCB_SET_SCHED_CMDID, 493 WMI_RSSI_BREACH_MONITOR_CONFIG_CMDID, 494 WMI_LRO_CONFIG_CMDID, 495 WMI_TRANSFER_DATA_TO_FLASH_CMDID, 496 WMI_CONFIG_ENHANCED_MCAST_FILTER_CMDID, 497 WMI_VDEV_WISA_CMDID, 498 WMI_DBGLOG_TIME_STAMP_SYNC_CMDID, 499 WMI_SET_MULTIPLE_MCAST_FILTER_CMDID, 500 WMI_READ_DATA_FROM_FLASH_CMDID, 501 WMI_THERM_THROT_SET_CONF_CMDID, 502 WMI_RUNTIME_DPD_RECAL_CMDID, 503 WMI_GET_TPC_POWER_CMDID, 504 WMI_IDLE_TRIGGER_MONITOR_CMDID, 505 WMI_GPIO_CONFIG_CMDID = WMI_TLV_CMD(WMI_GRP_GPIO), 506 WMI_GPIO_OUTPUT_CMDID, 507 WMI_TXBF_CMDID, 508 WMI_FWTEST_VDEV_MCC_SET_TBTT_MODE_CMDID = WMI_TLV_CMD(WMI_GRP_FWTEST), 509 WMI_FWTEST_P2P_SET_NOA_PARAM_CMDID, 510 WMI_UNIT_TEST_CMDID, 511 WMI_FWTEST_CMDID, 512 WMI_QBOOST_CFG_CMDID, 513 WMI_TDLS_SET_STATE_CMDID = WMI_TLV_CMD(WMI_GRP_TDLS), 514 WMI_TDLS_PEER_UPDATE_CMDID, 515 WMI_TDLS_SET_OFFCHAN_MODE_CMDID, 516 WMI_RESMGR_ADAPTIVE_OCS_EN_DIS_CMDID = WMI_TLV_CMD(WMI_GRP_RESMGR), 517 WMI_RESMGR_SET_CHAN_TIME_QUOTA_CMDID, 518 WMI_RESMGR_SET_CHAN_LATENCY_CMDID, 519 WMI_STA_SMPS_FORCE_MODE_CMDID = WMI_TLV_CMD(WMI_GRP_STA_SMPS), 520 WMI_STA_SMPS_PARAM_CMDID, 521 WMI_HB_SET_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_WLAN_HB), 522 WMI_HB_SET_TCP_PARAMS_CMDID, 523 WMI_HB_SET_TCP_PKT_FILTER_CMDID, 524 WMI_HB_SET_UDP_PARAMS_CMDID, 525 WMI_HB_SET_UDP_PKT_FILTER_CMDID, 526 WMI_RMC_SET_MODE_CMDID = WMI_TLV_CMD(WMI_GRP_RMC), 527 WMI_RMC_SET_ACTION_PERIOD_CMDID, 528 WMI_RMC_CONFIG_CMDID, 529 WMI_RMC_SET_MANUAL_LEADER_CMDID, 530 WMI_MHF_OFFLOAD_SET_MODE_CMDID = WMI_TLV_CMD(WMI_GRP_MHF_OFL), 531 WMI_MHF_OFFLOAD_PLUMB_ROUTING_TBL_CMDID, 532 WMI_BATCH_SCAN_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_LOCATION_SCAN), 533 WMI_BATCH_SCAN_DISABLE_CMDID, 534 WMI_BATCH_SCAN_TRIGGER_RESULT_CMDID, 535 WMI_OEM_REQ_CMDID = WMI_TLV_CMD(WMI_GRP_OEM), 536 WMI_OEM_REQUEST_CMDID, 537 WMI_LPI_OEM_REQ_CMDID, 538 WMI_NAN_CMDID = WMI_TLV_CMD(WMI_GRP_NAN), 539 WMI_MODEM_POWER_STATE_CMDID = WMI_TLV_CMD(WMI_GRP_COEX), 540 WMI_CHAN_AVOID_UPDATE_CMDID, 541 WMI_COEX_CONFIG_CMDID, 542 WMI_CHAN_AVOID_RPT_ALLOW_CMDID, 543 WMI_COEX_GET_ANTENNA_ISOLATION_CMDID, 544 WMI_SAR_LIMITS_CMDID, 545 WMI_OBSS_SCAN_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_OBSS_OFL), 546 WMI_OBSS_SCAN_DISABLE_CMDID, 547 WMI_OBSS_COLOR_COLLISION_DET_CONFIG_CMDID, 548 WMI_LPI_MGMT_SNOOPING_CONFIG_CMDID = WMI_TLV_CMD(WMI_GRP_LPI), 549 WMI_LPI_START_SCAN_CMDID, 550 WMI_LPI_STOP_SCAN_CMDID, 551 WMI_EXTSCAN_START_CMDID = WMI_TLV_CMD(WMI_GRP_EXTSCAN), 552 WMI_EXTSCAN_STOP_CMDID, 553 WMI_EXTSCAN_CONFIGURE_WLAN_CHANGE_MONITOR_CMDID, 554 WMI_EXTSCAN_CONFIGURE_HOTLIST_MONITOR_CMDID, 555 WMI_EXTSCAN_GET_CACHED_RESULTS_CMDID, 556 WMI_EXTSCAN_GET_WLAN_CHANGE_RESULTS_CMDID, 557 WMI_EXTSCAN_SET_CAPABILITIES_CMDID, 558 WMI_EXTSCAN_GET_CAPABILITIES_CMDID, 559 WMI_EXTSCAN_CONFIGURE_HOTLIST_SSID_MONITOR_CMDID, 560 WMI_EXTSCAN_CONFIGURE_MAWC_CMDID, 561 WMI_SET_DHCP_SERVER_OFFLOAD_CMDID = WMI_TLV_CMD(WMI_GRP_DHCP_OFL), 562 WMI_IPA_OFFLOAD_ENABLE_DISABLE_CMDID = WMI_TLV_CMD(WMI_GRP_IPA), 563 WMI_MDNS_OFFLOAD_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_MDNS_OFL), 564 WMI_MDNS_SET_FQDN_CMDID, 565 WMI_MDNS_SET_RESPONSE_CMDID, 566 WMI_MDNS_GET_STATS_CMDID, 567 WMI_SAP_OFL_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_SAP_OFL), 568 WMI_SAP_SET_BLACKLIST_PARAM_CMDID, 569 WMI_OCB_SET_CONFIG_CMDID = WMI_TLV_CMD(WMI_GRP_OCB), 570 WMI_OCB_SET_UTC_TIME_CMDID, 571 WMI_OCB_START_TIMING_ADVERT_CMDID, 572 WMI_OCB_STOP_TIMING_ADVERT_CMDID, 573 WMI_OCB_GET_TSF_TIMER_CMDID, 574 WMI_DCC_GET_STATS_CMDID, 575 WMI_DCC_CLEAR_STATS_CMDID, 576 WMI_DCC_UPDATE_NDL_CMDID, 577 WMI_SOC_SET_PCL_CMDID = WMI_TLV_CMD(WMI_GRP_SOC), 578 WMI_SOC_SET_HW_MODE_CMDID, 579 WMI_SOC_SET_DUAL_MAC_CONFIG_CMDID, 580 WMI_SOC_SET_ANTENNA_MODE_CMDID, 581 WMI_PACKET_FILTER_CONFIG_CMDID = WMI_TLV_CMD(WMI_GRP_PKT_FILTER), 582 WMI_PACKET_FILTER_ENABLE_CMDID, 583 WMI_MAWC_SENSOR_REPORT_IND_CMDID = WMI_TLV_CMD(WMI_GRP_MAWC), 584 WMI_PMF_OFFLOAD_SET_SA_QUERY_CMDID = WMI_TLV_CMD(WMI_GRP_PMF_OFFLOAD), 585 WMI_BPF_GET_CAPABILITY_CMDID = WMI_TLV_CMD(WMI_GRP_BPF_OFFLOAD), 586 WMI_BPF_GET_VDEV_STATS_CMDID, 587 WMI_BPF_SET_VDEV_INSTRUCTIONS_CMDID, 588 WMI_BPF_DEL_VDEV_INSTRUCTIONS_CMDID, 589 WMI_BPF_SET_VDEV_ACTIVE_MODE_CMDID, 590 WMI_MNT_FILTER_CMDID = WMI_TLV_CMD(WMI_GRP_MONITOR), 591 WMI_SET_CURRENT_COUNTRY_CMDID = WMI_TLV_CMD(WMI_GRP_REGULATORY), 592 WMI_11D_SCAN_START_CMDID, 593 WMI_11D_SCAN_STOP_CMDID, 594 WMI_SET_INIT_COUNTRY_CMDID, 595 WMI_NDI_GET_CAP_REQ_CMDID = WMI_TLV_CMD(WMI_GRP_PROTOTYPE), 596 WMI_NDP_INITIATOR_REQ_CMDID, 597 WMI_NDP_RESPONDER_REQ_CMDID, 598 WMI_NDP_END_REQ_CMDID, 599 WMI_HW_DATA_FILTER_CMDID = WMI_TLV_CMD(WMI_GRP_HW_DATA_FILTER), 600 WMI_TWT_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_TWT), 601 WMI_TWT_DISABLE_CMDID, 602 WMI_TWT_ADD_DIALOG_CMDID, 603 WMI_TWT_DEL_DIALOG_CMDID, 604 WMI_TWT_PAUSE_DIALOG_CMDID, 605 WMI_TWT_RESUME_DIALOG_CMDID, 606 WMI_PDEV_OBSS_PD_SPATIAL_REUSE_CMDID = 607 WMI_TLV_CMD(WMI_GRP_SPATIAL_REUSE), 608 WMI_PDEV_OBSS_PD_SPATIAL_REUSE_SET_DEF_OBSS_THRESH_CMDID, 609 }; 610 611 enum wmi_tlv_event_id { 612 WMI_SERVICE_READY_EVENTID = 0x1, 613 WMI_READY_EVENTID, 614 WMI_SERVICE_AVAILABLE_EVENTID, 615 WMI_SCAN_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_SCAN), 616 WMI_PDEV_TPC_CONFIG_EVENTID = WMI_TLV_CMD(WMI_GRP_PDEV), 617 WMI_CHAN_INFO_EVENTID, 618 WMI_PHYERR_EVENTID, 619 WMI_PDEV_DUMP_EVENTID, 620 WMI_TX_PAUSE_EVENTID, 621 WMI_DFS_RADAR_EVENTID, 622 WMI_PDEV_L1SS_TRACK_EVENTID, 623 WMI_PDEV_TEMPERATURE_EVENTID, 624 WMI_SERVICE_READY_EXT_EVENTID, 625 WMI_PDEV_FIPS_EVENTID, 626 WMI_PDEV_CHANNEL_HOPPING_EVENTID, 627 WMI_PDEV_ANI_CCK_LEVEL_EVENTID, 628 WMI_PDEV_ANI_OFDM_LEVEL_EVENTID, 629 WMI_PDEV_TPC_EVENTID, 630 WMI_PDEV_NFCAL_POWER_ALL_CHANNELS_EVENTID, 631 WMI_PDEV_SET_HW_MODE_RESP_EVENTID, 632 WMI_PDEV_HW_MODE_TRANSITION_EVENTID, 633 WMI_PDEV_SET_MAC_CONFIG_RESP_EVENTID, 634 WMI_PDEV_ANTDIV_STATUS_EVENTID, 635 WMI_PDEV_CHIP_POWER_STATS_EVENTID, 636 WMI_PDEV_CHIP_POWER_SAVE_FAILURE_DETECTED_EVENTID, 637 WMI_PDEV_CSA_SWITCH_COUNT_STATUS_EVENTID, 638 WMI_PDEV_CHECK_CAL_VERSION_EVENTID, 639 WMI_PDEV_DIV_RSSI_ANTID_EVENTID, 640 WMI_PDEV_BSS_CHAN_INFO_EVENTID, 641 WMI_PDEV_UPDATE_CTLTABLE_EVENTID, 642 WMI_PDEV_DMA_RING_CFG_RSP_EVENTID, 643 WMI_PDEV_DMA_RING_BUF_RELEASE_EVENTID, 644 WMI_PDEV_CTL_FAILSAFE_CHECK_EVENTID, 645 WMI_PDEV_CSC_SWITCH_COUNT_STATUS_EVENTID, 646 WMI_PDEV_COLD_BOOT_CAL_DATA_EVENTID, 647 WMI_PDEV_RAP_INFO_EVENTID, 648 WMI_CHAN_RF_CHARACTERIZATION_INFO_EVENTID, 649 WMI_SERVICE_READY_EXT2_EVENTID, 650 WMI_VDEV_START_RESP_EVENTID = WMI_TLV_CMD(WMI_GRP_VDEV), 651 WMI_VDEV_STOPPED_EVENTID, 652 WMI_VDEV_INSTALL_KEY_COMPLETE_EVENTID, 653 WMI_VDEV_MCC_BCN_INTERVAL_CHANGE_REQ_EVENTID, 654 WMI_VDEV_TSF_REPORT_EVENTID, 655 WMI_VDEV_DELETE_RESP_EVENTID, 656 WMI_VDEV_ENCRYPT_DECRYPT_DATA_RESP_EVENTID, 657 WMI_VDEV_ADD_MAC_ADDR_TO_RX_FILTER_STATUS_EVENTID, 658 WMI_PEER_STA_KICKOUT_EVENTID = WMI_TLV_CMD(WMI_GRP_PEER), 659 WMI_PEER_INFO_EVENTID, 660 WMI_PEER_TX_FAIL_CNT_THR_EVENTID, 661 WMI_PEER_ESTIMATED_LINKSPEED_EVENTID, 662 WMI_PEER_STATE_EVENTID, 663 WMI_PEER_ASSOC_CONF_EVENTID, 664 WMI_PEER_DELETE_RESP_EVENTID, 665 WMI_PEER_RATECODE_LIST_EVENTID, 666 WMI_WDS_PEER_EVENTID, 667 WMI_PEER_STA_PS_STATECHG_EVENTID, 668 WMI_PEER_ANTDIV_INFO_EVENTID, 669 WMI_PEER_RESERVED0_EVENTID, 670 WMI_PEER_RESERVED1_EVENTID, 671 WMI_PEER_RESERVED2_EVENTID, 672 WMI_PEER_RESERVED3_EVENTID, 673 WMI_PEER_RESERVED4_EVENTID, 674 WMI_PEER_RESERVED5_EVENTID, 675 WMI_PEER_RESERVED6_EVENTID, 676 WMI_PEER_RESERVED7_EVENTID, 677 WMI_PEER_RESERVED8_EVENTID, 678 WMI_PEER_RESERVED9_EVENTID, 679 WMI_PEER_RESERVED10_EVENTID, 680 WMI_PEER_OPER_MODE_CHANGE_EVENTID, 681 WMI_PEER_TX_PN_RESPONSE_EVENTID, 682 WMI_PEER_CFR_CAPTURE_EVENTID, 683 WMI_PEER_CREATE_CONF_EVENTID, 684 WMI_MGMT_RX_EVENTID = WMI_TLV_CMD(WMI_GRP_MGMT), 685 WMI_HOST_SWBA_EVENTID, 686 WMI_TBTTOFFSET_UPDATE_EVENTID, 687 WMI_OFFLOAD_BCN_TX_STATUS_EVENTID, 688 WMI_OFFLOAD_PROB_RESP_TX_STATUS_EVENTID, 689 WMI_MGMT_TX_COMPLETION_EVENTID, 690 WMI_MGMT_TX_BUNDLE_COMPLETION_EVENTID, 691 WMI_TBTTOFFSET_EXT_UPDATE_EVENTID, 692 WMI_OFFCHAN_DATA_TX_COMPLETION_EVENTID, 693 WMI_HOST_FILS_DISCOVERY_EVENTID, 694 WMI_TX_DELBA_COMPLETE_EVENTID = WMI_TLV_CMD(WMI_GRP_BA_NEG), 695 WMI_TX_ADDBA_COMPLETE_EVENTID, 696 WMI_BA_RSP_SSN_EVENTID, 697 WMI_AGGR_STATE_TRIG_EVENTID, 698 WMI_ROAM_EVENTID = WMI_TLV_CMD(WMI_GRP_ROAM), 699 WMI_PROFILE_MATCH, 700 WMI_ROAM_SYNCH_EVENTID, 701 WMI_P2P_DISC_EVENTID = WMI_TLV_CMD(WMI_GRP_P2P), 702 WMI_P2P_NOA_EVENTID, 703 WMI_P2P_LISTEN_OFFLOAD_STOPPED_EVENTID, 704 WMI_AP_PS_EGAP_INFO_EVENTID = WMI_TLV_CMD(WMI_GRP_AP_PS), 705 WMI_PDEV_RESUME_EVENTID = WMI_TLV_CMD(WMI_GRP_SUSPEND), 706 WMI_WOW_WAKEUP_HOST_EVENTID = WMI_TLV_CMD(WMI_GRP_WOW), 707 WMI_D0_WOW_DISABLE_ACK_EVENTID, 708 WMI_WOW_INITIAL_WAKEUP_EVENTID, 709 WMI_RTT_MEASUREMENT_REPORT_EVENTID = WMI_TLV_CMD(WMI_GRP_RTT), 710 WMI_TSF_MEASUREMENT_REPORT_EVENTID, 711 WMI_RTT_ERROR_REPORT_EVENTID, 712 WMI_STATS_EXT_EVENTID = WMI_TLV_CMD(WMI_GRP_STATS), 713 WMI_IFACE_LINK_STATS_EVENTID, 714 WMI_PEER_LINK_STATS_EVENTID, 715 WMI_RADIO_LINK_STATS_EVENTID, 716 WMI_UPDATE_FW_MEM_DUMP_EVENTID, 717 WMI_DIAG_EVENT_LOG_SUPPORTED_EVENTID, 718 WMI_INST_RSSI_STATS_EVENTID, 719 WMI_RADIO_TX_POWER_LEVEL_STATS_EVENTID, 720 WMI_REPORT_STATS_EVENTID, 721 WMI_UPDATE_RCPI_EVENTID, 722 WMI_PEER_STATS_INFO_EVENTID, 723 WMI_RADIO_CHAN_STATS_EVENTID, 724 WMI_NLO_MATCH_EVENTID = WMI_TLV_CMD(WMI_GRP_NLO_OFL), 725 WMI_NLO_SCAN_COMPLETE_EVENTID, 726 WMI_APFIND_EVENTID, 727 WMI_PASSPOINT_MATCH_EVENTID, 728 WMI_GTK_OFFLOAD_STATUS_EVENTID = WMI_TLV_CMD(WMI_GRP_GTK_OFL), 729 WMI_GTK_REKEY_FAIL_EVENTID, 730 WMI_CSA_HANDLING_EVENTID = WMI_TLV_CMD(WMI_GRP_CSA_OFL), 731 WMI_CHATTER_PC_QUERY_EVENTID = WMI_TLV_CMD(WMI_GRP_CHATTER), 732 WMI_PDEV_DFS_RADAR_DETECTION_EVENTID = WMI_TLV_CMD(WMI_GRP_DFS), 733 WMI_VDEV_DFS_CAC_COMPLETE_EVENTID, 734 WMI_VDEV_ADFS_OCAC_COMPLETE_EVENTID, 735 WMI_ECHO_EVENTID = WMI_TLV_CMD(WMI_GRP_MISC), 736 WMI_PDEV_UTF_EVENTID, 737 WMI_DEBUG_MESG_EVENTID, 738 WMI_UPDATE_STATS_EVENTID, 739 WMI_DEBUG_PRINT_EVENTID, 740 WMI_DCS_INTERFERENCE_EVENTID, 741 WMI_PDEV_QVIT_EVENTID, 742 WMI_WLAN_PROFILE_DATA_EVENTID, 743 WMI_PDEV_FTM_INTG_EVENTID, 744 WMI_WLAN_FREQ_AVOID_EVENTID, 745 WMI_VDEV_GET_KEEPALIVE_EVENTID, 746 WMI_THERMAL_MGMT_EVENTID, 747 WMI_DIAG_DATA_CONTAINER_EVENTID, 748 WMI_HOST_AUTO_SHUTDOWN_EVENTID, 749 WMI_UPDATE_WHAL_MIB_STATS_EVENTID, 750 WMI_UPDATE_VDEV_RATE_STATS_EVENTID, 751 WMI_DIAG_EVENTID, 752 WMI_OCB_SET_SCHED_EVENTID, 753 WMI_DEBUG_MESG_FLUSH_COMPLETE_EVENTID, 754 WMI_RSSI_BREACH_EVENTID, 755 WMI_TRANSFER_DATA_TO_FLASH_COMPLETE_EVENTID, 756 WMI_PDEV_UTF_SCPC_EVENTID, 757 WMI_READ_DATA_FROM_FLASH_EVENTID, 758 WMI_REPORT_RX_AGGR_FAILURE_EVENTID, 759 WMI_PKGID_EVENTID, 760 WMI_GPIO_INPUT_EVENTID = WMI_TLV_CMD(WMI_GRP_GPIO), 761 WMI_UPLOADH_EVENTID, 762 WMI_CAPTUREH_EVENTID, 763 WMI_RFKILL_STATE_CHANGE_EVENTID, 764 WMI_TDLS_PEER_EVENTID = WMI_TLV_CMD(WMI_GRP_TDLS), 765 WMI_STA_SMPS_FORCE_MODE_COMPL_EVENTID = WMI_TLV_CMD(WMI_GRP_STA_SMPS), 766 WMI_BATCH_SCAN_ENABLED_EVENTID = WMI_TLV_CMD(WMI_GRP_LOCATION_SCAN), 767 WMI_BATCH_SCAN_RESULT_EVENTID, 768 WMI_OEM_CAPABILITY_EVENTID = WMI_TLV_CMD(WMI_GRP_OEM), 769 WMI_OEM_MEASUREMENT_REPORT_EVENTID, 770 WMI_OEM_ERROR_REPORT_EVENTID, 771 WMI_OEM_RESPONSE_EVENTID, 772 WMI_NAN_EVENTID = WMI_TLV_CMD(WMI_GRP_NAN), 773 WMI_NAN_DISC_IFACE_CREATED_EVENTID, 774 WMI_NAN_DISC_IFACE_DELETED_EVENTID, 775 WMI_NAN_STARTED_CLUSTER_EVENTID, 776 WMI_NAN_JOINED_CLUSTER_EVENTID, 777 WMI_COEX_REPORT_ANTENNA_ISOLATION_EVENTID = WMI_TLV_CMD(WMI_GRP_COEX), 778 WMI_LPI_RESULT_EVENTID = WMI_TLV_CMD(WMI_GRP_LPI), 779 WMI_LPI_STATUS_EVENTID, 780 WMI_LPI_HANDOFF_EVENTID, 781 WMI_EXTSCAN_START_STOP_EVENTID = WMI_TLV_CMD(WMI_GRP_EXTSCAN), 782 WMI_EXTSCAN_OPERATION_EVENTID, 783 WMI_EXTSCAN_TABLE_USAGE_EVENTID, 784 WMI_EXTSCAN_CACHED_RESULTS_EVENTID, 785 WMI_EXTSCAN_WLAN_CHANGE_RESULTS_EVENTID, 786 WMI_EXTSCAN_HOTLIST_MATCH_EVENTID, 787 WMI_EXTSCAN_CAPABILITIES_EVENTID, 788 WMI_EXTSCAN_HOTLIST_SSID_MATCH_EVENTID, 789 WMI_MDNS_STATS_EVENTID = WMI_TLV_CMD(WMI_GRP_MDNS_OFL), 790 WMI_SAP_OFL_ADD_STA_EVENTID = WMI_TLV_CMD(WMI_GRP_SAP_OFL), 791 WMI_SAP_OFL_DEL_STA_EVENTID, 792 WMI_OBSS_COLOR_COLLISION_DETECTION_EVENTID = 793 WMI_EVT_GRP_START_ID(WMI_GRP_OBSS_OFL), 794 WMI_OCB_SET_CONFIG_RESP_EVENTID = WMI_TLV_CMD(WMI_GRP_OCB), 795 WMI_OCB_GET_TSF_TIMER_RESP_EVENTID, 796 WMI_DCC_GET_STATS_RESP_EVENTID, 797 WMI_DCC_UPDATE_NDL_RESP_EVENTID, 798 WMI_DCC_STATS_EVENTID, 799 WMI_SOC_SET_HW_MODE_RESP_EVENTID = WMI_TLV_CMD(WMI_GRP_SOC), 800 WMI_SOC_HW_MODE_TRANSITION_EVENTID, 801 WMI_SOC_SET_DUAL_MAC_CONFIG_RESP_EVENTID, 802 WMI_MAWC_ENABLE_SENSOR_EVENTID = WMI_TLV_CMD(WMI_GRP_MAWC), 803 WMI_BPF_CAPABILIY_INFO_EVENTID = WMI_TLV_CMD(WMI_GRP_BPF_OFFLOAD), 804 WMI_BPF_VDEV_STATS_INFO_EVENTID, 805 WMI_RMC_NEW_LEADER_EVENTID = WMI_TLV_CMD(WMI_GRP_RMC), 806 WMI_REG_CHAN_LIST_CC_EVENTID = WMI_TLV_CMD(WMI_GRP_REGULATORY), 807 WMI_11D_NEW_COUNTRY_EVENTID, 808 WMI_REG_CHAN_LIST_CC_EXT_EVENTID, 809 WMI_NDI_CAP_RSP_EVENTID = WMI_TLV_CMD(WMI_GRP_PROTOTYPE), 810 WMI_NDP_INITIATOR_RSP_EVENTID, 811 WMI_NDP_RESPONDER_RSP_EVENTID, 812 WMI_NDP_END_RSP_EVENTID, 813 WMI_NDP_INDICATION_EVENTID, 814 WMI_NDP_CONFIRM_EVENTID, 815 WMI_NDP_END_INDICATION_EVENTID, 816 817 WMI_TWT_ENABLE_EVENTID = WMI_TLV_CMD(WMI_GRP_TWT), 818 WMI_TWT_DISABLE_EVENTID, 819 WMI_TWT_ADD_DIALOG_EVENTID, 820 WMI_TWT_DEL_DIALOG_EVENTID, 821 WMI_TWT_PAUSE_DIALOG_EVENTID, 822 WMI_TWT_RESUME_DIALOG_EVENTID, 823 }; 824 825 enum wmi_tlv_pdev_param { 826 WMI_PDEV_PARAM_TX_CHAIN_MASK = 0x1, 827 WMI_PDEV_PARAM_RX_CHAIN_MASK, 828 WMI_PDEV_PARAM_TXPOWER_LIMIT2G, 829 WMI_PDEV_PARAM_TXPOWER_LIMIT5G, 830 WMI_PDEV_PARAM_TXPOWER_SCALE, 831 WMI_PDEV_PARAM_BEACON_GEN_MODE, 832 WMI_PDEV_PARAM_BEACON_TX_MODE, 833 WMI_PDEV_PARAM_RESMGR_OFFCHAN_MODE, 834 WMI_PDEV_PARAM_PROTECTION_MODE, 835 WMI_PDEV_PARAM_DYNAMIC_BW, 836 WMI_PDEV_PARAM_NON_AGG_SW_RETRY_TH, 837 WMI_PDEV_PARAM_AGG_SW_RETRY_TH, 838 WMI_PDEV_PARAM_STA_KICKOUT_TH, 839 WMI_PDEV_PARAM_AC_AGGRSIZE_SCALING, 840 WMI_PDEV_PARAM_LTR_ENABLE, 841 WMI_PDEV_PARAM_LTR_AC_LATENCY_BE, 842 WMI_PDEV_PARAM_LTR_AC_LATENCY_BK, 843 WMI_PDEV_PARAM_LTR_AC_LATENCY_VI, 844 WMI_PDEV_PARAM_LTR_AC_LATENCY_VO, 845 WMI_PDEV_PARAM_LTR_AC_LATENCY_TIMEOUT, 846 WMI_PDEV_PARAM_LTR_SLEEP_OVERRIDE, 847 WMI_PDEV_PARAM_LTR_RX_OVERRIDE, 848 WMI_PDEV_PARAM_LTR_TX_ACTIVITY_TIMEOUT, 849 WMI_PDEV_PARAM_L1SS_ENABLE, 850 WMI_PDEV_PARAM_DSLEEP_ENABLE, 851 WMI_PDEV_PARAM_PCIELP_TXBUF_FLUSH, 852 WMI_PDEV_PARAM_PCIELP_TXBUF_WATERMARK, 853 WMI_PDEV_PARAM_PCIELP_TXBUF_TMO_EN, 854 WMI_PDEV_PARAM_PCIELP_TXBUF_TMO_VALUE, 855 WMI_PDEV_PARAM_PDEV_STATS_UPDATE_PERIOD, 856 WMI_PDEV_PARAM_VDEV_STATS_UPDATE_PERIOD, 857 WMI_PDEV_PARAM_PEER_STATS_UPDATE_PERIOD, 858 WMI_PDEV_PARAM_BCNFLT_STATS_UPDATE_PERIOD, 859 WMI_PDEV_PARAM_PMF_QOS, 860 WMI_PDEV_PARAM_ARP_AC_OVERRIDE, 861 WMI_PDEV_PARAM_DCS, 862 WMI_PDEV_PARAM_ANI_ENABLE, 863 WMI_PDEV_PARAM_ANI_POLL_PERIOD, 864 WMI_PDEV_PARAM_ANI_LISTEN_PERIOD, 865 WMI_PDEV_PARAM_ANI_OFDM_LEVEL, 866 WMI_PDEV_PARAM_ANI_CCK_LEVEL, 867 WMI_PDEV_PARAM_DYNTXCHAIN, 868 WMI_PDEV_PARAM_PROXY_STA, 869 WMI_PDEV_PARAM_IDLE_PS_CONFIG, 870 WMI_PDEV_PARAM_POWER_GATING_SLEEP, 871 WMI_PDEV_PARAM_RFKILL_ENABLE, 872 WMI_PDEV_PARAM_BURST_DUR, 873 WMI_PDEV_PARAM_BURST_ENABLE, 874 WMI_PDEV_PARAM_HW_RFKILL_CONFIG, 875 WMI_PDEV_PARAM_LOW_POWER_RF_ENABLE, 876 WMI_PDEV_PARAM_L1SS_TRACK, 877 WMI_PDEV_PARAM_HYST_EN, 878 WMI_PDEV_PARAM_POWER_COLLAPSE_ENABLE, 879 WMI_PDEV_PARAM_LED_SYS_STATE, 880 WMI_PDEV_PARAM_LED_ENABLE, 881 WMI_PDEV_PARAM_AUDIO_OVER_WLAN_LATENCY, 882 WMI_PDEV_PARAM_AUDIO_OVER_WLAN_ENABLE, 883 WMI_PDEV_PARAM_WHAL_MIB_STATS_UPDATE_ENABLE, 884 WMI_PDEV_PARAM_VDEV_RATE_STATS_UPDATE_PERIOD, 885 WMI_PDEV_PARAM_CTS_CBW, 886 WMI_PDEV_PARAM_WNTS_CONFIG, 887 WMI_PDEV_PARAM_ADAPTIVE_EARLY_RX_ENABLE, 888 WMI_PDEV_PARAM_ADAPTIVE_EARLY_RX_MIN_SLEEP_SLOP, 889 WMI_PDEV_PARAM_ADAPTIVE_EARLY_RX_INC_DEC_STEP, 890 WMI_PDEV_PARAM_EARLY_RX_FIX_SLEEP_SLOP, 891 WMI_PDEV_PARAM_BMISS_BASED_ADAPTIVE_BTO_ENABLE, 892 WMI_PDEV_PARAM_BMISS_BTO_MIN_BCN_TIMEOUT, 893 WMI_PDEV_PARAM_BMISS_BTO_INC_DEC_STEP, 894 WMI_PDEV_PARAM_BTO_FIX_BCN_TIMEOUT, 895 WMI_PDEV_PARAM_CE_BASED_ADAPTIVE_BTO_ENABLE, 896 WMI_PDEV_PARAM_CE_BTO_COMBO_CE_VALUE, 897 WMI_PDEV_PARAM_TX_CHAIN_MASK_2G, 898 WMI_PDEV_PARAM_RX_CHAIN_MASK_2G, 899 WMI_PDEV_PARAM_TX_CHAIN_MASK_5G, 900 WMI_PDEV_PARAM_RX_CHAIN_MASK_5G, 901 WMI_PDEV_PARAM_TX_CHAIN_MASK_CCK, 902 WMI_PDEV_PARAM_TX_CHAIN_MASK_1SS, 903 WMI_PDEV_PARAM_CTS2SELF_FOR_P2P_GO_CONFIG, 904 WMI_PDEV_PARAM_TXPOWER_DECR_DB, 905 WMI_PDEV_PARAM_AGGR_BURST, 906 WMI_PDEV_PARAM_RX_DECAP_MODE, 907 WMI_PDEV_PARAM_FAST_CHANNEL_RESET, 908 WMI_PDEV_PARAM_SMART_ANTENNA_DEFAULT_ANTENNA, 909 WMI_PDEV_PARAM_ANTENNA_GAIN, 910 WMI_PDEV_PARAM_RX_FILTER, 911 WMI_PDEV_SET_MCAST_TO_UCAST_TID, 912 WMI_PDEV_PARAM_PROXY_STA_MODE, 913 WMI_PDEV_PARAM_SET_MCAST2UCAST_MODE, 914 WMI_PDEV_PARAM_SET_MCAST2UCAST_BUFFER, 915 WMI_PDEV_PARAM_REMOVE_MCAST2UCAST_BUFFER, 916 WMI_PDEV_PEER_STA_PS_STATECHG_ENABLE, 917 WMI_PDEV_PARAM_IGMPMLD_AC_OVERRIDE, 918 WMI_PDEV_PARAM_BLOCK_INTERBSS, 919 WMI_PDEV_PARAM_SET_DISABLE_RESET_CMDID, 920 WMI_PDEV_PARAM_SET_MSDU_TTL_CMDID, 921 WMI_PDEV_PARAM_SET_PPDU_DURATION_CMDID, 922 WMI_PDEV_PARAM_TXBF_SOUND_PERIOD_CMDID, 923 WMI_PDEV_PARAM_SET_PROMISC_MODE_CMDID, 924 WMI_PDEV_PARAM_SET_BURST_MODE_CMDID, 925 WMI_PDEV_PARAM_EN_STATS, 926 WMI_PDEV_PARAM_MU_GROUP_POLICY, 927 WMI_PDEV_PARAM_NOISE_DETECTION, 928 WMI_PDEV_PARAM_NOISE_THRESHOLD, 929 WMI_PDEV_PARAM_DPD_ENABLE, 930 WMI_PDEV_PARAM_SET_MCAST_BCAST_ECHO, 931 WMI_PDEV_PARAM_ATF_STRICT_SCH, 932 WMI_PDEV_PARAM_ATF_SCHED_DURATION, 933 WMI_PDEV_PARAM_ANT_PLZN, 934 WMI_PDEV_PARAM_MGMT_RETRY_LIMIT, 935 WMI_PDEV_PARAM_SENSITIVITY_LEVEL, 936 WMI_PDEV_PARAM_SIGNED_TXPOWER_2G, 937 WMI_PDEV_PARAM_SIGNED_TXPOWER_5G, 938 WMI_PDEV_PARAM_ENABLE_PER_TID_AMSDU, 939 WMI_PDEV_PARAM_ENABLE_PER_TID_AMPDU, 940 WMI_PDEV_PARAM_CCA_THRESHOLD, 941 WMI_PDEV_PARAM_RTS_FIXED_RATE, 942 WMI_PDEV_PARAM_PDEV_RESET, 943 WMI_PDEV_PARAM_WAPI_MBSSID_OFFSET, 944 WMI_PDEV_PARAM_ARP_DBG_SRCADDR, 945 WMI_PDEV_PARAM_ARP_DBG_DSTADDR, 946 WMI_PDEV_PARAM_ATF_OBSS_NOISE_SCH, 947 WMI_PDEV_PARAM_ATF_OBSS_NOISE_SCALING_FACTOR, 948 WMI_PDEV_PARAM_CUST_TXPOWER_SCALE, 949 WMI_PDEV_PARAM_ATF_DYNAMIC_ENABLE, 950 WMI_PDEV_PARAM_CTRL_RETRY_LIMIT, 951 WMI_PDEV_PARAM_PROPAGATION_DELAY, 952 WMI_PDEV_PARAM_ENA_ANT_DIV, 953 WMI_PDEV_PARAM_FORCE_CHAIN_ANT, 954 WMI_PDEV_PARAM_ANT_DIV_SELFTEST, 955 WMI_PDEV_PARAM_ANT_DIV_SELFTEST_INTVL, 956 WMI_PDEV_PARAM_STATS_OBSERVATION_PERIOD, 957 WMI_PDEV_PARAM_TX_PPDU_DELAY_BIN_SIZE_MS, 958 WMI_PDEV_PARAM_TX_PPDU_DELAY_ARRAY_LEN, 959 WMI_PDEV_PARAM_TX_MPDU_AGGR_ARRAY_LEN, 960 WMI_PDEV_PARAM_RX_MPDU_AGGR_ARRAY_LEN, 961 WMI_PDEV_PARAM_TX_SCH_DELAY, 962 WMI_PDEV_PARAM_ENABLE_RTS_SIFS_BURSTING, 963 WMI_PDEV_PARAM_MAX_MPDUS_IN_AMPDU, 964 WMI_PDEV_PARAM_PEER_STATS_INFO_ENABLE, 965 WMI_PDEV_PARAM_FAST_PWR_TRANSITION, 966 WMI_PDEV_PARAM_RADIO_CHAN_STATS_ENABLE, 967 WMI_PDEV_PARAM_RADIO_DIAGNOSIS_ENABLE, 968 WMI_PDEV_PARAM_MESH_MCAST_ENABLE, 969 WMI_PDEV_PARAM_SET_CMD_OBSS_PD_THRESHOLD = 0xbc, 970 WMI_PDEV_PARAM_SET_CMD_OBSS_PD_PER_AC = 0xbe, 971 WMI_PDEV_PARAM_ENABLE_SR_PROHIBIT = 0xc6, 972 }; 973 974 enum wmi_tlv_vdev_param { 975 WMI_VDEV_PARAM_RTS_THRESHOLD = 0x1, 976 WMI_VDEV_PARAM_FRAGMENTATION_THRESHOLD, 977 WMI_VDEV_PARAM_BEACON_INTERVAL, 978 WMI_VDEV_PARAM_LISTEN_INTERVAL, 979 WMI_VDEV_PARAM_MULTICAST_RATE, 980 WMI_VDEV_PARAM_MGMT_TX_RATE, 981 WMI_VDEV_PARAM_SLOT_TIME, 982 WMI_VDEV_PARAM_PREAMBLE, 983 WMI_VDEV_PARAM_SWBA_TIME, 984 WMI_VDEV_STATS_UPDATE_PERIOD, 985 WMI_VDEV_PWRSAVE_AGEOUT_TIME, 986 WMI_VDEV_HOST_SWBA_INTERVAL, 987 WMI_VDEV_PARAM_DTIM_PERIOD, 988 WMI_VDEV_OC_SCHEDULER_AIR_TIME_LIMIT, 989 WMI_VDEV_PARAM_WDS, 990 WMI_VDEV_PARAM_ATIM_WINDOW, 991 WMI_VDEV_PARAM_BMISS_COUNT_MAX, 992 WMI_VDEV_PARAM_BMISS_FIRST_BCNT, 993 WMI_VDEV_PARAM_BMISS_FINAL_BCNT, 994 WMI_VDEV_PARAM_FEATURE_WMM, 995 WMI_VDEV_PARAM_CHWIDTH, 996 WMI_VDEV_PARAM_CHEXTOFFSET, 997 WMI_VDEV_PARAM_DISABLE_HTPROTECTION, 998 WMI_VDEV_PARAM_STA_QUICKKICKOUT, 999 WMI_VDEV_PARAM_MGMT_RATE, 1000 WMI_VDEV_PARAM_PROTECTION_MODE, 1001 WMI_VDEV_PARAM_FIXED_RATE, 1002 WMI_VDEV_PARAM_SGI, 1003 WMI_VDEV_PARAM_LDPC, 1004 WMI_VDEV_PARAM_TX_STBC, 1005 WMI_VDEV_PARAM_RX_STBC, 1006 WMI_VDEV_PARAM_INTRA_BSS_FWD, 1007 WMI_VDEV_PARAM_DEF_KEYID, 1008 WMI_VDEV_PARAM_NSS, 1009 WMI_VDEV_PARAM_BCAST_DATA_RATE, 1010 WMI_VDEV_PARAM_MCAST_DATA_RATE, 1011 WMI_VDEV_PARAM_MCAST_INDICATE, 1012 WMI_VDEV_PARAM_DHCP_INDICATE, 1013 WMI_VDEV_PARAM_UNKNOWN_DEST_INDICATE, 1014 WMI_VDEV_PARAM_AP_KEEPALIVE_MIN_IDLE_INACTIVE_TIME_SECS, 1015 WMI_VDEV_PARAM_AP_KEEPALIVE_MAX_IDLE_INACTIVE_TIME_SECS, 1016 WMI_VDEV_PARAM_AP_KEEPALIVE_MAX_UNRESPONSIVE_TIME_SECS, 1017 WMI_VDEV_PARAM_AP_ENABLE_NAWDS, 1018 WMI_VDEV_PARAM_ENABLE_RTSCTS, 1019 WMI_VDEV_PARAM_TXBF, 1020 WMI_VDEV_PARAM_PACKET_POWERSAVE, 1021 WMI_VDEV_PARAM_DROP_UNENCRY, 1022 WMI_VDEV_PARAM_TX_ENCAP_TYPE, 1023 WMI_VDEV_PARAM_AP_DETECT_OUT_OF_SYNC_SLEEPING_STA_TIME_SECS, 1024 WMI_VDEV_PARAM_EARLY_RX_ADJUST_ENABLE, 1025 WMI_VDEV_PARAM_EARLY_RX_TGT_BMISS_NUM, 1026 WMI_VDEV_PARAM_EARLY_RX_BMISS_SAMPLE_CYCLE, 1027 WMI_VDEV_PARAM_EARLY_RX_SLOP_STEP, 1028 WMI_VDEV_PARAM_EARLY_RX_INIT_SLOP, 1029 WMI_VDEV_PARAM_EARLY_RX_ADJUST_PAUSE, 1030 WMI_VDEV_PARAM_TX_PWRLIMIT, 1031 WMI_VDEV_PARAM_SNR_NUM_FOR_CAL, 1032 WMI_VDEV_PARAM_ROAM_FW_OFFLOAD, 1033 WMI_VDEV_PARAM_ENABLE_RMC, 1034 WMI_VDEV_PARAM_IBSS_MAX_BCN_LOST_MS, 1035 WMI_VDEV_PARAM_MAX_RATE, 1036 WMI_VDEV_PARAM_EARLY_RX_DRIFT_SAMPLE, 1037 WMI_VDEV_PARAM_SET_IBSS_TX_FAIL_CNT_THR, 1038 WMI_VDEV_PARAM_EBT_RESYNC_TIMEOUT, 1039 WMI_VDEV_PARAM_AGGR_TRIG_EVENT_ENABLE, 1040 WMI_VDEV_PARAM_IS_IBSS_POWER_SAVE_ALLOWED, 1041 WMI_VDEV_PARAM_IS_POWER_COLLAPSE_ALLOWED, 1042 WMI_VDEV_PARAM_IS_AWAKE_ON_TXRX_ENABLED, 1043 WMI_VDEV_PARAM_INACTIVITY_CNT, 1044 WMI_VDEV_PARAM_TXSP_END_INACTIVITY_TIME_MS, 1045 WMI_VDEV_PARAM_DTIM_POLICY, 1046 WMI_VDEV_PARAM_IBSS_PS_WARMUP_TIME_SECS, 1047 WMI_VDEV_PARAM_IBSS_PS_1RX_CHAIN_IN_ATIM_WINDOW_ENABLE, 1048 WMI_VDEV_PARAM_RX_LEAK_WINDOW, 1049 WMI_VDEV_PARAM_STATS_AVG_FACTOR, 1050 WMI_VDEV_PARAM_DISCONNECT_TH, 1051 WMI_VDEV_PARAM_RTSCTS_RATE, 1052 WMI_VDEV_PARAM_MCC_RTSCTS_PROTECTION_ENABLE, 1053 WMI_VDEV_PARAM_MCC_BROADCAST_PROBE_ENABLE, 1054 WMI_VDEV_PARAM_TXPOWER_SCALE, 1055 WMI_VDEV_PARAM_TXPOWER_SCALE_DECR_DB, 1056 WMI_VDEV_PARAM_MCAST2UCAST_SET, 1057 WMI_VDEV_PARAM_RC_NUM_RETRIES, 1058 WMI_VDEV_PARAM_CABQ_MAXDUR, 1059 WMI_VDEV_PARAM_MFPTEST_SET, 1060 WMI_VDEV_PARAM_RTS_FIXED_RATE, 1061 WMI_VDEV_PARAM_VHT_SGIMASK, 1062 WMI_VDEV_PARAM_VHT80_RATEMASK, 1063 WMI_VDEV_PARAM_PROXY_STA, 1064 WMI_VDEV_PARAM_VIRTUAL_CELL_MODE, 1065 WMI_VDEV_PARAM_RX_DECAP_TYPE, 1066 WMI_VDEV_PARAM_BW_NSS_RATEMASK, 1067 WMI_VDEV_PARAM_SENSOR_AP, 1068 WMI_VDEV_PARAM_BEACON_RATE, 1069 WMI_VDEV_PARAM_DTIM_ENABLE_CTS, 1070 WMI_VDEV_PARAM_STA_KICKOUT, 1071 WMI_VDEV_PARAM_CAPABILITIES, 1072 WMI_VDEV_PARAM_TSF_INCREMENT, 1073 WMI_VDEV_PARAM_AMPDU_PER_AC, 1074 WMI_VDEV_PARAM_RX_FILTER, 1075 WMI_VDEV_PARAM_MGMT_TX_POWER, 1076 WMI_VDEV_PARAM_NON_AGG_SW_RETRY_TH, 1077 WMI_VDEV_PARAM_AGG_SW_RETRY_TH, 1078 WMI_VDEV_PARAM_DISABLE_DYN_BW_RTS, 1079 WMI_VDEV_PARAM_ATF_SSID_SCHED_POLICY, 1080 WMI_VDEV_PARAM_HE_DCM, 1081 WMI_VDEV_PARAM_HE_RANGE_EXT, 1082 WMI_VDEV_PARAM_ENABLE_BCAST_PROBE_RESPONSE, 1083 WMI_VDEV_PARAM_FILS_MAX_CHANNEL_GUARD_TIME, 1084 WMI_VDEV_PARAM_HE_LTF = 0x74, 1085 WMI_VDEV_PARAM_ENABLE_DISABLE_RTT_RESPONDER_ROLE = 0x7d, 1086 WMI_VDEV_PARAM_BA_MODE = 0x7e, 1087 WMI_VDEV_PARAM_AUTORATE_MISC_CFG = 0x80, 1088 WMI_VDEV_PARAM_SET_HE_SOUNDING_MODE = 0x87, 1089 WMI_VDEV_PARAM_6GHZ_PARAMS = 0x99, 1090 WMI_VDEV_PARAM_PROTOTYPE = 0x8000, 1091 WMI_VDEV_PARAM_BSS_COLOR, 1092 WMI_VDEV_PARAM_SET_HEMU_MODE, 1093 WMI_VDEV_PARAM_HEOPS_0_31 = 0x8003, 1094 }; 1095 1096 enum wmi_tlv_peer_flags { 1097 WMI_TLV_PEER_AUTH = 0x00000001, 1098 WMI_TLV_PEER_QOS = 0x00000002, 1099 WMI_TLV_PEER_NEED_PTK_4_WAY = 0x00000004, 1100 WMI_TLV_PEER_NEED_GTK_2_WAY = 0x00000010, 1101 WMI_TLV_PEER_APSD = 0x00000800, 1102 WMI_TLV_PEER_HT = 0x00001000, 1103 WMI_TLV_PEER_40MHZ = 0x00002000, 1104 WMI_TLV_PEER_STBC = 0x00008000, 1105 WMI_TLV_PEER_LDPC = 0x00010000, 1106 WMI_TLV_PEER_DYN_MIMOPS = 0x00020000, 1107 WMI_TLV_PEER_STATIC_MIMOPS = 0x00040000, 1108 WMI_TLV_PEER_SPATIAL_MUX = 0x00200000, 1109 WMI_TLV_PEER_VHT = 0x02000000, 1110 WMI_TLV_PEER_80MHZ = 0x04000000, 1111 WMI_TLV_PEER_PMF = 0x08000000, 1112 WMI_PEER_IS_P2P_CAPABLE = 0x20000000, 1113 WMI_PEER_160MHZ = 0x40000000, 1114 WMI_PEER_SAFEMODE_EN = 0x80000000, 1115 1116 }; 1117 1118 /** Enum list of TLV Tags for each parameter structure type. */ 1119 enum wmi_tlv_tag { 1120 WMI_TAG_LAST_RESERVED = 15, 1121 WMI_TAG_FIRST_ARRAY_ENUM, 1122 WMI_TAG_ARRAY_UINT32 = WMI_TAG_FIRST_ARRAY_ENUM, 1123 WMI_TAG_ARRAY_BYTE, 1124 WMI_TAG_ARRAY_STRUCT, 1125 WMI_TAG_ARRAY_FIXED_STRUCT, 1126 WMI_TAG_LAST_ARRAY_ENUM = 31, 1127 WMI_TAG_SERVICE_READY_EVENT, 1128 WMI_TAG_HAL_REG_CAPABILITIES, 1129 WMI_TAG_WLAN_HOST_MEM_REQ, 1130 WMI_TAG_READY_EVENT, 1131 WMI_TAG_SCAN_EVENT, 1132 WMI_TAG_PDEV_TPC_CONFIG_EVENT, 1133 WMI_TAG_CHAN_INFO_EVENT, 1134 WMI_TAG_COMB_PHYERR_RX_HDR, 1135 WMI_TAG_VDEV_START_RESPONSE_EVENT, 1136 WMI_TAG_VDEV_STOPPED_EVENT, 1137 WMI_TAG_VDEV_INSTALL_KEY_COMPLETE_EVENT, 1138 WMI_TAG_PEER_STA_KICKOUT_EVENT, 1139 WMI_TAG_MGMT_RX_HDR, 1140 WMI_TAG_TBTT_OFFSET_EVENT, 1141 WMI_TAG_TX_DELBA_COMPLETE_EVENT, 1142 WMI_TAG_TX_ADDBA_COMPLETE_EVENT, 1143 WMI_TAG_ROAM_EVENT, 1144 WMI_TAG_WOW_EVENT_INFO, 1145 WMI_TAG_WOW_EVENT_INFO_SECTION_BITMAP, 1146 WMI_TAG_RTT_EVENT_HEADER, 1147 WMI_TAG_RTT_ERROR_REPORT_EVENT, 1148 WMI_TAG_RTT_MEAS_EVENT, 1149 WMI_TAG_ECHO_EVENT, 1150 WMI_TAG_FTM_INTG_EVENT, 1151 WMI_TAG_VDEV_GET_KEEPALIVE_EVENT, 1152 WMI_TAG_GPIO_INPUT_EVENT, 1153 WMI_TAG_CSA_EVENT, 1154 WMI_TAG_GTK_OFFLOAD_STATUS_EVENT, 1155 WMI_TAG_IGTK_INFO, 1156 WMI_TAG_DCS_INTERFERENCE_EVENT, 1157 WMI_TAG_ATH_DCS_CW_INT, 1158 WMI_TAG_WLAN_DCS_CW_INT = /* ALIAS */ 1159 WMI_TAG_ATH_DCS_CW_INT, 1160 WMI_TAG_ATH_DCS_WLAN_INT_STAT, 1161 WMI_TAG_WLAN_DCS_IM_TGT_STATS_T = /* ALIAS */ 1162 WMI_TAG_ATH_DCS_WLAN_INT_STAT, 1163 WMI_TAG_WLAN_PROFILE_CTX_T, 1164 WMI_TAG_WLAN_PROFILE_T, 1165 WMI_TAG_PDEV_QVIT_EVENT, 1166 WMI_TAG_HOST_SWBA_EVENT, 1167 WMI_TAG_TIM_INFO, 1168 WMI_TAG_P2P_NOA_INFO, 1169 WMI_TAG_STATS_EVENT, 1170 WMI_TAG_AVOID_FREQ_RANGES_EVENT, 1171 WMI_TAG_AVOID_FREQ_RANGE_DESC, 1172 WMI_TAG_GTK_REKEY_FAIL_EVENT, 1173 WMI_TAG_INIT_CMD, 1174 WMI_TAG_RESOURCE_CONFIG, 1175 WMI_TAG_WLAN_HOST_MEMORY_CHUNK, 1176 WMI_TAG_START_SCAN_CMD, 1177 WMI_TAG_STOP_SCAN_CMD, 1178 WMI_TAG_SCAN_CHAN_LIST_CMD, 1179 WMI_TAG_CHANNEL, 1180 WMI_TAG_PDEV_SET_REGDOMAIN_CMD, 1181 WMI_TAG_PDEV_SET_PARAM_CMD, 1182 WMI_TAG_PDEV_SET_WMM_PARAMS_CMD, 1183 WMI_TAG_WMM_PARAMS, 1184 WMI_TAG_PDEV_SET_QUIET_CMD, 1185 WMI_TAG_VDEV_CREATE_CMD, 1186 WMI_TAG_VDEV_DELETE_CMD, 1187 WMI_TAG_VDEV_START_REQUEST_CMD, 1188 WMI_TAG_P2P_NOA_DESCRIPTOR, 1189 WMI_TAG_P2P_GO_SET_BEACON_IE, 1190 WMI_TAG_GTK_OFFLOAD_CMD, 1191 WMI_TAG_VDEV_UP_CMD, 1192 WMI_TAG_VDEV_STOP_CMD, 1193 WMI_TAG_VDEV_DOWN_CMD, 1194 WMI_TAG_VDEV_SET_PARAM_CMD, 1195 WMI_TAG_VDEV_INSTALL_KEY_CMD, 1196 WMI_TAG_PEER_CREATE_CMD, 1197 WMI_TAG_PEER_DELETE_CMD, 1198 WMI_TAG_PEER_FLUSH_TIDS_CMD, 1199 WMI_TAG_PEER_SET_PARAM_CMD, 1200 WMI_TAG_PEER_ASSOC_COMPLETE_CMD, 1201 WMI_TAG_VHT_RATE_SET, 1202 WMI_TAG_BCN_TMPL_CMD, 1203 WMI_TAG_PRB_TMPL_CMD, 1204 WMI_TAG_BCN_PRB_INFO, 1205 WMI_TAG_PEER_TID_ADDBA_CMD, 1206 WMI_TAG_PEER_TID_DELBA_CMD, 1207 WMI_TAG_STA_POWERSAVE_MODE_CMD, 1208 WMI_TAG_STA_POWERSAVE_PARAM_CMD, 1209 WMI_TAG_STA_DTIM_PS_METHOD_CMD, 1210 WMI_TAG_ROAM_SCAN_MODE, 1211 WMI_TAG_ROAM_SCAN_RSSI_THRESHOLD, 1212 WMI_TAG_ROAM_SCAN_PERIOD, 1213 WMI_TAG_ROAM_SCAN_RSSI_CHANGE_THRESHOLD, 1214 WMI_TAG_PDEV_SUSPEND_CMD, 1215 WMI_TAG_PDEV_RESUME_CMD, 1216 WMI_TAG_ADD_BCN_FILTER_CMD, 1217 WMI_TAG_RMV_BCN_FILTER_CMD, 1218 WMI_TAG_WOW_ENABLE_CMD, 1219 WMI_TAG_WOW_HOSTWAKEUP_FROM_SLEEP_CMD, 1220 WMI_TAG_STA_UAPSD_AUTO_TRIG_CMD, 1221 WMI_TAG_STA_UAPSD_AUTO_TRIG_PARAM, 1222 WMI_TAG_SET_ARP_NS_OFFLOAD_CMD, 1223 WMI_TAG_ARP_OFFLOAD_TUPLE, 1224 WMI_TAG_NS_OFFLOAD_TUPLE, 1225 WMI_TAG_FTM_INTG_CMD, 1226 WMI_TAG_STA_KEEPALIVE_CMD, 1227 WMI_TAG_STA_KEEPALIVE_ARP_RESPONSE, 1228 WMI_TAG_P2P_SET_VENDOR_IE_DATA_CMD, 1229 WMI_TAG_AP_PS_PEER_CMD, 1230 WMI_TAG_PEER_RATE_RETRY_SCHED_CMD, 1231 WMI_TAG_WLAN_PROFILE_TRIGGER_CMD, 1232 WMI_TAG_WLAN_PROFILE_SET_HIST_INTVL_CMD, 1233 WMI_TAG_WLAN_PROFILE_GET_PROF_DATA_CMD, 1234 WMI_TAG_WLAN_PROFILE_ENABLE_PROFILE_ID_CMD, 1235 WMI_TAG_WOW_DEL_PATTERN_CMD, 1236 WMI_TAG_WOW_ADD_DEL_EVT_CMD, 1237 WMI_TAG_RTT_MEASREQ_HEAD, 1238 WMI_TAG_RTT_MEASREQ_BODY, 1239 WMI_TAG_RTT_TSF_CMD, 1240 WMI_TAG_VDEV_SPECTRAL_CONFIGURE_CMD, 1241 WMI_TAG_VDEV_SPECTRAL_ENABLE_CMD, 1242 WMI_TAG_REQUEST_STATS_CMD, 1243 WMI_TAG_NLO_CONFIG_CMD, 1244 WMI_TAG_NLO_CONFIGURED_PARAMETERS, 1245 WMI_TAG_CSA_OFFLOAD_ENABLE_CMD, 1246 WMI_TAG_CSA_OFFLOAD_CHANSWITCH_CMD, 1247 WMI_TAG_CHATTER_SET_MODE_CMD, 1248 WMI_TAG_ECHO_CMD, 1249 WMI_TAG_VDEV_SET_KEEPALIVE_CMD, 1250 WMI_TAG_VDEV_GET_KEEPALIVE_CMD, 1251 WMI_TAG_FORCE_FW_HANG_CMD, 1252 WMI_TAG_GPIO_CONFIG_CMD, 1253 WMI_TAG_GPIO_OUTPUT_CMD, 1254 WMI_TAG_PEER_ADD_WDS_ENTRY_CMD, 1255 WMI_TAG_PEER_REMOVE_WDS_ENTRY_CMD, 1256 WMI_TAG_BCN_TX_HDR, 1257 WMI_TAG_BCN_SEND_FROM_HOST_CMD, 1258 WMI_TAG_MGMT_TX_HDR, 1259 WMI_TAG_ADDBA_CLEAR_RESP_CMD, 1260 WMI_TAG_ADDBA_SEND_CMD, 1261 WMI_TAG_DELBA_SEND_CMD, 1262 WMI_TAG_ADDBA_SETRESPONSE_CMD, 1263 WMI_TAG_SEND_SINGLEAMSDU_CMD, 1264 WMI_TAG_PDEV_PKTLOG_ENABLE_CMD, 1265 WMI_TAG_PDEV_PKTLOG_DISABLE_CMD, 1266 WMI_TAG_PDEV_SET_HT_IE_CMD, 1267 WMI_TAG_PDEV_SET_VHT_IE_CMD, 1268 WMI_TAG_PDEV_SET_DSCP_TID_MAP_CMD, 1269 WMI_TAG_PDEV_GREEN_AP_PS_ENABLE_CMD, 1270 WMI_TAG_PDEV_GET_TPC_CONFIG_CMD, 1271 WMI_TAG_PDEV_SET_BASE_MACADDR_CMD, 1272 WMI_TAG_PEER_MCAST_GROUP_CMD, 1273 WMI_TAG_ROAM_AP_PROFILE, 1274 WMI_TAG_AP_PROFILE, 1275 WMI_TAG_SCAN_SCH_PRIORITY_TABLE_CMD, 1276 WMI_TAG_PDEV_DFS_ENABLE_CMD, 1277 WMI_TAG_PDEV_DFS_DISABLE_CMD, 1278 WMI_TAG_WOW_ADD_PATTERN_CMD, 1279 WMI_TAG_WOW_BITMAP_PATTERN_T, 1280 WMI_TAG_WOW_IPV4_SYNC_PATTERN_T, 1281 WMI_TAG_WOW_IPV6_SYNC_PATTERN_T, 1282 WMI_TAG_WOW_MAGIC_PATTERN_CMD, 1283 WMI_TAG_SCAN_UPDATE_REQUEST_CMD, 1284 WMI_TAG_CHATTER_PKT_COALESCING_FILTER, 1285 WMI_TAG_CHATTER_COALESCING_ADD_FILTER_CMD, 1286 WMI_TAG_CHATTER_COALESCING_DELETE_FILTER_CMD, 1287 WMI_TAG_CHATTER_COALESCING_QUERY_CMD, 1288 WMI_TAG_TXBF_CMD, 1289 WMI_TAG_DEBUG_LOG_CONFIG_CMD, 1290 WMI_TAG_NLO_EVENT, 1291 WMI_TAG_CHATTER_QUERY_REPLY_EVENT, 1292 WMI_TAG_UPLOAD_H_HDR, 1293 WMI_TAG_CAPTURE_H_EVENT_HDR, 1294 WMI_TAG_VDEV_WNM_SLEEPMODE_CMD, 1295 WMI_TAG_VDEV_IPSEC_NATKEEPALIVE_FILTER_CMD, 1296 WMI_TAG_VDEV_WMM_ADDTS_CMD, 1297 WMI_TAG_VDEV_WMM_DELTS_CMD, 1298 WMI_TAG_VDEV_SET_WMM_PARAMS_CMD, 1299 WMI_TAG_TDLS_SET_STATE_CMD, 1300 WMI_TAG_TDLS_PEER_UPDATE_CMD, 1301 WMI_TAG_TDLS_PEER_EVENT, 1302 WMI_TAG_TDLS_PEER_CAPABILITIES, 1303 WMI_TAG_VDEV_MCC_SET_TBTT_MODE_CMD, 1304 WMI_TAG_ROAM_CHAN_LIST, 1305 WMI_TAG_VDEV_MCC_BCN_INTVL_CHANGE_EVENT, 1306 WMI_TAG_RESMGR_ADAPTIVE_OCS_ENABLE_DISABLE_CMD, 1307 WMI_TAG_RESMGR_SET_CHAN_TIME_QUOTA_CMD, 1308 WMI_TAG_RESMGR_SET_CHAN_LATENCY_CMD, 1309 WMI_TAG_BA_REQ_SSN_CMD, 1310 WMI_TAG_BA_RSP_SSN_EVENT, 1311 WMI_TAG_STA_SMPS_FORCE_MODE_CMD, 1312 WMI_TAG_SET_MCASTBCAST_FILTER_CMD, 1313 WMI_TAG_P2P_SET_OPPPS_CMD, 1314 WMI_TAG_P2P_SET_NOA_CMD, 1315 WMI_TAG_BA_REQ_SSN_CMD_SUB_STRUCT_PARAM, 1316 WMI_TAG_BA_REQ_SSN_EVENT_SUB_STRUCT_PARAM, 1317 WMI_TAG_STA_SMPS_PARAM_CMD, 1318 WMI_TAG_VDEV_SET_GTX_PARAMS_CMD, 1319 WMI_TAG_MCC_SCHED_TRAFFIC_STATS_CMD, 1320 WMI_TAG_MCC_SCHED_STA_TRAFFIC_STATS, 1321 WMI_TAG_OFFLOAD_BCN_TX_STATUS_EVENT, 1322 WMI_TAG_P2P_NOA_EVENT, 1323 WMI_TAG_HB_SET_ENABLE_CMD, 1324 WMI_TAG_HB_SET_TCP_PARAMS_CMD, 1325 WMI_TAG_HB_SET_TCP_PKT_FILTER_CMD, 1326 WMI_TAG_HB_SET_UDP_PARAMS_CMD, 1327 WMI_TAG_HB_SET_UDP_PKT_FILTER_CMD, 1328 WMI_TAG_HB_IND_EVENT, 1329 WMI_TAG_TX_PAUSE_EVENT, 1330 WMI_TAG_RFKILL_EVENT, 1331 WMI_TAG_DFS_RADAR_EVENT, 1332 WMI_TAG_DFS_PHYERR_FILTER_ENA_CMD, 1333 WMI_TAG_DFS_PHYERR_FILTER_DIS_CMD, 1334 WMI_TAG_BATCH_SCAN_RESULT_SCAN_LIST, 1335 WMI_TAG_BATCH_SCAN_RESULT_NETWORK_INFO, 1336 WMI_TAG_BATCH_SCAN_ENABLE_CMD, 1337 WMI_TAG_BATCH_SCAN_DISABLE_CMD, 1338 WMI_TAG_BATCH_SCAN_TRIGGER_RESULT_CMD, 1339 WMI_TAG_BATCH_SCAN_ENABLED_EVENT, 1340 WMI_TAG_BATCH_SCAN_RESULT_EVENT, 1341 WMI_TAG_VDEV_PLMREQ_START_CMD, 1342 WMI_TAG_VDEV_PLMREQ_STOP_CMD, 1343 WMI_TAG_THERMAL_MGMT_CMD, 1344 WMI_TAG_THERMAL_MGMT_EVENT, 1345 WMI_TAG_PEER_INFO_REQ_CMD, 1346 WMI_TAG_PEER_INFO_EVENT, 1347 WMI_TAG_PEER_INFO, 1348 WMI_TAG_PEER_TX_FAIL_CNT_THR_EVENT, 1349 WMI_TAG_RMC_SET_MODE_CMD, 1350 WMI_TAG_RMC_SET_ACTION_PERIOD_CMD, 1351 WMI_TAG_RMC_CONFIG_CMD, 1352 WMI_TAG_MHF_OFFLOAD_SET_MODE_CMD, 1353 WMI_TAG_MHF_OFFLOAD_PLUMB_ROUTING_TABLE_CMD, 1354 WMI_TAG_ADD_PROACTIVE_ARP_RSP_PATTERN_CMD, 1355 WMI_TAG_DEL_PROACTIVE_ARP_RSP_PATTERN_CMD, 1356 WMI_TAG_NAN_CMD_PARAM, 1357 WMI_TAG_NAN_EVENT_HDR, 1358 WMI_TAG_PDEV_L1SS_TRACK_EVENT, 1359 WMI_TAG_DIAG_DATA_CONTAINER_EVENT, 1360 WMI_TAG_MODEM_POWER_STATE_CMD_PARAM, 1361 WMI_TAG_PEER_GET_ESTIMATED_LINKSPEED_CMD, 1362 WMI_TAG_PEER_ESTIMATED_LINKSPEED_EVENT, 1363 WMI_TAG_AGGR_STATE_TRIG_EVENT, 1364 WMI_TAG_MHF_OFFLOAD_ROUTING_TABLE_ENTRY, 1365 WMI_TAG_ROAM_SCAN_CMD, 1366 WMI_TAG_REQ_STATS_EXT_CMD, 1367 WMI_TAG_STATS_EXT_EVENT, 1368 WMI_TAG_OBSS_SCAN_ENABLE_CMD, 1369 WMI_TAG_OBSS_SCAN_DISABLE_CMD, 1370 WMI_TAG_OFFLOAD_PRB_RSP_TX_STATUS_EVENT, 1371 WMI_TAG_PDEV_SET_LED_CONFIG_CMD, 1372 WMI_TAG_HOST_AUTO_SHUTDOWN_CFG_CMD, 1373 WMI_TAG_HOST_AUTO_SHUTDOWN_EVENT, 1374 WMI_TAG_UPDATE_WHAL_MIB_STATS_EVENT, 1375 WMI_TAG_CHAN_AVOID_UPDATE_CMD_PARAM, 1376 WMI_TAG_WOW_IOAC_PKT_PATTERN_T, 1377 WMI_TAG_WOW_IOAC_TMR_PATTERN_T, 1378 WMI_TAG_WOW_IOAC_ADD_KEEPALIVE_CMD, 1379 WMI_TAG_WOW_IOAC_DEL_KEEPALIVE_CMD, 1380 WMI_TAG_WOW_IOAC_KEEPALIVE_T, 1381 WMI_TAG_WOW_IOAC_ADD_PATTERN_CMD, 1382 WMI_TAG_WOW_IOAC_DEL_PATTERN_CMD, 1383 WMI_TAG_START_LINK_STATS_CMD, 1384 WMI_TAG_CLEAR_LINK_STATS_CMD, 1385 WMI_TAG_REQUEST_LINK_STATS_CMD, 1386 WMI_TAG_IFACE_LINK_STATS_EVENT, 1387 WMI_TAG_RADIO_LINK_STATS_EVENT, 1388 WMI_TAG_PEER_STATS_EVENT, 1389 WMI_TAG_CHANNEL_STATS, 1390 WMI_TAG_RADIO_LINK_STATS, 1391 WMI_TAG_RATE_STATS, 1392 WMI_TAG_PEER_LINK_STATS, 1393 WMI_TAG_WMM_AC_STATS, 1394 WMI_TAG_IFACE_LINK_STATS, 1395 WMI_TAG_LPI_MGMT_SNOOPING_CONFIG_CMD, 1396 WMI_TAG_LPI_START_SCAN_CMD, 1397 WMI_TAG_LPI_STOP_SCAN_CMD, 1398 WMI_TAG_LPI_RESULT_EVENT, 1399 WMI_TAG_PEER_STATE_EVENT, 1400 WMI_TAG_EXTSCAN_BUCKET_CMD, 1401 WMI_TAG_EXTSCAN_BUCKET_CHANNEL_EVENT, 1402 WMI_TAG_EXTSCAN_START_CMD, 1403 WMI_TAG_EXTSCAN_STOP_CMD, 1404 WMI_TAG_EXTSCAN_CONFIGURE_WLAN_CHANGE_MONITOR_CMD, 1405 WMI_TAG_EXTSCAN_WLAN_CHANGE_BSSID_PARAM_CMD, 1406 WMI_TAG_EXTSCAN_CONFIGURE_HOTLIST_MONITOR_CMD, 1407 WMI_TAG_EXTSCAN_GET_CACHED_RESULTS_CMD, 1408 WMI_TAG_EXTSCAN_GET_WLAN_CHANGE_RESULTS_CMD, 1409 WMI_TAG_EXTSCAN_SET_CAPABILITIES_CMD, 1410 WMI_TAG_EXTSCAN_GET_CAPABILITIES_CMD, 1411 WMI_TAG_EXTSCAN_OPERATION_EVENT, 1412 WMI_TAG_EXTSCAN_START_STOP_EVENT, 1413 WMI_TAG_EXTSCAN_TABLE_USAGE_EVENT, 1414 WMI_TAG_EXTSCAN_WLAN_DESCRIPTOR_EVENT, 1415 WMI_TAG_EXTSCAN_RSSI_INFO_EVENT, 1416 WMI_TAG_EXTSCAN_CACHED_RESULTS_EVENT, 1417 WMI_TAG_EXTSCAN_WLAN_CHANGE_RESULTS_EVENT, 1418 WMI_TAG_EXTSCAN_WLAN_CHANGE_RESULT_BSSID_EVENT, 1419 WMI_TAG_EXTSCAN_HOTLIST_MATCH_EVENT, 1420 WMI_TAG_EXTSCAN_CAPABILITIES_EVENT, 1421 WMI_TAG_EXTSCAN_CACHE_CAPABILITIES_EVENT, 1422 WMI_TAG_EXTSCAN_WLAN_CHANGE_MONITOR_CAPABILITIES_EVENT, 1423 WMI_TAG_EXTSCAN_HOTLIST_MONITOR_CAPABILITIES_EVENT, 1424 WMI_TAG_D0_WOW_ENABLE_DISABLE_CMD, 1425 WMI_TAG_D0_WOW_DISABLE_ACK_EVENT, 1426 WMI_TAG_UNIT_TEST_CMD, 1427 WMI_TAG_ROAM_OFFLOAD_TLV_PARAM, 1428 WMI_TAG_ROAM_11I_OFFLOAD_TLV_PARAM, 1429 WMI_TAG_ROAM_11R_OFFLOAD_TLV_PARAM, 1430 WMI_TAG_ROAM_ESE_OFFLOAD_TLV_PARAM, 1431 WMI_TAG_ROAM_SYNCH_EVENT, 1432 WMI_TAG_ROAM_SYNCH_COMPLETE, 1433 WMI_TAG_EXTWOW_ENABLE_CMD, 1434 WMI_TAG_EXTWOW_SET_APP_TYPE1_PARAMS_CMD, 1435 WMI_TAG_EXTWOW_SET_APP_TYPE2_PARAMS_CMD, 1436 WMI_TAG_LPI_STATUS_EVENT, 1437 WMI_TAG_LPI_HANDOFF_EVENT, 1438 WMI_TAG_VDEV_RATE_STATS_EVENT, 1439 WMI_TAG_VDEV_RATE_HT_INFO, 1440 WMI_TAG_RIC_REQUEST, 1441 WMI_TAG_PDEV_GET_TEMPERATURE_CMD, 1442 WMI_TAG_PDEV_TEMPERATURE_EVENT, 1443 WMI_TAG_SET_DHCP_SERVER_OFFLOAD_CMD, 1444 WMI_TAG_TPC_CHAINMASK_CONFIG_CMD, 1445 WMI_TAG_RIC_TSPEC, 1446 WMI_TAG_TPC_CHAINMASK_CONFIG, 1447 WMI_TAG_IPA_OFFLOAD_ENABLE_DISABLE_CMD, 1448 WMI_TAG_SCAN_PROB_REQ_OUI_CMD, 1449 WMI_TAG_KEY_MATERIAL, 1450 WMI_TAG_TDLS_SET_OFFCHAN_MODE_CMD, 1451 WMI_TAG_SET_LED_FLASHING_CMD, 1452 WMI_TAG_MDNS_OFFLOAD_CMD, 1453 WMI_TAG_MDNS_SET_FQDN_CMD, 1454 WMI_TAG_MDNS_SET_RESP_CMD, 1455 WMI_TAG_MDNS_GET_STATS_CMD, 1456 WMI_TAG_MDNS_STATS_EVENT, 1457 WMI_TAG_ROAM_INVOKE_CMD, 1458 WMI_TAG_PDEV_RESUME_EVENT, 1459 WMI_TAG_PDEV_SET_ANTENNA_DIVERSITY_CMD, 1460 WMI_TAG_SAP_OFL_ENABLE_CMD, 1461 WMI_TAG_SAP_OFL_ADD_STA_EVENT, 1462 WMI_TAG_SAP_OFL_DEL_STA_EVENT, 1463 WMI_TAG_APFIND_CMD_PARAM, 1464 WMI_TAG_APFIND_EVENT_HDR, 1465 WMI_TAG_OCB_SET_SCHED_CMD, 1466 WMI_TAG_OCB_SET_SCHED_EVENT, 1467 WMI_TAG_OCB_SET_CONFIG_CMD, 1468 WMI_TAG_OCB_SET_CONFIG_RESP_EVENT, 1469 WMI_TAG_OCB_SET_UTC_TIME_CMD, 1470 WMI_TAG_OCB_START_TIMING_ADVERT_CMD, 1471 WMI_TAG_OCB_STOP_TIMING_ADVERT_CMD, 1472 WMI_TAG_OCB_GET_TSF_TIMER_CMD, 1473 WMI_TAG_OCB_GET_TSF_TIMER_RESP_EVENT, 1474 WMI_TAG_DCC_GET_STATS_CMD, 1475 WMI_TAG_DCC_CHANNEL_STATS_REQUEST, 1476 WMI_TAG_DCC_GET_STATS_RESP_EVENT, 1477 WMI_TAG_DCC_CLEAR_STATS_CMD, 1478 WMI_TAG_DCC_UPDATE_NDL_CMD, 1479 WMI_TAG_DCC_UPDATE_NDL_RESP_EVENT, 1480 WMI_TAG_DCC_STATS_EVENT, 1481 WMI_TAG_OCB_CHANNEL, 1482 WMI_TAG_OCB_SCHEDULE_ELEMENT, 1483 WMI_TAG_DCC_NDL_STATS_PER_CHANNEL, 1484 WMI_TAG_DCC_NDL_CHAN, 1485 WMI_TAG_QOS_PARAMETER, 1486 WMI_TAG_DCC_NDL_ACTIVE_STATE_CONFIG, 1487 WMI_TAG_ROAM_SCAN_EXTENDED_THRESHOLD_PARAM, 1488 WMI_TAG_ROAM_FILTER, 1489 WMI_TAG_PASSPOINT_CONFIG_CMD, 1490 WMI_TAG_PASSPOINT_EVENT_HDR, 1491 WMI_TAG_EXTSCAN_CONFIGURE_HOTLIST_SSID_MONITOR_CMD, 1492 WMI_TAG_EXTSCAN_HOTLIST_SSID_MATCH_EVENT, 1493 WMI_TAG_VDEV_TSF_TSTAMP_ACTION_CMD, 1494 WMI_TAG_VDEV_TSF_REPORT_EVENT, 1495 WMI_TAG_GET_FW_MEM_DUMP, 1496 WMI_TAG_UPDATE_FW_MEM_DUMP, 1497 WMI_TAG_FW_MEM_DUMP_PARAMS, 1498 WMI_TAG_DEBUG_MESG_FLUSH, 1499 WMI_TAG_DEBUG_MESG_FLUSH_COMPLETE, 1500 WMI_TAG_PEER_SET_RATE_REPORT_CONDITION, 1501 WMI_TAG_ROAM_SUBNET_CHANGE_CONFIG, 1502 WMI_TAG_VDEV_SET_IE_CMD, 1503 WMI_TAG_RSSI_BREACH_MONITOR_CONFIG, 1504 WMI_TAG_RSSI_BREACH_EVENT, 1505 WMI_TAG_WOW_EVENT_INITIAL_WAKEUP, 1506 WMI_TAG_SOC_SET_PCL_CMD, 1507 WMI_TAG_SOC_SET_HW_MODE_CMD, 1508 WMI_TAG_SOC_SET_HW_MODE_RESPONSE_EVENT, 1509 WMI_TAG_SOC_HW_MODE_TRANSITION_EVENT, 1510 WMI_TAG_VDEV_TXRX_STREAMS, 1511 WMI_TAG_SOC_SET_HW_MODE_RESPONSE_VDEV_MAC_ENTRY, 1512 WMI_TAG_SOC_SET_DUAL_MAC_CONFIG_CMD, 1513 WMI_TAG_SOC_SET_DUAL_MAC_CONFIG_RESPONSE_EVENT, 1514 WMI_TAG_WOW_IOAC_SOCK_PATTERN_T, 1515 WMI_TAG_WOW_ENABLE_ICMPV6_NA_FLT_CMD, 1516 WMI_TAG_DIAG_EVENT_LOG_CONFIG, 1517 WMI_TAG_DIAG_EVENT_LOG_SUPPORTED_EVENT_FIXED_PARAMS, 1518 WMI_TAG_PACKET_FILTER_CONFIG, 1519 WMI_TAG_PACKET_FILTER_ENABLE, 1520 WMI_TAG_SAP_SET_BLACKLIST_PARAM_CMD, 1521 WMI_TAG_MGMT_TX_SEND_CMD, 1522 WMI_TAG_MGMT_TX_COMPL_EVENT, 1523 WMI_TAG_SOC_SET_ANTENNA_MODE_CMD, 1524 WMI_TAG_WOW_UDP_SVC_OFLD_CMD, 1525 WMI_TAG_LRO_INFO_CMD, 1526 WMI_TAG_ROAM_EARLYSTOP_RSSI_THRES_PARAM, 1527 WMI_TAG_SERVICE_READY_EXT_EVENT, 1528 WMI_TAG_MAWC_SENSOR_REPORT_IND_CMD, 1529 WMI_TAG_MAWC_ENABLE_SENSOR_EVENT, 1530 WMI_TAG_ROAM_CONFIGURE_MAWC_CMD, 1531 WMI_TAG_NLO_CONFIGURE_MAWC_CMD, 1532 WMI_TAG_EXTSCAN_CONFIGURE_MAWC_CMD, 1533 WMI_TAG_PEER_ASSOC_CONF_EVENT, 1534 WMI_TAG_WOW_HOSTWAKEUP_GPIO_PIN_PATTERN_CONFIG_CMD, 1535 WMI_TAG_AP_PS_EGAP_PARAM_CMD, 1536 WMI_TAG_AP_PS_EGAP_INFO_EVENT, 1537 WMI_TAG_PMF_OFFLOAD_SET_SA_QUERY_CMD, 1538 WMI_TAG_TRANSFER_DATA_TO_FLASH_CMD, 1539 WMI_TAG_TRANSFER_DATA_TO_FLASH_COMPLETE_EVENT, 1540 WMI_TAG_SCPC_EVENT, 1541 WMI_TAG_AP_PS_EGAP_INFO_CHAINMASK_LIST, 1542 WMI_TAG_STA_SMPS_FORCE_MODE_COMPLETE_EVENT, 1543 WMI_TAG_BPF_GET_CAPABILITY_CMD, 1544 WMI_TAG_BPF_CAPABILITY_INFO_EVT, 1545 WMI_TAG_BPF_GET_VDEV_STATS_CMD, 1546 WMI_TAG_BPF_VDEV_STATS_INFO_EVT, 1547 WMI_TAG_BPF_SET_VDEV_INSTRUCTIONS_CMD, 1548 WMI_TAG_BPF_DEL_VDEV_INSTRUCTIONS_CMD, 1549 WMI_TAG_VDEV_DELETE_RESP_EVENT, 1550 WMI_TAG_PEER_DELETE_RESP_EVENT, 1551 WMI_TAG_ROAM_DENSE_THRES_PARAM, 1552 WMI_TAG_ENLO_CANDIDATE_SCORE_PARAM, 1553 WMI_TAG_PEER_UPDATE_WDS_ENTRY_CMD, 1554 WMI_TAG_VDEV_CONFIG_RATEMASK, 1555 WMI_TAG_PDEV_FIPS_CMD, 1556 WMI_TAG_PDEV_SMART_ANT_ENABLE_CMD, 1557 WMI_TAG_PDEV_SMART_ANT_SET_RX_ANTENNA_CMD, 1558 WMI_TAG_PEER_SMART_ANT_SET_TX_ANTENNA_CMD, 1559 WMI_TAG_PEER_SMART_ANT_SET_TRAIN_ANTENNA_CMD, 1560 WMI_TAG_PEER_SMART_ANT_SET_NODE_CONFIG_OPS_CMD, 1561 WMI_TAG_PDEV_SET_ANT_SWITCH_TBL_CMD, 1562 WMI_TAG_PDEV_SET_CTL_TABLE_CMD, 1563 WMI_TAG_PDEV_SET_MIMOGAIN_TABLE_CMD, 1564 WMI_TAG_FWTEST_SET_PARAM_CMD, 1565 WMI_TAG_PEER_ATF_REQUEST, 1566 WMI_TAG_VDEV_ATF_REQUEST, 1567 WMI_TAG_PDEV_GET_ANI_CCK_CONFIG_CMD, 1568 WMI_TAG_PDEV_GET_ANI_OFDM_CONFIG_CMD, 1569 WMI_TAG_INST_RSSI_STATS_RESP, 1570 WMI_TAG_MED_UTIL_REPORT_EVENT, 1571 WMI_TAG_PEER_STA_PS_STATECHANGE_EVENT, 1572 WMI_TAG_WDS_ADDR_EVENT, 1573 WMI_TAG_PEER_RATECODE_LIST_EVENT, 1574 WMI_TAG_PDEV_NFCAL_POWER_ALL_CHANNELS_EVENT, 1575 WMI_TAG_PDEV_TPC_EVENT, 1576 WMI_TAG_ANI_OFDM_EVENT, 1577 WMI_TAG_ANI_CCK_EVENT, 1578 WMI_TAG_PDEV_CHANNEL_HOPPING_EVENT, 1579 WMI_TAG_PDEV_FIPS_EVENT, 1580 WMI_TAG_ATF_PEER_INFO, 1581 WMI_TAG_PDEV_GET_TPC_CMD, 1582 WMI_TAG_VDEV_FILTER_NRP_CONFIG_CMD, 1583 WMI_TAG_QBOOST_CFG_CMD, 1584 WMI_TAG_PDEV_SMART_ANT_GPIO_HANDLE, 1585 WMI_TAG_PEER_SMART_ANT_SET_TX_ANTENNA_SERIES, 1586 WMI_TAG_PEER_SMART_ANT_SET_TRAIN_ANTENNA_PARAM, 1587 WMI_TAG_PDEV_SET_ANT_CTRL_CHAIN, 1588 WMI_TAG_PEER_CCK_OFDM_RATE_INFO, 1589 WMI_TAG_PEER_MCS_RATE_INFO, 1590 WMI_TAG_PDEV_NFCAL_POWER_ALL_CHANNELS_NFDBR, 1591 WMI_TAG_PDEV_NFCAL_POWER_ALL_CHANNELS_NFDBM, 1592 WMI_TAG_PDEV_NFCAL_POWER_ALL_CHANNELS_FREQNUM, 1593 WMI_TAG_MU_REPORT_TOTAL_MU, 1594 WMI_TAG_VDEV_SET_DSCP_TID_MAP_CMD, 1595 WMI_TAG_ROAM_SET_MBO, 1596 WMI_TAG_MIB_STATS_ENABLE_CMD, 1597 WMI_TAG_NAN_DISC_IFACE_CREATED_EVENT, 1598 WMI_TAG_NAN_DISC_IFACE_DELETED_EVENT, 1599 WMI_TAG_NAN_STARTED_CLUSTER_EVENT, 1600 WMI_TAG_NAN_JOINED_CLUSTER_EVENT, 1601 WMI_TAG_NDI_GET_CAP_REQ, 1602 WMI_TAG_NDP_INITIATOR_REQ, 1603 WMI_TAG_NDP_RESPONDER_REQ, 1604 WMI_TAG_NDP_END_REQ, 1605 WMI_TAG_NDI_CAP_RSP_EVENT, 1606 WMI_TAG_NDP_INITIATOR_RSP_EVENT, 1607 WMI_TAG_NDP_RESPONDER_RSP_EVENT, 1608 WMI_TAG_NDP_END_RSP_EVENT, 1609 WMI_TAG_NDP_INDICATION_EVENT, 1610 WMI_TAG_NDP_CONFIRM_EVENT, 1611 WMI_TAG_NDP_END_INDICATION_EVENT, 1612 WMI_TAG_VDEV_SET_QUIET_CMD, 1613 WMI_TAG_PDEV_SET_PCL_CMD, 1614 WMI_TAG_PDEV_SET_HW_MODE_CMD, 1615 WMI_TAG_PDEV_SET_MAC_CONFIG_CMD, 1616 WMI_TAG_PDEV_SET_ANTENNA_MODE_CMD, 1617 WMI_TAG_PDEV_SET_HW_MODE_RESPONSE_EVENT, 1618 WMI_TAG_PDEV_HW_MODE_TRANSITION_EVENT, 1619 WMI_TAG_PDEV_SET_HW_MODE_RESPONSE_VDEV_MAC_ENTRY, 1620 WMI_TAG_PDEV_SET_MAC_CONFIG_RESPONSE_EVENT, 1621 WMI_TAG_COEX_CONFIG_CMD, 1622 WMI_TAG_CONFIG_ENHANCED_MCAST_FILTER, 1623 WMI_TAG_CHAN_AVOID_RPT_ALLOW_CMD, 1624 WMI_TAG_SET_PERIODIC_CHANNEL_STATS_CONFIG, 1625 WMI_TAG_VDEV_SET_CUSTOM_AGGR_SIZE_CMD, 1626 WMI_TAG_PDEV_WAL_POWER_DEBUG_CMD, 1627 WMI_TAG_MAC_PHY_CAPABILITIES, 1628 WMI_TAG_HW_MODE_CAPABILITIES, 1629 WMI_TAG_SOC_MAC_PHY_HW_MODE_CAPS, 1630 WMI_TAG_HAL_REG_CAPABILITIES_EXT, 1631 WMI_TAG_SOC_HAL_REG_CAPABILITIES, 1632 WMI_TAG_VDEV_WISA_CMD, 1633 WMI_TAG_TX_POWER_LEVEL_STATS_EVT, 1634 WMI_TAG_SCAN_ADAPTIVE_DWELL_PARAMETERS_TLV, 1635 WMI_TAG_SCAN_ADAPTIVE_DWELL_CONFIG, 1636 WMI_TAG_WOW_SET_ACTION_WAKE_UP_CMD, 1637 WMI_TAG_NDP_END_RSP_PER_NDI, 1638 WMI_TAG_PEER_BWF_REQUEST, 1639 WMI_TAG_BWF_PEER_INFO, 1640 WMI_TAG_DBGLOG_TIME_STAMP_SYNC_CMD, 1641 WMI_TAG_RMC_SET_LEADER_CMD, 1642 WMI_TAG_RMC_MANUAL_LEADER_EVENT, 1643 WMI_TAG_PER_CHAIN_RSSI_STATS, 1644 WMI_TAG_RSSI_STATS, 1645 WMI_TAG_P2P_LO_START_CMD, 1646 WMI_TAG_P2P_LO_STOP_CMD, 1647 WMI_TAG_P2P_LO_STOPPED_EVENT, 1648 WMI_TAG_REORDER_QUEUE_SETUP_CMD, 1649 WMI_TAG_REORDER_QUEUE_REMOVE_CMD, 1650 WMI_TAG_SET_MULTIPLE_MCAST_FILTER_CMD, 1651 WMI_TAG_MGMT_TX_COMPL_BUNDLE_EVENT, 1652 WMI_TAG_READ_DATA_FROM_FLASH_CMD, 1653 WMI_TAG_READ_DATA_FROM_FLASH_EVENT, 1654 WMI_TAG_PDEV_SET_REORDER_TIMEOUT_VAL_CMD, 1655 WMI_TAG_PEER_SET_RX_BLOCKSIZE_CMD, 1656 WMI_TAG_PDEV_SET_WAKEUP_CONFIG_CMDID, 1657 WMI_TAG_TLV_BUF_LEN_PARAM, 1658 WMI_TAG_SERVICE_AVAILABLE_EVENT, 1659 WMI_TAG_PEER_ANTDIV_INFO_REQ_CMD, 1660 WMI_TAG_PEER_ANTDIV_INFO_EVENT, 1661 WMI_TAG_PEER_ANTDIV_INFO, 1662 WMI_TAG_PDEV_GET_ANTDIV_STATUS_CMD, 1663 WMI_TAG_PDEV_ANTDIV_STATUS_EVENT, 1664 WMI_TAG_MNT_FILTER_CMD, 1665 WMI_TAG_GET_CHIP_POWER_STATS_CMD, 1666 WMI_TAG_PDEV_CHIP_POWER_STATS_EVENT, 1667 WMI_TAG_COEX_GET_ANTENNA_ISOLATION_CMD, 1668 WMI_TAG_COEX_REPORT_ISOLATION_EVENT, 1669 WMI_TAG_CHAN_CCA_STATS, 1670 WMI_TAG_PEER_SIGNAL_STATS, 1671 WMI_TAG_TX_STATS, 1672 WMI_TAG_PEER_AC_TX_STATS, 1673 WMI_TAG_RX_STATS, 1674 WMI_TAG_PEER_AC_RX_STATS, 1675 WMI_TAG_REPORT_STATS_EVENT, 1676 WMI_TAG_CHAN_CCA_STATS_THRESH, 1677 WMI_TAG_PEER_SIGNAL_STATS_THRESH, 1678 WMI_TAG_TX_STATS_THRESH, 1679 WMI_TAG_RX_STATS_THRESH, 1680 WMI_TAG_PDEV_SET_STATS_THRESHOLD_CMD, 1681 WMI_TAG_REQUEST_WLAN_STATS_CMD, 1682 WMI_TAG_RX_AGGR_FAILURE_EVENT, 1683 WMI_TAG_RX_AGGR_FAILURE_INFO, 1684 WMI_TAG_VDEV_ENCRYPT_DECRYPT_DATA_REQ_CMD, 1685 WMI_TAG_VDEV_ENCRYPT_DECRYPT_DATA_RESP_EVENT, 1686 WMI_TAG_PDEV_BAND_TO_MAC, 1687 WMI_TAG_TBTT_OFFSET_INFO, 1688 WMI_TAG_TBTT_OFFSET_EXT_EVENT, 1689 WMI_TAG_SAR_LIMITS_CMD, 1690 WMI_TAG_SAR_LIMIT_CMD_ROW, 1691 WMI_TAG_PDEV_DFS_PHYERR_OFFLOAD_ENABLE_CMD, 1692 WMI_TAG_PDEV_DFS_PHYERR_OFFLOAD_DISABLE_CMD, 1693 WMI_TAG_VDEV_ADFS_CH_CFG_CMD, 1694 WMI_TAG_VDEV_ADFS_OCAC_ABORT_CMD, 1695 WMI_TAG_PDEV_DFS_RADAR_DETECTION_EVENT, 1696 WMI_TAG_VDEV_ADFS_OCAC_COMPLETE_EVENT, 1697 WMI_TAG_VDEV_DFS_CAC_COMPLETE_EVENT, 1698 WMI_TAG_VENDOR_OUI, 1699 WMI_TAG_REQUEST_RCPI_CMD, 1700 WMI_TAG_UPDATE_RCPI_EVENT, 1701 WMI_TAG_REQUEST_PEER_STATS_INFO_CMD, 1702 WMI_TAG_PEER_STATS_INFO, 1703 WMI_TAG_PEER_STATS_INFO_EVENT, 1704 WMI_TAG_PKGID_EVENT, 1705 WMI_TAG_CONNECTED_NLO_RSSI_PARAMS, 1706 WMI_TAG_SET_CURRENT_COUNTRY_CMD, 1707 WMI_TAG_REGULATORY_RULE_STRUCT, 1708 WMI_TAG_REG_CHAN_LIST_CC_EVENT, 1709 WMI_TAG_11D_SCAN_START_CMD, 1710 WMI_TAG_11D_SCAN_STOP_CMD, 1711 WMI_TAG_11D_NEW_COUNTRY_EVENT, 1712 WMI_TAG_REQUEST_RADIO_CHAN_STATS_CMD, 1713 WMI_TAG_RADIO_CHAN_STATS, 1714 WMI_TAG_RADIO_CHAN_STATS_EVENT, 1715 WMI_TAG_ROAM_PER_CONFIG, 1716 WMI_TAG_VDEV_ADD_MAC_ADDR_TO_RX_FILTER_CMD, 1717 WMI_TAG_VDEV_ADD_MAC_ADDR_TO_RX_FILTER_STATUS_EVENT, 1718 WMI_TAG_BPF_SET_VDEV_ACTIVE_MODE_CMD, 1719 WMI_TAG_HW_DATA_FILTER_CMD, 1720 WMI_TAG_CONNECTED_NLO_BSS_BAND_RSSI_PREF, 1721 WMI_TAG_PEER_OPER_MODE_CHANGE_EVENT, 1722 WMI_TAG_CHIP_POWER_SAVE_FAILURE_DETECTED, 1723 WMI_TAG_PDEV_MULTIPLE_VDEV_RESTART_REQUEST_CMD, 1724 WMI_TAG_PDEV_CSA_SWITCH_COUNT_STATUS_EVENT, 1725 WMI_TAG_PDEV_UPDATE_PKT_ROUTING_CMD, 1726 WMI_TAG_PDEV_CHECK_CAL_VERSION_CMD, 1727 WMI_TAG_PDEV_CHECK_CAL_VERSION_EVENT, 1728 WMI_TAG_PDEV_SET_DIVERSITY_GAIN_CMD, 1729 WMI_TAG_MAC_PHY_CHAINMASK_COMBO, 1730 WMI_TAG_MAC_PHY_CHAINMASK_CAPABILITY, 1731 WMI_TAG_VDEV_SET_ARP_STATS_CMD, 1732 WMI_TAG_VDEV_GET_ARP_STATS_CMD, 1733 WMI_TAG_VDEV_GET_ARP_STATS_EVENT, 1734 WMI_TAG_IFACE_OFFLOAD_STATS, 1735 WMI_TAG_REQUEST_STATS_CMD_SUB_STRUCT_PARAM, 1736 WMI_TAG_RSSI_CTL_EXT, 1737 WMI_TAG_SINGLE_PHYERR_EXT_RX_HDR, 1738 WMI_TAG_COEX_BT_ACTIVITY_EVENT, 1739 WMI_TAG_VDEV_GET_TX_POWER_CMD, 1740 WMI_TAG_VDEV_TX_POWER_EVENT, 1741 WMI_TAG_OFFCHAN_DATA_TX_COMPL_EVENT, 1742 WMI_TAG_OFFCHAN_DATA_TX_SEND_CMD, 1743 WMI_TAG_TX_SEND_PARAMS, 1744 WMI_TAG_HE_RATE_SET, 1745 WMI_TAG_CONGESTION_STATS, 1746 WMI_TAG_SET_INIT_COUNTRY_CMD, 1747 WMI_TAG_SCAN_DBS_DUTY_CYCLE, 1748 WMI_TAG_SCAN_DBS_DUTY_CYCLE_PARAM_TLV, 1749 WMI_TAG_PDEV_DIV_GET_RSSI_ANTID, 1750 WMI_TAG_THERM_THROT_CONFIG_REQUEST, 1751 WMI_TAG_THERM_THROT_LEVEL_CONFIG_INFO, 1752 WMI_TAG_THERM_THROT_STATS_EVENT, 1753 WMI_TAG_THERM_THROT_LEVEL_STATS_INFO, 1754 WMI_TAG_PDEV_DIV_RSSI_ANTID_EVENT, 1755 WMI_TAG_OEM_DMA_RING_CAPABILITIES, 1756 WMI_TAG_OEM_DMA_RING_CFG_REQ, 1757 WMI_TAG_OEM_DMA_RING_CFG_RSP, 1758 WMI_TAG_OEM_INDIRECT_DATA, 1759 WMI_TAG_OEM_DMA_BUF_RELEASE, 1760 WMI_TAG_OEM_DMA_BUF_RELEASE_ENTRY, 1761 WMI_TAG_PDEV_BSS_CHAN_INFO_REQUEST, 1762 WMI_TAG_PDEV_BSS_CHAN_INFO_EVENT, 1763 WMI_TAG_ROAM_LCA_DISALLOW_CONFIG, 1764 WMI_TAG_VDEV_LIMIT_OFFCHAN_CMD, 1765 WMI_TAG_ROAM_RSSI_REJECTION_OCE_CONFIG, 1766 WMI_TAG_UNIT_TEST_EVENT, 1767 WMI_TAG_ROAM_FILS_OFFLOAD, 1768 WMI_TAG_PDEV_UPDATE_PMK_CACHE_CMD, 1769 WMI_TAG_PMK_CACHE, 1770 WMI_TAG_PDEV_UPDATE_FILS_HLP_PKT_CMD, 1771 WMI_TAG_ROAM_FILS_SYNCH, 1772 WMI_TAG_GTK_OFFLOAD_EXTENDED, 1773 WMI_TAG_ROAM_BG_SCAN_ROAMING, 1774 WMI_TAG_OIC_PING_OFFLOAD_PARAMS_CMD, 1775 WMI_TAG_OIC_PING_OFFLOAD_SET_ENABLE_CMD, 1776 WMI_TAG_OIC_PING_HANDOFF_EVENT, 1777 WMI_TAG_DHCP_LEASE_RENEW_OFFLOAD_CMD, 1778 WMI_TAG_DHCP_LEASE_RENEW_EVENT, 1779 WMI_TAG_BTM_CONFIG, 1780 WMI_TAG_DEBUG_MESG_FW_DATA_STALL, 1781 WMI_TAG_WLM_CONFIG_CMD, 1782 WMI_TAG_PDEV_UPDATE_CTLTABLE_REQUEST, 1783 WMI_TAG_PDEV_UPDATE_CTLTABLE_EVENT, 1784 WMI_TAG_ROAM_CND_SCORING_PARAM, 1785 WMI_TAG_PDEV_CONFIG_VENDOR_OUI_ACTION, 1786 WMI_TAG_VENDOR_OUI_EXT, 1787 WMI_TAG_ROAM_SYNCH_FRAME_EVENT, 1788 WMI_TAG_FD_SEND_FROM_HOST_CMD, 1789 WMI_TAG_ENABLE_FILS_CMD, 1790 WMI_TAG_HOST_SWFDA_EVENT, 1791 WMI_TAG_BCN_OFFLOAD_CTRL_CMD, 1792 WMI_TAG_PDEV_SET_AC_TX_QUEUE_OPTIMIZED_CMD, 1793 WMI_TAG_STATS_PERIOD, 1794 WMI_TAG_NDL_SCHEDULE_UPDATE, 1795 WMI_TAG_PEER_TID_MSDUQ_QDEPTH_THRESH_UPDATE_CMD, 1796 WMI_TAG_MSDUQ_QDEPTH_THRESH_UPDATE, 1797 WMI_TAG_PDEV_SET_RX_FILTER_PROMISCUOUS_CMD, 1798 WMI_TAG_SAR2_RESULT_EVENT, 1799 WMI_TAG_SAR_CAPABILITIES, 1800 WMI_TAG_SAP_OBSS_DETECTION_CFG_CMD, 1801 WMI_TAG_SAP_OBSS_DETECTION_INFO_EVT, 1802 WMI_TAG_DMA_RING_CAPABILITIES, 1803 WMI_TAG_DMA_RING_CFG_REQ, 1804 WMI_TAG_DMA_RING_CFG_RSP, 1805 WMI_TAG_DMA_BUF_RELEASE, 1806 WMI_TAG_DMA_BUF_RELEASE_ENTRY, 1807 WMI_TAG_SAR_GET_LIMITS_CMD, 1808 WMI_TAG_SAR_GET_LIMITS_EVENT, 1809 WMI_TAG_SAR_GET_LIMITS_EVENT_ROW, 1810 WMI_TAG_OFFLOAD_11K_REPORT, 1811 WMI_TAG_INVOKE_NEIGHBOR_REPORT, 1812 WMI_TAG_NEIGHBOR_REPORT_OFFLOAD, 1813 WMI_TAG_VDEV_SET_CONNECTIVITY_CHECK_STATS, 1814 WMI_TAG_VDEV_GET_CONNECTIVITY_CHECK_STATS, 1815 WMI_TAG_BPF_SET_VDEV_ENABLE_CMD, 1816 WMI_TAG_BPF_SET_VDEV_WORK_MEMORY_CMD, 1817 WMI_TAG_BPF_GET_VDEV_WORK_MEMORY_CMD, 1818 WMI_TAG_BPF_GET_VDEV_WORK_MEMORY_RESP_EVT, 1819 WMI_TAG_PDEV_GET_NFCAL_POWER, 1820 WMI_TAG_BSS_COLOR_CHANGE_ENABLE, 1821 WMI_TAG_OBSS_COLOR_COLLISION_DET_CONFIG, 1822 WMI_TAG_OBSS_COLOR_COLLISION_EVT, 1823 WMI_TAG_RUNTIME_DPD_RECAL_CMD, 1824 WMI_TAG_TWT_ENABLE_CMD, 1825 WMI_TAG_TWT_DISABLE_CMD, 1826 WMI_TAG_TWT_ADD_DIALOG_CMD, 1827 WMI_TAG_TWT_DEL_DIALOG_CMD, 1828 WMI_TAG_TWT_PAUSE_DIALOG_CMD, 1829 WMI_TAG_TWT_RESUME_DIALOG_CMD, 1830 WMI_TAG_TWT_ENABLE_COMPLETE_EVENT, 1831 WMI_TAG_TWT_DISABLE_COMPLETE_EVENT, 1832 WMI_TAG_TWT_ADD_DIALOG_COMPLETE_EVENT, 1833 WMI_TAG_TWT_DEL_DIALOG_COMPLETE_EVENT, 1834 WMI_TAG_TWT_PAUSE_DIALOG_COMPLETE_EVENT, 1835 WMI_TAG_TWT_RESUME_DIALOG_COMPLETE_EVENT, 1836 WMI_TAG_REQUEST_ROAM_SCAN_STATS_CMD, 1837 WMI_TAG_ROAM_SCAN_STATS_EVENT, 1838 WMI_TAG_PEER_TID_CONFIGURATIONS_CMD, 1839 WMI_TAG_VDEV_SET_CUSTOM_SW_RETRY_TH_CMD, 1840 WMI_TAG_GET_TPC_POWER_CMD, 1841 WMI_TAG_GET_TPC_POWER_EVENT, 1842 WMI_TAG_DMA_BUF_RELEASE_SPECTRAL_META_DATA, 1843 WMI_TAG_MOTION_DET_CONFIG_PARAMS_CMD, 1844 WMI_TAG_MOTION_DET_BASE_LINE_CONFIG_PARAMS_CMD, 1845 WMI_TAG_MOTION_DET_START_STOP_CMD, 1846 WMI_TAG_MOTION_DET_BASE_LINE_START_STOP_CMD, 1847 WMI_TAG_MOTION_DET_EVENT, 1848 WMI_TAG_MOTION_DET_BASE_LINE_EVENT, 1849 WMI_TAG_NDP_TRANSPORT_IP, 1850 WMI_TAG_OBSS_SPATIAL_REUSE_SET_CMD, 1851 WMI_TAG_ESP_ESTIMATE_EVENT, 1852 WMI_TAG_NAN_HOST_CONFIG, 1853 WMI_TAG_SPECTRAL_BIN_SCALING_PARAMS, 1854 WMI_TAG_PEER_CFR_CAPTURE_CMD, 1855 WMI_TAG_PEER_CHAN_WIDTH_SWITCH_CMD, 1856 WMI_TAG_CHAN_WIDTH_PEER_LIST, 1857 WMI_TAG_OBSS_SPATIAL_REUSE_SET_DEF_OBSS_THRESH_CMD, 1858 WMI_TAG_PDEV_HE_TB_ACTION_FRM_CMD, 1859 WMI_TAG_PEER_EXTD2_STATS, 1860 WMI_TAG_HPCS_PULSE_START_CMD, 1861 WMI_TAG_PDEV_CTL_FAILSAFE_CHECK_EVENT, 1862 WMI_TAG_VDEV_CHAINMASK_CONFIG_CMD, 1863 WMI_TAG_VDEV_BCN_OFFLOAD_QUIET_CONFIG_CMD, 1864 WMI_TAG_NAN_EVENT_INFO, 1865 WMI_TAG_NDP_CHANNEL_INFO, 1866 WMI_TAG_NDP_CMD, 1867 WMI_TAG_NDP_EVENT, 1868 WMI_TAG_PDEV_PEER_PKTLOG_FILTER_CMD = 0x301, 1869 WMI_TAG_PDEV_PEER_PKTLOG_FILTER_INFO, 1870 WMI_TAG_FILS_DISCOVERY_TMPL_CMD = 0x344, 1871 WMI_TAG_PDEV_SRG_BSS_COLOR_BITMAP_CMD = 0x37b, 1872 WMI_TAG_PDEV_SRG_PARTIAL_BSSID_BITMAP_CMD, 1873 WMI_TAG_PDEV_SRG_OBSS_COLOR_ENABLE_BITMAP_CMD = 0x381, 1874 WMI_TAG_PDEV_SRG_OBSS_BSSID_ENABLE_BITMAP_CMD, 1875 WMI_TAG_PDEV_NON_SRG_OBSS_COLOR_ENABLE_BITMAP_CMD, 1876 WMI_TAG_PDEV_NON_SRG_OBSS_BSSID_ENABLE_BITMAP_CMD, 1877 WMI_TAG_REGULATORY_RULE_EXT_STRUCT = 0x3A9, 1878 WMI_TAG_REG_CHAN_LIST_CC_EXT_EVENT, 1879 WMI_TAG_PDEV_SET_BIOS_SAR_TABLE_CMD = 0x3D8, 1880 WMI_TAG_PDEV_SET_BIOS_GEO_TABLE_CMD, 1881 WMI_TAG_MAX 1882 }; 1883 1884 enum wmi_tlv_service { 1885 WMI_TLV_SERVICE_BEACON_OFFLOAD = 0, 1886 WMI_TLV_SERVICE_SCAN_OFFLOAD = 1, 1887 WMI_TLV_SERVICE_ROAM_SCAN_OFFLOAD = 2, 1888 WMI_TLV_SERVICE_BCN_MISS_OFFLOAD = 3, 1889 WMI_TLV_SERVICE_STA_PWRSAVE = 4, 1890 WMI_TLV_SERVICE_STA_ADVANCED_PWRSAVE = 5, 1891 WMI_TLV_SERVICE_AP_UAPSD = 6, 1892 WMI_TLV_SERVICE_AP_DFS = 7, 1893 WMI_TLV_SERVICE_11AC = 8, 1894 WMI_TLV_SERVICE_BLOCKACK = 9, 1895 WMI_TLV_SERVICE_PHYERR = 10, 1896 WMI_TLV_SERVICE_BCN_FILTER = 11, 1897 WMI_TLV_SERVICE_RTT = 12, 1898 WMI_TLV_SERVICE_WOW = 13, 1899 WMI_TLV_SERVICE_RATECTRL_CACHE = 14, 1900 WMI_TLV_SERVICE_IRAM_TIDS = 15, 1901 WMI_TLV_SERVICE_ARPNS_OFFLOAD = 16, 1902 WMI_TLV_SERVICE_NLO = 17, 1903 WMI_TLV_SERVICE_GTK_OFFLOAD = 18, 1904 WMI_TLV_SERVICE_SCAN_SCH = 19, 1905 WMI_TLV_SERVICE_CSA_OFFLOAD = 20, 1906 WMI_TLV_SERVICE_CHATTER = 21, 1907 WMI_TLV_SERVICE_COEX_FREQAVOID = 22, 1908 WMI_TLV_SERVICE_PACKET_POWER_SAVE = 23, 1909 WMI_TLV_SERVICE_FORCE_FW_HANG = 24, 1910 WMI_TLV_SERVICE_GPIO = 25, 1911 WMI_TLV_SERVICE_STA_DTIM_PS_MODULATED_DTIM = 26, 1912 WMI_STA_UAPSD_BASIC_AUTO_TRIG = 27, 1913 WMI_STA_UAPSD_VAR_AUTO_TRIG = 28, 1914 WMI_TLV_SERVICE_STA_KEEP_ALIVE = 29, 1915 WMI_TLV_SERVICE_TX_ENCAP = 30, 1916 WMI_TLV_SERVICE_AP_PS_DETECT_OUT_OF_SYNC = 31, 1917 WMI_TLV_SERVICE_EARLY_RX = 32, 1918 WMI_TLV_SERVICE_STA_SMPS = 33, 1919 WMI_TLV_SERVICE_FWTEST = 34, 1920 WMI_TLV_SERVICE_STA_WMMAC = 35, 1921 WMI_TLV_SERVICE_TDLS = 36, 1922 WMI_TLV_SERVICE_BURST = 37, 1923 WMI_TLV_SERVICE_MCC_BCN_INTERVAL_CHANGE = 38, 1924 WMI_TLV_SERVICE_ADAPTIVE_OCS = 39, 1925 WMI_TLV_SERVICE_BA_SSN_SUPPORT = 40, 1926 WMI_TLV_SERVICE_FILTER_IPSEC_NATKEEPALIVE = 41, 1927 WMI_TLV_SERVICE_WLAN_HB = 42, 1928 WMI_TLV_SERVICE_LTE_ANT_SHARE_SUPPORT = 43, 1929 WMI_TLV_SERVICE_BATCH_SCAN = 44, 1930 WMI_TLV_SERVICE_QPOWER = 45, 1931 WMI_TLV_SERVICE_PLMREQ = 46, 1932 WMI_TLV_SERVICE_THERMAL_MGMT = 47, 1933 WMI_TLV_SERVICE_RMC = 48, 1934 WMI_TLV_SERVICE_MHF_OFFLOAD = 49, 1935 WMI_TLV_SERVICE_COEX_SAR = 50, 1936 WMI_TLV_SERVICE_BCN_TXRATE_OVERRIDE = 51, 1937 WMI_TLV_SERVICE_NAN = 52, 1938 WMI_TLV_SERVICE_L1SS_STAT = 53, 1939 WMI_TLV_SERVICE_ESTIMATE_LINKSPEED = 54, 1940 WMI_TLV_SERVICE_OBSS_SCAN = 55, 1941 WMI_TLV_SERVICE_TDLS_OFFCHAN = 56, 1942 WMI_TLV_SERVICE_TDLS_UAPSD_BUFFER_STA = 57, 1943 WMI_TLV_SERVICE_TDLS_UAPSD_SLEEP_STA = 58, 1944 WMI_TLV_SERVICE_IBSS_PWRSAVE = 59, 1945 WMI_TLV_SERVICE_LPASS = 60, 1946 WMI_TLV_SERVICE_EXTSCAN = 61, 1947 WMI_TLV_SERVICE_D0WOW = 62, 1948 WMI_TLV_SERVICE_HSOFFLOAD = 63, 1949 WMI_TLV_SERVICE_ROAM_HO_OFFLOAD = 64, 1950 WMI_TLV_SERVICE_RX_FULL_REORDER = 65, 1951 WMI_TLV_SERVICE_DHCP_OFFLOAD = 66, 1952 WMI_TLV_SERVICE_STA_RX_IPA_OFFLOAD_SUPPORT = 67, 1953 WMI_TLV_SERVICE_MDNS_OFFLOAD = 68, 1954 WMI_TLV_SERVICE_SAP_AUTH_OFFLOAD = 69, 1955 WMI_TLV_SERVICE_DUAL_BAND_SIMULTANEOUS_SUPPORT = 70, 1956 WMI_TLV_SERVICE_OCB = 71, 1957 WMI_TLV_SERVICE_AP_ARPNS_OFFLOAD = 72, 1958 WMI_TLV_SERVICE_PER_BAND_CHAINMASK_SUPPORT = 73, 1959 WMI_TLV_SERVICE_PACKET_FILTER_OFFLOAD = 74, 1960 WMI_TLV_SERVICE_MGMT_TX_HTT = 75, 1961 WMI_TLV_SERVICE_MGMT_TX_WMI = 76, 1962 WMI_TLV_SERVICE_EXT_MSG = 77, 1963 WMI_TLV_SERVICE_MAWC = 78, 1964 WMI_TLV_SERVICE_PEER_ASSOC_CONF = 79, 1965 WMI_TLV_SERVICE_EGAP = 80, 1966 WMI_TLV_SERVICE_STA_PMF_OFFLOAD = 81, 1967 WMI_TLV_SERVICE_UNIFIED_WOW_CAPABILITY = 82, 1968 WMI_TLV_SERVICE_ENHANCED_PROXY_STA = 83, 1969 WMI_TLV_SERVICE_ATF = 84, 1970 WMI_TLV_SERVICE_COEX_GPIO = 85, 1971 WMI_TLV_SERVICE_AUX_SPECTRAL_INTF = 86, 1972 WMI_TLV_SERVICE_AUX_CHAN_LOAD_INTF = 87, 1973 WMI_TLV_SERVICE_BSS_CHANNEL_INFO_64 = 88, 1974 WMI_TLV_SERVICE_ENTERPRISE_MESH = 89, 1975 WMI_TLV_SERVICE_RESTRT_CHNL_SUPPORT = 90, 1976 WMI_TLV_SERVICE_BPF_OFFLOAD = 91, 1977 WMI_TLV_SERVICE_SYNC_DELETE_CMDS = 92, 1978 WMI_TLV_SERVICE_SMART_ANTENNA_SW_SUPPORT = 93, 1979 WMI_TLV_SERVICE_SMART_ANTENNA_HW_SUPPORT = 94, 1980 WMI_TLV_SERVICE_RATECTRL_LIMIT_MAX_MIN_RATES = 95, 1981 WMI_TLV_SERVICE_NAN_DATA = 96, 1982 WMI_TLV_SERVICE_NAN_RTT = 97, 1983 WMI_TLV_SERVICE_11AX = 98, 1984 WMI_TLV_SERVICE_DEPRECATED_REPLACE = 99, 1985 WMI_TLV_SERVICE_TDLS_CONN_TRACKER_IN_HOST_MODE = 100, 1986 WMI_TLV_SERVICE_ENHANCED_MCAST_FILTER = 101, 1987 WMI_TLV_SERVICE_PERIODIC_CHAN_STAT_SUPPORT = 102, 1988 WMI_TLV_SERVICE_MESH_11S = 103, 1989 WMI_TLV_SERVICE_HALF_RATE_QUARTER_RATE_SUPPORT = 104, 1990 WMI_TLV_SERVICE_VDEV_RX_FILTER = 105, 1991 WMI_TLV_SERVICE_P2P_LISTEN_OFFLOAD_SUPPORT = 106, 1992 WMI_TLV_SERVICE_MARK_FIRST_WAKEUP_PACKET = 107, 1993 WMI_TLV_SERVICE_MULTIPLE_MCAST_FILTER_SET = 108, 1994 WMI_TLV_SERVICE_HOST_MANAGED_RX_REORDER = 109, 1995 WMI_TLV_SERVICE_FLASH_RDWR_SUPPORT = 110, 1996 WMI_TLV_SERVICE_WLAN_STATS_REPORT = 111, 1997 WMI_TLV_SERVICE_TX_MSDU_ID_NEW_PARTITION_SUPPORT = 112, 1998 WMI_TLV_SERVICE_DFS_PHYERR_OFFLOAD = 113, 1999 WMI_TLV_SERVICE_RCPI_SUPPORT = 114, 2000 WMI_TLV_SERVICE_FW_MEM_DUMP_SUPPORT = 115, 2001 WMI_TLV_SERVICE_PEER_STATS_INFO = 116, 2002 WMI_TLV_SERVICE_REGULATORY_DB = 117, 2003 WMI_TLV_SERVICE_11D_OFFLOAD = 118, 2004 WMI_TLV_SERVICE_HW_DATA_FILTERING = 119, 2005 WMI_TLV_SERVICE_MULTIPLE_VDEV_RESTART = 120, 2006 WMI_TLV_SERVICE_PKT_ROUTING = 121, 2007 WMI_TLV_SERVICE_CHECK_CAL_VERSION = 122, 2008 WMI_TLV_SERVICE_OFFCHAN_TX_WMI = 123, 2009 WMI_TLV_SERVICE_8SS_TX_BFEE = 124, 2010 WMI_TLV_SERVICE_EXTENDED_NSS_SUPPORT = 125, 2011 WMI_TLV_SERVICE_ACK_TIMEOUT = 126, 2012 WMI_TLV_SERVICE_PDEV_BSS_CHANNEL_INFO_64 = 127, 2013 2014 /* The first 128 bits */ 2015 WMI_MAX_SERVICE = 128, 2016 2017 WMI_TLV_SERVICE_CHAN_LOAD_INFO = 128, 2018 WMI_TLV_SERVICE_TX_PPDU_INFO_STATS_SUPPORT = 129, 2019 WMI_TLV_SERVICE_VDEV_LIMIT_OFFCHAN_SUPPORT = 130, 2020 WMI_TLV_SERVICE_FILS_SUPPORT = 131, 2021 WMI_TLV_SERVICE_WLAN_OIC_PING_OFFLOAD = 132, 2022 WMI_TLV_SERVICE_WLAN_DHCP_RENEW = 133, 2023 WMI_TLV_SERVICE_MAWC_SUPPORT = 134, 2024 WMI_TLV_SERVICE_VDEV_LATENCY_CONFIG = 135, 2025 WMI_TLV_SERVICE_PDEV_UPDATE_CTLTABLE_SUPPORT = 136, 2026 WMI_TLV_SERVICE_PKTLOG_SUPPORT_OVER_HTT = 137, 2027 WMI_TLV_SERVICE_VDEV_MULTI_GROUP_KEY_SUPPORT = 138, 2028 WMI_TLV_SERVICE_SCAN_PHYMODE_SUPPORT = 139, 2029 WMI_TLV_SERVICE_THERM_THROT = 140, 2030 WMI_TLV_SERVICE_BCN_OFFLOAD_START_STOP_SUPPORT = 141, 2031 WMI_TLV_SERVICE_WOW_WAKEUP_BY_TIMER_PATTERN = 142, 2032 WMI_TLV_SERVICE_PEER_MAP_UNMAP_V2_SUPPORT = 143, 2033 WMI_TLV_SERVICE_OFFCHAN_DATA_TID_SUPPORT = 144, 2034 WMI_TLV_SERVICE_RX_PROMISC_ENABLE_SUPPORT = 145, 2035 WMI_TLV_SERVICE_SUPPORT_DIRECT_DMA = 146, 2036 WMI_TLV_SERVICE_AP_OBSS_DETECTION_OFFLOAD = 147, 2037 WMI_TLV_SERVICE_11K_NEIGHBOUR_REPORT_SUPPORT = 148, 2038 WMI_TLV_SERVICE_LISTEN_INTERVAL_OFFLOAD_SUPPORT = 149, 2039 WMI_TLV_SERVICE_BSS_COLOR_OFFLOAD = 150, 2040 WMI_TLV_SERVICE_RUNTIME_DPD_RECAL = 151, 2041 WMI_TLV_SERVICE_STA_TWT = 152, 2042 WMI_TLV_SERVICE_AP_TWT = 153, 2043 WMI_TLV_SERVICE_GMAC_OFFLOAD_SUPPORT = 154, 2044 WMI_TLV_SERVICE_SPOOF_MAC_SUPPORT = 155, 2045 WMI_TLV_SERVICE_PEER_TID_CONFIGS_SUPPORT = 156, 2046 WMI_TLV_SERVICE_VDEV_SWRETRY_PER_AC_CONFIG_SUPPORT = 157, 2047 WMI_TLV_SERVICE_DUAL_BEACON_ON_SINGLE_MAC_SCC_SUPPORT = 158, 2048 WMI_TLV_SERVICE_DUAL_BEACON_ON_SINGLE_MAC_MCC_SUPPORT = 159, 2049 WMI_TLV_SERVICE_MOTION_DET = 160, 2050 WMI_TLV_SERVICE_INFRA_MBSSID = 161, 2051 WMI_TLV_SERVICE_OBSS_SPATIAL_REUSE = 162, 2052 WMI_TLV_SERVICE_VDEV_DIFFERENT_BEACON_INTERVAL_SUPPORT = 163, 2053 WMI_TLV_SERVICE_NAN_DBS_SUPPORT = 164, 2054 WMI_TLV_SERVICE_NDI_DBS_SUPPORT = 165, 2055 WMI_TLV_SERVICE_NAN_SAP_SUPPORT = 166, 2056 WMI_TLV_SERVICE_NDI_SAP_SUPPORT = 167, 2057 WMI_TLV_SERVICE_CFR_CAPTURE_SUPPORT = 168, 2058 WMI_TLV_SERVICE_CFR_CAPTURE_IND_MSG_TYPE_1 = 169, 2059 WMI_TLV_SERVICE_ESP_SUPPORT = 170, 2060 WMI_TLV_SERVICE_PEER_CHWIDTH_CHANGE = 171, 2061 WMI_TLV_SERVICE_WLAN_HPCS_PULSE = 172, 2062 WMI_TLV_SERVICE_PER_VDEV_CHAINMASK_CONFIG_SUPPORT = 173, 2063 WMI_TLV_SERVICE_TX_DATA_MGMT_ACK_RSSI = 174, 2064 WMI_TLV_SERVICE_NAN_DISABLE_SUPPORT = 175, 2065 WMI_TLV_SERVICE_HTT_H2T_NO_HTC_HDR_LEN_IN_MSG_LEN = 176, 2066 WMI_TLV_SERVICE_COEX_SUPPORT_UNEQUAL_ISOLATION = 177, 2067 WMI_TLV_SERVICE_HW_DB2DBM_CONVERSION_SUPPORT = 178, 2068 WMI_TLV_SERVICE_SUPPORT_EXTEND_ADDRESS = 179, 2069 WMI_TLV_SERVICE_BEACON_RECEPTION_STATS = 180, 2070 WMI_TLV_SERVICE_FETCH_TX_PN = 181, 2071 WMI_TLV_SERVICE_PEER_UNMAP_RESPONSE_SUPPORT = 182, 2072 WMI_TLV_SERVICE_TX_PER_PEER_AMPDU_SIZE = 183, 2073 WMI_TLV_SERVICE_BSS_COLOR_SWITCH_COUNT = 184, 2074 WMI_TLV_SERVICE_HTT_PEER_STATS_SUPPORT = 185, 2075 WMI_TLV_SERVICE_UL_RU26_ALLOWED = 186, 2076 WMI_TLV_SERVICE_GET_MWS_COEX_STATE = 187, 2077 WMI_TLV_SERVICE_GET_MWS_DPWB_STATE = 188, 2078 WMI_TLV_SERVICE_GET_MWS_TDM_STATE = 189, 2079 WMI_TLV_SERVICE_GET_MWS_IDRX_STATE = 190, 2080 WMI_TLV_SERVICE_GET_MWS_ANTENNA_SHARING_STATE = 191, 2081 WMI_TLV_SERVICE_ENHANCED_TPC_CONFIG_EVENT = 192, 2082 WMI_TLV_SERVICE_WLM_STATS_REQUEST = 193, 2083 WMI_TLV_SERVICE_EXT_PEER_TID_CONFIGS_SUPPORT = 194, 2084 WMI_TLV_SERVICE_WPA3_FT_SAE_SUPPORT = 195, 2085 WMI_TLV_SERVICE_WPA3_FT_SUITE_B_SUPPORT = 196, 2086 WMI_TLV_SERVICE_VOW_ENABLE = 197, 2087 WMI_TLV_SERVICE_CFR_CAPTURE_IND_EVT_TYPE_1 = 198, 2088 WMI_TLV_SERVICE_BROADCAST_TWT = 199, 2089 WMI_TLV_SERVICE_RAP_DETECTION_SUPPORT = 200, 2090 WMI_TLV_SERVICE_PS_TDCC = 201, 2091 WMI_TLV_SERVICE_THREE_WAY_COEX_CONFIG_LEGACY = 202, 2092 WMI_TLV_SERVICE_THREE_WAY_COEX_CONFIG_OVERRIDE = 203, 2093 WMI_TLV_SERVICE_TX_PWR_PER_PEER = 204, 2094 WMI_TLV_SERVICE_STA_PLUS_STA_SUPPORT = 205, 2095 WMI_TLV_SERVICE_WPA3_FT_FILS = 206, 2096 WMI_TLV_SERVICE_ADAPTIVE_11R_ROAM = 207, 2097 WMI_TLV_SERVICE_CHAN_RF_CHARACTERIZATION_INFO = 208, 2098 WMI_TLV_SERVICE_FW_IFACE_COMBINATION_SUPPORT = 209, 2099 WMI_TLV_SERVICE_TX_COMPL_TSF64 = 210, 2100 WMI_TLV_SERVICE_DSM_ROAM_FILTER = 211, 2101 WMI_TLV_SERVICE_PACKET_CAPTURE_SUPPORT = 212, 2102 WMI_TLV_SERVICE_PER_PEER_HTT_STATS_RESET = 213, 2103 WMI_TLV_SERVICE_FREQINFO_IN_METADATA = 219, 2104 WMI_TLV_SERVICE_EXT2_MSG = 220, 2105 WMI_TLV_SERVICE_PEER_POWER_SAVE_DURATION_SUPPORT = 246, 2106 WMI_TLV_SERVICE_SRG_SRP_SPATIAL_REUSE_SUPPORT = 249, 2107 WMI_TLV_SERVICE_MBSS_PARAM_IN_VDEV_START_SUPPORT = 253, 2108 WMI_TLV_SERVICE_PASSIVE_SCAN_START_TIME_ENHANCE = 263, 2109 2110 /* The second 128 bits */ 2111 WMI_MAX_EXT_SERVICE = 256, 2112 WMI_TLV_SERVICE_SCAN_CONFIG_PER_CHANNEL = 265, 2113 WMI_TLV_SERVICE_REG_CC_EXT_EVENT_SUPPORT = 281, 2114 WMI_TLV_SERVICE_BIOS_SAR_SUPPORT = 326, 2115 WMI_TLV_SERVICE_SUPPORT_11D_FOR_HOST_SCAN = 357, 2116 2117 /* The third 128 bits */ 2118 WMI_MAX_EXT2_SERVICE = 384 2119 }; 2120 2121 enum { 2122 WMI_SMPS_FORCED_MODE_NONE = 0, 2123 WMI_SMPS_FORCED_MODE_DISABLED, 2124 WMI_SMPS_FORCED_MODE_STATIC, 2125 WMI_SMPS_FORCED_MODE_DYNAMIC 2126 }; 2127 2128 #define WMI_TPC_CHAINMASK_CONFIG_BAND_2G 0 2129 #define WMI_TPC_CHAINMASK_CONFIG_BAND_5G 1 2130 #define WMI_NUM_SUPPORTED_BAND_MAX 2 2131 2132 #define WMI_PEER_MIMO_PS_STATE 0x1 2133 #define WMI_PEER_AMPDU 0x2 2134 #define WMI_PEER_AUTHORIZE 0x3 2135 #define WMI_PEER_CHWIDTH 0x4 2136 #define WMI_PEER_NSS 0x5 2137 #define WMI_PEER_USE_4ADDR 0x6 2138 #define WMI_PEER_MEMBERSHIP 0x7 2139 #define WMI_PEER_USERPOS 0x8 2140 #define WMI_PEER_CRIT_PROTO_HINT_ENABLED 0x9 2141 #define WMI_PEER_TX_FAIL_CNT_THR 0xA 2142 #define WMI_PEER_SET_HW_RETRY_CTS2S 0xB 2143 #define WMI_PEER_IBSS_ATIM_WINDOW_LENGTH 0xC 2144 #define WMI_PEER_PHYMODE 0xD 2145 #define WMI_PEER_USE_FIXED_PWR 0xE 2146 #define WMI_PEER_PARAM_FIXED_RATE 0xF 2147 #define WMI_PEER_SET_MU_WHITELIST 0x10 2148 #define WMI_PEER_SET_MAX_TX_RATE 0x11 2149 #define WMI_PEER_SET_MIN_TX_RATE 0x12 2150 #define WMI_PEER_SET_DEFAULT_ROUTING 0x13 2151 2152 /* slot time long */ 2153 #define WMI_VDEV_SLOT_TIME_LONG 0x1 2154 /* slot time short */ 2155 #define WMI_VDEV_SLOT_TIME_SHORT 0x2 2156 /* preablbe long */ 2157 #define WMI_VDEV_PREAMBLE_LONG 0x1 2158 /* preablbe short */ 2159 #define WMI_VDEV_PREAMBLE_SHORT 0x2 2160 2161 enum wmi_peer_smps_state { 2162 WMI_PEER_SMPS_PS_NONE = 0x0, 2163 WMI_PEER_SMPS_STATIC = 0x1, 2164 WMI_PEER_SMPS_DYNAMIC = 0x2 2165 }; 2166 2167 enum wmi_peer_chwidth { 2168 WMI_PEER_CHWIDTH_20MHZ = 0, 2169 WMI_PEER_CHWIDTH_40MHZ = 1, 2170 WMI_PEER_CHWIDTH_80MHZ = 2, 2171 WMI_PEER_CHWIDTH_160MHZ = 3, 2172 }; 2173 2174 enum wmi_beacon_gen_mode { 2175 WMI_BEACON_STAGGERED_MODE = 0, 2176 WMI_BEACON_BURST_MODE = 1 2177 }; 2178 2179 enum wmi_direct_buffer_module { 2180 WMI_DIRECT_BUF_SPECTRAL = 0, 2181 WMI_DIRECT_BUF_CFR = 1, 2182 2183 /* keep it last */ 2184 WMI_DIRECT_BUF_MAX 2185 }; 2186 2187 /* enum wmi_nss_ratio - NSS ratio received from FW during service ready ext 2188 * event 2189 * WMI_NSS_RATIO_1BY2_NSS -Max nss of 160MHz is equals to half of the max nss 2190 * of 80MHz 2191 * WMI_NSS_RATIO_3BY4_NSS - Max nss of 160MHz is equals to 3/4 of the max nss 2192 * of 80MHz 2193 * WMI_NSS_RATIO_1_NSS - Max nss of 160MHz is equals to the max nss of 80MHz 2194 * WMI_NSS_RATIO_2_NSS - Max nss of 160MHz is equals to two times the max 2195 * nss of 80MHz 2196 */ 2197 2198 enum wmi_nss_ratio { 2199 WMI_NSS_RATIO_1BY2_NSS = 0x0, 2200 WMI_NSS_RATIO_3BY4_NSS = 0x1, 2201 WMI_NSS_RATIO_1_NSS = 0x2, 2202 WMI_NSS_RATIO_2_NSS = 0x3, 2203 }; 2204 2205 enum wmi_dtim_policy { 2206 WMI_DTIM_POLICY_IGNORE = 1, 2207 WMI_DTIM_POLICY_NORMAL = 2, 2208 WMI_DTIM_POLICY_STICK = 3, 2209 WMI_DTIM_POLICY_AUTO = 4, 2210 }; 2211 2212 struct wmi_host_pdev_band_to_mac { 2213 u32 pdev_id; 2214 u32 start_freq; 2215 u32 end_freq; 2216 }; 2217 2218 struct ath11k_ppe_threshold { 2219 u32 numss_m1; 2220 u32 ru_bit_mask; 2221 u32 ppet16_ppet8_ru3_ru0[PSOC_HOST_MAX_NUM_SS]; 2222 }; 2223 2224 struct ath11k_service_ext_param { 2225 u32 default_conc_scan_config_bits; 2226 u32 default_fw_config_bits; 2227 struct ath11k_ppe_threshold ppet; 2228 u32 he_cap_info; 2229 u32 mpdu_density; 2230 u32 max_bssid_rx_filters; 2231 u32 num_hw_modes; 2232 u32 num_phy; 2233 }; 2234 2235 struct ath11k_hw_mode_caps { 2236 u32 hw_mode_id; 2237 u32 phy_id_map; 2238 u32 hw_mode_config_type; 2239 }; 2240 2241 #define PSOC_HOST_MAX_PHY_SIZE (3) 2242 #define ATH11K_11B_SUPPORT BIT(0) 2243 #define ATH11K_11G_SUPPORT BIT(1) 2244 #define ATH11K_11A_SUPPORT BIT(2) 2245 #define ATH11K_11N_SUPPORT BIT(3) 2246 #define ATH11K_11AC_SUPPORT BIT(4) 2247 #define ATH11K_11AX_SUPPORT BIT(5) 2248 2249 struct ath11k_hal_reg_capabilities_ext { 2250 u32 phy_id; 2251 u32 eeprom_reg_domain; 2252 u32 eeprom_reg_domain_ext; 2253 u32 regcap1; 2254 u32 regcap2; 2255 u32 wireless_modes; 2256 u32 low_2ghz_chan; 2257 u32 high_2ghz_chan; 2258 u32 low_5ghz_chan; 2259 u32 high_5ghz_chan; 2260 }; 2261 2262 #define WMI_HOST_MAX_PDEV 3 2263 2264 struct wlan_host_mem_chunk { 2265 u32 tlv_header; 2266 u32 req_id; 2267 u32 ptr; 2268 u32 size; 2269 } __packed; 2270 2271 struct wmi_host_mem_chunk { 2272 void *vaddr; 2273 dma_addr_t paddr; 2274 u32 len; 2275 u32 req_id; 2276 }; 2277 2278 struct wmi_init_cmd_param { 2279 u32 tlv_header; 2280 struct target_resource_config *res_cfg; 2281 u8 num_mem_chunks; 2282 struct wmi_host_mem_chunk *mem_chunks; 2283 u32 hw_mode_id; 2284 u32 num_band_to_mac; 2285 struct wmi_host_pdev_band_to_mac band_to_mac[WMI_HOST_MAX_PDEV]; 2286 }; 2287 2288 struct wmi_pdev_band_to_mac { 2289 u32 tlv_header; 2290 u32 pdev_id; 2291 u32 start_freq; 2292 u32 end_freq; 2293 } __packed; 2294 2295 struct wmi_pdev_set_hw_mode_cmd_param { 2296 u32 tlv_header; 2297 u32 pdev_id; 2298 u32 hw_mode_index; 2299 u32 num_band_to_mac; 2300 } __packed; 2301 2302 struct wmi_ppe_threshold { 2303 u32 numss_m1; /** NSS - 1*/ 2304 union { 2305 u32 ru_count; 2306 u32 ru_mask; 2307 } __packed; 2308 u32 ppet16_ppet8_ru3_ru0[WMI_MAX_NUM_SS]; 2309 } __packed; 2310 2311 #define HW_BD_INFO_SIZE 5 2312 2313 struct wmi_abi_version { 2314 u32 abi_version_0; 2315 u32 abi_version_1; 2316 u32 abi_version_ns_0; 2317 u32 abi_version_ns_1; 2318 u32 abi_version_ns_2; 2319 u32 abi_version_ns_3; 2320 } __packed; 2321 2322 struct wmi_init_cmd { 2323 u32 tlv_header; 2324 struct wmi_abi_version host_abi_vers; 2325 u32 num_host_mem_chunks; 2326 } __packed; 2327 2328 #define WMI_RSRC_CFG_FLAG1_BSS_CHANNEL_INFO_64 BIT(5) 2329 #define WMI_RSRC_CFG_FLAG2_CALC_NEXT_DTIM_COUNT_SET BIT(9) 2330 #define WMI_RSRC_CFG_FLAG1_ACK_RSSI BIT(18) 2331 2332 #define WMI_CFG_HOST_SERVICE_FLAG_REG_CC_EXT 4 2333 2334 struct wmi_resource_config { 2335 u32 tlv_header; 2336 u32 num_vdevs; 2337 u32 num_peers; 2338 u32 num_offload_peers; 2339 u32 num_offload_reorder_buffs; 2340 u32 num_peer_keys; 2341 u32 num_tids; 2342 u32 ast_skid_limit; 2343 u32 tx_chain_mask; 2344 u32 rx_chain_mask; 2345 u32 rx_timeout_pri[4]; 2346 u32 rx_decap_mode; 2347 u32 scan_max_pending_req; 2348 u32 bmiss_offload_max_vdev; 2349 u32 roam_offload_max_vdev; 2350 u32 roam_offload_max_ap_profiles; 2351 u32 num_mcast_groups; 2352 u32 num_mcast_table_elems; 2353 u32 mcast2ucast_mode; 2354 u32 tx_dbg_log_size; 2355 u32 num_wds_entries; 2356 u32 dma_burst_size; 2357 u32 mac_aggr_delim; 2358 u32 rx_skip_defrag_timeout_dup_detection_check; 2359 u32 vow_config; 2360 u32 gtk_offload_max_vdev; 2361 u32 num_msdu_desc; 2362 u32 max_frag_entries; 2363 u32 num_tdls_vdevs; 2364 u32 num_tdls_conn_table_entries; 2365 u32 beacon_tx_offload_max_vdev; 2366 u32 num_multicast_filter_entries; 2367 u32 num_wow_filters; 2368 u32 num_keep_alive_pattern; 2369 u32 keep_alive_pattern_size; 2370 u32 max_tdls_concurrent_sleep_sta; 2371 u32 max_tdls_concurrent_buffer_sta; 2372 u32 wmi_send_separate; 2373 u32 num_ocb_vdevs; 2374 u32 num_ocb_channels; 2375 u32 num_ocb_schedules; 2376 u32 flag1; 2377 u32 smart_ant_cap; 2378 u32 bk_minfree; 2379 u32 be_minfree; 2380 u32 vi_minfree; 2381 u32 vo_minfree; 2382 u32 alloc_frag_desc_for_data_pkt; 2383 u32 num_ns_ext_tuples_cfg; 2384 u32 bpf_instruction_size; 2385 u32 max_bssid_rx_filters; 2386 u32 use_pdev_id; 2387 u32 max_num_dbs_scan_duty_cycle; 2388 u32 max_num_group_keys; 2389 u32 peer_map_unmap_v2_support; 2390 u32 sched_params; 2391 u32 twt_ap_pdev_count; 2392 u32 twt_ap_sta_count; 2393 u32 max_nlo_ssids; 2394 u32 num_pkt_filters; 2395 u32 num_max_sta_vdevs; 2396 u32 max_bssid_indicator; 2397 u32 ul_resp_config; 2398 u32 msdu_flow_override_config0; 2399 u32 msdu_flow_override_config1; 2400 u32 flags2; 2401 u32 host_service_flags; 2402 u32 max_rnr_neighbours; 2403 u32 ema_max_vap_cnt; 2404 u32 ema_max_profile_period; 2405 } __packed; 2406 2407 struct wmi_service_ready_event { 2408 u32 fw_build_vers; 2409 struct wmi_abi_version fw_abi_vers; 2410 u32 phy_capability; 2411 u32 max_frag_entry; 2412 u32 num_rf_chains; 2413 u32 ht_cap_info; 2414 u32 vht_cap_info; 2415 u32 vht_supp_mcs; 2416 u32 hw_min_tx_power; 2417 u32 hw_max_tx_power; 2418 u32 sys_cap_info; 2419 u32 min_pkt_size_enable; 2420 u32 max_bcn_ie_size; 2421 u32 num_mem_reqs; 2422 u32 max_num_scan_channels; 2423 u32 hw_bd_id; 2424 u32 hw_bd_info[HW_BD_INFO_SIZE]; 2425 u32 max_supported_macs; 2426 u32 wmi_fw_sub_feat_caps; 2427 u32 num_dbs_hw_modes; 2428 /* txrx_chainmask 2429 * [7:0] - 2G band tx chain mask 2430 * [15:8] - 2G band rx chain mask 2431 * [23:16] - 5G band tx chain mask 2432 * [31:24] - 5G band rx chain mask 2433 */ 2434 u32 txrx_chainmask; 2435 u32 default_dbs_hw_mode_index; 2436 u32 num_msdu_desc; 2437 } __packed; 2438 2439 #define WMI_SERVICE_BM_SIZE ((WMI_MAX_SERVICE + sizeof(u32) - 1) / sizeof(u32)) 2440 2441 #define WMI_SERVICE_SEGMENT_BM_SIZE32 4 /* 4x u32 = 128 bits */ 2442 #define WMI_SERVICE_EXT_BM_SIZE (WMI_SERVICE_SEGMENT_BM_SIZE32 * sizeof(u32)) 2443 #define WMI_AVAIL_SERVICE_BITS_IN_SIZE32 32 2444 #define WMI_SERVICE_BITS_IN_SIZE32 4 2445 2446 struct wmi_service_ready_ext_event { 2447 u32 default_conc_scan_config_bits; 2448 u32 default_fw_config_bits; 2449 struct wmi_ppe_threshold ppet; 2450 u32 he_cap_info; 2451 u32 mpdu_density; 2452 u32 max_bssid_rx_filters; 2453 u32 fw_build_vers_ext; 2454 u32 max_nlo_ssids; 2455 u32 max_bssid_indicator; 2456 u32 he_cap_info_ext; 2457 } __packed; 2458 2459 struct wmi_soc_mac_phy_hw_mode_caps { 2460 u32 num_hw_modes; 2461 u32 num_chainmask_tables; 2462 } __packed; 2463 2464 struct wmi_hw_mode_capabilities { 2465 u32 tlv_header; 2466 u32 hw_mode_id; 2467 u32 phy_id_map; 2468 u32 hw_mode_config_type; 2469 } __packed; 2470 2471 #define WMI_MAX_HECAP_PHY_SIZE (3) 2472 #define WMI_NSS_RATIO_ENABLE_DISABLE_BITPOS BIT(0) 2473 #define WMI_NSS_RATIO_ENABLE_DISABLE_GET(_val) \ 2474 FIELD_GET(WMI_NSS_RATIO_ENABLE_DISABLE_BITPOS, _val) 2475 #define WMI_NSS_RATIO_INFO_BITPOS GENMASK(4, 1) 2476 #define WMI_NSS_RATIO_INFO_GET(_val) \ 2477 FIELD_GET(WMI_NSS_RATIO_INFO_BITPOS, _val) 2478 2479 struct wmi_mac_phy_capabilities { 2480 u32 hw_mode_id; 2481 u32 pdev_id; 2482 u32 phy_id; 2483 u32 supported_flags; 2484 u32 supported_bands; 2485 u32 ampdu_density; 2486 u32 max_bw_supported_2g; 2487 u32 ht_cap_info_2g; 2488 u32 vht_cap_info_2g; 2489 u32 vht_supp_mcs_2g; 2490 u32 he_cap_info_2g; 2491 u32 he_supp_mcs_2g; 2492 u32 tx_chain_mask_2g; 2493 u32 rx_chain_mask_2g; 2494 u32 max_bw_supported_5g; 2495 u32 ht_cap_info_5g; 2496 u32 vht_cap_info_5g; 2497 u32 vht_supp_mcs_5g; 2498 u32 he_cap_info_5g; 2499 u32 he_supp_mcs_5g; 2500 u32 tx_chain_mask_5g; 2501 u32 rx_chain_mask_5g; 2502 u32 he_cap_phy_info_2g[WMI_MAX_HECAP_PHY_SIZE]; 2503 u32 he_cap_phy_info_5g[WMI_MAX_HECAP_PHY_SIZE]; 2504 struct wmi_ppe_threshold he_ppet2g; 2505 struct wmi_ppe_threshold he_ppet5g; 2506 u32 chainmask_table_id; 2507 u32 lmac_id; 2508 u32 he_cap_info_2g_ext; 2509 u32 he_cap_info_5g_ext; 2510 u32 he_cap_info_internal; 2511 u32 wireless_modes; 2512 u32 low_2ghz_chan_freq; 2513 u32 high_2ghz_chan_freq; 2514 u32 low_5ghz_chan_freq; 2515 u32 high_5ghz_chan_freq; 2516 u32 nss_ratio; 2517 } __packed; 2518 2519 struct wmi_hal_reg_capabilities_ext { 2520 u32 tlv_header; 2521 u32 phy_id; 2522 u32 eeprom_reg_domain; 2523 u32 eeprom_reg_domain_ext; 2524 u32 regcap1; 2525 u32 regcap2; 2526 u32 wireless_modes; 2527 u32 low_2ghz_chan; 2528 u32 high_2ghz_chan; 2529 u32 low_5ghz_chan; 2530 u32 high_5ghz_chan; 2531 } __packed; 2532 2533 struct wmi_soc_hal_reg_capabilities { 2534 u32 num_phy; 2535 } __packed; 2536 2537 /* 2 word representation of MAC addr */ 2538 struct wmi_mac_addr { 2539 union { 2540 u8 addr[6]; 2541 struct { 2542 u32 word0; 2543 u32 word1; 2544 } __packed; 2545 } __packed; 2546 } __packed; 2547 2548 struct wmi_dma_ring_capabilities { 2549 u32 tlv_header; 2550 u32 pdev_id; 2551 u32 module_id; 2552 u32 min_elem; 2553 u32 min_buf_sz; 2554 u32 min_buf_align; 2555 } __packed; 2556 2557 struct wmi_ready_event_min { 2558 struct wmi_abi_version fw_abi_vers; 2559 struct wmi_mac_addr mac_addr; 2560 u32 status; 2561 u32 num_dscp_table; 2562 u32 num_extra_mac_addr; 2563 u32 num_total_peers; 2564 u32 num_extra_peers; 2565 } __packed; 2566 2567 struct wmi_ready_event { 2568 struct wmi_ready_event_min ready_event_min; 2569 u32 max_ast_index; 2570 u32 pktlog_defs_checksum; 2571 } __packed; 2572 2573 struct wmi_service_available_event { 2574 u32 wmi_service_segment_offset; 2575 u32 wmi_service_segment_bitmap[WMI_SERVICE_SEGMENT_BM_SIZE32]; 2576 } __packed; 2577 2578 struct ath11k_pdev_wmi { 2579 struct ath11k_wmi_base *wmi_ab; 2580 enum ath11k_htc_ep_id eid; 2581 const struct wmi_peer_flags_map *peer_flags; 2582 u32 rx_decap_mode; 2583 wait_queue_head_t tx_ce_desc_wq; 2584 }; 2585 2586 struct vdev_create_params { 2587 u8 if_id; 2588 u32 type; 2589 u32 subtype; 2590 struct { 2591 u8 tx; 2592 u8 rx; 2593 } chains[NUM_NL80211_BANDS]; 2594 u32 pdev_id; 2595 u32 mbssid_flags; 2596 u32 mbssid_tx_vdev_id; 2597 }; 2598 2599 struct wmi_vdev_create_cmd { 2600 u32 tlv_header; 2601 u32 vdev_id; 2602 u32 vdev_type; 2603 u32 vdev_subtype; 2604 struct wmi_mac_addr vdev_macaddr; 2605 u32 num_cfg_txrx_streams; 2606 u32 pdev_id; 2607 u32 mbssid_flags; 2608 u32 mbssid_tx_vdev_id; 2609 } __packed; 2610 2611 struct wmi_vdev_txrx_streams { 2612 u32 tlv_header; 2613 u32 band; 2614 u32 supported_tx_streams; 2615 u32 supported_rx_streams; 2616 } __packed; 2617 2618 struct wmi_vdev_delete_cmd { 2619 u32 tlv_header; 2620 u32 vdev_id; 2621 } __packed; 2622 2623 struct wmi_vdev_up_cmd { 2624 u32 tlv_header; 2625 u32 vdev_id; 2626 u32 vdev_assoc_id; 2627 struct wmi_mac_addr vdev_bssid; 2628 struct wmi_mac_addr tx_vdev_bssid; 2629 u32 nontx_profile_idx; 2630 u32 nontx_profile_cnt; 2631 } __packed; 2632 2633 struct wmi_vdev_stop_cmd { 2634 u32 tlv_header; 2635 u32 vdev_id; 2636 } __packed; 2637 2638 struct wmi_vdev_down_cmd { 2639 u32 tlv_header; 2640 u32 vdev_id; 2641 } __packed; 2642 2643 #define WMI_VDEV_START_HIDDEN_SSID BIT(0) 2644 #define WMI_VDEV_START_PMF_ENABLED BIT(1) 2645 #define WMI_VDEV_START_LDPC_RX_ENABLED BIT(3) 2646 #define WMI_VDEV_START_HW_ENCRYPTION_DISABLED BIT(4) 2647 2648 struct wmi_ssid { 2649 u32 ssid_len; 2650 u32 ssid[8]; 2651 } __packed; 2652 2653 #define ATH11K_VDEV_SETUP_TIMEOUT_HZ (1 * HZ) 2654 2655 struct wmi_vdev_start_request_cmd { 2656 u32 tlv_header; 2657 u32 vdev_id; 2658 u32 requestor_id; 2659 u32 beacon_interval; 2660 u32 dtim_period; 2661 u32 flags; 2662 struct wmi_ssid ssid; 2663 u32 bcn_tx_rate; 2664 u32 bcn_txpower; 2665 u32 num_noa_descriptors; 2666 u32 disable_hw_ack; 2667 u32 preferred_tx_streams; 2668 u32 preferred_rx_streams; 2669 u32 he_ops; 2670 u32 cac_duration_ms; 2671 u32 regdomain; 2672 u32 min_data_rate; 2673 u32 mbssid_flags; 2674 u32 mbssid_tx_vdev_id; 2675 } __packed; 2676 2677 #define MGMT_TX_DL_FRM_LEN 64 2678 #define WMI_MAC_MAX_SSID_LENGTH 32 2679 struct mac_ssid { 2680 u8 length; 2681 u8 mac_ssid[WMI_MAC_MAX_SSID_LENGTH]; 2682 } __packed; 2683 2684 struct wmi_p2p_noa_descriptor { 2685 u32 type_count; 2686 u32 duration; 2687 u32 interval; 2688 u32 start_time; 2689 }; 2690 2691 struct channel_param { 2692 u8 chan_id; 2693 u8 pwr; 2694 u32 mhz; 2695 u32 half_rate:1, 2696 quarter_rate:1, 2697 dfs_set:1, 2698 dfs_set_cfreq2:1, 2699 is_chan_passive:1, 2700 allow_ht:1, 2701 allow_vht:1, 2702 allow_he:1, 2703 set_agile:1, 2704 psc_channel:1; 2705 u32 phy_mode; 2706 u32 cfreq1; 2707 u32 cfreq2; 2708 char maxpower; 2709 char minpower; 2710 char maxregpower; 2711 u8 antennamax; 2712 u8 reg_class_id; 2713 } __packed; 2714 2715 enum wmi_phy_mode { 2716 MODE_11A = 0, 2717 MODE_11G = 1, /* 11b/g Mode */ 2718 MODE_11B = 2, /* 11b Mode */ 2719 MODE_11GONLY = 3, /* 11g only Mode */ 2720 MODE_11NA_HT20 = 4, 2721 MODE_11NG_HT20 = 5, 2722 MODE_11NA_HT40 = 6, 2723 MODE_11NG_HT40 = 7, 2724 MODE_11AC_VHT20 = 8, 2725 MODE_11AC_VHT40 = 9, 2726 MODE_11AC_VHT80 = 10, 2727 MODE_11AC_VHT20_2G = 11, 2728 MODE_11AC_VHT40_2G = 12, 2729 MODE_11AC_VHT80_2G = 13, 2730 MODE_11AC_VHT80_80 = 14, 2731 MODE_11AC_VHT160 = 15, 2732 MODE_11AX_HE20 = 16, 2733 MODE_11AX_HE40 = 17, 2734 MODE_11AX_HE80 = 18, 2735 MODE_11AX_HE80_80 = 19, 2736 MODE_11AX_HE160 = 20, 2737 MODE_11AX_HE20_2G = 21, 2738 MODE_11AX_HE40_2G = 22, 2739 MODE_11AX_HE80_2G = 23, 2740 MODE_UNKNOWN = 24, 2741 MODE_MAX = 24 2742 }; 2743 2744 static inline const char *ath11k_wmi_phymode_str(enum wmi_phy_mode mode) 2745 { 2746 switch (mode) { 2747 case MODE_11A: 2748 return "11a"; 2749 case MODE_11G: 2750 return "11g"; 2751 case MODE_11B: 2752 return "11b"; 2753 case MODE_11GONLY: 2754 return "11gonly"; 2755 case MODE_11NA_HT20: 2756 return "11na-ht20"; 2757 case MODE_11NG_HT20: 2758 return "11ng-ht20"; 2759 case MODE_11NA_HT40: 2760 return "11na-ht40"; 2761 case MODE_11NG_HT40: 2762 return "11ng-ht40"; 2763 case MODE_11AC_VHT20: 2764 return "11ac-vht20"; 2765 case MODE_11AC_VHT40: 2766 return "11ac-vht40"; 2767 case MODE_11AC_VHT80: 2768 return "11ac-vht80"; 2769 case MODE_11AC_VHT160: 2770 return "11ac-vht160"; 2771 case MODE_11AC_VHT80_80: 2772 return "11ac-vht80+80"; 2773 case MODE_11AC_VHT20_2G: 2774 return "11ac-vht20-2g"; 2775 case MODE_11AC_VHT40_2G: 2776 return "11ac-vht40-2g"; 2777 case MODE_11AC_VHT80_2G: 2778 return "11ac-vht80-2g"; 2779 case MODE_11AX_HE20: 2780 return "11ax-he20"; 2781 case MODE_11AX_HE40: 2782 return "11ax-he40"; 2783 case MODE_11AX_HE80: 2784 return "11ax-he80"; 2785 case MODE_11AX_HE80_80: 2786 return "11ax-he80+80"; 2787 case MODE_11AX_HE160: 2788 return "11ax-he160"; 2789 case MODE_11AX_HE20_2G: 2790 return "11ax-he20-2g"; 2791 case MODE_11AX_HE40_2G: 2792 return "11ax-he40-2g"; 2793 case MODE_11AX_HE80_2G: 2794 return "11ax-he80-2g"; 2795 case MODE_UNKNOWN: 2796 /* skip */ 2797 break; 2798 2799 /* no default handler to allow compiler to check that the 2800 * enum is fully handled 2801 */ 2802 } 2803 2804 return "<unknown>"; 2805 } 2806 2807 struct wmi_channel_arg { 2808 u32 freq; 2809 u32 band_center_freq1; 2810 u32 band_center_freq2; 2811 bool passive; 2812 bool allow_ibss; 2813 bool allow_ht; 2814 bool allow_vht; 2815 bool ht40plus; 2816 bool chan_radar; 2817 bool freq2_radar; 2818 bool allow_he; 2819 u32 min_power; 2820 u32 max_power; 2821 u32 max_reg_power; 2822 u32 max_antenna_gain; 2823 enum wmi_phy_mode mode; 2824 }; 2825 2826 struct wmi_vdev_start_req_arg { 2827 u32 vdev_id; 2828 struct wmi_channel_arg channel; 2829 u32 bcn_intval; 2830 u32 dtim_period; 2831 u8 *ssid; 2832 u32 ssid_len; 2833 u32 bcn_tx_rate; 2834 u32 bcn_tx_power; 2835 bool disable_hw_ack; 2836 bool hidden_ssid; 2837 bool pmf_enabled; 2838 u32 he_ops; 2839 u32 cac_duration_ms; 2840 u32 regdomain; 2841 u32 pref_rx_streams; 2842 u32 pref_tx_streams; 2843 u32 num_noa_descriptors; 2844 u32 min_data_rate; 2845 u32 mbssid_flags; 2846 u32 mbssid_tx_vdev_id; 2847 }; 2848 2849 struct peer_create_params { 2850 const u8 *peer_addr; 2851 u32 peer_type; 2852 u32 vdev_id; 2853 }; 2854 2855 struct peer_delete_params { 2856 u8 vdev_id; 2857 }; 2858 2859 struct peer_flush_params { 2860 u32 peer_tid_bitmap; 2861 u8 vdev_id; 2862 }; 2863 2864 struct pdev_set_regdomain_params { 2865 u16 current_rd_in_use; 2866 u16 current_rd_2g; 2867 u16 current_rd_5g; 2868 u32 ctl_2g; 2869 u32 ctl_5g; 2870 u8 dfs_domain; 2871 u32 pdev_id; 2872 }; 2873 2874 struct rx_reorder_queue_remove_params { 2875 u8 *peer_macaddr; 2876 u16 vdev_id; 2877 u32 peer_tid_bitmap; 2878 }; 2879 2880 #define WMI_HOST_PDEV_ID_SOC 0xFF 2881 #define WMI_HOST_PDEV_ID_0 0 2882 #define WMI_HOST_PDEV_ID_1 1 2883 #define WMI_HOST_PDEV_ID_2 2 2884 2885 #define WMI_PDEV_ID_SOC 0 2886 #define WMI_PDEV_ID_1ST 1 2887 #define WMI_PDEV_ID_2ND 2 2888 #define WMI_PDEV_ID_3RD 3 2889 2890 /* Freq units in MHz */ 2891 #define REG_RULE_START_FREQ 0x0000ffff 2892 #define REG_RULE_END_FREQ 0xffff0000 2893 #define REG_RULE_FLAGS 0x0000ffff 2894 #define REG_RULE_MAX_BW 0x0000ffff 2895 #define REG_RULE_REG_PWR 0x00ff0000 2896 #define REG_RULE_ANT_GAIN 0xff000000 2897 #define REG_RULE_PSD_INFO BIT(0) 2898 #define REG_RULE_PSD_EIRP 0xff0000 2899 2900 #define WMI_VDEV_PARAM_TXBF_SU_TX_BFEE BIT(0) 2901 #define WMI_VDEV_PARAM_TXBF_MU_TX_BFEE BIT(1) 2902 #define WMI_VDEV_PARAM_TXBF_SU_TX_BFER BIT(2) 2903 #define WMI_VDEV_PARAM_TXBF_MU_TX_BFER BIT(3) 2904 2905 #define HE_PHYCAP_BYTE_0 0 2906 #define HE_PHYCAP_BYTE_1 1 2907 #define HE_PHYCAP_BYTE_2 2 2908 #define HE_PHYCAP_BYTE_3 3 2909 #define HE_PHYCAP_BYTE_4 4 2910 2911 #define HECAP_PHY_SU_BFER BIT(7) 2912 #define HECAP_PHY_SU_BFEE BIT(0) 2913 #define HECAP_PHY_MU_BFER BIT(1) 2914 #define HECAP_PHY_UL_MUMIMO BIT(6) 2915 #define HECAP_PHY_UL_MUOFDMA BIT(7) 2916 2917 #define HECAP_PHY_SUBFMR_GET(hecap_phy) \ 2918 FIELD_GET(HECAP_PHY_SU_BFER, hecap_phy[HE_PHYCAP_BYTE_3]) 2919 2920 #define HECAP_PHY_SUBFME_GET(hecap_phy) \ 2921 FIELD_GET(HECAP_PHY_SU_BFEE, hecap_phy[HE_PHYCAP_BYTE_4]) 2922 2923 #define HECAP_PHY_MUBFMR_GET(hecap_phy) \ 2924 FIELD_GET(HECAP_PHY_MU_BFER, hecap_phy[HE_PHYCAP_BYTE_4]) 2925 2926 #define HECAP_PHY_ULMUMIMO_GET(hecap_phy) \ 2927 FIELD_GET(HECAP_PHY_UL_MUMIMO, hecap_phy[HE_PHYCAP_BYTE_2]) 2928 2929 #define HECAP_PHY_ULOFDMA_GET(hecap_phy) \ 2930 FIELD_GET(HECAP_PHY_UL_MUOFDMA, hecap_phy[HE_PHYCAP_BYTE_2]) 2931 2932 #define HE_MODE_SU_TX_BFEE BIT(0) 2933 #define HE_MODE_SU_TX_BFER BIT(1) 2934 #define HE_MODE_MU_TX_BFEE BIT(2) 2935 #define HE_MODE_MU_TX_BFER BIT(3) 2936 #define HE_MODE_DL_OFDMA BIT(4) 2937 #define HE_MODE_UL_OFDMA BIT(5) 2938 #define HE_MODE_UL_MUMIMO BIT(6) 2939 2940 #define HE_DL_MUOFDMA_ENABLE 1 2941 #define HE_UL_MUOFDMA_ENABLE 1 2942 #define HE_DL_MUMIMO_ENABLE 1 2943 #define HE_UL_MUMIMO_ENABLE 1 2944 #define HE_MU_BFEE_ENABLE 1 2945 #define HE_SU_BFEE_ENABLE 1 2946 #define HE_MU_BFER_ENABLE 1 2947 #define HE_SU_BFER_ENABLE 1 2948 2949 #define HE_VHT_SOUNDING_MODE_ENABLE 1 2950 #define HE_SU_MU_SOUNDING_MODE_ENABLE 1 2951 #define HE_TRIG_NONTRIG_SOUNDING_MODE_ENABLE 1 2952 2953 /* HE or VHT Sounding */ 2954 #define HE_VHT_SOUNDING_MODE BIT(0) 2955 /* SU or MU Sounding */ 2956 #define HE_SU_MU_SOUNDING_MODE BIT(2) 2957 /* Trig or Non-Trig Sounding */ 2958 #define HE_TRIG_NONTRIG_SOUNDING_MODE BIT(3) 2959 2960 #define WMI_TXBF_STS_CAP_OFFSET_LSB 4 2961 #define WMI_TXBF_STS_CAP_OFFSET_MASK 0x70 2962 #define WMI_BF_SOUND_DIM_OFFSET_LSB 8 2963 #define WMI_BF_SOUND_DIM_OFFSET_MASK 0x700 2964 2965 struct pdev_params { 2966 u32 param_id; 2967 u32 param_value; 2968 }; 2969 2970 enum wmi_peer_type { 2971 WMI_PEER_TYPE_DEFAULT = 0, 2972 WMI_PEER_TYPE_BSS = 1, 2973 WMI_PEER_TYPE_TDLS = 2, 2974 }; 2975 2976 struct wmi_peer_create_cmd { 2977 u32 tlv_header; 2978 u32 vdev_id; 2979 struct wmi_mac_addr peer_macaddr; 2980 u32 peer_type; 2981 } __packed; 2982 2983 struct wmi_peer_delete_cmd { 2984 u32 tlv_header; 2985 u32 vdev_id; 2986 struct wmi_mac_addr peer_macaddr; 2987 } __packed; 2988 2989 struct wmi_peer_reorder_queue_setup_cmd { 2990 u32 tlv_header; 2991 u32 vdev_id; 2992 struct wmi_mac_addr peer_macaddr; 2993 u32 tid; 2994 u32 queue_ptr_lo; 2995 u32 queue_ptr_hi; 2996 u32 queue_no; 2997 u32 ba_window_size_valid; 2998 u32 ba_window_size; 2999 } __packed; 3000 3001 struct wmi_peer_reorder_queue_remove_cmd { 3002 u32 tlv_header; 3003 u32 vdev_id; 3004 struct wmi_mac_addr peer_macaddr; 3005 u32 tid_mask; 3006 } __packed; 3007 3008 struct gpio_config_params { 3009 u32 gpio_num; 3010 u32 input; 3011 u32 pull_type; 3012 u32 intr_mode; 3013 }; 3014 3015 enum wmi_gpio_type { 3016 WMI_GPIO_PULL_NONE, 3017 WMI_GPIO_PULL_UP, 3018 WMI_GPIO_PULL_DOWN 3019 }; 3020 3021 enum wmi_gpio_intr_type { 3022 WMI_GPIO_INTTYPE_DISABLE, 3023 WMI_GPIO_INTTYPE_RISING_EDGE, 3024 WMI_GPIO_INTTYPE_FALLING_EDGE, 3025 WMI_GPIO_INTTYPE_BOTH_EDGE, 3026 WMI_GPIO_INTTYPE_LEVEL_LOW, 3027 WMI_GPIO_INTTYPE_LEVEL_HIGH 3028 }; 3029 3030 enum wmi_bss_chan_info_req_type { 3031 WMI_BSS_SURVEY_REQ_TYPE_READ = 1, 3032 WMI_BSS_SURVEY_REQ_TYPE_READ_CLEAR, 3033 }; 3034 3035 struct wmi_gpio_config_cmd_param { 3036 u32 tlv_header; 3037 u32 gpio_num; 3038 u32 input; 3039 u32 pull_type; 3040 u32 intr_mode; 3041 }; 3042 3043 struct gpio_output_params { 3044 u32 gpio_num; 3045 u32 set; 3046 }; 3047 3048 struct wmi_gpio_output_cmd_param { 3049 u32 tlv_header; 3050 u32 gpio_num; 3051 u32 set; 3052 }; 3053 3054 struct set_fwtest_params { 3055 u32 arg; 3056 u32 value; 3057 }; 3058 3059 struct wmi_fwtest_set_param_cmd_param { 3060 u32 tlv_header; 3061 u32 param_id; 3062 u32 param_value; 3063 }; 3064 3065 struct wmi_pdev_set_param_cmd { 3066 u32 tlv_header; 3067 u32 pdev_id; 3068 u32 param_id; 3069 u32 param_value; 3070 } __packed; 3071 3072 struct wmi_pdev_set_ps_mode_cmd { 3073 u32 tlv_header; 3074 u32 vdev_id; 3075 u32 sta_ps_mode; 3076 } __packed; 3077 3078 struct wmi_pdev_suspend_cmd { 3079 u32 tlv_header; 3080 u32 pdev_id; 3081 u32 suspend_opt; 3082 } __packed; 3083 3084 struct wmi_pdev_resume_cmd { 3085 u32 tlv_header; 3086 u32 pdev_id; 3087 } __packed; 3088 3089 struct wmi_pdev_bss_chan_info_req_cmd { 3090 u32 tlv_header; 3091 /* ref wmi_bss_chan_info_req_type */ 3092 u32 req_type; 3093 u32 pdev_id; 3094 } __packed; 3095 3096 struct wmi_ap_ps_peer_cmd { 3097 u32 tlv_header; 3098 u32 vdev_id; 3099 struct wmi_mac_addr peer_macaddr; 3100 u32 param; 3101 u32 value; 3102 } __packed; 3103 3104 struct wmi_sta_powersave_param_cmd { 3105 u32 tlv_header; 3106 u32 vdev_id; 3107 u32 param; 3108 u32 value; 3109 } __packed; 3110 3111 struct wmi_pdev_set_regdomain_cmd { 3112 u32 tlv_header; 3113 u32 pdev_id; 3114 u32 reg_domain; 3115 u32 reg_domain_2g; 3116 u32 reg_domain_5g; 3117 u32 conformance_test_limit_2g; 3118 u32 conformance_test_limit_5g; 3119 u32 dfs_domain; 3120 } __packed; 3121 3122 struct wmi_peer_set_param_cmd { 3123 u32 tlv_header; 3124 u32 vdev_id; 3125 struct wmi_mac_addr peer_macaddr; 3126 u32 param_id; 3127 u32 param_value; 3128 } __packed; 3129 3130 struct wmi_peer_flush_tids_cmd { 3131 u32 tlv_header; 3132 u32 vdev_id; 3133 struct wmi_mac_addr peer_macaddr; 3134 u32 peer_tid_bitmap; 3135 } __packed; 3136 3137 struct wmi_dfs_phyerr_offload_cmd { 3138 u32 tlv_header; 3139 u32 pdev_id; 3140 } __packed; 3141 3142 struct wmi_bcn_offload_ctrl_cmd { 3143 u32 tlv_header; 3144 u32 vdev_id; 3145 u32 bcn_ctrl_op; 3146 } __packed; 3147 3148 enum scan_dwelltime_adaptive_mode { 3149 SCAN_DWELL_MODE_DEFAULT = 0, 3150 SCAN_DWELL_MODE_CONSERVATIVE = 1, 3151 SCAN_DWELL_MODE_MODERATE = 2, 3152 SCAN_DWELL_MODE_AGGRESSIVE = 3, 3153 SCAN_DWELL_MODE_STATIC = 4 3154 }; 3155 3156 #define WLAN_SSID_MAX_LEN 32 3157 3158 struct element_info { 3159 u32 len; 3160 u8 *ptr; 3161 }; 3162 3163 struct wlan_ssid { 3164 u8 length; 3165 u8 ssid[WLAN_SSID_MAX_LEN]; 3166 }; 3167 3168 #define WMI_IE_BITMAP_SIZE 8 3169 3170 /* prefix used by scan requestor ids on the host */ 3171 #define WMI_HOST_SCAN_REQUESTOR_ID_PREFIX 0xA000 3172 3173 /* prefix used by scan request ids generated on the host */ 3174 /* host cycles through the lower 12 bits to generate ids */ 3175 #define WMI_HOST_SCAN_REQ_ID_PREFIX 0xA000 3176 3177 /* Values lower than this may be refused by some firmware revisions with a scan 3178 * completion with a timedout reason. 3179 */ 3180 #define WMI_SCAN_CHAN_MIN_TIME_MSEC 40 3181 3182 /* Scan priority numbers must be sequential, starting with 0 */ 3183 enum wmi_scan_priority { 3184 WMI_SCAN_PRIORITY_VERY_LOW = 0, 3185 WMI_SCAN_PRIORITY_LOW, 3186 WMI_SCAN_PRIORITY_MEDIUM, 3187 WMI_SCAN_PRIORITY_HIGH, 3188 WMI_SCAN_PRIORITY_VERY_HIGH, 3189 WMI_SCAN_PRIORITY_COUNT /* number of priorities supported */ 3190 }; 3191 3192 enum wmi_scan_event_type { 3193 WMI_SCAN_EVENT_STARTED = BIT(0), 3194 WMI_SCAN_EVENT_COMPLETED = BIT(1), 3195 WMI_SCAN_EVENT_BSS_CHANNEL = BIT(2), 3196 WMI_SCAN_EVENT_FOREIGN_CHAN = BIT(3), 3197 WMI_SCAN_EVENT_DEQUEUED = BIT(4), 3198 /* possibly by high-prio scan */ 3199 WMI_SCAN_EVENT_PREEMPTED = BIT(5), 3200 WMI_SCAN_EVENT_START_FAILED = BIT(6), 3201 WMI_SCAN_EVENT_RESTARTED = BIT(7), 3202 WMI_SCAN_EVENT_FOREIGN_CHAN_EXIT = BIT(8), 3203 WMI_SCAN_EVENT_SUSPENDED = BIT(9), 3204 WMI_SCAN_EVENT_RESUMED = BIT(10), 3205 WMI_SCAN_EVENT_MAX = BIT(15), 3206 }; 3207 3208 enum wmi_scan_completion_reason { 3209 WMI_SCAN_REASON_COMPLETED, 3210 WMI_SCAN_REASON_CANCELLED, 3211 WMI_SCAN_REASON_PREEMPTED, 3212 WMI_SCAN_REASON_TIMEDOUT, 3213 WMI_SCAN_REASON_INTERNAL_FAILURE, 3214 WMI_SCAN_REASON_MAX, 3215 }; 3216 3217 struct wmi_start_scan_cmd { 3218 u32 tlv_header; 3219 u32 scan_id; 3220 u32 scan_req_id; 3221 u32 vdev_id; 3222 u32 scan_priority; 3223 u32 notify_scan_events; 3224 u32 dwell_time_active; 3225 u32 dwell_time_passive; 3226 u32 min_rest_time; 3227 u32 max_rest_time; 3228 u32 repeat_probe_time; 3229 u32 probe_spacing_time; 3230 u32 idle_time; 3231 u32 max_scan_time; 3232 u32 probe_delay; 3233 u32 scan_ctrl_flags; 3234 u32 burst_duration; 3235 u32 num_chan; 3236 u32 num_bssid; 3237 u32 num_ssids; 3238 u32 ie_len; 3239 u32 n_probes; 3240 struct wmi_mac_addr mac_addr; 3241 struct wmi_mac_addr mac_mask; 3242 u32 ie_bitmap[WMI_IE_BITMAP_SIZE]; 3243 u32 num_vendor_oui; 3244 u32 scan_ctrl_flags_ext; 3245 u32 dwell_time_active_2g; 3246 u32 dwell_time_active_6g; 3247 u32 dwell_time_passive_6g; 3248 u32 scan_start_offset; 3249 } __packed; 3250 3251 #define WMI_SCAN_FLAG_PASSIVE 0x1 3252 #define WMI_SCAN_ADD_BCAST_PROBE_REQ 0x2 3253 #define WMI_SCAN_ADD_CCK_RATES 0x4 3254 #define WMI_SCAN_ADD_OFDM_RATES 0x8 3255 #define WMI_SCAN_CHAN_STAT_EVENT 0x10 3256 #define WMI_SCAN_FILTER_PROBE_REQ 0x20 3257 #define WMI_SCAN_BYPASS_DFS_CHN 0x40 3258 #define WMI_SCAN_CONTINUE_ON_ERROR 0x80 3259 #define WMI_SCAN_FILTER_PROMISCUOS 0x100 3260 #define WMI_SCAN_FLAG_FORCE_ACTIVE_ON_DFS 0x200 3261 #define WMI_SCAN_ADD_TPC_IE_IN_PROBE_REQ 0x400 3262 #define WMI_SCAN_ADD_DS_IE_IN_PROBE_REQ 0x800 3263 #define WMI_SCAN_ADD_SPOOF_MAC_IN_PROBE_REQ 0x1000 3264 #define WMI_SCAN_OFFCHAN_MGMT_TX 0x2000 3265 #define WMI_SCAN_OFFCHAN_DATA_TX 0x4000 3266 #define WMI_SCAN_CAPTURE_PHY_ERROR 0x8000 3267 #define WMI_SCAN_FLAG_STRICT_PASSIVE_ON_PCHN 0x10000 3268 #define WMI_SCAN_FLAG_HALF_RATE_SUPPORT 0x20000 3269 #define WMI_SCAN_FLAG_QUARTER_RATE_SUPPORT 0x40000 3270 #define WMI_SCAN_RANDOM_SEQ_NO_IN_PROBE_REQ 0x80000 3271 #define WMI_SCAN_ENABLE_IE_WHTELIST_IN_PROBE_REQ 0x100000 3272 3273 #define WMI_SCAN_DWELL_MODE_MASK 0x00E00000 3274 #define WMI_SCAN_DWELL_MODE_SHIFT 21 3275 #define WMI_SCAN_FLAG_EXT_PASSIVE_SCAN_START_TIME_ENHANCE 0x00000800 3276 3277 #define WMI_SCAN_CONFIG_PER_CHANNEL_MASK GENMASK(19, 0) 3278 #define WMI_SCAN_CH_FLAG_SCAN_ONLY_IF_RNR_FOUND BIT(20) 3279 3280 enum { 3281 WMI_SCAN_DWELL_MODE_DEFAULT = 0, 3282 WMI_SCAN_DWELL_MODE_CONSERVATIVE = 1, 3283 WMI_SCAN_DWELL_MODE_MODERATE = 2, 3284 WMI_SCAN_DWELL_MODE_AGGRESSIVE = 3, 3285 WMI_SCAN_DWELL_MODE_STATIC = 4, 3286 }; 3287 3288 #define WMI_SCAN_SET_DWELL_MODE(flag, mode) \ 3289 ((flag) |= (((mode) << WMI_SCAN_DWELL_MODE_SHIFT) & \ 3290 WMI_SCAN_DWELL_MODE_MASK)) 3291 3292 struct hint_short_ssid { 3293 u32 freq_flags; 3294 u32 short_ssid; 3295 }; 3296 3297 struct hint_bssid { 3298 u32 freq_flags; 3299 struct wmi_mac_addr bssid; 3300 }; 3301 3302 struct scan_req_params { 3303 u32 scan_id; 3304 u32 scan_req_id; 3305 u32 vdev_id; 3306 u32 pdev_id; 3307 enum wmi_scan_priority scan_priority; 3308 union { 3309 struct { 3310 u32 scan_ev_started:1, 3311 scan_ev_completed:1, 3312 scan_ev_bss_chan:1, 3313 scan_ev_foreign_chan:1, 3314 scan_ev_dequeued:1, 3315 scan_ev_preempted:1, 3316 scan_ev_start_failed:1, 3317 scan_ev_restarted:1, 3318 scan_ev_foreign_chn_exit:1, 3319 scan_ev_invalid:1, 3320 scan_ev_gpio_timeout:1, 3321 scan_ev_suspended:1, 3322 scan_ev_resumed:1; 3323 }; 3324 u32 scan_events; 3325 }; 3326 u32 scan_ctrl_flags_ext; 3327 u32 dwell_time_active; 3328 u32 dwell_time_active_2g; 3329 u32 dwell_time_passive; 3330 u32 dwell_time_active_6g; 3331 u32 dwell_time_passive_6g; 3332 u32 min_rest_time; 3333 u32 max_rest_time; 3334 u32 repeat_probe_time; 3335 u32 probe_spacing_time; 3336 u32 idle_time; 3337 u32 max_scan_time; 3338 u32 probe_delay; 3339 union { 3340 struct { 3341 u32 scan_f_passive:1, 3342 scan_f_bcast_probe:1, 3343 scan_f_cck_rates:1, 3344 scan_f_ofdm_rates:1, 3345 scan_f_chan_stat_evnt:1, 3346 scan_f_filter_prb_req:1, 3347 scan_f_bypass_dfs_chn:1, 3348 scan_f_continue_on_err:1, 3349 scan_f_offchan_mgmt_tx:1, 3350 scan_f_offchan_data_tx:1, 3351 scan_f_promisc_mode:1, 3352 scan_f_capture_phy_err:1, 3353 scan_f_strict_passive_pch:1, 3354 scan_f_half_rate:1, 3355 scan_f_quarter_rate:1, 3356 scan_f_force_active_dfs_chn:1, 3357 scan_f_add_tpc_ie_in_probe:1, 3358 scan_f_add_ds_ie_in_probe:1, 3359 scan_f_add_spoofed_mac_in_probe:1, 3360 scan_f_add_rand_seq_in_probe:1, 3361 scan_f_en_ie_whitelist_in_probe:1, 3362 scan_f_forced:1, 3363 scan_f_2ghz:1, 3364 scan_f_5ghz:1, 3365 scan_f_80mhz:1; 3366 }; 3367 u32 scan_flags; 3368 }; 3369 enum scan_dwelltime_adaptive_mode adaptive_dwell_time_mode; 3370 u32 burst_duration; 3371 u32 num_chan; 3372 u32 num_bssid; 3373 u32 num_ssids; 3374 u32 n_probes; 3375 u32 *chan_list; 3376 u32 notify_scan_events; 3377 struct wlan_ssid ssid[WLAN_SCAN_PARAMS_MAX_SSID]; 3378 struct wmi_mac_addr bssid_list[WLAN_SCAN_PARAMS_MAX_BSSID]; 3379 struct element_info extraie; 3380 struct element_info htcap; 3381 struct element_info vhtcap; 3382 u32 num_hint_s_ssid; 3383 u32 num_hint_bssid; 3384 struct hint_short_ssid hint_s_ssid[WLAN_SCAN_MAX_HINT_S_SSID]; 3385 struct hint_bssid hint_bssid[WLAN_SCAN_MAX_HINT_BSSID]; 3386 struct wmi_mac_addr mac_addr; 3387 struct wmi_mac_addr mac_mask; 3388 }; 3389 3390 struct wmi_ssid_arg { 3391 int len; 3392 const u8 *ssid; 3393 }; 3394 3395 struct wmi_bssid_arg { 3396 const u8 *bssid; 3397 }; 3398 3399 struct wmi_start_scan_arg { 3400 u32 scan_id; 3401 u32 scan_req_id; 3402 u32 vdev_id; 3403 u32 scan_priority; 3404 u32 notify_scan_events; 3405 u32 dwell_time_active; 3406 u32 dwell_time_passive; 3407 u32 min_rest_time; 3408 u32 max_rest_time; 3409 u32 repeat_probe_time; 3410 u32 probe_spacing_time; 3411 u32 idle_time; 3412 u32 max_scan_time; 3413 u32 probe_delay; 3414 u32 scan_ctrl_flags; 3415 3416 u32 ie_len; 3417 u32 n_channels; 3418 u32 n_ssids; 3419 u32 n_bssids; 3420 3421 u8 ie[WLAN_SCAN_PARAMS_MAX_IE_LEN]; 3422 u32 channels[64]; 3423 struct wmi_ssid_arg ssids[WLAN_SCAN_PARAMS_MAX_SSID]; 3424 struct wmi_bssid_arg bssids[WLAN_SCAN_PARAMS_MAX_BSSID]; 3425 }; 3426 3427 #define WMI_SCAN_STOP_ONE 0x00000000 3428 #define WMI_SCN_STOP_VAP_ALL 0x01000000 3429 #define WMI_SCAN_STOP_ALL 0x04000000 3430 3431 /* Prefix 0xA000 indicates that the scan request 3432 * is trigger by HOST 3433 */ 3434 #define ATH11K_SCAN_ID 0xA000 3435 3436 enum scan_cancel_req_type { 3437 WLAN_SCAN_CANCEL_SINGLE = 1, 3438 WLAN_SCAN_CANCEL_VDEV_ALL, 3439 WLAN_SCAN_CANCEL_PDEV_ALL, 3440 }; 3441 3442 struct scan_cancel_param { 3443 u32 requester; 3444 u32 scan_id; 3445 enum scan_cancel_req_type req_type; 3446 u32 vdev_id; 3447 u32 pdev_id; 3448 }; 3449 3450 struct wmi_bcn_send_from_host_cmd { 3451 u32 tlv_header; 3452 u32 vdev_id; 3453 u32 data_len; 3454 union { 3455 u32 frag_ptr; 3456 u32 frag_ptr_lo; 3457 }; 3458 u32 frame_ctrl; 3459 u32 dtim_flag; 3460 u32 bcn_antenna; 3461 u32 frag_ptr_hi; 3462 }; 3463 3464 #define WMI_CHAN_INFO_MODE GENMASK(5, 0) 3465 #define WMI_CHAN_INFO_HT40_PLUS BIT(6) 3466 #define WMI_CHAN_INFO_PASSIVE BIT(7) 3467 #define WMI_CHAN_INFO_ADHOC_ALLOWED BIT(8) 3468 #define WMI_CHAN_INFO_AP_DISABLED BIT(9) 3469 #define WMI_CHAN_INFO_DFS BIT(10) 3470 #define WMI_CHAN_INFO_ALLOW_HT BIT(11) 3471 #define WMI_CHAN_INFO_ALLOW_VHT BIT(12) 3472 #define WMI_CHAN_INFO_CHAN_CHANGE_CAUSE_CSA BIT(13) 3473 #define WMI_CHAN_INFO_HALF_RATE BIT(14) 3474 #define WMI_CHAN_INFO_QUARTER_RATE BIT(15) 3475 #define WMI_CHAN_INFO_DFS_FREQ2 BIT(16) 3476 #define WMI_CHAN_INFO_ALLOW_HE BIT(17) 3477 #define WMI_CHAN_INFO_PSC BIT(18) 3478 3479 #define WMI_CHAN_REG_INFO1_MIN_PWR GENMASK(7, 0) 3480 #define WMI_CHAN_REG_INFO1_MAX_PWR GENMASK(15, 8) 3481 #define WMI_CHAN_REG_INFO1_MAX_REG_PWR GENMASK(23, 16) 3482 #define WMI_CHAN_REG_INFO1_REG_CLS GENMASK(31, 24) 3483 3484 #define WMI_CHAN_REG_INFO2_ANT_MAX GENMASK(7, 0) 3485 #define WMI_CHAN_REG_INFO2_MAX_TX_PWR GENMASK(15, 8) 3486 3487 struct wmi_channel { 3488 u32 tlv_header; 3489 u32 mhz; 3490 u32 band_center_freq1; 3491 u32 band_center_freq2; 3492 u32 info; 3493 u32 reg_info_1; 3494 u32 reg_info_2; 3495 } __packed; 3496 3497 struct wmi_mgmt_params { 3498 void *tx_frame; 3499 u16 frm_len; 3500 u8 vdev_id; 3501 u16 chanfreq; 3502 void *pdata; 3503 u16 desc_id; 3504 u8 *macaddr; 3505 }; 3506 3507 enum wmi_sta_ps_mode { 3508 WMI_STA_PS_MODE_DISABLED = 0, 3509 WMI_STA_PS_MODE_ENABLED = 1, 3510 }; 3511 3512 #define WMI_SMPS_MASK_LOWER_16BITS 0xFF 3513 #define WMI_SMPS_MASK_UPPER_3BITS 0x7 3514 #define WMI_SMPS_PARAM_VALUE_SHIFT 29 3515 3516 #define ATH11K_WMI_FW_HANG_ASSERT_TYPE 1 3517 #define ATH11K_WMI_FW_HANG_DELAY 0 3518 3519 /* type, 0:unused 1: ASSERT 2: not respond detect command 3520 * delay_time_ms, the simulate will delay time 3521 */ 3522 3523 struct wmi_force_fw_hang_cmd { 3524 u32 tlv_header; 3525 u32 type; 3526 u32 delay_time_ms; 3527 }; 3528 3529 struct wmi_vdev_set_param_cmd { 3530 u32 tlv_header; 3531 u32 vdev_id; 3532 u32 param_id; 3533 u32 param_value; 3534 } __packed; 3535 3536 enum wmi_stats_id { 3537 WMI_REQUEST_PEER_STAT = BIT(0), 3538 WMI_REQUEST_AP_STAT = BIT(1), 3539 WMI_REQUEST_PDEV_STAT = BIT(2), 3540 WMI_REQUEST_VDEV_STAT = BIT(3), 3541 WMI_REQUEST_BCNFLT_STAT = BIT(4), 3542 WMI_REQUEST_VDEV_RATE_STAT = BIT(5), 3543 WMI_REQUEST_INST_STAT = BIT(6), 3544 WMI_REQUEST_MIB_STAT = BIT(7), 3545 WMI_REQUEST_RSSI_PER_CHAIN_STAT = BIT(8), 3546 WMI_REQUEST_CONGESTION_STAT = BIT(9), 3547 WMI_REQUEST_PEER_EXTD_STAT = BIT(10), 3548 WMI_REQUEST_BCN_STAT = BIT(11), 3549 WMI_REQUEST_BCN_STAT_RESET = BIT(12), 3550 WMI_REQUEST_PEER_EXTD2_STAT = BIT(13), 3551 }; 3552 3553 struct wmi_request_stats_cmd { 3554 u32 tlv_header; 3555 enum wmi_stats_id stats_id; 3556 u32 vdev_id; 3557 struct wmi_mac_addr peer_macaddr; 3558 u32 pdev_id; 3559 } __packed; 3560 3561 struct wmi_get_pdev_temperature_cmd { 3562 u32 tlv_header; 3563 u32 param; 3564 u32 pdev_id; 3565 } __packed; 3566 3567 #define WMI_BEACON_TX_BUFFER_SIZE 512 3568 3569 struct wmi_bcn_tmpl_cmd { 3570 u32 tlv_header; 3571 u32 vdev_id; 3572 u32 tim_ie_offset; 3573 u32 buf_len; 3574 u32 csa_switch_count_offset; 3575 u32 ext_csa_switch_count_offset; 3576 u32 csa_event_bitmap; 3577 u32 mbssid_ie_offset; 3578 u32 esp_ie_offset; 3579 } __packed; 3580 3581 struct wmi_key_seq_counter { 3582 u32 key_seq_counter_l; 3583 u32 key_seq_counter_h; 3584 } __packed; 3585 3586 struct wmi_vdev_install_key_cmd { 3587 u32 tlv_header; 3588 u32 vdev_id; 3589 struct wmi_mac_addr peer_macaddr; 3590 u32 key_idx; 3591 u32 key_flags; 3592 u32 key_cipher; 3593 struct wmi_key_seq_counter key_rsc_counter; 3594 struct wmi_key_seq_counter key_global_rsc_counter; 3595 struct wmi_key_seq_counter key_tsc_counter; 3596 u8 wpi_key_rsc_counter[16]; 3597 u8 wpi_key_tsc_counter[16]; 3598 u32 key_len; 3599 u32 key_txmic_len; 3600 u32 key_rxmic_len; 3601 u32 is_group_key_id_valid; 3602 u32 group_key_id; 3603 3604 /* Followed by key_data containing key followed by 3605 * tx mic and then rx mic 3606 */ 3607 } __packed; 3608 3609 struct wmi_vdev_install_key_arg { 3610 u32 vdev_id; 3611 const u8 *macaddr; 3612 u32 key_idx; 3613 u32 key_flags; 3614 u32 key_cipher; 3615 u32 key_len; 3616 u32 key_txmic_len; 3617 u32 key_rxmic_len; 3618 u64 key_rsc_counter; 3619 const void *key_data; 3620 }; 3621 3622 #define WMI_MAX_SUPPORTED_RATES 128 3623 #define WMI_HOST_MAX_HECAP_PHY_SIZE 3 3624 #define WMI_HOST_MAX_HE_RATE_SET 3 3625 #define WMI_HECAP_TXRX_MCS_NSS_IDX_80 0 3626 #define WMI_HECAP_TXRX_MCS_NSS_IDX_160 1 3627 #define WMI_HECAP_TXRX_MCS_NSS_IDX_80_80 2 3628 3629 struct wmi_rate_set_arg { 3630 u32 num_rates; 3631 u8 rates[WMI_MAX_SUPPORTED_RATES]; 3632 }; 3633 3634 struct peer_assoc_params { 3635 struct wmi_mac_addr peer_macaddr; 3636 u32 vdev_id; 3637 u32 peer_new_assoc; 3638 u32 peer_associd; 3639 u32 peer_flags; 3640 u32 peer_caps; 3641 u32 peer_listen_intval; 3642 u32 peer_ht_caps; 3643 u32 peer_max_mpdu; 3644 u32 peer_mpdu_density; 3645 u32 peer_rate_caps; 3646 u32 peer_nss; 3647 u32 peer_vht_caps; 3648 u32 peer_phymode; 3649 u32 peer_ht_info[2]; 3650 struct wmi_rate_set_arg peer_legacy_rates; 3651 struct wmi_rate_set_arg peer_ht_rates; 3652 u32 rx_max_rate; 3653 u32 rx_mcs_set; 3654 u32 tx_max_rate; 3655 u32 tx_mcs_set; 3656 u8 vht_capable; 3657 u8 min_data_rate; 3658 u32 tx_max_mcs_nss; 3659 u32 peer_bw_rxnss_override; 3660 bool is_pmf_enabled; 3661 bool is_wme_set; 3662 bool qos_flag; 3663 bool apsd_flag; 3664 bool ht_flag; 3665 bool bw_40; 3666 bool bw_80; 3667 bool bw_160; 3668 bool stbc_flag; 3669 bool ldpc_flag; 3670 bool static_mimops_flag; 3671 bool dynamic_mimops_flag; 3672 bool spatial_mux_flag; 3673 bool vht_flag; 3674 bool vht_ng_flag; 3675 bool need_ptk_4_way; 3676 bool need_gtk_2_way; 3677 bool auth_flag; 3678 bool safe_mode_enabled; 3679 bool amsdu_disable; 3680 /* Use common structure */ 3681 u8 peer_mac[ETH_ALEN]; 3682 3683 bool he_flag; 3684 u32 peer_he_cap_macinfo[2]; 3685 u32 peer_he_cap_macinfo_internal; 3686 u32 peer_he_caps_6ghz; 3687 u32 peer_he_ops; 3688 u32 peer_he_cap_phyinfo[WMI_HOST_MAX_HECAP_PHY_SIZE]; 3689 u32 peer_he_mcs_count; 3690 u32 peer_he_rx_mcs_set[WMI_HOST_MAX_HE_RATE_SET]; 3691 u32 peer_he_tx_mcs_set[WMI_HOST_MAX_HE_RATE_SET]; 3692 bool twt_responder; 3693 bool twt_requester; 3694 bool is_assoc; 3695 struct ath11k_ppe_threshold peer_ppet; 3696 }; 3697 3698 struct wmi_peer_assoc_complete_cmd { 3699 u32 tlv_header; 3700 struct wmi_mac_addr peer_macaddr; 3701 u32 vdev_id; 3702 u32 peer_new_assoc; 3703 u32 peer_associd; 3704 u32 peer_flags; 3705 u32 peer_caps; 3706 u32 peer_listen_intval; 3707 u32 peer_ht_caps; 3708 u32 peer_max_mpdu; 3709 u32 peer_mpdu_density; 3710 u32 peer_rate_caps; 3711 u32 peer_nss; 3712 u32 peer_vht_caps; 3713 u32 peer_phymode; 3714 u32 peer_ht_info[2]; 3715 u32 num_peer_legacy_rates; 3716 u32 num_peer_ht_rates; 3717 u32 peer_bw_rxnss_override; 3718 struct wmi_ppe_threshold peer_ppet; 3719 u32 peer_he_cap_info; 3720 u32 peer_he_ops; 3721 u32 peer_he_cap_phy[WMI_MAX_HECAP_PHY_SIZE]; 3722 u32 peer_he_mcs; 3723 u32 peer_he_cap_info_ext; 3724 u32 peer_he_cap_info_internal; 3725 u32 min_data_rate; 3726 u32 peer_he_caps_6ghz; 3727 } __packed; 3728 3729 struct wmi_stop_scan_cmd { 3730 u32 tlv_header; 3731 u32 requestor; 3732 u32 scan_id; 3733 u32 req_type; 3734 u32 vdev_id; 3735 u32 pdev_id; 3736 }; 3737 3738 struct scan_chan_list_params { 3739 u32 pdev_id; 3740 u16 nallchans; 3741 struct channel_param ch_param[]; 3742 }; 3743 3744 struct wmi_scan_chan_list_cmd { 3745 u32 tlv_header; 3746 u32 num_scan_chans; 3747 u32 flags; 3748 u32 pdev_id; 3749 } __packed; 3750 3751 struct wmi_scan_prob_req_oui_cmd { 3752 u32 tlv_header; 3753 u32 prob_req_oui; 3754 } __packed; 3755 3756 #define WMI_MGMT_SEND_DOWNLD_LEN 64 3757 3758 #define WMI_TX_PARAMS_DWORD0_POWER GENMASK(7, 0) 3759 #define WMI_TX_PARAMS_DWORD0_MCS_MASK GENMASK(19, 8) 3760 #define WMI_TX_PARAMS_DWORD0_NSS_MASK GENMASK(27, 20) 3761 #define WMI_TX_PARAMS_DWORD0_RETRY_LIMIT GENMASK(31, 28) 3762 3763 #define WMI_TX_PARAMS_DWORD1_CHAIN_MASK GENMASK(7, 0) 3764 #define WMI_TX_PARAMS_DWORD1_BW_MASK GENMASK(14, 8) 3765 #define WMI_TX_PARAMS_DWORD1_PREAMBLE_TYPE GENMASK(19, 15) 3766 #define WMI_TX_PARAMS_DWORD1_FRAME_TYPE BIT(20) 3767 #define WMI_TX_PARAMS_DWORD1_RSVD GENMASK(31, 21) 3768 3769 struct wmi_mgmt_send_params { 3770 u32 tlv_header; 3771 u32 tx_params_dword0; 3772 u32 tx_params_dword1; 3773 }; 3774 3775 struct wmi_mgmt_send_cmd { 3776 u32 tlv_header; 3777 u32 vdev_id; 3778 u32 desc_id; 3779 u32 chanfreq; 3780 u32 paddr_lo; 3781 u32 paddr_hi; 3782 u32 frame_len; 3783 u32 buf_len; 3784 u32 tx_params_valid; 3785 3786 /* This TLV is followed by struct wmi_mgmt_frame */ 3787 3788 /* Followed by struct wmi_mgmt_send_params */ 3789 } __packed; 3790 3791 struct wmi_sta_powersave_mode_cmd { 3792 u32 tlv_header; 3793 u32 vdev_id; 3794 u32 sta_ps_mode; 3795 }; 3796 3797 struct wmi_sta_smps_force_mode_cmd { 3798 u32 tlv_header; 3799 u32 vdev_id; 3800 u32 forced_mode; 3801 }; 3802 3803 struct wmi_sta_smps_param_cmd { 3804 u32 tlv_header; 3805 u32 vdev_id; 3806 u32 param; 3807 u32 value; 3808 }; 3809 3810 struct wmi_bcn_prb_info { 3811 u32 tlv_header; 3812 u32 caps; 3813 u32 erp; 3814 } __packed; 3815 3816 enum { 3817 WMI_PDEV_SUSPEND, 3818 WMI_PDEV_SUSPEND_AND_DISABLE_INTR, 3819 }; 3820 3821 struct green_ap_ps_params { 3822 u32 value; 3823 }; 3824 3825 struct wmi_pdev_green_ap_ps_enable_cmd_param { 3826 u32 tlv_header; 3827 u32 pdev_id; 3828 u32 enable; 3829 }; 3830 3831 struct ap_ps_params { 3832 u32 vdev_id; 3833 u32 param; 3834 u32 value; 3835 }; 3836 3837 struct vdev_set_params { 3838 u32 if_id; 3839 u32 param_id; 3840 u32 param_value; 3841 }; 3842 3843 struct stats_request_params { 3844 u32 stats_id; 3845 u32 vdev_id; 3846 u32 pdev_id; 3847 }; 3848 3849 struct wmi_set_current_country_params { 3850 u8 alpha2[3]; 3851 }; 3852 3853 struct wmi_set_current_country_cmd { 3854 u32 tlv_header; 3855 u32 pdev_id; 3856 u32 new_alpha2; 3857 } __packed; 3858 3859 enum set_init_cc_type { 3860 WMI_COUNTRY_INFO_TYPE_ALPHA, 3861 WMI_COUNTRY_INFO_TYPE_COUNTRY_CODE, 3862 WMI_COUNTRY_INFO_TYPE_REGDOMAIN, 3863 }; 3864 3865 enum set_init_cc_flags { 3866 INVALID_CC, 3867 CC_IS_SET, 3868 REGDMN_IS_SET, 3869 ALPHA_IS_SET, 3870 }; 3871 3872 struct wmi_init_country_params { 3873 union { 3874 u16 country_code; 3875 u16 regdom_id; 3876 u8 alpha2[3]; 3877 } cc_info; 3878 enum set_init_cc_flags flags; 3879 }; 3880 3881 struct wmi_init_country_cmd { 3882 u32 tlv_header; 3883 u32 pdev_id; 3884 u32 init_cc_type; 3885 union { 3886 u32 country_code; 3887 u32 regdom_id; 3888 u32 alpha2; 3889 } cc_info; 3890 } __packed; 3891 3892 struct wmi_11d_scan_start_params { 3893 u32 vdev_id; 3894 u32 scan_period_msec; 3895 u32 start_interval_msec; 3896 }; 3897 3898 struct wmi_11d_scan_start_cmd { 3899 u32 tlv_header; 3900 u32 vdev_id; 3901 u32 scan_period_msec; 3902 u32 start_interval_msec; 3903 } __packed; 3904 3905 struct wmi_11d_scan_stop_cmd { 3906 u32 tlv_header; 3907 u32 vdev_id; 3908 } __packed; 3909 3910 struct wmi_11d_new_cc_ev { 3911 u32 new_alpha2; 3912 } __packed; 3913 3914 #define THERMAL_LEVELS 1 3915 struct tt_level_config { 3916 u32 tmplwm; 3917 u32 tmphwm; 3918 u32 dcoffpercent; 3919 u32 priority; 3920 }; 3921 3922 struct thermal_mitigation_params { 3923 u32 pdev_id; 3924 u32 enable; 3925 u32 dc; 3926 u32 dc_per_event; 3927 struct tt_level_config levelconf[THERMAL_LEVELS]; 3928 }; 3929 3930 struct wmi_therm_throt_config_request_cmd { 3931 u32 tlv_header; 3932 u32 pdev_id; 3933 u32 enable; 3934 u32 dc; 3935 u32 dc_per_event; 3936 u32 therm_throt_levels; 3937 } __packed; 3938 3939 struct wmi_therm_throt_level_config_info { 3940 u32 tlv_header; 3941 u32 temp_lwm; 3942 u32 temp_hwm; 3943 u32 dc_off_percent; 3944 u32 prio; 3945 } __packed; 3946 3947 struct wmi_delba_send_cmd { 3948 u32 tlv_header; 3949 u32 vdev_id; 3950 struct wmi_mac_addr peer_macaddr; 3951 u32 tid; 3952 u32 initiator; 3953 u32 reasoncode; 3954 } __packed; 3955 3956 struct wmi_addba_setresponse_cmd { 3957 u32 tlv_header; 3958 u32 vdev_id; 3959 struct wmi_mac_addr peer_macaddr; 3960 u32 tid; 3961 u32 statuscode; 3962 } __packed; 3963 3964 struct wmi_addba_send_cmd { 3965 u32 tlv_header; 3966 u32 vdev_id; 3967 struct wmi_mac_addr peer_macaddr; 3968 u32 tid; 3969 u32 buffersize; 3970 } __packed; 3971 3972 struct wmi_addba_clear_resp_cmd { 3973 u32 tlv_header; 3974 u32 vdev_id; 3975 struct wmi_mac_addr peer_macaddr; 3976 } __packed; 3977 3978 struct wmi_pdev_pktlog_filter_info { 3979 u32 tlv_header; 3980 struct wmi_mac_addr peer_macaddr; 3981 } __packed; 3982 3983 struct wmi_pdev_pktlog_filter_cmd { 3984 u32 tlv_header; 3985 u32 pdev_id; 3986 u32 enable; 3987 u32 filter_type; 3988 u32 num_mac; 3989 } __packed; 3990 3991 enum ath11k_wmi_pktlog_enable { 3992 ATH11K_WMI_PKTLOG_ENABLE_AUTO = 0, 3993 ATH11K_WMI_PKTLOG_ENABLE_FORCE = 1, 3994 }; 3995 3996 struct wmi_pktlog_enable_cmd { 3997 u32 tlv_header; 3998 u32 pdev_id; 3999 u32 evlist; /* WMI_PKTLOG_EVENT */ 4000 u32 enable; 4001 } __packed; 4002 4003 struct wmi_pktlog_disable_cmd { 4004 u32 tlv_header; 4005 u32 pdev_id; 4006 } __packed; 4007 4008 #define DFS_PHYERR_UNIT_TEST_CMD 0 4009 #define DFS_UNIT_TEST_MODULE 0x2b 4010 #define DFS_UNIT_TEST_TOKEN 0xAA 4011 4012 enum dfs_test_args_idx { 4013 DFS_TEST_CMDID = 0, 4014 DFS_TEST_PDEV_ID, 4015 DFS_TEST_RADAR_PARAM, 4016 DFS_MAX_TEST_ARGS, 4017 }; 4018 4019 struct wmi_dfs_unit_test_arg { 4020 u32 cmd_id; 4021 u32 pdev_id; 4022 u32 radar_param; 4023 }; 4024 4025 struct wmi_unit_test_cmd { 4026 u32 tlv_header; 4027 u32 vdev_id; 4028 u32 module_id; 4029 u32 num_args; 4030 u32 diag_token; 4031 /* Followed by test args*/ 4032 } __packed; 4033 4034 #define MAX_SUPPORTED_RATES 128 4035 4036 #define WMI_PEER_AUTH 0x00000001 4037 #define WMI_PEER_QOS 0x00000002 4038 #define WMI_PEER_NEED_PTK_4_WAY 0x00000004 4039 #define WMI_PEER_NEED_GTK_2_WAY 0x00000010 4040 #define WMI_PEER_HE 0x00000400 4041 #define WMI_PEER_APSD 0x00000800 4042 #define WMI_PEER_HT 0x00001000 4043 #define WMI_PEER_40MHZ 0x00002000 4044 #define WMI_PEER_STBC 0x00008000 4045 #define WMI_PEER_LDPC 0x00010000 4046 #define WMI_PEER_DYN_MIMOPS 0x00020000 4047 #define WMI_PEER_STATIC_MIMOPS 0x00040000 4048 #define WMI_PEER_SPATIAL_MUX 0x00200000 4049 #define WMI_PEER_TWT_REQ 0x00400000 4050 #define WMI_PEER_TWT_RESP 0x00800000 4051 #define WMI_PEER_VHT 0x02000000 4052 #define WMI_PEER_80MHZ 0x04000000 4053 #define WMI_PEER_PMF 0x08000000 4054 /* TODO: Place holder for WLAN_PEER_F_PS_PRESEND_REQUIRED = 0x10000000. 4055 * Need to be cleaned up 4056 */ 4057 #define WMI_PEER_IS_P2P_CAPABLE 0x20000000 4058 #define WMI_PEER_160MHZ 0x40000000 4059 #define WMI_PEER_SAFEMODE_EN 0x80000000 4060 4061 struct beacon_tmpl_params { 4062 u8 vdev_id; 4063 u32 tim_ie_offset; 4064 u32 tmpl_len; 4065 u32 tmpl_len_aligned; 4066 u32 csa_switch_count_offset; 4067 u32 ext_csa_switch_count_offset; 4068 u8 *frm; 4069 }; 4070 4071 struct wmi_rate_set { 4072 u32 num_rates; 4073 u32 rates[(MAX_SUPPORTED_RATES / 4) + 1]; 4074 }; 4075 4076 struct wmi_vht_rate_set { 4077 u32 tlv_header; 4078 u32 rx_max_rate; 4079 u32 rx_mcs_set; 4080 u32 tx_max_rate; 4081 u32 tx_mcs_set; 4082 u32 tx_max_mcs_nss; 4083 } __packed; 4084 4085 struct wmi_he_rate_set { 4086 u32 tlv_header; 4087 4088 /* MCS at which the peer can receive */ 4089 u32 rx_mcs_set; 4090 4091 /* MCS at which the peer can transmit */ 4092 u32 tx_mcs_set; 4093 } __packed; 4094 4095 #define MAX_REG_RULES 10 4096 #define REG_ALPHA2_LEN 2 4097 #define MAX_6GHZ_REG_RULES 5 4098 4099 enum wmi_start_event_param { 4100 WMI_VDEV_START_RESP_EVENT = 0, 4101 WMI_VDEV_RESTART_RESP_EVENT, 4102 }; 4103 4104 struct wmi_vdev_start_resp_event { 4105 u32 vdev_id; 4106 u32 requestor_id; 4107 enum wmi_start_event_param resp_type; 4108 u32 status; 4109 u32 chain_mask; 4110 u32 smps_mode; 4111 union { 4112 u32 mac_id; 4113 u32 pdev_id; 4114 }; 4115 u32 cfgd_tx_streams; 4116 u32 cfgd_rx_streams; 4117 } __packed; 4118 4119 /* VDEV start response status codes */ 4120 enum wmi_vdev_start_resp_status_code { 4121 WMI_VDEV_START_RESPONSE_STATUS_SUCCESS = 0, 4122 WMI_VDEV_START_RESPONSE_INVALID_VDEVID = 1, 4123 WMI_VDEV_START_RESPONSE_NOT_SUPPORTED = 2, 4124 WMI_VDEV_START_RESPONSE_DFS_VIOLATION = 3, 4125 WMI_VDEV_START_RESPONSE_INVALID_REGDOMAIN = 4, 4126 }; 4127 4128 /* Regaulatory Rule Flags Passed by FW */ 4129 #define REGULATORY_CHAN_DISABLED BIT(0) 4130 #define REGULATORY_CHAN_NO_IR BIT(1) 4131 #define REGULATORY_CHAN_RADAR BIT(3) 4132 #define REGULATORY_CHAN_NO_OFDM BIT(6) 4133 #define REGULATORY_CHAN_INDOOR_ONLY BIT(9) 4134 4135 #define REGULATORY_CHAN_NO_HT40 BIT(4) 4136 #define REGULATORY_CHAN_NO_80MHZ BIT(7) 4137 #define REGULATORY_CHAN_NO_160MHZ BIT(8) 4138 #define REGULATORY_CHAN_NO_20MHZ BIT(11) 4139 #define REGULATORY_CHAN_NO_10MHZ BIT(12) 4140 4141 enum wmi_reg_chan_list_cmd_type { 4142 WMI_REG_CHAN_LIST_CC_ID = 0, 4143 WMI_REG_CHAN_LIST_CC_EXT_ID = 1, 4144 }; 4145 4146 enum wmi_reg_cc_setting_code { 4147 WMI_REG_SET_CC_STATUS_PASS = 0, 4148 WMI_REG_CURRENT_ALPHA2_NOT_FOUND = 1, 4149 WMI_REG_INIT_ALPHA2_NOT_FOUND = 2, 4150 WMI_REG_SET_CC_CHANGE_NOT_ALLOWED = 3, 4151 WMI_REG_SET_CC_STATUS_NO_MEMORY = 4, 4152 WMI_REG_SET_CC_STATUS_FAIL = 5, 4153 4154 /* add new setting code above, update in 4155 * @enum cc_setting_code as well. 4156 * Also handle it in ath11k_wmi_cc_setting_code_to_reg() 4157 */ 4158 }; 4159 4160 enum cc_setting_code { 4161 REG_SET_CC_STATUS_PASS = 0, 4162 REG_CURRENT_ALPHA2_NOT_FOUND = 1, 4163 REG_INIT_ALPHA2_NOT_FOUND = 2, 4164 REG_SET_CC_CHANGE_NOT_ALLOWED = 3, 4165 REG_SET_CC_STATUS_NO_MEMORY = 4, 4166 REG_SET_CC_STATUS_FAIL = 5, 4167 4168 /* add new setting code above, update in 4169 * @enum wmi_reg_cc_setting_code as well. 4170 * Also handle it in ath11k_cc_status_to_str() 4171 */ 4172 }; 4173 4174 static inline enum cc_setting_code 4175 ath11k_wmi_cc_setting_code_to_reg(enum wmi_reg_cc_setting_code status_code) 4176 { 4177 switch (status_code) { 4178 case WMI_REG_SET_CC_STATUS_PASS: 4179 return REG_SET_CC_STATUS_PASS; 4180 case WMI_REG_CURRENT_ALPHA2_NOT_FOUND: 4181 return REG_CURRENT_ALPHA2_NOT_FOUND; 4182 case WMI_REG_INIT_ALPHA2_NOT_FOUND: 4183 return REG_INIT_ALPHA2_NOT_FOUND; 4184 case WMI_REG_SET_CC_CHANGE_NOT_ALLOWED: 4185 return REG_SET_CC_CHANGE_NOT_ALLOWED; 4186 case WMI_REG_SET_CC_STATUS_NO_MEMORY: 4187 return REG_SET_CC_STATUS_NO_MEMORY; 4188 case WMI_REG_SET_CC_STATUS_FAIL: 4189 return REG_SET_CC_STATUS_FAIL; 4190 } 4191 4192 return REG_SET_CC_STATUS_FAIL; 4193 } 4194 4195 static inline const char *ath11k_cc_status_to_str(enum cc_setting_code code) 4196 { 4197 switch (code) { 4198 case REG_SET_CC_STATUS_PASS: 4199 return "REG_SET_CC_STATUS_PASS"; 4200 case REG_CURRENT_ALPHA2_NOT_FOUND: 4201 return "REG_CURRENT_ALPHA2_NOT_FOUND"; 4202 case REG_INIT_ALPHA2_NOT_FOUND: 4203 return "REG_INIT_ALPHA2_NOT_FOUND"; 4204 case REG_SET_CC_CHANGE_NOT_ALLOWED: 4205 return "REG_SET_CC_CHANGE_NOT_ALLOWED"; 4206 case REG_SET_CC_STATUS_NO_MEMORY: 4207 return "REG_SET_CC_STATUS_NO_MEMORY"; 4208 case REG_SET_CC_STATUS_FAIL: 4209 return "REG_SET_CC_STATUS_FAIL"; 4210 } 4211 4212 return "Unknown CC status"; 4213 } 4214 4215 enum wmi_reg_6ghz_ap_type { 4216 WMI_REG_INDOOR_AP = 0, 4217 WMI_REG_STANDARD_POWER_AP = 1, 4218 WMI_REG_VERY_LOW_POWER_AP = 2, 4219 4220 /* add AP type above, handle in ath11k_6ghz_ap_type_to_str() 4221 */ 4222 WMI_REG_CURRENT_MAX_AP_TYPE, 4223 WMI_REG_MAX_AP_TYPE = 7, 4224 }; 4225 4226 static inline const char * 4227 ath11k_6ghz_ap_type_to_str(enum wmi_reg_6ghz_ap_type type) 4228 { 4229 switch (type) { 4230 case WMI_REG_INDOOR_AP: 4231 return "INDOOR AP"; 4232 case WMI_REG_STANDARD_POWER_AP: 4233 return "STANDARD POWER AP"; 4234 case WMI_REG_VERY_LOW_POWER_AP: 4235 return "VERY LOW POWER AP"; 4236 case WMI_REG_CURRENT_MAX_AP_TYPE: 4237 return "CURRENT_MAX_AP_TYPE"; 4238 case WMI_REG_MAX_AP_TYPE: 4239 return "MAX_AP_TYPE"; 4240 } 4241 4242 return "unknown 6 GHz AP type"; 4243 } 4244 4245 enum wmi_reg_6ghz_client_type { 4246 WMI_REG_DEFAULT_CLIENT = 0, 4247 WMI_REG_SUBORDINATE_CLIENT = 1, 4248 WMI_REG_MAX_CLIENT_TYPE = 2, 4249 4250 /* add client type above, handle it in 4251 * ath11k_6ghz_client_type_to_str() 4252 */ 4253 }; 4254 4255 static inline const char * 4256 ath11k_6ghz_client_type_to_str(enum wmi_reg_6ghz_client_type type) 4257 { 4258 switch (type) { 4259 case WMI_REG_DEFAULT_CLIENT: 4260 return "DEFAULT CLIENT"; 4261 case WMI_REG_SUBORDINATE_CLIENT: 4262 return "SUBORDINATE CLIENT"; 4263 case WMI_REG_MAX_CLIENT_TYPE: 4264 return "MAX_CLIENT_TYPE"; 4265 } 4266 4267 return "unknown 6 GHz client type"; 4268 } 4269 4270 enum reg_subdomains_6ghz { 4271 EMPTY_6GHZ = 0x0, 4272 FCC1_CLIENT_LPI_REGULAR_6GHZ = 0x01, 4273 FCC1_CLIENT_SP_6GHZ = 0x02, 4274 FCC1_AP_LPI_6GHZ = 0x03, 4275 FCC1_CLIENT_LPI_SUBORDINATE = FCC1_AP_LPI_6GHZ, 4276 FCC1_AP_SP_6GHZ = 0x04, 4277 ETSI1_LPI_6GHZ = 0x10, 4278 ETSI1_VLP_6GHZ = 0x11, 4279 ETSI2_LPI_6GHZ = 0x12, 4280 ETSI2_VLP_6GHZ = 0x13, 4281 APL1_LPI_6GHZ = 0x20, 4282 APL1_VLP_6GHZ = 0x21, 4283 4284 /* add sub-domain above, handle it in 4285 * ath11k_sub_reg_6ghz_to_str() 4286 */ 4287 }; 4288 4289 static inline const char * 4290 ath11k_sub_reg_6ghz_to_str(enum reg_subdomains_6ghz sub_id) 4291 { 4292 switch (sub_id) { 4293 case EMPTY_6GHZ: 4294 return "N/A"; 4295 case FCC1_CLIENT_LPI_REGULAR_6GHZ: 4296 return "FCC1_CLIENT_LPI_REGULAR_6GHZ"; 4297 case FCC1_CLIENT_SP_6GHZ: 4298 return "FCC1_CLIENT_SP_6GHZ"; 4299 case FCC1_AP_LPI_6GHZ: 4300 return "FCC1_AP_LPI_6GHZ/FCC1_CLIENT_LPI_SUBORDINATE"; 4301 case FCC1_AP_SP_6GHZ: 4302 return "FCC1_AP_SP_6GHZ"; 4303 case ETSI1_LPI_6GHZ: 4304 return "ETSI1_LPI_6GHZ"; 4305 case ETSI1_VLP_6GHZ: 4306 return "ETSI1_VLP_6GHZ"; 4307 case ETSI2_LPI_6GHZ: 4308 return "ETSI2_LPI_6GHZ"; 4309 case ETSI2_VLP_6GHZ: 4310 return "ETSI2_VLP_6GHZ"; 4311 case APL1_LPI_6GHZ: 4312 return "APL1_LPI_6GHZ"; 4313 case APL1_VLP_6GHZ: 4314 return "APL1_VLP_6GHZ"; 4315 } 4316 4317 return "unknown sub reg id"; 4318 } 4319 4320 enum reg_super_domain_6ghz { 4321 FCC1_6GHZ = 0x01, 4322 ETSI1_6GHZ = 0x02, 4323 ETSI2_6GHZ = 0x03, 4324 APL1_6GHZ = 0x04, 4325 FCC1_6GHZ_CL = 0x05, 4326 4327 /* add super domain above, handle it in 4328 * ath11k_super_reg_6ghz_to_str() 4329 */ 4330 }; 4331 4332 static inline const char * 4333 ath11k_super_reg_6ghz_to_str(enum reg_super_domain_6ghz domain_id) 4334 { 4335 switch (domain_id) { 4336 case FCC1_6GHZ: 4337 return "FCC1_6GHZ"; 4338 case ETSI1_6GHZ: 4339 return "ETSI1_6GHZ"; 4340 case ETSI2_6GHZ: 4341 return "ETSI2_6GHZ"; 4342 case APL1_6GHZ: 4343 return "APL1_6GHZ"; 4344 case FCC1_6GHZ_CL: 4345 return "FCC1_6GHZ_CL"; 4346 } 4347 4348 return "unknown domain id"; 4349 } 4350 4351 struct cur_reg_rule { 4352 u16 start_freq; 4353 u16 end_freq; 4354 u16 max_bw; 4355 u8 reg_power; 4356 u8 ant_gain; 4357 u16 flags; 4358 bool psd_flag; 4359 s8 psd_eirp; 4360 }; 4361 4362 struct cur_regulatory_info { 4363 enum cc_setting_code status_code; 4364 u8 num_phy; 4365 u8 phy_id; 4366 u16 reg_dmn_pair; 4367 u16 ctry_code; 4368 u8 alpha2[REG_ALPHA2_LEN + 1]; 4369 u32 dfs_region; 4370 u32 phybitmap; 4371 u32 min_bw_2ghz; 4372 u32 max_bw_2ghz; 4373 u32 min_bw_5ghz; 4374 u32 max_bw_5ghz; 4375 u32 num_2ghz_reg_rules; 4376 u32 num_5ghz_reg_rules; 4377 struct cur_reg_rule *reg_rules_2ghz_ptr; 4378 struct cur_reg_rule *reg_rules_5ghz_ptr; 4379 bool is_ext_reg_event; 4380 enum wmi_reg_6ghz_client_type client_type; 4381 bool rnr_tpe_usable; 4382 bool unspecified_ap_usable; 4383 u8 domain_code_6ghz_ap[WMI_REG_CURRENT_MAX_AP_TYPE]; 4384 u8 domain_code_6ghz_client[WMI_REG_CURRENT_MAX_AP_TYPE][WMI_REG_MAX_CLIENT_TYPE]; 4385 u32 domain_code_6ghz_super_id; 4386 u32 min_bw_6ghz_ap[WMI_REG_CURRENT_MAX_AP_TYPE]; 4387 u32 max_bw_6ghz_ap[WMI_REG_CURRENT_MAX_AP_TYPE]; 4388 u32 min_bw_6ghz_client[WMI_REG_CURRENT_MAX_AP_TYPE][WMI_REG_MAX_CLIENT_TYPE]; 4389 u32 max_bw_6ghz_client[WMI_REG_CURRENT_MAX_AP_TYPE][WMI_REG_MAX_CLIENT_TYPE]; 4390 u32 num_6ghz_rules_ap[WMI_REG_CURRENT_MAX_AP_TYPE]; 4391 u32 num_6ghz_rules_client[WMI_REG_CURRENT_MAX_AP_TYPE][WMI_REG_MAX_CLIENT_TYPE]; 4392 struct cur_reg_rule *reg_rules_6ghz_ap_ptr[WMI_REG_CURRENT_MAX_AP_TYPE]; 4393 struct cur_reg_rule *reg_rules_6ghz_client_ptr 4394 [WMI_REG_CURRENT_MAX_AP_TYPE][WMI_REG_MAX_CLIENT_TYPE]; 4395 }; 4396 4397 struct wmi_reg_chan_list_cc_event { 4398 u32 status_code; 4399 u32 phy_id; 4400 u32 alpha2; 4401 u32 num_phy; 4402 u32 country_id; 4403 u32 domain_code; 4404 u32 dfs_region; 4405 u32 phybitmap; 4406 u32 min_bw_2ghz; 4407 u32 max_bw_2ghz; 4408 u32 min_bw_5ghz; 4409 u32 max_bw_5ghz; 4410 u32 num_2ghz_reg_rules; 4411 u32 num_5ghz_reg_rules; 4412 } __packed; 4413 4414 struct wmi_regulatory_rule_struct { 4415 u32 tlv_header; 4416 u32 freq_info; 4417 u32 bw_pwr_info; 4418 u32 flag_info; 4419 }; 4420 4421 #define WMI_REG_CLIENT_MAX 4 4422 4423 struct wmi_reg_chan_list_cc_ext_event { 4424 u32 status_code; 4425 u32 phy_id; 4426 u32 alpha2; 4427 u32 num_phy; 4428 u32 country_id; 4429 u32 domain_code; 4430 u32 dfs_region; 4431 u32 phybitmap; 4432 u32 min_bw_2ghz; 4433 u32 max_bw_2ghz; 4434 u32 min_bw_5ghz; 4435 u32 max_bw_5ghz; 4436 u32 num_2ghz_reg_rules; 4437 u32 num_5ghz_reg_rules; 4438 u32 client_type; 4439 u32 rnr_tpe_usable; 4440 u32 unspecified_ap_usable; 4441 u32 domain_code_6ghz_ap_lpi; 4442 u32 domain_code_6ghz_ap_sp; 4443 u32 domain_code_6ghz_ap_vlp; 4444 u32 domain_code_6ghz_client_lpi[WMI_REG_CLIENT_MAX]; 4445 u32 domain_code_6ghz_client_sp[WMI_REG_CLIENT_MAX]; 4446 u32 domain_code_6ghz_client_vlp[WMI_REG_CLIENT_MAX]; 4447 u32 domain_code_6ghz_super_id; 4448 u32 min_bw_6ghz_ap_sp; 4449 u32 max_bw_6ghz_ap_sp; 4450 u32 min_bw_6ghz_ap_lpi; 4451 u32 max_bw_6ghz_ap_lpi; 4452 u32 min_bw_6ghz_ap_vlp; 4453 u32 max_bw_6ghz_ap_vlp; 4454 u32 min_bw_6ghz_client_sp[WMI_REG_CLIENT_MAX]; 4455 u32 max_bw_6ghz_client_sp[WMI_REG_CLIENT_MAX]; 4456 u32 min_bw_6ghz_client_lpi[WMI_REG_CLIENT_MAX]; 4457 u32 max_bw_6ghz_client_lpi[WMI_REG_CLIENT_MAX]; 4458 u32 min_bw_6ghz_client_vlp[WMI_REG_CLIENT_MAX]; 4459 u32 max_bw_6ghz_client_vlp[WMI_REG_CLIENT_MAX]; 4460 u32 num_6ghz_reg_rules_ap_sp; 4461 u32 num_6ghz_reg_rules_ap_lpi; 4462 u32 num_6ghz_reg_rules_ap_vlp; 4463 u32 num_6ghz_reg_rules_client_sp[WMI_REG_CLIENT_MAX]; 4464 u32 num_6ghz_reg_rules_client_lpi[WMI_REG_CLIENT_MAX]; 4465 u32 num_6ghz_reg_rules_client_vlp[WMI_REG_CLIENT_MAX]; 4466 } __packed; 4467 4468 struct wmi_regulatory_ext_rule { 4469 u32 tlv_header; 4470 u32 freq_info; 4471 u32 bw_pwr_info; 4472 u32 flag_info; 4473 u32 psd_power_info; 4474 } __packed; 4475 4476 struct wmi_vdev_delete_resp_event { 4477 u32 vdev_id; 4478 } __packed; 4479 4480 struct wmi_peer_delete_resp_event { 4481 u32 vdev_id; 4482 struct wmi_mac_addr peer_macaddr; 4483 } __packed; 4484 4485 struct wmi_bcn_tx_status_event { 4486 u32 vdev_id; 4487 u32 tx_status; 4488 } __packed; 4489 4490 struct wmi_vdev_stopped_event { 4491 u32 vdev_id; 4492 } __packed; 4493 4494 struct wmi_pdev_bss_chan_info_event { 4495 u32 freq; /* Units in MHz */ 4496 u32 noise_floor; /* units are dBm */ 4497 /* rx clear - how often the channel was unused */ 4498 u32 rx_clear_count_low; 4499 u32 rx_clear_count_high; 4500 /* cycle count - elapsed time during measured period, in clock ticks */ 4501 u32 cycle_count_low; 4502 u32 cycle_count_high; 4503 /* tx cycle count - elapsed time spent in tx, in clock ticks */ 4504 u32 tx_cycle_count_low; 4505 u32 tx_cycle_count_high; 4506 /* rx cycle count - elapsed time spent in rx, in clock ticks */ 4507 u32 rx_cycle_count_low; 4508 u32 rx_cycle_count_high; 4509 /*rx_cycle cnt for my bss in 64bits format */ 4510 u32 rx_bss_cycle_count_low; 4511 u32 rx_bss_cycle_count_high; 4512 u32 pdev_id; 4513 } __packed; 4514 4515 #define WMI_VDEV_INSTALL_KEY_COMPL_STATUS_SUCCESS 0 4516 4517 struct wmi_vdev_install_key_compl_event { 4518 u32 vdev_id; 4519 struct wmi_mac_addr peer_macaddr; 4520 u32 key_idx; 4521 u32 key_flags; 4522 u32 status; 4523 } __packed; 4524 4525 struct wmi_vdev_install_key_complete_arg { 4526 u32 vdev_id; 4527 const u8 *macaddr; 4528 u32 key_idx; 4529 u32 key_flags; 4530 u32 status; 4531 }; 4532 4533 struct wmi_peer_assoc_conf_event { 4534 u32 vdev_id; 4535 struct wmi_mac_addr peer_macaddr; 4536 } __packed; 4537 4538 struct wmi_peer_assoc_conf_arg { 4539 u32 vdev_id; 4540 const u8 *macaddr; 4541 }; 4542 4543 struct wmi_fils_discovery_event { 4544 u32 vdev_id; 4545 u32 fils_tt; 4546 u32 tbtt; 4547 } __packed; 4548 4549 struct wmi_probe_resp_tx_status_event { 4550 u32 vdev_id; 4551 u32 tx_status; 4552 } __packed; 4553 4554 /* 4555 * PDEV statistics 4556 */ 4557 struct wmi_pdev_stats_base { 4558 s32 chan_nf; 4559 u32 tx_frame_count; /* Cycles spent transmitting frames */ 4560 u32 rx_frame_count; /* Cycles spent receiving frames */ 4561 u32 rx_clear_count; /* Total channel busy time, evidently */ 4562 u32 cycle_count; /* Total on-channel time */ 4563 u32 phy_err_count; 4564 u32 chan_tx_pwr; 4565 } __packed; 4566 4567 struct wmi_pdev_stats_extra { 4568 u32 ack_rx_bad; 4569 u32 rts_bad; 4570 u32 rts_good; 4571 u32 fcs_bad; 4572 u32 no_beacons; 4573 u32 mib_int_count; 4574 } __packed; 4575 4576 struct wmi_pdev_stats_tx { 4577 /* Num HTT cookies queued to dispatch list */ 4578 s32 comp_queued; 4579 4580 /* Num HTT cookies dispatched */ 4581 s32 comp_delivered; 4582 4583 /* Num MSDU queued to WAL */ 4584 s32 msdu_enqued; 4585 4586 /* Num MPDU queue to WAL */ 4587 s32 mpdu_enqued; 4588 4589 /* Num MSDUs dropped by WMM limit */ 4590 s32 wmm_drop; 4591 4592 /* Num Local frames queued */ 4593 s32 local_enqued; 4594 4595 /* Num Local frames done */ 4596 s32 local_freed; 4597 4598 /* Num queued to HW */ 4599 s32 hw_queued; 4600 4601 /* Num PPDU reaped from HW */ 4602 s32 hw_reaped; 4603 4604 /* Num underruns */ 4605 s32 underrun; 4606 4607 /* Num hw paused */ 4608 u32 hw_paused; 4609 4610 /* Num PPDUs cleaned up in TX abort */ 4611 s32 tx_abort; 4612 4613 /* Num MPDUs requeued by SW */ 4614 s32 mpdus_requeued; 4615 4616 /* excessive retries */ 4617 u32 tx_ko; 4618 4619 u32 tx_xretry; 4620 4621 /* data hw rate code */ 4622 u32 data_rc; 4623 4624 /* Scheduler self triggers */ 4625 u32 self_triggers; 4626 4627 /* frames dropped due to excessive sw retries */ 4628 u32 sw_retry_failure; 4629 4630 /* illegal rate phy errors */ 4631 u32 illgl_rate_phy_err; 4632 4633 /* wal pdev continuous xretry */ 4634 u32 pdev_cont_xretry; 4635 4636 /* wal pdev tx timeouts */ 4637 u32 pdev_tx_timeout; 4638 4639 /* wal pdev resets */ 4640 u32 pdev_resets; 4641 4642 /* frames dropped due to non-availability of stateless TIDs */ 4643 u32 stateless_tid_alloc_failure; 4644 4645 /* PhY/BB underrun */ 4646 u32 phy_underrun; 4647 4648 /* MPDU is more than txop limit */ 4649 u32 txop_ovf; 4650 4651 /* Num sequences posted */ 4652 u32 seq_posted; 4653 4654 /* Num sequences failed in queueing */ 4655 u32 seq_failed_queueing; 4656 4657 /* Num sequences completed */ 4658 u32 seq_completed; 4659 4660 /* Num sequences restarted */ 4661 u32 seq_restarted; 4662 4663 /* Num of MU sequences posted */ 4664 u32 mu_seq_posted; 4665 4666 /* Num MPDUs flushed by SW, HWPAUSED, SW TXABORT 4667 * (Reset,channel change) 4668 */ 4669 s32 mpdus_sw_flush; 4670 4671 /* Num MPDUs filtered by HW, all filter condition (TTL expired) */ 4672 s32 mpdus_hw_filter; 4673 4674 /* Num MPDUs truncated by PDG (TXOP, TBTT, 4675 * PPDU_duration based on rate, dyn_bw) 4676 */ 4677 s32 mpdus_truncated; 4678 4679 /* Num MPDUs that was tried but didn't receive ACK or BA */ 4680 s32 mpdus_ack_failed; 4681 4682 /* Num MPDUs that was dropped du to expiry. */ 4683 s32 mpdus_expired; 4684 } __packed; 4685 4686 struct wmi_pdev_stats_rx { 4687 /* Cnts any change in ring routing mid-ppdu */ 4688 s32 mid_ppdu_route_change; 4689 4690 /* Total number of statuses processed */ 4691 s32 status_rcvd; 4692 4693 /* Extra frags on rings 0-3 */ 4694 s32 r0_frags; 4695 s32 r1_frags; 4696 s32 r2_frags; 4697 s32 r3_frags; 4698 4699 /* MSDUs / MPDUs delivered to HTT */ 4700 s32 htt_msdus; 4701 s32 htt_mpdus; 4702 4703 /* MSDUs / MPDUs delivered to local stack */ 4704 s32 loc_msdus; 4705 s32 loc_mpdus; 4706 4707 /* AMSDUs that have more MSDUs than the status ring size */ 4708 s32 oversize_amsdu; 4709 4710 /* Number of PHY errors */ 4711 s32 phy_errs; 4712 4713 /* Number of PHY errors drops */ 4714 s32 phy_err_drop; 4715 4716 /* Number of mpdu errors - FCS, MIC, ENC etc. */ 4717 s32 mpdu_errs; 4718 4719 /* Num overflow errors */ 4720 s32 rx_ovfl_errs; 4721 } __packed; 4722 4723 struct wmi_pdev_stats { 4724 struct wmi_pdev_stats_base base; 4725 struct wmi_pdev_stats_tx tx; 4726 struct wmi_pdev_stats_rx rx; 4727 } __packed; 4728 4729 #define WLAN_MAX_AC 4 4730 #define MAX_TX_RATE_VALUES 10 4731 #define MAX_TX_RATE_VALUES 10 4732 4733 struct wmi_vdev_stats { 4734 u32 vdev_id; 4735 u32 beacon_snr; 4736 u32 data_snr; 4737 u32 num_tx_frames[WLAN_MAX_AC]; 4738 u32 num_rx_frames; 4739 u32 num_tx_frames_retries[WLAN_MAX_AC]; 4740 u32 num_tx_frames_failures[WLAN_MAX_AC]; 4741 u32 num_rts_fail; 4742 u32 num_rts_success; 4743 u32 num_rx_err; 4744 u32 num_rx_discard; 4745 u32 num_tx_not_acked; 4746 u32 tx_rate_history[MAX_TX_RATE_VALUES]; 4747 u32 beacon_rssi_history[MAX_TX_RATE_VALUES]; 4748 } __packed; 4749 4750 struct wmi_bcn_stats { 4751 u32 vdev_id; 4752 u32 tx_bcn_succ_cnt; 4753 u32 tx_bcn_outage_cnt; 4754 } __packed; 4755 4756 struct wmi_stats_event { 4757 u32 stats_id; 4758 u32 num_pdev_stats; 4759 u32 num_vdev_stats; 4760 u32 num_peer_stats; 4761 u32 num_bcnflt_stats; 4762 u32 num_chan_stats; 4763 u32 num_mib_stats; 4764 u32 pdev_id; 4765 u32 num_bcn_stats; 4766 u32 num_peer_extd_stats; 4767 u32 num_peer_extd2_stats; 4768 } __packed; 4769 4770 struct wmi_rssi_stats { 4771 u32 vdev_id; 4772 u32 rssi_avg_beacon[WMI_MAX_CHAINS]; 4773 u32 rssi_avg_data[WMI_MAX_CHAINS]; 4774 struct wmi_mac_addr peer_macaddr; 4775 } __packed; 4776 4777 struct wmi_per_chain_rssi_stats { 4778 u32 num_per_chain_rssi_stats; 4779 } __packed; 4780 4781 struct wmi_pdev_ctl_failsafe_chk_event { 4782 u32 pdev_id; 4783 u32 ctl_failsafe_status; 4784 } __packed; 4785 4786 struct wmi_pdev_csa_switch_ev { 4787 u32 pdev_id; 4788 u32 current_switch_count; 4789 u32 num_vdevs; 4790 } __packed; 4791 4792 struct wmi_pdev_radar_ev { 4793 u32 pdev_id; 4794 u32 detection_mode; 4795 u32 chan_freq; 4796 u32 chan_width; 4797 u32 detector_id; 4798 u32 segment_id; 4799 u32 timestamp; 4800 u32 is_chirp; 4801 s32 freq_offset; 4802 s32 sidx; 4803 } __packed; 4804 4805 struct wmi_pdev_temperature_event { 4806 /* temperature value in Celsius degree */ 4807 s32 temp; 4808 u32 pdev_id; 4809 } __packed; 4810 4811 #define WMI_RX_STATUS_OK 0x00 4812 #define WMI_RX_STATUS_ERR_CRC 0x01 4813 #define WMI_RX_STATUS_ERR_DECRYPT 0x08 4814 #define WMI_RX_STATUS_ERR_MIC 0x10 4815 #define WMI_RX_STATUS_ERR_KEY_CACHE_MISS 0x20 4816 4817 #define WLAN_MGMT_TXRX_HOST_MAX_ANTENNA 4 4818 4819 struct mgmt_rx_event_params { 4820 u32 chan_freq; 4821 u32 channel; 4822 u32 snr; 4823 u8 rssi_ctl[WLAN_MGMT_TXRX_HOST_MAX_ANTENNA]; 4824 u32 rate; 4825 enum wmi_phy_mode phy_mode; 4826 u32 buf_len; 4827 int status; 4828 u32 flags; 4829 int rssi; 4830 u32 tsf_delta; 4831 u8 pdev_id; 4832 }; 4833 4834 #define ATH_MAX_ANTENNA 4 4835 4836 struct wmi_mgmt_rx_hdr { 4837 u32 channel; 4838 u32 snr; 4839 u32 rate; 4840 u32 phy_mode; 4841 u32 buf_len; 4842 u32 status; 4843 u32 rssi_ctl[ATH_MAX_ANTENNA]; 4844 u32 flags; 4845 int rssi; 4846 u32 tsf_delta; 4847 u32 rx_tsf_l32; 4848 u32 rx_tsf_u32; 4849 u32 pdev_id; 4850 u32 chan_freq; 4851 } __packed; 4852 4853 #define MAX_ANTENNA_EIGHT 8 4854 4855 struct wmi_rssi_ctl_ext { 4856 u32 tlv_header; 4857 u32 rssi_ctl_ext[MAX_ANTENNA_EIGHT - ATH_MAX_ANTENNA]; 4858 }; 4859 4860 struct wmi_mgmt_tx_compl_event { 4861 u32 desc_id; 4862 u32 status; 4863 u32 pdev_id; 4864 u32 ppdu_id; 4865 u32 ack_rssi; 4866 } __packed; 4867 4868 struct wmi_scan_event { 4869 u32 event_type; /* %WMI_SCAN_EVENT_ */ 4870 u32 reason; /* %WMI_SCAN_REASON_ */ 4871 u32 channel_freq; /* only valid for WMI_SCAN_EVENT_FOREIGN_CHANNEL */ 4872 u32 scan_req_id; 4873 u32 scan_id; 4874 u32 vdev_id; 4875 /* TSF Timestamp when the scan event (%WMI_SCAN_EVENT_) is completed 4876 * In case of AP it is TSF of the AP vdev 4877 * In case of STA connected state, this is the TSF of the AP 4878 * In case of STA not connected, it will be the free running HW timer 4879 */ 4880 u32 tsf_timestamp; 4881 } __packed; 4882 4883 struct wmi_peer_sta_kickout_arg { 4884 const u8 *mac_addr; 4885 }; 4886 4887 struct wmi_peer_sta_kickout_event { 4888 struct wmi_mac_addr peer_macaddr; 4889 } __packed; 4890 4891 enum wmi_roam_reason { 4892 WMI_ROAM_REASON_BETTER_AP = 1, 4893 WMI_ROAM_REASON_BEACON_MISS = 2, 4894 WMI_ROAM_REASON_LOW_RSSI = 3, 4895 WMI_ROAM_REASON_SUITABLE_AP_FOUND = 4, 4896 WMI_ROAM_REASON_HO_FAILED = 5, 4897 4898 /* keep last */ 4899 WMI_ROAM_REASON_MAX, 4900 }; 4901 4902 struct wmi_roam_event { 4903 u32 vdev_id; 4904 u32 reason; 4905 u32 rssi; 4906 } __packed; 4907 4908 #define WMI_CHAN_INFO_START_RESP 0 4909 #define WMI_CHAN_INFO_END_RESP 1 4910 4911 struct wmi_chan_info_event { 4912 u32 err_code; 4913 u32 freq; 4914 u32 cmd_flags; 4915 u32 noise_floor; 4916 u32 rx_clear_count; 4917 u32 cycle_count; 4918 u32 chan_tx_pwr_range; 4919 u32 chan_tx_pwr_tp; 4920 u32 rx_frame_count; 4921 u32 my_bss_rx_cycle_count; 4922 u32 rx_11b_mode_data_duration; 4923 u32 tx_frame_cnt; 4924 u32 mac_clk_mhz; 4925 u32 vdev_id; 4926 } __packed; 4927 4928 struct ath11k_targ_cap { 4929 u32 phy_capability; 4930 u32 max_frag_entry; 4931 u32 num_rf_chains; 4932 u32 ht_cap_info; 4933 u32 vht_cap_info; 4934 u32 vht_supp_mcs; 4935 u32 hw_min_tx_power; 4936 u32 hw_max_tx_power; 4937 u32 sys_cap_info; 4938 u32 min_pkt_size_enable; 4939 u32 max_bcn_ie_size; 4940 u32 max_num_scan_channels; 4941 u32 max_supported_macs; 4942 u32 wmi_fw_sub_feat_caps; 4943 u32 txrx_chainmask; 4944 u32 default_dbs_hw_mode_index; 4945 u32 num_msdu_desc; 4946 }; 4947 4948 enum wmi_vdev_type { 4949 WMI_VDEV_TYPE_AP = 1, 4950 WMI_VDEV_TYPE_STA = 2, 4951 WMI_VDEV_TYPE_IBSS = 3, 4952 WMI_VDEV_TYPE_MONITOR = 4, 4953 }; 4954 4955 enum wmi_vdev_subtype { 4956 WMI_VDEV_SUBTYPE_NONE, 4957 WMI_VDEV_SUBTYPE_P2P_DEVICE, 4958 WMI_VDEV_SUBTYPE_P2P_CLIENT, 4959 WMI_VDEV_SUBTYPE_P2P_GO, 4960 WMI_VDEV_SUBTYPE_PROXY_STA, 4961 WMI_VDEV_SUBTYPE_MESH_NON_11S, 4962 WMI_VDEV_SUBTYPE_MESH_11S, 4963 }; 4964 4965 enum wmi_sta_powersave_param { 4966 WMI_STA_PS_PARAM_RX_WAKE_POLICY = 0, 4967 WMI_STA_PS_PARAM_TX_WAKE_THRESHOLD = 1, 4968 WMI_STA_PS_PARAM_PSPOLL_COUNT = 2, 4969 WMI_STA_PS_PARAM_INACTIVITY_TIME = 3, 4970 WMI_STA_PS_PARAM_UAPSD = 4, 4971 }; 4972 4973 #define WMI_UAPSD_AC_TYPE_DELI 0 4974 #define WMI_UAPSD_AC_TYPE_TRIG 1 4975 4976 #define WMI_UAPSD_AC_BIT_MASK(ac, type) \ 4977 ((type == WMI_UAPSD_AC_TYPE_DELI) ? \ 4978 (1 << (ac << 1)) : (1 << ((ac << 1) + 1))) 4979 4980 enum wmi_sta_ps_param_uapsd { 4981 WMI_STA_PS_UAPSD_AC0_DELIVERY_EN = (1 << 0), 4982 WMI_STA_PS_UAPSD_AC0_TRIGGER_EN = (1 << 1), 4983 WMI_STA_PS_UAPSD_AC1_DELIVERY_EN = (1 << 2), 4984 WMI_STA_PS_UAPSD_AC1_TRIGGER_EN = (1 << 3), 4985 WMI_STA_PS_UAPSD_AC2_DELIVERY_EN = (1 << 4), 4986 WMI_STA_PS_UAPSD_AC2_TRIGGER_EN = (1 << 5), 4987 WMI_STA_PS_UAPSD_AC3_DELIVERY_EN = (1 << 6), 4988 WMI_STA_PS_UAPSD_AC3_TRIGGER_EN = (1 << 7), 4989 }; 4990 4991 #define WMI_STA_UAPSD_MAX_INTERVAL_MSEC UINT_MAX 4992 4993 struct wmi_sta_uapsd_auto_trig_param { 4994 u32 wmm_ac; 4995 u32 user_priority; 4996 u32 service_interval; 4997 u32 suspend_interval; 4998 u32 delay_interval; 4999 }; 5000 5001 struct wmi_sta_uapsd_auto_trig_cmd_fixed_param { 5002 u32 vdev_id; 5003 struct wmi_mac_addr peer_macaddr; 5004 u32 num_ac; 5005 }; 5006 5007 struct wmi_sta_uapsd_auto_trig_arg { 5008 u32 wmm_ac; 5009 u32 user_priority; 5010 u32 service_interval; 5011 u32 suspend_interval; 5012 u32 delay_interval; 5013 }; 5014 5015 enum wmi_sta_ps_param_tx_wake_threshold { 5016 WMI_STA_PS_TX_WAKE_THRESHOLD_NEVER = 0, 5017 WMI_STA_PS_TX_WAKE_THRESHOLD_ALWAYS = 1, 5018 5019 /* Values greater than one indicate that many TX attempts per beacon 5020 * interval before the STA will wake up 5021 */ 5022 }; 5023 5024 /* The maximum number of PS-Poll frames the FW will send in response to 5025 * traffic advertised in TIM before waking up (by sending a null frame with PS 5026 * = 0). Value 0 has a special meaning: there is no maximum count and the FW 5027 * will send as many PS-Poll as are necessary to retrieve buffered BU. This 5028 * parameter is used when the RX wake policy is 5029 * WMI_STA_PS_RX_WAKE_POLICY_POLL_UAPSD and ignored when the RX wake 5030 * policy is WMI_STA_PS_RX_WAKE_POLICY_WAKE. 5031 */ 5032 enum wmi_sta_ps_param_pspoll_count { 5033 WMI_STA_PS_PSPOLL_COUNT_NO_MAX = 0, 5034 /* Values greater than 0 indicate the maximum number of PS-Poll frames 5035 * FW will send before waking up. 5036 */ 5037 }; 5038 5039 /* U-APSD configuration of peer station from (re)assoc request and TSPECs */ 5040 enum wmi_ap_ps_param_uapsd { 5041 WMI_AP_PS_UAPSD_AC0_DELIVERY_EN = (1 << 0), 5042 WMI_AP_PS_UAPSD_AC0_TRIGGER_EN = (1 << 1), 5043 WMI_AP_PS_UAPSD_AC1_DELIVERY_EN = (1 << 2), 5044 WMI_AP_PS_UAPSD_AC1_TRIGGER_EN = (1 << 3), 5045 WMI_AP_PS_UAPSD_AC2_DELIVERY_EN = (1 << 4), 5046 WMI_AP_PS_UAPSD_AC2_TRIGGER_EN = (1 << 5), 5047 WMI_AP_PS_UAPSD_AC3_DELIVERY_EN = (1 << 6), 5048 WMI_AP_PS_UAPSD_AC3_TRIGGER_EN = (1 << 7), 5049 }; 5050 5051 /* U-APSD maximum service period of peer station */ 5052 enum wmi_ap_ps_peer_param_max_sp { 5053 WMI_AP_PS_PEER_PARAM_MAX_SP_UNLIMITED = 0, 5054 WMI_AP_PS_PEER_PARAM_MAX_SP_2 = 1, 5055 WMI_AP_PS_PEER_PARAM_MAX_SP_4 = 2, 5056 WMI_AP_PS_PEER_PARAM_MAX_SP_6 = 3, 5057 MAX_WMI_AP_PS_PEER_PARAM_MAX_SP, 5058 }; 5059 5060 enum wmi_ap_ps_peer_param { 5061 /** Set uapsd configuration for a given peer. 5062 * 5063 * This include the delivery and trigger enabled state for each AC. 5064 * The host MLME needs to set this based on AP capability and stations 5065 * request Set in the association request received from the station. 5066 * 5067 * Lower 8 bits of the value specify the UAPSD configuration. 5068 * 5069 * (see enum wmi_ap_ps_param_uapsd) 5070 * The default value is 0. 5071 */ 5072 WMI_AP_PS_PEER_PARAM_UAPSD = 0, 5073 5074 /** 5075 * Set the service period for a UAPSD capable station 5076 * 5077 * The service period from wme ie in the (re)assoc request frame. 5078 * 5079 * (see enum wmi_ap_ps_peer_param_max_sp) 5080 */ 5081 WMI_AP_PS_PEER_PARAM_MAX_SP = 1, 5082 5083 /** Time in seconds for aging out buffered frames 5084 * for STA in power save 5085 */ 5086 WMI_AP_PS_PEER_PARAM_AGEOUT_TIME = 2, 5087 5088 /** Specify frame types that are considered SIFS 5089 * RESP trigger frame 5090 */ 5091 WMI_AP_PS_PEER_PARAM_SIFS_RESP_FRMTYPE = 3, 5092 5093 /** Specifies the trigger state of TID. 5094 * Valid only for UAPSD frame type 5095 */ 5096 WMI_AP_PS_PEER_PARAM_SIFS_RESP_UAPSD = 4, 5097 5098 /* Specifies the WNM sleep state of a STA */ 5099 WMI_AP_PS_PEER_PARAM_WNM_SLEEP = 5, 5100 }; 5101 5102 #define DISABLE_SIFS_RESPONSE_TRIGGER 0 5103 5104 #define WMI_MAX_KEY_INDEX 3 5105 #define WMI_MAX_KEY_LEN 32 5106 5107 #define WMI_KEY_PAIRWISE 0x00 5108 #define WMI_KEY_GROUP 0x01 5109 5110 #define WMI_CIPHER_NONE 0x0 /* clear key */ 5111 #define WMI_CIPHER_WEP 0x1 5112 #define WMI_CIPHER_TKIP 0x2 5113 #define WMI_CIPHER_AES_OCB 0x3 5114 #define WMI_CIPHER_AES_CCM 0x4 5115 #define WMI_CIPHER_WAPI 0x5 5116 #define WMI_CIPHER_CKIP 0x6 5117 #define WMI_CIPHER_AES_CMAC 0x7 5118 #define WMI_CIPHER_ANY 0x8 5119 #define WMI_CIPHER_AES_GCM 0x9 5120 #define WMI_CIPHER_AES_GMAC 0xa 5121 5122 /* Value to disable fixed rate setting */ 5123 #define WMI_FIXED_RATE_NONE (0xffff) 5124 5125 #define ATH11K_RC_VERSION_OFFSET 28 5126 #define ATH11K_RC_PREAMBLE_OFFSET 8 5127 #define ATH11K_RC_NSS_OFFSET 5 5128 5129 #define ATH11K_HW_RATE_CODE(rate, nss, preamble) \ 5130 ((1 << ATH11K_RC_VERSION_OFFSET) | \ 5131 ((nss) << ATH11K_RC_NSS_OFFSET) | \ 5132 ((preamble) << ATH11K_RC_PREAMBLE_OFFSET) | \ 5133 (rate)) 5134 5135 /* Preamble types to be used with VDEV fixed rate configuration */ 5136 enum wmi_rate_preamble { 5137 WMI_RATE_PREAMBLE_OFDM, 5138 WMI_RATE_PREAMBLE_CCK, 5139 WMI_RATE_PREAMBLE_HT, 5140 WMI_RATE_PREAMBLE_VHT, 5141 WMI_RATE_PREAMBLE_HE, 5142 }; 5143 5144 /** 5145 * enum wmi_rtscts_prot_mode - Enable/Disable RTS/CTS and CTS2Self Protection. 5146 * @WMI_RTS_CTS_DISABLED: RTS/CTS protection is disabled. 5147 * @WMI_USE_RTS_CTS: RTS/CTS Enabled. 5148 * @WMI_USE_CTS2SELF: CTS to self protection Enabled. 5149 */ 5150 enum wmi_rtscts_prot_mode { 5151 WMI_RTS_CTS_DISABLED = 0, 5152 WMI_USE_RTS_CTS = 1, 5153 WMI_USE_CTS2SELF = 2, 5154 }; 5155 5156 /** 5157 * enum wmi_rtscts_profile - Selection of RTS CTS profile along with enabling 5158 * protection mode. 5159 * @WMI_RTSCTS_FOR_NO_RATESERIES: Neither of rate-series should use RTS-CTS 5160 * @WMI_RTSCTS_FOR_SECOND_RATESERIES: Only second rate-series will use RTS-CTS 5161 * @WMI_RTSCTS_ACROSS_SW_RETRIES: Only the second rate-series will use RTS-CTS, 5162 * but if there's a sw retry, both the rate 5163 * series will use RTS-CTS. 5164 * @WMI_RTSCTS_ERP: RTS/CTS used for ERP protection for every PPDU. 5165 * @WMI_RTSCTS_FOR_ALL_RATESERIES: Enable RTS-CTS for all rate series. 5166 */ 5167 enum wmi_rtscts_profile { 5168 WMI_RTSCTS_FOR_NO_RATESERIES = 0, 5169 WMI_RTSCTS_FOR_SECOND_RATESERIES = 1, 5170 WMI_RTSCTS_ACROSS_SW_RETRIES = 2, 5171 WMI_RTSCTS_ERP = 3, 5172 WMI_RTSCTS_FOR_ALL_RATESERIES = 4, 5173 }; 5174 5175 struct ath11k_hal_reg_cap { 5176 u32 eeprom_rd; 5177 u32 eeprom_rd_ext; 5178 u32 regcap1; 5179 u32 regcap2; 5180 u32 wireless_modes; 5181 u32 low_2ghz_chan; 5182 u32 high_2ghz_chan; 5183 u32 low_5ghz_chan; 5184 u32 high_5ghz_chan; 5185 }; 5186 5187 struct ath11k_mem_chunk { 5188 void *vaddr; 5189 dma_addr_t paddr; 5190 u32 len; 5191 u32 req_id; 5192 }; 5193 5194 #define WMI_SKB_HEADROOM sizeof(struct wmi_cmd_hdr) 5195 5196 enum wmi_sta_ps_param_rx_wake_policy { 5197 WMI_STA_PS_RX_WAKE_POLICY_WAKE = 0, 5198 WMI_STA_PS_RX_WAKE_POLICY_POLL_UAPSD = 1, 5199 }; 5200 5201 /* Do not change existing values! Used by ath11k_frame_mode parameter 5202 * module parameter. 5203 */ 5204 enum ath11k_hw_txrx_mode { 5205 ATH11K_HW_TXRX_RAW = 0, 5206 ATH11K_HW_TXRX_NATIVE_WIFI = 1, 5207 ATH11K_HW_TXRX_ETHERNET = 2, 5208 }; 5209 5210 struct wmi_wmm_params { 5211 u32 tlv_header; 5212 u32 cwmin; 5213 u32 cwmax; 5214 u32 aifs; 5215 u32 txoplimit; 5216 u32 acm; 5217 u32 no_ack; 5218 } __packed; 5219 5220 struct wmi_wmm_params_arg { 5221 u8 acm; 5222 u8 aifs; 5223 u16 cwmin; 5224 u16 cwmax; 5225 u16 txop; 5226 u8 no_ack; 5227 }; 5228 5229 struct wmi_vdev_set_wmm_params_cmd { 5230 u32 tlv_header; 5231 u32 vdev_id; 5232 struct wmi_wmm_params wmm_params[4]; 5233 u32 wmm_param_type; 5234 } __packed; 5235 5236 struct wmi_wmm_params_all_arg { 5237 struct wmi_wmm_params_arg ac_be; 5238 struct wmi_wmm_params_arg ac_bk; 5239 struct wmi_wmm_params_arg ac_vi; 5240 struct wmi_wmm_params_arg ac_vo; 5241 }; 5242 5243 #define ATH11K_TWT_DEF_STA_CONG_TIMER_MS 5000 5244 #define ATH11K_TWT_DEF_DEFAULT_SLOT_SIZE 10 5245 #define ATH11K_TWT_DEF_CONGESTION_THRESH_SETUP 50 5246 #define ATH11K_TWT_DEF_CONGESTION_THRESH_TEARDOWN 20 5247 #define ATH11K_TWT_DEF_CONGESTION_THRESH_CRITICAL 100 5248 #define ATH11K_TWT_DEF_INTERFERENCE_THRESH_TEARDOWN 80 5249 #define ATH11K_TWT_DEF_INTERFERENCE_THRESH_SETUP 50 5250 #define ATH11K_TWT_DEF_MIN_NO_STA_SETUP 10 5251 #define ATH11K_TWT_DEF_MIN_NO_STA_TEARDOWN 2 5252 #define ATH11K_TWT_DEF_NO_OF_BCAST_MCAST_SLOTS 2 5253 #define ATH11K_TWT_DEF_MIN_NO_TWT_SLOTS 2 5254 #define ATH11K_TWT_DEF_MAX_NO_STA_TWT 500 5255 #define ATH11K_TWT_DEF_MODE_CHECK_INTERVAL 10000 5256 #define ATH11K_TWT_DEF_ADD_STA_SLOT_INTERVAL 1000 5257 #define ATH11K_TWT_DEF_REMOVE_STA_SLOT_INTERVAL 5000 5258 5259 struct wmi_twt_enable_params { 5260 u32 sta_cong_timer_ms; 5261 u32 mbss_support; 5262 u32 default_slot_size; 5263 u32 congestion_thresh_setup; 5264 u32 congestion_thresh_teardown; 5265 u32 congestion_thresh_critical; 5266 u32 interference_thresh_teardown; 5267 u32 interference_thresh_setup; 5268 u32 min_no_sta_setup; 5269 u32 min_no_sta_teardown; 5270 u32 no_of_bcast_mcast_slots; 5271 u32 min_no_twt_slots; 5272 u32 max_no_sta_twt; 5273 u32 mode_check_interval; 5274 u32 add_sta_slot_interval; 5275 u32 remove_sta_slot_interval; 5276 }; 5277 5278 struct wmi_twt_enable_params_cmd { 5279 u32 tlv_header; 5280 u32 pdev_id; 5281 u32 sta_cong_timer_ms; 5282 u32 mbss_support; 5283 u32 default_slot_size; 5284 u32 congestion_thresh_setup; 5285 u32 congestion_thresh_teardown; 5286 u32 congestion_thresh_critical; 5287 u32 interference_thresh_teardown; 5288 u32 interference_thresh_setup; 5289 u32 min_no_sta_setup; 5290 u32 min_no_sta_teardown; 5291 u32 no_of_bcast_mcast_slots; 5292 u32 min_no_twt_slots; 5293 u32 max_no_sta_twt; 5294 u32 mode_check_interval; 5295 u32 add_sta_slot_interval; 5296 u32 remove_sta_slot_interval; 5297 } __packed; 5298 5299 struct wmi_twt_disable_params_cmd { 5300 u32 tlv_header; 5301 u32 pdev_id; 5302 } __packed; 5303 5304 enum WMI_HOST_TWT_COMMAND { 5305 WMI_HOST_TWT_COMMAND_REQUEST_TWT = 0, 5306 WMI_HOST_TWT_COMMAND_SUGGEST_TWT, 5307 WMI_HOST_TWT_COMMAND_DEMAND_TWT, 5308 WMI_HOST_TWT_COMMAND_TWT_GROUPING, 5309 WMI_HOST_TWT_COMMAND_ACCEPT_TWT, 5310 WMI_HOST_TWT_COMMAND_ALTERNATE_TWT, 5311 WMI_HOST_TWT_COMMAND_DICTATE_TWT, 5312 WMI_HOST_TWT_COMMAND_REJECT_TWT, 5313 }; 5314 5315 #define WMI_TWT_ADD_DIALOG_FLAG_BCAST BIT(8) 5316 #define WMI_TWT_ADD_DIALOG_FLAG_TRIGGER BIT(9) 5317 #define WMI_TWT_ADD_DIALOG_FLAG_FLOW_TYPE BIT(10) 5318 #define WMI_TWT_ADD_DIALOG_FLAG_PROTECTION BIT(11) 5319 5320 struct wmi_twt_add_dialog_params_cmd { 5321 u32 tlv_header; 5322 u32 vdev_id; 5323 struct wmi_mac_addr peer_macaddr; 5324 u32 dialog_id; 5325 u32 wake_intvl_us; 5326 u32 wake_intvl_mantis; 5327 u32 wake_dura_us; 5328 u32 sp_offset_us; 5329 u32 flags; 5330 } __packed; 5331 5332 struct wmi_twt_add_dialog_params { 5333 u32 vdev_id; 5334 u8 peer_macaddr[ETH_ALEN]; 5335 u32 dialog_id; 5336 u32 wake_intvl_us; 5337 u32 wake_intvl_mantis; 5338 u32 wake_dura_us; 5339 u32 sp_offset_us; 5340 u8 twt_cmd; 5341 u8 flag_bcast; 5342 u8 flag_trigger; 5343 u8 flag_flow_type; 5344 u8 flag_protection; 5345 } __packed; 5346 5347 enum wmi_twt_add_dialog_status { 5348 WMI_ADD_TWT_STATUS_OK, 5349 WMI_ADD_TWT_STATUS_TWT_NOT_ENABLED, 5350 WMI_ADD_TWT_STATUS_USED_DIALOG_ID, 5351 WMI_ADD_TWT_STATUS_INVALID_PARAM, 5352 WMI_ADD_TWT_STATUS_NOT_READY, 5353 WMI_ADD_TWT_STATUS_NO_RESOURCE, 5354 WMI_ADD_TWT_STATUS_NO_ACK, 5355 WMI_ADD_TWT_STATUS_NO_RESPONSE, 5356 WMI_ADD_TWT_STATUS_DENIED, 5357 WMI_ADD_TWT_STATUS_UNKNOWN_ERROR, 5358 }; 5359 5360 struct wmi_twt_add_dialog_event { 5361 u32 vdev_id; 5362 struct wmi_mac_addr peer_macaddr; 5363 u32 dialog_id; 5364 u32 status; 5365 } __packed; 5366 5367 struct wmi_twt_del_dialog_params { 5368 u32 vdev_id; 5369 u8 peer_macaddr[ETH_ALEN]; 5370 u32 dialog_id; 5371 } __packed; 5372 5373 struct wmi_twt_del_dialog_params_cmd { 5374 u32 tlv_header; 5375 u32 vdev_id; 5376 struct wmi_mac_addr peer_macaddr; 5377 u32 dialog_id; 5378 } __packed; 5379 5380 struct wmi_twt_pause_dialog_params { 5381 u32 vdev_id; 5382 u8 peer_macaddr[ETH_ALEN]; 5383 u32 dialog_id; 5384 } __packed; 5385 5386 struct wmi_twt_pause_dialog_params_cmd { 5387 u32 tlv_header; 5388 u32 vdev_id; 5389 struct wmi_mac_addr peer_macaddr; 5390 u32 dialog_id; 5391 } __packed; 5392 5393 struct wmi_twt_resume_dialog_params { 5394 u32 vdev_id; 5395 u8 peer_macaddr[ETH_ALEN]; 5396 u32 dialog_id; 5397 u32 sp_offset_us; 5398 u32 next_twt_size; 5399 } __packed; 5400 5401 struct wmi_twt_resume_dialog_params_cmd { 5402 u32 tlv_header; 5403 u32 vdev_id; 5404 struct wmi_mac_addr peer_macaddr; 5405 u32 dialog_id; 5406 u32 sp_offset_us; 5407 u32 next_twt_size; 5408 } __packed; 5409 5410 struct wmi_obss_spatial_reuse_params_cmd { 5411 u32 tlv_header; 5412 u32 pdev_id; 5413 u32 enable; 5414 s32 obss_min; 5415 s32 obss_max; 5416 u32 vdev_id; 5417 } __packed; 5418 5419 struct wmi_pdev_obss_pd_bitmap_cmd { 5420 u32 tlv_header; 5421 u32 pdev_id; 5422 u32 bitmap[2]; 5423 } __packed; 5424 5425 #define ATH11K_BSS_COLOR_COLLISION_SCAN_PERIOD_MS 200 5426 #define ATH11K_OBSS_COLOR_COLLISION_DETECTION_DISABLE 0 5427 #define ATH11K_OBSS_COLOR_COLLISION_DETECTION 1 5428 5429 #define ATH11K_BSS_COLOR_COLLISION_DETECTION_STA_PERIOD_MS 10000 5430 #define ATH11K_BSS_COLOR_COLLISION_DETECTION_AP_PERIOD_MS 5000 5431 5432 enum wmi_bss_color_collision { 5433 WMI_BSS_COLOR_COLLISION_DISABLE = 0, 5434 WMI_BSS_COLOR_COLLISION_DETECTION, 5435 WMI_BSS_COLOR_FREE_SLOT_TIMER_EXPIRY, 5436 WMI_BSS_COLOR_FREE_SLOT_AVAILABLE, 5437 }; 5438 5439 struct wmi_obss_color_collision_cfg_params_cmd { 5440 u32 tlv_header; 5441 u32 vdev_id; 5442 u32 flags; 5443 u32 evt_type; 5444 u32 current_bss_color; 5445 u32 detection_period_ms; 5446 u32 scan_period_ms; 5447 u32 free_slot_expiry_time_ms; 5448 } __packed; 5449 5450 struct wmi_bss_color_change_enable_params_cmd { 5451 u32 tlv_header; 5452 u32 vdev_id; 5453 u32 enable; 5454 } __packed; 5455 5456 struct wmi_obss_color_collision_event { 5457 u32 vdev_id; 5458 u32 evt_type; 5459 u64 obss_color_bitmap; 5460 } __packed; 5461 5462 #define ATH11K_IPV4_TH_SEED_SIZE 5 5463 #define ATH11K_IPV6_TH_SEED_SIZE 11 5464 5465 struct ath11k_wmi_pdev_lro_config_cmd { 5466 u32 tlv_header; 5467 u32 lro_enable; 5468 u32 res; 5469 u32 th_4[ATH11K_IPV4_TH_SEED_SIZE]; 5470 u32 th_6[ATH11K_IPV6_TH_SEED_SIZE]; 5471 u32 pdev_id; 5472 } __packed; 5473 5474 #define ATH11K_WMI_SPECTRAL_COUNT_DEFAULT 0 5475 #define ATH11K_WMI_SPECTRAL_PERIOD_DEFAULT 224 5476 #define ATH11K_WMI_SPECTRAL_PRIORITY_DEFAULT 1 5477 #define ATH11K_WMI_SPECTRAL_FFT_SIZE_DEFAULT 7 5478 #define ATH11K_WMI_SPECTRAL_GC_ENA_DEFAULT 1 5479 #define ATH11K_WMI_SPECTRAL_RESTART_ENA_DEFAULT 0 5480 #define ATH11K_WMI_SPECTRAL_NOISE_FLOOR_REF_DEFAULT -96 5481 #define ATH11K_WMI_SPECTRAL_INIT_DELAY_DEFAULT 80 5482 #define ATH11K_WMI_SPECTRAL_NB_TONE_THR_DEFAULT 12 5483 #define ATH11K_WMI_SPECTRAL_STR_BIN_THR_DEFAULT 8 5484 #define ATH11K_WMI_SPECTRAL_WB_RPT_MODE_DEFAULT 0 5485 #define ATH11K_WMI_SPECTRAL_RSSI_RPT_MODE_DEFAULT 0 5486 #define ATH11K_WMI_SPECTRAL_RSSI_THR_DEFAULT 0xf0 5487 #define ATH11K_WMI_SPECTRAL_PWR_FORMAT_DEFAULT 0 5488 #define ATH11K_WMI_SPECTRAL_RPT_MODE_DEFAULT 2 5489 #define ATH11K_WMI_SPECTRAL_BIN_SCALE_DEFAULT 1 5490 #define ATH11K_WMI_SPECTRAL_DBM_ADJ_DEFAULT 1 5491 #define ATH11K_WMI_SPECTRAL_CHN_MASK_DEFAULT 1 5492 5493 struct ath11k_wmi_vdev_spectral_conf_param { 5494 u32 vdev_id; 5495 u32 scan_count; 5496 u32 scan_period; 5497 u32 scan_priority; 5498 u32 scan_fft_size; 5499 u32 scan_gc_ena; 5500 u32 scan_restart_ena; 5501 u32 scan_noise_floor_ref; 5502 u32 scan_init_delay; 5503 u32 scan_nb_tone_thr; 5504 u32 scan_str_bin_thr; 5505 u32 scan_wb_rpt_mode; 5506 u32 scan_rssi_rpt_mode; 5507 u32 scan_rssi_thr; 5508 u32 scan_pwr_format; 5509 u32 scan_rpt_mode; 5510 u32 scan_bin_scale; 5511 u32 scan_dbm_adj; 5512 u32 scan_chn_mask; 5513 } __packed; 5514 5515 struct ath11k_wmi_vdev_spectral_conf_cmd { 5516 u32 tlv_header; 5517 struct ath11k_wmi_vdev_spectral_conf_param param; 5518 } __packed; 5519 5520 #define ATH11K_WMI_SPECTRAL_TRIGGER_CMD_TRIGGER 1 5521 #define ATH11K_WMI_SPECTRAL_TRIGGER_CMD_CLEAR 2 5522 #define ATH11K_WMI_SPECTRAL_ENABLE_CMD_ENABLE 1 5523 #define ATH11K_WMI_SPECTRAL_ENABLE_CMD_DISABLE 2 5524 5525 struct ath11k_wmi_vdev_spectral_enable_cmd { 5526 u32 tlv_header; 5527 u32 vdev_id; 5528 u32 trigger_cmd; 5529 u32 enable_cmd; 5530 } __packed; 5531 5532 struct ath11k_wmi_pdev_dma_ring_cfg_req_cmd { 5533 u32 tlv_header; 5534 u32 pdev_id; 5535 u32 module_id; /* see enum wmi_direct_buffer_module */ 5536 u32 base_paddr_lo; 5537 u32 base_paddr_hi; 5538 u32 head_idx_paddr_lo; 5539 u32 head_idx_paddr_hi; 5540 u32 tail_idx_paddr_lo; 5541 u32 tail_idx_paddr_hi; 5542 u32 num_elems; /* Number of elems in the ring */ 5543 u32 buf_size; /* size of allocated buffer in bytes */ 5544 5545 /* Number of wmi_dma_buf_release_entry packed together */ 5546 u32 num_resp_per_event; 5547 5548 /* Target should timeout and send whatever resp 5549 * it has if this time expires, units in milliseconds 5550 */ 5551 u32 event_timeout_ms; 5552 } __packed; 5553 5554 struct ath11k_wmi_dma_buf_release_fixed_param { 5555 u32 pdev_id; 5556 u32 module_id; 5557 u32 num_buf_release_entry; 5558 u32 num_meta_data_entry; 5559 } __packed; 5560 5561 struct wmi_dma_buf_release_entry { 5562 u32 tlv_header; 5563 u32 paddr_lo; 5564 5565 /* Bits 11:0: address of data 5566 * Bits 31:12: host context data 5567 */ 5568 u32 paddr_hi; 5569 } __packed; 5570 5571 #define WMI_SPECTRAL_META_INFO1_FREQ1 GENMASK(15, 0) 5572 #define WMI_SPECTRAL_META_INFO1_FREQ2 GENMASK(31, 16) 5573 5574 #define WMI_SPECTRAL_META_INFO2_CHN_WIDTH GENMASK(7, 0) 5575 5576 struct wmi_dma_buf_release_meta_data { 5577 u32 tlv_header; 5578 s32 noise_floor[WMI_MAX_CHAINS]; 5579 u32 reset_delay; 5580 u32 freq1; 5581 u32 freq2; 5582 u32 ch_width; 5583 } __packed; 5584 5585 enum wmi_fils_discovery_cmd_type { 5586 WMI_FILS_DISCOVERY_CMD, 5587 WMI_UNSOL_BCAST_PROBE_RESP, 5588 }; 5589 5590 struct wmi_fils_discovery_cmd { 5591 u32 tlv_header; 5592 u32 vdev_id; 5593 u32 interval; 5594 u32 config; /* enum wmi_fils_discovery_cmd_type */ 5595 } __packed; 5596 5597 struct wmi_fils_discovery_tmpl_cmd { 5598 u32 tlv_header; 5599 u32 vdev_id; 5600 u32 buf_len; 5601 } __packed; 5602 5603 struct wmi_probe_tmpl_cmd { 5604 u32 tlv_header; 5605 u32 vdev_id; 5606 u32 buf_len; 5607 } __packed; 5608 5609 struct target_resource_config { 5610 u32 num_vdevs; 5611 u32 num_peers; 5612 u32 num_active_peers; 5613 u32 num_offload_peers; 5614 u32 num_offload_reorder_buffs; 5615 u32 num_peer_keys; 5616 u32 num_tids; 5617 u32 ast_skid_limit; 5618 u32 tx_chain_mask; 5619 u32 rx_chain_mask; 5620 u32 rx_timeout_pri[4]; 5621 u32 rx_decap_mode; 5622 u32 scan_max_pending_req; 5623 u32 bmiss_offload_max_vdev; 5624 u32 roam_offload_max_vdev; 5625 u32 roam_offload_max_ap_profiles; 5626 u32 num_mcast_groups; 5627 u32 num_mcast_table_elems; 5628 u32 mcast2ucast_mode; 5629 u32 tx_dbg_log_size; 5630 u32 num_wds_entries; 5631 u32 dma_burst_size; 5632 u32 mac_aggr_delim; 5633 u32 rx_skip_defrag_timeout_dup_detection_check; 5634 u32 vow_config; 5635 u32 gtk_offload_max_vdev; 5636 u32 num_msdu_desc; 5637 u32 max_frag_entries; 5638 u32 max_peer_ext_stats; 5639 u32 smart_ant_cap; 5640 u32 bk_minfree; 5641 u32 be_minfree; 5642 u32 vi_minfree; 5643 u32 vo_minfree; 5644 u32 rx_batchmode; 5645 u32 tt_support; 5646 u32 flag1; 5647 u32 iphdr_pad_config; 5648 u32 qwrap_config:16, 5649 alloc_frag_desc_for_data_pkt:16; 5650 u32 num_tdls_vdevs; 5651 u32 num_tdls_conn_table_entries; 5652 u32 beacon_tx_offload_max_vdev; 5653 u32 num_multicast_filter_entries; 5654 u32 num_wow_filters; 5655 u32 num_keep_alive_pattern; 5656 u32 keep_alive_pattern_size; 5657 u32 max_tdls_concurrent_sleep_sta; 5658 u32 max_tdls_concurrent_buffer_sta; 5659 u32 wmi_send_separate; 5660 u32 num_ocb_vdevs; 5661 u32 num_ocb_channels; 5662 u32 num_ocb_schedules; 5663 u32 num_ns_ext_tuples_cfg; 5664 u32 bpf_instruction_size; 5665 u32 max_bssid_rx_filters; 5666 u32 use_pdev_id; 5667 u32 peer_map_unmap_v2_support; 5668 u32 sched_params; 5669 u32 twt_ap_pdev_count; 5670 u32 twt_ap_sta_count; 5671 u8 is_reg_cc_ext_event_supported; 5672 u32 ema_max_vap_cnt; 5673 u32 ema_max_profile_period; 5674 }; 5675 5676 enum wmi_debug_log_param { 5677 WMI_DEBUG_LOG_PARAM_LOG_LEVEL = 0x1, 5678 WMI_DEBUG_LOG_PARAM_VDEV_ENABLE, 5679 WMI_DEBUG_LOG_PARAM_VDEV_DISABLE, 5680 WMI_DEBUG_LOG_PARAM_VDEV_ENABLE_BITMAP, 5681 WMI_DEBUG_LOG_PARAM_MOD_ENABLE_BITMAP, 5682 WMI_DEBUG_LOG_PARAM_WOW_MOD_ENABLE_BITMAP, 5683 }; 5684 5685 struct wmi_debug_log_config_cmd_fixed_param { 5686 u32 tlv_header; 5687 u32 dbg_log_param; 5688 u32 value; 5689 } __packed; 5690 5691 #define WMI_MAX_MEM_REQS 32 5692 5693 #define MAX_RADIOS 3 5694 5695 #define WMI_SERVICE_READY_TIMEOUT_HZ (5 * HZ) 5696 #define WMI_SEND_TIMEOUT_HZ (3 * HZ) 5697 5698 enum ath11k_wmi_peer_ps_state { 5699 WMI_PEER_PS_STATE_OFF, 5700 WMI_PEER_PS_STATE_ON, 5701 WMI_PEER_PS_STATE_DISABLED, 5702 }; 5703 5704 enum wmi_peer_ps_supported_bitmap { 5705 /* Used to indicate that power save state change is valid */ 5706 WMI_PEER_PS_VALID = 0x1, 5707 WMI_PEER_PS_STATE_TIMESTAMP = 0x2, 5708 }; 5709 5710 struct wmi_peer_sta_ps_state_chg_event { 5711 struct wmi_mac_addr peer_macaddr; 5712 u32 peer_ps_state; 5713 u32 ps_supported_bitmap; 5714 u32 peer_ps_valid; 5715 u32 peer_ps_timestamp; 5716 } __packed; 5717 5718 struct ath11k_wmi_base { 5719 struct ath11k_base *ab; 5720 struct ath11k_pdev_wmi wmi[MAX_RADIOS]; 5721 enum ath11k_htc_ep_id wmi_endpoint_id[MAX_RADIOS]; 5722 u32 max_msg_len[MAX_RADIOS]; 5723 5724 struct completion service_ready; 5725 struct completion unified_ready; 5726 DECLARE_BITMAP(svc_map, WMI_MAX_EXT2_SERVICE); 5727 wait_queue_head_t tx_credits_wq; 5728 const struct wmi_peer_flags_map *peer_flags; 5729 u32 num_mem_chunks; 5730 u32 rx_decap_mode; 5731 struct wmi_host_mem_chunk mem_chunks[WMI_MAX_MEM_REQS]; 5732 5733 enum wmi_host_hw_mode_config_type preferred_hw_mode; 5734 struct target_resource_config wlan_resource_config; 5735 5736 struct ath11k_targ_cap *targ_cap; 5737 }; 5738 5739 /* Definition of HW data filtering */ 5740 enum hw_data_filter_type { 5741 WMI_HW_DATA_FILTER_DROP_NON_ARP_BC = BIT(0), 5742 WMI_HW_DATA_FILTER_DROP_NON_ICMPV6_MC = BIT(1), 5743 }; 5744 5745 struct wmi_hw_data_filter_cmd { 5746 u32 tlv_header; 5747 u32 vdev_id; 5748 u32 enable; 5749 u32 hw_filter_bitmap; 5750 } __packed; 5751 5752 /* WOW structures */ 5753 enum wmi_wow_wakeup_event { 5754 WOW_BMISS_EVENT = 0, 5755 WOW_BETTER_AP_EVENT, 5756 WOW_DEAUTH_RECVD_EVENT, 5757 WOW_MAGIC_PKT_RECVD_EVENT, 5758 WOW_GTK_ERR_EVENT, 5759 WOW_FOURWAY_HSHAKE_EVENT, 5760 WOW_EAPOL_RECVD_EVENT, 5761 WOW_NLO_DETECTED_EVENT, 5762 WOW_DISASSOC_RECVD_EVENT, 5763 WOW_PATTERN_MATCH_EVENT, 5764 WOW_CSA_IE_EVENT, 5765 WOW_PROBE_REQ_WPS_IE_EVENT, 5766 WOW_AUTH_REQ_EVENT, 5767 WOW_ASSOC_REQ_EVENT, 5768 WOW_HTT_EVENT, 5769 WOW_RA_MATCH_EVENT, 5770 WOW_HOST_AUTO_SHUTDOWN_EVENT, 5771 WOW_IOAC_MAGIC_EVENT, 5772 WOW_IOAC_SHORT_EVENT, 5773 WOW_IOAC_EXTEND_EVENT, 5774 WOW_IOAC_TIMER_EVENT, 5775 WOW_DFS_PHYERR_RADAR_EVENT, 5776 WOW_BEACON_EVENT, 5777 WOW_CLIENT_KICKOUT_EVENT, 5778 WOW_EVENT_MAX, 5779 }; 5780 5781 enum wmi_wow_interface_cfg { 5782 WOW_IFACE_PAUSE_ENABLED, 5783 WOW_IFACE_PAUSE_DISABLED 5784 }; 5785 5786 #define C2S(x) case x: return #x 5787 5788 static inline const char *wow_wakeup_event(enum wmi_wow_wakeup_event ev) 5789 { 5790 switch (ev) { 5791 C2S(WOW_BMISS_EVENT); 5792 C2S(WOW_BETTER_AP_EVENT); 5793 C2S(WOW_DEAUTH_RECVD_EVENT); 5794 C2S(WOW_MAGIC_PKT_RECVD_EVENT); 5795 C2S(WOW_GTK_ERR_EVENT); 5796 C2S(WOW_FOURWAY_HSHAKE_EVENT); 5797 C2S(WOW_EAPOL_RECVD_EVENT); 5798 C2S(WOW_NLO_DETECTED_EVENT); 5799 C2S(WOW_DISASSOC_RECVD_EVENT); 5800 C2S(WOW_PATTERN_MATCH_EVENT); 5801 C2S(WOW_CSA_IE_EVENT); 5802 C2S(WOW_PROBE_REQ_WPS_IE_EVENT); 5803 C2S(WOW_AUTH_REQ_EVENT); 5804 C2S(WOW_ASSOC_REQ_EVENT); 5805 C2S(WOW_HTT_EVENT); 5806 C2S(WOW_RA_MATCH_EVENT); 5807 C2S(WOW_HOST_AUTO_SHUTDOWN_EVENT); 5808 C2S(WOW_IOAC_MAGIC_EVENT); 5809 C2S(WOW_IOAC_SHORT_EVENT); 5810 C2S(WOW_IOAC_EXTEND_EVENT); 5811 C2S(WOW_IOAC_TIMER_EVENT); 5812 C2S(WOW_DFS_PHYERR_RADAR_EVENT); 5813 C2S(WOW_BEACON_EVENT); 5814 C2S(WOW_CLIENT_KICKOUT_EVENT); 5815 C2S(WOW_EVENT_MAX); 5816 default: 5817 return NULL; 5818 } 5819 } 5820 5821 enum wmi_wow_wake_reason { 5822 WOW_REASON_UNSPECIFIED = -1, 5823 WOW_REASON_NLOD = 0, 5824 WOW_REASON_AP_ASSOC_LOST, 5825 WOW_REASON_LOW_RSSI, 5826 WOW_REASON_DEAUTH_RECVD, 5827 WOW_REASON_DISASSOC_RECVD, 5828 WOW_REASON_GTK_HS_ERR, 5829 WOW_REASON_EAP_REQ, 5830 WOW_REASON_FOURWAY_HS_RECV, 5831 WOW_REASON_TIMER_INTR_RECV, 5832 WOW_REASON_PATTERN_MATCH_FOUND, 5833 WOW_REASON_RECV_MAGIC_PATTERN, 5834 WOW_REASON_P2P_DISC, 5835 WOW_REASON_WLAN_HB, 5836 WOW_REASON_CSA_EVENT, 5837 WOW_REASON_PROBE_REQ_WPS_IE_RECV, 5838 WOW_REASON_AUTH_REQ_RECV, 5839 WOW_REASON_ASSOC_REQ_RECV, 5840 WOW_REASON_HTT_EVENT, 5841 WOW_REASON_RA_MATCH, 5842 WOW_REASON_HOST_AUTO_SHUTDOWN, 5843 WOW_REASON_IOAC_MAGIC_EVENT, 5844 WOW_REASON_IOAC_SHORT_EVENT, 5845 WOW_REASON_IOAC_EXTEND_EVENT, 5846 WOW_REASON_IOAC_TIMER_EVENT, 5847 WOW_REASON_ROAM_HO, 5848 WOW_REASON_DFS_PHYERR_RADADR_EVENT, 5849 WOW_REASON_BEACON_RECV, 5850 WOW_REASON_CLIENT_KICKOUT_EVENT, 5851 WOW_REASON_PAGE_FAULT = 0x3a, 5852 WOW_REASON_DEBUG_TEST = 0xFF, 5853 }; 5854 5855 static inline const char *wow_reason(enum wmi_wow_wake_reason reason) 5856 { 5857 switch (reason) { 5858 C2S(WOW_REASON_UNSPECIFIED); 5859 C2S(WOW_REASON_NLOD); 5860 C2S(WOW_REASON_AP_ASSOC_LOST); 5861 C2S(WOW_REASON_LOW_RSSI); 5862 C2S(WOW_REASON_DEAUTH_RECVD); 5863 C2S(WOW_REASON_DISASSOC_RECVD); 5864 C2S(WOW_REASON_GTK_HS_ERR); 5865 C2S(WOW_REASON_EAP_REQ); 5866 C2S(WOW_REASON_FOURWAY_HS_RECV); 5867 C2S(WOW_REASON_TIMER_INTR_RECV); 5868 C2S(WOW_REASON_PATTERN_MATCH_FOUND); 5869 C2S(WOW_REASON_RECV_MAGIC_PATTERN); 5870 C2S(WOW_REASON_P2P_DISC); 5871 C2S(WOW_REASON_WLAN_HB); 5872 C2S(WOW_REASON_CSA_EVENT); 5873 C2S(WOW_REASON_PROBE_REQ_WPS_IE_RECV); 5874 C2S(WOW_REASON_AUTH_REQ_RECV); 5875 C2S(WOW_REASON_ASSOC_REQ_RECV); 5876 C2S(WOW_REASON_HTT_EVENT); 5877 C2S(WOW_REASON_RA_MATCH); 5878 C2S(WOW_REASON_HOST_AUTO_SHUTDOWN); 5879 C2S(WOW_REASON_IOAC_MAGIC_EVENT); 5880 C2S(WOW_REASON_IOAC_SHORT_EVENT); 5881 C2S(WOW_REASON_IOAC_EXTEND_EVENT); 5882 C2S(WOW_REASON_IOAC_TIMER_EVENT); 5883 C2S(WOW_REASON_ROAM_HO); 5884 C2S(WOW_REASON_DFS_PHYERR_RADADR_EVENT); 5885 C2S(WOW_REASON_BEACON_RECV); 5886 C2S(WOW_REASON_CLIENT_KICKOUT_EVENT); 5887 C2S(WOW_REASON_PAGE_FAULT); 5888 C2S(WOW_REASON_DEBUG_TEST); 5889 default: 5890 return NULL; 5891 } 5892 } 5893 5894 #undef C2S 5895 5896 struct wmi_wow_ev_arg { 5897 u32 vdev_id; 5898 u32 flag; 5899 enum wmi_wow_wake_reason wake_reason; 5900 u32 data_len; 5901 }; 5902 5903 enum wmi_tlv_pattern_type { 5904 WOW_PATTERN_MIN = 0, 5905 WOW_BITMAP_PATTERN = WOW_PATTERN_MIN, 5906 WOW_IPV4_SYNC_PATTERN, 5907 WOW_IPV6_SYNC_PATTERN, 5908 WOW_WILD_CARD_PATTERN, 5909 WOW_TIMER_PATTERN, 5910 WOW_MAGIC_PATTERN, 5911 WOW_IPV6_RA_PATTERN, 5912 WOW_IOAC_PKT_PATTERN, 5913 WOW_IOAC_TMR_PATTERN, 5914 WOW_PATTERN_MAX 5915 }; 5916 5917 #define WOW_DEFAULT_BITMAP_PATTERN_SIZE 148 5918 #define WOW_DEFAULT_BITMASK_SIZE 148 5919 5920 #define WOW_MIN_PATTERN_SIZE 1 5921 #define WOW_MAX_PATTERN_SIZE 148 5922 #define WOW_MAX_PKT_OFFSET 128 5923 #define WOW_HDR_LEN (sizeof(struct ieee80211_hdr_3addr) + \ 5924 sizeof(struct rfc1042_hdr)) 5925 #define WOW_MAX_REDUCE (WOW_HDR_LEN - sizeof(struct ethhdr) - \ 5926 offsetof(struct ieee80211_hdr_3addr, addr1)) 5927 5928 struct wmi_wow_add_del_event_cmd { 5929 u32 tlv_header; 5930 u32 vdev_id; 5931 u32 is_add; 5932 u32 event_bitmap; 5933 } __packed; 5934 5935 struct wmi_wow_enable_cmd { 5936 u32 tlv_header; 5937 u32 enable; 5938 u32 pause_iface_config; 5939 u32 flags; 5940 } __packed; 5941 5942 struct wmi_wow_host_wakeup_ind { 5943 u32 tlv_header; 5944 u32 reserved; 5945 } __packed; 5946 5947 struct wmi_tlv_wow_event_info { 5948 u32 vdev_id; 5949 u32 flag; 5950 u32 wake_reason; 5951 u32 data_len; 5952 } __packed; 5953 5954 struct wmi_wow_bitmap_pattern { 5955 u32 tlv_header; 5956 u8 patternbuf[WOW_DEFAULT_BITMAP_PATTERN_SIZE]; 5957 u8 bitmaskbuf[WOW_DEFAULT_BITMASK_SIZE]; 5958 u32 pattern_offset; 5959 u32 pattern_len; 5960 u32 bitmask_len; 5961 u32 pattern_id; 5962 } __packed; 5963 5964 struct wmi_wow_add_pattern_cmd { 5965 u32 tlv_header; 5966 u32 vdev_id; 5967 u32 pattern_id; 5968 u32 pattern_type; 5969 } __packed; 5970 5971 struct wmi_wow_del_pattern_cmd { 5972 u32 tlv_header; 5973 u32 vdev_id; 5974 u32 pattern_id; 5975 u32 pattern_type; 5976 } __packed; 5977 5978 #define WMI_PNO_MAX_SCHED_SCAN_PLANS 2 5979 #define WMI_PNO_MAX_SCHED_SCAN_PLAN_INT 7200 5980 #define WMI_PNO_MAX_SCHED_SCAN_PLAN_ITRNS 100 5981 #define WMI_PNO_MAX_NETW_CHANNELS 26 5982 #define WMI_PNO_MAX_NETW_CHANNELS_EX 60 5983 #define WMI_PNO_MAX_SUPP_NETWORKS WLAN_SCAN_PARAMS_MAX_SSID 5984 #define WMI_PNO_MAX_IE_LENGTH WLAN_SCAN_PARAMS_MAX_IE_LEN 5985 5986 /* size based of dot11 declaration without extra IEs as we will not carry those for PNO */ 5987 #define WMI_PNO_MAX_PB_REQ_SIZE 450 5988 5989 #define WMI_PNO_24G_DEFAULT_CH 1 5990 #define WMI_PNO_5G_DEFAULT_CH 36 5991 5992 #define WMI_ACTIVE_MAX_CHANNEL_TIME 40 5993 #define WMI_PASSIVE_MAX_CHANNEL_TIME 110 5994 5995 /* SSID broadcast type */ 5996 enum wmi_ssid_bcast_type { 5997 BCAST_UNKNOWN = 0, 5998 BCAST_NORMAL = 1, 5999 BCAST_HIDDEN = 2, 6000 }; 6001 6002 #define WMI_NLO_MAX_SSIDS 16 6003 #define WMI_NLO_MAX_CHAN 48 6004 6005 #define WMI_NLO_CONFIG_STOP BIT(0) 6006 #define WMI_NLO_CONFIG_START BIT(1) 6007 #define WMI_NLO_CONFIG_RESET BIT(2) 6008 #define WMI_NLO_CONFIG_SLOW_SCAN BIT(4) 6009 #define WMI_NLO_CONFIG_FAST_SCAN BIT(5) 6010 #define WMI_NLO_CONFIG_SSID_HIDE_EN BIT(6) 6011 6012 /* This bit is used to indicate if EPNO or supplicant PNO is enabled. 6013 * Only one of them can be enabled at a given time 6014 */ 6015 #define WMI_NLO_CONFIG_ENLO BIT(7) 6016 #define WMI_NLO_CONFIG_SCAN_PASSIVE BIT(8) 6017 #define WMI_NLO_CONFIG_ENLO_RESET BIT(9) 6018 #define WMI_NLO_CONFIG_SPOOFED_MAC_IN_PROBE_REQ BIT(10) 6019 #define WMI_NLO_CONFIG_RANDOM_SEQ_NO_IN_PROBE_REQ BIT(11) 6020 #define WMI_NLO_CONFIG_ENABLE_IE_WHITELIST_IN_PROBE_REQ BIT(12) 6021 #define WMI_NLO_CONFIG_ENABLE_CNLO_RSSI_CONFIG BIT(13) 6022 6023 struct wmi_nlo_ssid_param { 6024 u32 valid; 6025 struct wmi_ssid ssid; 6026 } __packed; 6027 6028 struct wmi_nlo_enc_param { 6029 u32 valid; 6030 u32 enc_type; 6031 } __packed; 6032 6033 struct wmi_nlo_auth_param { 6034 u32 valid; 6035 u32 auth_type; 6036 } __packed; 6037 6038 struct wmi_nlo_bcast_nw_param { 6039 u32 valid; 6040 u32 bcast_nw_type; 6041 } __packed; 6042 6043 struct wmi_nlo_rssi_param { 6044 u32 valid; 6045 s32 rssi; 6046 } __packed; 6047 6048 struct nlo_configured_parameters { 6049 /* TLV tag and len;*/ 6050 u32 tlv_header; 6051 struct wmi_nlo_ssid_param ssid; 6052 struct wmi_nlo_enc_param enc_type; 6053 struct wmi_nlo_auth_param auth_type; 6054 struct wmi_nlo_rssi_param rssi_cond; 6055 6056 /* indicates if the SSID is hidden or not */ 6057 struct wmi_nlo_bcast_nw_param bcast_nw_type; 6058 } __packed; 6059 6060 struct wmi_network_type { 6061 struct wmi_ssid ssid; 6062 u32 authentication; 6063 u32 encryption; 6064 u32 bcast_nw_type; 6065 u8 channel_count; 6066 u16 channels[WMI_PNO_MAX_NETW_CHANNELS_EX]; 6067 s32 rssi_threshold; 6068 }; 6069 6070 struct wmi_pno_scan_req { 6071 u8 enable; 6072 u8 vdev_id; 6073 u8 uc_networks_count; 6074 struct wmi_network_type a_networks[WMI_PNO_MAX_SUPP_NETWORKS]; 6075 u32 fast_scan_period; 6076 u32 slow_scan_period; 6077 u8 fast_scan_max_cycles; 6078 6079 bool do_passive_scan; 6080 6081 u32 delay_start_time; 6082 u32 active_min_time; 6083 u32 active_max_time; 6084 u32 passive_min_time; 6085 u32 passive_max_time; 6086 6087 /* mac address randomization attributes */ 6088 u32 enable_pno_scan_randomization; 6089 u8 mac_addr[ETH_ALEN]; 6090 u8 mac_addr_mask[ETH_ALEN]; 6091 }; 6092 6093 struct wmi_wow_nlo_config_cmd { 6094 u32 tlv_header; 6095 u32 flags; 6096 u32 vdev_id; 6097 u32 fast_scan_max_cycles; 6098 u32 active_dwell_time; 6099 u32 passive_dwell_time; 6100 u32 probe_bundle_size; 6101 6102 /* ART = IRT */ 6103 u32 rest_time; 6104 6105 /* Max value that can be reached after SBM */ 6106 u32 max_rest_time; 6107 6108 /* SBM */ 6109 u32 scan_backoff_multiplier; 6110 6111 /* SCBM */ 6112 u32 fast_scan_period; 6113 6114 /* specific to windows */ 6115 u32 slow_scan_period; 6116 6117 u32 no_of_ssids; 6118 6119 u32 num_of_channels; 6120 6121 /* NLO scan start delay time in milliseconds */ 6122 u32 delay_start_time; 6123 6124 /* MAC Address to use in Probe Req as SA */ 6125 struct wmi_mac_addr mac_addr; 6126 6127 /* Mask on which MAC has to be randomized */ 6128 struct wmi_mac_addr mac_mask; 6129 6130 /* IE bitmap to use in Probe Req */ 6131 u32 ie_bitmap[8]; 6132 6133 /* Number of vendor OUIs. In the TLV vendor_oui[] */ 6134 u32 num_vendor_oui; 6135 6136 /* Number of connected NLO band preferences */ 6137 u32 num_cnlo_band_pref; 6138 6139 /* The TLVs will follow. 6140 * nlo_configured_parameters nlo_list[]; 6141 * u32 channel_list[num_of_channels]; 6142 */ 6143 } __packed; 6144 6145 #define WMI_MAX_NS_OFFLOADS 2 6146 #define WMI_MAX_ARP_OFFLOADS 2 6147 6148 #define WMI_ARPOL_FLAGS_VALID BIT(0) 6149 #define WMI_ARPOL_FLAGS_MAC_VALID BIT(1) 6150 #define WMI_ARPOL_FLAGS_REMOTE_IP_VALID BIT(2) 6151 6152 struct wmi_arp_offload_tuple { 6153 u32 tlv_header; 6154 u32 flags; 6155 u8 target_ipaddr[4]; 6156 u8 remote_ipaddr[4]; 6157 struct wmi_mac_addr target_mac; 6158 } __packed; 6159 6160 #define WMI_NSOL_FLAGS_VALID BIT(0) 6161 #define WMI_NSOL_FLAGS_MAC_VALID BIT(1) 6162 #define WMI_NSOL_FLAGS_REMOTE_IP_VALID BIT(2) 6163 #define WMI_NSOL_FLAGS_IS_IPV6_ANYCAST BIT(3) 6164 6165 #define WMI_NSOL_MAX_TARGET_IPS 2 6166 6167 struct wmi_ns_offload_tuple { 6168 u32 tlv_header; 6169 u32 flags; 6170 u8 target_ipaddr[WMI_NSOL_MAX_TARGET_IPS][16]; 6171 u8 solicitation_ipaddr[16]; 6172 u8 remote_ipaddr[16]; 6173 struct wmi_mac_addr target_mac; 6174 } __packed; 6175 6176 struct wmi_set_arp_ns_offload_cmd { 6177 u32 tlv_header; 6178 u32 flags; 6179 u32 vdev_id; 6180 u32 num_ns_ext_tuples; 6181 /* The TLVs follow: 6182 * wmi_ns_offload_tuple ns_tuples[WMI_MAX_NS_OFFLOADS]; 6183 * wmi_arp_offload_tuple arp_tuples[WMI_MAX_ARP_OFFLOADS]; 6184 * wmi_ns_offload_tuple ns_ext_tuples[num_ns_ext_tuples]; 6185 */ 6186 } __packed; 6187 6188 #define GTK_OFFLOAD_OPCODE_MASK 0xFF000000 6189 #define GTK_OFFLOAD_ENABLE_OPCODE 0x01000000 6190 #define GTK_OFFLOAD_DISABLE_OPCODE 0x02000000 6191 #define GTK_OFFLOAD_REQUEST_STATUS_OPCODE 0x04000000 6192 6193 #define GTK_OFFLOAD_KEK_BYTES 16 6194 #define GTK_OFFLOAD_KCK_BYTES 16 6195 #define GTK_REPLAY_COUNTER_BYTES 8 6196 #define WMI_MAX_KEY_LEN 32 6197 #define IGTK_PN_SIZE 6 6198 6199 struct wmi_replayc_cnt { 6200 union { 6201 u8 counter[GTK_REPLAY_COUNTER_BYTES]; 6202 struct { 6203 u32 word0; 6204 u32 word1; 6205 } __packed; 6206 } __packed; 6207 } __packed; 6208 6209 struct wmi_gtk_offload_status_event { 6210 u32 vdev_id; 6211 u32 flags; 6212 u32 refresh_cnt; 6213 struct wmi_replayc_cnt replay_ctr; 6214 u8 igtk_key_index; 6215 u8 igtk_key_length; 6216 u8 igtk_key_rsc[IGTK_PN_SIZE]; 6217 u8 igtk_key[WMI_MAX_KEY_LEN]; 6218 u8 gtk_key_index; 6219 u8 gtk_key_length; 6220 u8 gtk_key_rsc[GTK_REPLAY_COUNTER_BYTES]; 6221 u8 gtk_key[WMI_MAX_KEY_LEN]; 6222 } __packed; 6223 6224 struct wmi_gtk_rekey_offload_cmd { 6225 u32 tlv_header; 6226 u32 vdev_id; 6227 u32 flags; 6228 u8 kek[GTK_OFFLOAD_KEK_BYTES]; 6229 u8 kck[GTK_OFFLOAD_KCK_BYTES]; 6230 u8 replay_ctr[GTK_REPLAY_COUNTER_BYTES]; 6231 } __packed; 6232 6233 #define BIOS_SAR_TABLE_LEN (22) 6234 #define BIOS_SAR_RSVD1_LEN (6) 6235 #define BIOS_SAR_RSVD2_LEN (18) 6236 6237 struct wmi_pdev_set_sar_table_cmd { 6238 u32 tlv_header; 6239 u32 pdev_id; 6240 u32 sar_len; 6241 u32 rsvd_len; 6242 } __packed; 6243 6244 struct wmi_pdev_set_geo_table_cmd { 6245 u32 tlv_header; 6246 u32 pdev_id; 6247 u32 rsvd_len; 6248 } __packed; 6249 6250 struct wmi_sta_keepalive_cmd { 6251 u32 tlv_header; 6252 u32 vdev_id; 6253 u32 enabled; 6254 6255 /* WMI_STA_KEEPALIVE_METHOD_ */ 6256 u32 method; 6257 6258 /* in seconds */ 6259 u32 interval; 6260 6261 /* following this structure is the TLV for struct 6262 * wmi_sta_keepalive_arp_resp 6263 */ 6264 } __packed; 6265 6266 struct wmi_sta_keepalive_arp_resp { 6267 u32 tlv_header; 6268 u32 src_ip4_addr; 6269 u32 dest_ip4_addr; 6270 struct wmi_mac_addr dest_mac_addr; 6271 } __packed; 6272 6273 struct wmi_sta_keepalive_arg { 6274 u32 vdev_id; 6275 u32 enabled; 6276 u32 method; 6277 u32 interval; 6278 u32 src_ip4_addr; 6279 u32 dest_ip4_addr; 6280 const u8 dest_mac_addr[ETH_ALEN]; 6281 }; 6282 6283 enum wmi_sta_keepalive_method { 6284 WMI_STA_KEEPALIVE_METHOD_NULL_FRAME = 1, 6285 WMI_STA_KEEPALIVE_METHOD_UNSOLICITED_ARP_RESPONSE = 2, 6286 WMI_STA_KEEPALIVE_METHOD_ETHERNET_LOOPBACK = 3, 6287 WMI_STA_KEEPALIVE_METHOD_GRATUITOUS_ARP_REQUEST = 4, 6288 WMI_STA_KEEPALIVE_METHOD_MGMT_VENDOR_ACTION = 5, 6289 }; 6290 6291 #define WMI_STA_KEEPALIVE_INTERVAL_DEFAULT 30 6292 #define WMI_STA_KEEPALIVE_INTERVAL_DISABLE 0 6293 6294 int ath11k_wmi_cmd_send(struct ath11k_pdev_wmi *wmi, struct sk_buff *skb, 6295 u32 cmd_id); 6296 struct sk_buff *ath11k_wmi_alloc_skb(struct ath11k_wmi_base *wmi_sc, u32 len); 6297 int ath11k_wmi_mgmt_send(struct ath11k *ar, u32 vdev_id, u32 buf_id, 6298 struct sk_buff *frame); 6299 int ath11k_wmi_bcn_tmpl(struct ath11k *ar, u32 vdev_id, 6300 struct ieee80211_mutable_offsets *offs, 6301 struct sk_buff *bcn); 6302 int ath11k_wmi_vdev_down(struct ath11k *ar, u8 vdev_id); 6303 int ath11k_wmi_vdev_up(struct ath11k *ar, u32 vdev_id, u32 aid, 6304 const u8 *bssid, u8 *tx_bssid, u32 nontx_profile_idx, 6305 u32 nontx_profile_cnt); 6306 int ath11k_wmi_vdev_stop(struct ath11k *ar, u8 vdev_id); 6307 int ath11k_wmi_vdev_start(struct ath11k *ar, struct wmi_vdev_start_req_arg *arg, 6308 bool restart); 6309 int ath11k_wmi_set_peer_param(struct ath11k *ar, const u8 *peer_addr, 6310 u32 vdev_id, u32 param_id, u32 param_val); 6311 int ath11k_wmi_pdev_set_param(struct ath11k *ar, u32 param_id, 6312 u32 param_value, u8 pdev_id); 6313 int ath11k_wmi_pdev_set_ps_mode(struct ath11k *ar, int vdev_id, 6314 enum wmi_sta_ps_mode psmode); 6315 int ath11k_wmi_wait_for_unified_ready(struct ath11k_base *ab); 6316 int ath11k_wmi_cmd_init(struct ath11k_base *ab); 6317 int ath11k_wmi_wait_for_service_ready(struct ath11k_base *ab); 6318 int ath11k_wmi_connect(struct ath11k_base *ab); 6319 int ath11k_wmi_pdev_attach(struct ath11k_base *ab, 6320 u8 pdev_id); 6321 int ath11k_wmi_attach(struct ath11k_base *ab); 6322 void ath11k_wmi_detach(struct ath11k_base *ab); 6323 int ath11k_wmi_vdev_create(struct ath11k *ar, u8 *macaddr, 6324 struct vdev_create_params *param); 6325 int ath11k_wmi_peer_rx_reorder_queue_setup(struct ath11k *ar, int vdev_id, 6326 const u8 *addr, dma_addr_t paddr, 6327 u8 tid, u8 ba_window_size_valid, 6328 u32 ba_window_size); 6329 int ath11k_wmi_send_peer_create_cmd(struct ath11k *ar, 6330 struct peer_create_params *param); 6331 int ath11k_wmi_vdev_set_param_cmd(struct ath11k *ar, u32 vdev_id, 6332 u32 param_id, u32 param_value); 6333 6334 int ath11k_wmi_set_sta_ps_param(struct ath11k *ar, u32 vdev_id, 6335 u32 param, u32 param_value); 6336 int ath11k_wmi_force_fw_hang_cmd(struct ath11k *ar, u32 type, u32 delay_time_ms); 6337 int ath11k_wmi_send_peer_delete_cmd(struct ath11k *ar, 6338 const u8 *peer_addr, u8 vdev_id); 6339 int ath11k_wmi_vdev_delete(struct ath11k *ar, u8 vdev_id); 6340 void ath11k_wmi_start_scan_init(struct ath11k *ar, struct scan_req_params *arg); 6341 int ath11k_wmi_send_scan_start_cmd(struct ath11k *ar, 6342 struct scan_req_params *params); 6343 int ath11k_wmi_send_scan_stop_cmd(struct ath11k *ar, 6344 struct scan_cancel_param *param); 6345 int ath11k_wmi_send_wmm_update_cmd_tlv(struct ath11k *ar, u32 vdev_id, 6346 struct wmi_wmm_params_all_arg *param); 6347 int ath11k_wmi_pdev_suspend(struct ath11k *ar, u32 suspend_opt, 6348 u32 pdev_id); 6349 int ath11k_wmi_pdev_resume(struct ath11k *ar, u32 pdev_id); 6350 6351 int ath11k_wmi_send_peer_assoc_cmd(struct ath11k *ar, 6352 struct peer_assoc_params *param); 6353 int ath11k_wmi_vdev_install_key(struct ath11k *ar, 6354 struct wmi_vdev_install_key_arg *arg); 6355 int ath11k_wmi_pdev_bss_chan_info_request(struct ath11k *ar, 6356 enum wmi_bss_chan_info_req_type type); 6357 int ath11k_wmi_send_stats_request_cmd(struct ath11k *ar, 6358 struct stats_request_params *param); 6359 int ath11k_wmi_send_pdev_temperature_cmd(struct ath11k *ar); 6360 int ath11k_wmi_send_peer_flush_tids_cmd(struct ath11k *ar, 6361 u8 peer_addr[ETH_ALEN], 6362 struct peer_flush_params *param); 6363 int ath11k_wmi_send_set_ap_ps_param_cmd(struct ath11k *ar, u8 *peer_addr, 6364 struct ap_ps_params *param); 6365 int ath11k_wmi_send_scan_chan_list_cmd(struct ath11k *ar, 6366 struct scan_chan_list_params *chan_list); 6367 int ath11k_wmi_send_dfs_phyerr_offload_enable_cmd(struct ath11k *ar, 6368 u32 pdev_id); 6369 int ath11k_wmi_addba_clear_resp(struct ath11k *ar, u32 vdev_id, const u8 *mac); 6370 int ath11k_wmi_addba_send(struct ath11k *ar, u32 vdev_id, const u8 *mac, 6371 u32 tid, u32 buf_size); 6372 int ath11k_wmi_addba_set_resp(struct ath11k *ar, u32 vdev_id, const u8 *mac, 6373 u32 tid, u32 status); 6374 int ath11k_wmi_delba_send(struct ath11k *ar, u32 vdev_id, const u8 *mac, 6375 u32 tid, u32 initiator, u32 reason); 6376 int ath11k_wmi_send_bcn_offload_control_cmd(struct ath11k *ar, 6377 u32 vdev_id, u32 bcn_ctrl_op); 6378 int ath11k_wmi_send_set_current_country_cmd(struct ath11k *ar, 6379 struct wmi_set_current_country_params *param); 6380 int 6381 ath11k_wmi_send_init_country_cmd(struct ath11k *ar, 6382 struct wmi_init_country_params init_cc_param); 6383 6384 int ath11k_wmi_send_11d_scan_start_cmd(struct ath11k *ar, 6385 struct wmi_11d_scan_start_params *param); 6386 int ath11k_wmi_send_11d_scan_stop_cmd(struct ath11k *ar, u32 vdev_id); 6387 6388 int 6389 ath11k_wmi_send_thermal_mitigation_param_cmd(struct ath11k *ar, 6390 struct thermal_mitigation_params *param); 6391 int ath11k_wmi_pdev_pktlog_enable(struct ath11k *ar, u32 pktlog_filter); 6392 int ath11k_wmi_pdev_pktlog_disable(struct ath11k *ar); 6393 int ath11k_wmi_pdev_peer_pktlog_filter(struct ath11k *ar, u8 *addr, u8 enable); 6394 int 6395 ath11k_wmi_rx_reord_queue_remove(struct ath11k *ar, 6396 struct rx_reorder_queue_remove_params *param); 6397 int ath11k_wmi_send_pdev_set_regdomain(struct ath11k *ar, 6398 struct pdev_set_regdomain_params *param); 6399 int ath11k_wmi_pull_fw_stats(struct ath11k_base *ab, struct sk_buff *skb, 6400 struct ath11k_fw_stats *stats); 6401 void ath11k_wmi_fw_stats_fill(struct ath11k *ar, 6402 struct ath11k_fw_stats *fw_stats, u32 stats_id, 6403 char *buf); 6404 int ath11k_wmi_simulate_radar(struct ath11k *ar); 6405 void ath11k_wmi_fill_default_twt_params(struct wmi_twt_enable_params *twt_params); 6406 int ath11k_wmi_send_twt_enable_cmd(struct ath11k *ar, u32 pdev_id, 6407 struct wmi_twt_enable_params *params); 6408 int ath11k_wmi_send_twt_disable_cmd(struct ath11k *ar, u32 pdev_id); 6409 int ath11k_wmi_send_twt_add_dialog_cmd(struct ath11k *ar, 6410 struct wmi_twt_add_dialog_params *params); 6411 int ath11k_wmi_send_twt_del_dialog_cmd(struct ath11k *ar, 6412 struct wmi_twt_del_dialog_params *params); 6413 int ath11k_wmi_send_twt_pause_dialog_cmd(struct ath11k *ar, 6414 struct wmi_twt_pause_dialog_params *params); 6415 int ath11k_wmi_send_twt_resume_dialog_cmd(struct ath11k *ar, 6416 struct wmi_twt_resume_dialog_params *params); 6417 int ath11k_wmi_send_obss_spr_cmd(struct ath11k *ar, u32 vdev_id, 6418 struct ieee80211_he_obss_pd *he_obss_pd); 6419 int ath11k_wmi_pdev_set_srg_bss_color_bitmap(struct ath11k *ar, u32 *bitmap); 6420 int ath11k_wmi_pdev_set_srg_patial_bssid_bitmap(struct ath11k *ar, u32 *bitmap); 6421 int ath11k_wmi_pdev_srg_obss_color_enable_bitmap(struct ath11k *ar, 6422 u32 *bitmap); 6423 int ath11k_wmi_pdev_srg_obss_bssid_enable_bitmap(struct ath11k *ar, 6424 u32 *bitmap); 6425 int ath11k_wmi_pdev_non_srg_obss_color_enable_bitmap(struct ath11k *ar, 6426 u32 *bitmap); 6427 int ath11k_wmi_pdev_non_srg_obss_bssid_enable_bitmap(struct ath11k *ar, 6428 u32 *bitmap); 6429 int ath11k_wmi_send_obss_color_collision_cfg_cmd(struct ath11k *ar, u32 vdev_id, 6430 u8 bss_color, u32 period, 6431 bool enable); 6432 int ath11k_wmi_send_bss_color_change_enable_cmd(struct ath11k *ar, u32 vdev_id, 6433 bool enable); 6434 int ath11k_wmi_pdev_lro_cfg(struct ath11k *ar, int pdev_id); 6435 int ath11k_wmi_pdev_dma_ring_cfg(struct ath11k *ar, 6436 struct ath11k_wmi_pdev_dma_ring_cfg_req_cmd *param); 6437 int ath11k_wmi_vdev_spectral_enable(struct ath11k *ar, u32 vdev_id, 6438 u32 trigger, u32 enable); 6439 int ath11k_wmi_vdev_spectral_conf(struct ath11k *ar, 6440 struct ath11k_wmi_vdev_spectral_conf_param *param); 6441 int ath11k_wmi_fils_discovery_tmpl(struct ath11k *ar, u32 vdev_id, 6442 struct sk_buff *tmpl); 6443 int ath11k_wmi_fils_discovery(struct ath11k *ar, u32 vdev_id, u32 interval, 6444 bool unsol_bcast_probe_resp_enabled); 6445 int ath11k_wmi_probe_resp_tmpl(struct ath11k *ar, u32 vdev_id, 6446 struct sk_buff *tmpl); 6447 int ath11k_wmi_set_hw_mode(struct ath11k_base *ab, 6448 enum wmi_host_hw_mode_config_type mode); 6449 int ath11k_wmi_wow_host_wakeup_ind(struct ath11k *ar); 6450 int ath11k_wmi_wow_enable(struct ath11k *ar); 6451 int ath11k_wmi_scan_prob_req_oui(struct ath11k *ar, 6452 const u8 mac_addr[ETH_ALEN]); 6453 int ath11k_wmi_fw_dbglog_cfg(struct ath11k *ar, u32 *module_id_bitmap, 6454 struct ath11k_fw_dbglog *dbglog); 6455 int ath11k_wmi_wow_config_pno(struct ath11k *ar, u32 vdev_id, 6456 struct wmi_pno_scan_req *pno_scan); 6457 int ath11k_wmi_wow_del_pattern(struct ath11k *ar, u32 vdev_id, u32 pattern_id); 6458 int ath11k_wmi_wow_add_pattern(struct ath11k *ar, u32 vdev_id, u32 pattern_id, 6459 const u8 *pattern, const u8 *mask, 6460 int pattern_len, int pattern_offset); 6461 int ath11k_wmi_wow_add_wakeup_event(struct ath11k *ar, u32 vdev_id, 6462 enum wmi_wow_wakeup_event event, 6463 u32 enable); 6464 int ath11k_wmi_hw_data_filter_cmd(struct ath11k *ar, u32 vdev_id, 6465 u32 filter_bitmap, bool enable); 6466 int ath11k_wmi_arp_ns_offload(struct ath11k *ar, 6467 struct ath11k_vif *arvif, bool enable); 6468 int ath11k_wmi_gtk_rekey_offload(struct ath11k *ar, 6469 struct ath11k_vif *arvif, bool enable); 6470 int ath11k_wmi_gtk_rekey_getinfo(struct ath11k *ar, 6471 struct ath11k_vif *arvif); 6472 int ath11k_wmi_pdev_set_bios_sar_table_param(struct ath11k *ar, const u8 *sar_val); 6473 int ath11k_wmi_pdev_set_bios_geo_table_param(struct ath11k *ar); 6474 int ath11k_wmi_sta_keepalive(struct ath11k *ar, 6475 const struct wmi_sta_keepalive_arg *arg); 6476 6477 #endif 6478