xref: /openbmc/linux/drivers/net/wireless/ath/ath11k/wmi.h (revision 7e24a55b2122746c2eef192296fc84624354f895)
1d5c65159SKalle Valo /* SPDX-License-Identifier: BSD-3-Clause-Clear */
2d5c65159SKalle Valo /*
3d5c65159SKalle Valo  * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
4*586c7fb1SJeff Johnson  * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
5d5c65159SKalle Valo  */
6d5c65159SKalle Valo 
7d5c65159SKalle Valo #ifndef ATH11K_WMI_H
8d5c65159SKalle Valo #define ATH11K_WMI_H
9d5c65159SKalle Valo 
10d5c65159SKalle Valo #include <net/mac80211.h>
11d5c65159SKalle Valo #include "htc.h"
12d5c65159SKalle Valo 
13d5c65159SKalle Valo struct ath11k_base;
14d5c65159SKalle Valo struct ath11k;
15d5c65159SKalle Valo struct ath11k_fw_stats;
16f295ad91SSeevalamuthu Mariappan struct ath11k_fw_dbglog;
17c3c36bfeSCarl Huang struct ath11k_vif;
18d5c65159SKalle Valo 
19d5c65159SKalle Valo #define PSOC_HOST_MAX_NUM_SS (8)
20d5c65159SKalle Valo 
213fecca0eSJeff Johnson /* defines to set Packet extension values which can be 0 us, 8 usec or 16 usec */
22d5c65159SKalle Valo #define MAX_HE_NSS               8
23d5c65159SKalle Valo #define MAX_HE_MODULATION        8
24d5c65159SKalle Valo #define MAX_HE_RU                4
25d5c65159SKalle Valo #define HE_MODULATION_NONE       7
26d5c65159SKalle Valo #define HE_PET_0_USEC            0
27d5c65159SKalle Valo #define HE_PET_8_USEC            1
28d5c65159SKalle Valo #define HE_PET_16_USEC           2
29d5c65159SKalle Valo 
30bd647855SKarthikeyan Periyasamy #define WMI_MAX_CHAINS		 8
31bd647855SKarthikeyan Periyasamy 
32d5c65159SKalle Valo #define WMI_MAX_NUM_SS                    MAX_HE_NSS
33d5c65159SKalle Valo #define WMI_MAX_NUM_RU                    MAX_HE_RU
34d5c65159SKalle Valo 
35d5c65159SKalle Valo #define WMI_TLV_CMD(grp_id) (((grp_id) << 12) | 0x1)
36d5c65159SKalle Valo #define WMI_TLV_EV(grp_id) (((grp_id) << 12) | 0x1)
37d5c65159SKalle Valo #define WMI_TLV_CMD_UNSUPPORTED 0
38d5c65159SKalle Valo #define WMI_TLV_PDEV_PARAM_UNSUPPORTED 0
39d5c65159SKalle Valo #define WMI_TLV_VDEV_PARAM_UNSUPPORTED 0
40d5c65159SKalle Valo 
41d5c65159SKalle Valo struct wmi_cmd_hdr {
42d5c65159SKalle Valo 	u32 cmd_id;
43d5c65159SKalle Valo } __packed;
44d5c65159SKalle Valo 
45d5c65159SKalle Valo struct wmi_tlv {
46d5c65159SKalle Valo 	u32 header;
4714dd3a71SGustavo A. R. Silva 	u8 value[];
48d5c65159SKalle Valo } __packed;
49d5c65159SKalle Valo 
50d5c65159SKalle Valo #define WMI_TLV_LEN	GENMASK(15, 0)
51d5c65159SKalle Valo #define WMI_TLV_TAG	GENMASK(31, 16)
52ca0e4779SKees Cook #define TLV_HDR_SIZE	sizeof_field(struct wmi_tlv, header)
53d5c65159SKalle Valo 
54d5c65159SKalle Valo #define WMI_CMD_HDR_CMD_ID      GENMASK(23, 0)
55d5c65159SKalle Valo #define WMI_MAX_MEM_REQS        32
56d5c65159SKalle Valo #define ATH11K_MAX_HW_LISTEN_INTERVAL 5
57d5c65159SKalle Valo 
5874601ecfSPradeep Kumar Chitrapu #define WLAN_SCAN_MAX_HINT_S_SSID        10
5974601ecfSPradeep Kumar Chitrapu #define WLAN_SCAN_MAX_HINT_BSSID         10
6074601ecfSPradeep Kumar Chitrapu #define MAX_RNR_BSS                    5
6174601ecfSPradeep Kumar Chitrapu 
6274601ecfSPradeep Kumar Chitrapu #define WLAN_SCAN_MAX_HINT_S_SSID        10
6374601ecfSPradeep Kumar Chitrapu #define WLAN_SCAN_MAX_HINT_BSSID         10
6474601ecfSPradeep Kumar Chitrapu #define MAX_RNR_BSS                    5
6574601ecfSPradeep Kumar Chitrapu 
66d5c65159SKalle Valo #define WLAN_SCAN_PARAMS_MAX_SSID    16
67d5c65159SKalle Valo #define WLAN_SCAN_PARAMS_MAX_BSSID   4
68d5c65159SKalle Valo #define WLAN_SCAN_PARAMS_MAX_IE_LEN  256
69d5c65159SKalle Valo 
70bff621fdSPradeep Kumar Chitrapu #define WMI_APPEND_TO_EXISTING_CHAN_LIST_FLAG 1
71bff621fdSPradeep Kumar Chitrapu 
72b43310e4SGovindaraj Saminathan #define MAX_WMI_UTF_LEN 252
73aacb4622SPradeep Kumar Chitrapu #define WMI_BA_MODE_BUFFER_SIZE_256  3
74d5c65159SKalle Valo /*
75d5c65159SKalle Valo  * HW mode config type replicated from FW header
76d5c65159SKalle Valo  * @WMI_HOST_HW_MODE_SINGLE: Only one PHY is active.
77d5c65159SKalle Valo  * @WMI_HOST_HW_MODE_DBS: Both PHYs are active in different bands,
78d5c65159SKalle Valo  *                        one in 2G and another in 5G.
79d5c65159SKalle Valo  * @WMI_HOST_HW_MODE_SBS_PASSIVE: Both PHYs are in passive mode (only rx) in
80d5c65159SKalle Valo  *                        same band; no tx allowed.
81d5c65159SKalle Valo  * @WMI_HOST_HW_MODE_SBS: Both PHYs are active in the same band.
82d5c65159SKalle Valo  *                        Support for both PHYs within one band is planned
83d5c65159SKalle Valo  *                        for 5G only(as indicated in WMI_MAC_PHY_CAPABILITIES),
84d5c65159SKalle Valo  *                        but could be extended to other bands in the future.
85d5c65159SKalle Valo  *                        The separation of the band between the two PHYs needs
86d5c65159SKalle Valo  *                        to be communicated separately.
87d5c65159SKalle Valo  * @WMI_HOST_HW_MODE_DBS_SBS: 3 PHYs, with 2 on the same band doing SBS
88d5c65159SKalle Valo  *                           as in WMI_HW_MODE_SBS, and 3rd on the other band
89d5c65159SKalle Valo  * @WMI_HOST_HW_MODE_DBS_OR_SBS: Two PHY with one PHY capabale of both 2G and
90d5c65159SKalle Valo  *                        5G. It can support SBS (5G + 5G) OR DBS (5G + 2G).
91d5c65159SKalle Valo  * @WMI_HOST_HW_MODE_MAX: Max hw_mode_id. Used to indicate invalid mode.
92d5c65159SKalle Valo  */
93d5c65159SKalle Valo enum wmi_host_hw_mode_config_type {
94d5c65159SKalle Valo 	WMI_HOST_HW_MODE_SINGLE       = 0,
95d5c65159SKalle Valo 	WMI_HOST_HW_MODE_DBS          = 1,
96d5c65159SKalle Valo 	WMI_HOST_HW_MODE_SBS_PASSIVE  = 2,
97d5c65159SKalle Valo 	WMI_HOST_HW_MODE_SBS          = 3,
98d5c65159SKalle Valo 	WMI_HOST_HW_MODE_DBS_SBS      = 4,
99d5c65159SKalle Valo 	WMI_HOST_HW_MODE_DBS_OR_SBS   = 5,
100d5c65159SKalle Valo 
101d5c65159SKalle Valo 	/* keep last */
102d5c65159SKalle Valo 	WMI_HOST_HW_MODE_MAX
103d5c65159SKalle Valo };
104d5c65159SKalle Valo 
105d5c65159SKalle Valo /* HW mode priority values used to detect the preferred HW mode
106d5c65159SKalle Valo  * on the available modes.
107d5c65159SKalle Valo  */
108d5c65159SKalle Valo enum wmi_host_hw_mode_priority {
109d5c65159SKalle Valo 	WMI_HOST_HW_MODE_DBS_SBS_PRI,
110d5c65159SKalle Valo 	WMI_HOST_HW_MODE_DBS_PRI,
111d5c65159SKalle Valo 	WMI_HOST_HW_MODE_DBS_OR_SBS_PRI,
112d5c65159SKalle Valo 	WMI_HOST_HW_MODE_SBS_PRI,
113d5c65159SKalle Valo 	WMI_HOST_HW_MODE_SBS_PASSIVE_PRI,
114d5c65159SKalle Valo 	WMI_HOST_HW_MODE_SINGLE_PRI,
115d5c65159SKalle Valo 
116d5c65159SKalle Valo 	/* keep last the lowest priority */
117d5c65159SKalle Valo 	WMI_HOST_HW_MODE_MAX_PRI
118d5c65159SKalle Valo };
119d5c65159SKalle Valo 
12013706340SWen Gong enum WMI_HOST_WLAN_BAND {
121d5c65159SKalle Valo 	WMI_HOST_WLAN_2G_CAP	= 0x1,
122d5c65159SKalle Valo 	WMI_HOST_WLAN_5G_CAP	= 0x2,
12313706340SWen Gong 	WMI_HOST_WLAN_2G_5G_CAP	= WMI_HOST_WLAN_2G_CAP | WMI_HOST_WLAN_5G_CAP,
124d5c65159SKalle Valo };
125d5c65159SKalle Valo 
12661fe43e7SMiles Hu /* Parameters used for WMI_VDEV_PARAM_AUTORATE_MISC_CFG command.
12761fe43e7SMiles Hu  * Used only for HE auto rate mode.
12861fe43e7SMiles Hu  */
12961fe43e7SMiles Hu enum {
13061fe43e7SMiles Hu 	/* HE LTF related configuration */
13161fe43e7SMiles Hu 	WMI_HE_AUTORATE_LTF_1X = BIT(0),
13261fe43e7SMiles Hu 	WMI_HE_AUTORATE_LTF_2X = BIT(1),
13361fe43e7SMiles Hu 	WMI_HE_AUTORATE_LTF_4X = BIT(2),
13461fe43e7SMiles Hu 
13561fe43e7SMiles Hu 	/* HE GI related configuration */
13661fe43e7SMiles Hu 	WMI_AUTORATE_400NS_GI = BIT(8),
13761fe43e7SMiles Hu 	WMI_AUTORATE_800NS_GI = BIT(9),
13861fe43e7SMiles Hu 	WMI_AUTORATE_1600NS_GI = BIT(10),
13961fe43e7SMiles Hu 	WMI_AUTORATE_3200NS_GI = BIT(11),
14061fe43e7SMiles Hu };
14161fe43e7SMiles Hu 
1425a81610aSAloka Dixit enum {
1435a81610aSAloka Dixit 	WMI_HOST_VDEV_FLAGS_NON_MBSSID_AP       = 0x00000001,
1445a81610aSAloka Dixit 	WMI_HOST_VDEV_FLAGS_TRANSMIT_AP         = 0x00000002,
1455a81610aSAloka Dixit 	WMI_HOST_VDEV_FLAGS_NON_TRANSMIT_AP     = 0x00000004,
1465a81610aSAloka Dixit 	WMI_HOST_VDEV_FLAGS_EMA_MODE            = 0x00000008,
1475a81610aSAloka Dixit 	WMI_HOST_VDEV_FLAGS_SCAN_MODE_VAP       = 0x00000010,
1485a81610aSAloka Dixit };
1495a81610aSAloka Dixit 
150d5c65159SKalle Valo /*
151d5c65159SKalle Valo  * wmi command groups.
152d5c65159SKalle Valo  */
153d5c65159SKalle Valo enum wmi_cmd_group {
154d5c65159SKalle Valo 	/* 0 to 2 are reserved */
155d5c65159SKalle Valo 	WMI_GRP_START = 0x3,
156d5c65159SKalle Valo 	WMI_GRP_SCAN = WMI_GRP_START,
157d5c65159SKalle Valo 	WMI_GRP_PDEV		= 0x4,
158d5c65159SKalle Valo 	WMI_GRP_VDEV           = 0x5,
159d5c65159SKalle Valo 	WMI_GRP_PEER           = 0x6,
160d5c65159SKalle Valo 	WMI_GRP_MGMT           = 0x7,
161d5c65159SKalle Valo 	WMI_GRP_BA_NEG         = 0x8,
162d5c65159SKalle Valo 	WMI_GRP_STA_PS         = 0x9,
163d5c65159SKalle Valo 	WMI_GRP_DFS            = 0xa,
164d5c65159SKalle Valo 	WMI_GRP_ROAM           = 0xb,
165d5c65159SKalle Valo 	WMI_GRP_OFL_SCAN       = 0xc,
166d5c65159SKalle Valo 	WMI_GRP_P2P            = 0xd,
167d5c65159SKalle Valo 	WMI_GRP_AP_PS          = 0xe,
168d5c65159SKalle Valo 	WMI_GRP_RATE_CTRL      = 0xf,
169d5c65159SKalle Valo 	WMI_GRP_PROFILE        = 0x10,
170d5c65159SKalle Valo 	WMI_GRP_SUSPEND        = 0x11,
171d5c65159SKalle Valo 	WMI_GRP_BCN_FILTER     = 0x12,
172d5c65159SKalle Valo 	WMI_GRP_WOW            = 0x13,
173d5c65159SKalle Valo 	WMI_GRP_RTT            = 0x14,
174d5c65159SKalle Valo 	WMI_GRP_SPECTRAL       = 0x15,
175d5c65159SKalle Valo 	WMI_GRP_STATS          = 0x16,
176d5c65159SKalle Valo 	WMI_GRP_ARP_NS_OFL     = 0x17,
177d5c65159SKalle Valo 	WMI_GRP_NLO_OFL        = 0x18,
178d5c65159SKalle Valo 	WMI_GRP_GTK_OFL        = 0x19,
179d5c65159SKalle Valo 	WMI_GRP_CSA_OFL        = 0x1a,
180d5c65159SKalle Valo 	WMI_GRP_CHATTER        = 0x1b,
181d5c65159SKalle Valo 	WMI_GRP_TID_ADDBA      = 0x1c,
182d5c65159SKalle Valo 	WMI_GRP_MISC           = 0x1d,
183d5c65159SKalle Valo 	WMI_GRP_GPIO           = 0x1e,
184d5c65159SKalle Valo 	WMI_GRP_FWTEST         = 0x1f,
185d5c65159SKalle Valo 	WMI_GRP_TDLS           = 0x20,
186d5c65159SKalle Valo 	WMI_GRP_RESMGR         = 0x21,
187d5c65159SKalle Valo 	WMI_GRP_STA_SMPS       = 0x22,
188d5c65159SKalle Valo 	WMI_GRP_WLAN_HB        = 0x23,
189d5c65159SKalle Valo 	WMI_GRP_RMC            = 0x24,
190d5c65159SKalle Valo 	WMI_GRP_MHF_OFL        = 0x25,
191d5c65159SKalle Valo 	WMI_GRP_LOCATION_SCAN  = 0x26,
192d5c65159SKalle Valo 	WMI_GRP_OEM            = 0x27,
193d5c65159SKalle Valo 	WMI_GRP_NAN            = 0x28,
194d5c65159SKalle Valo 	WMI_GRP_COEX           = 0x29,
195d5c65159SKalle Valo 	WMI_GRP_OBSS_OFL       = 0x2a,
196d5c65159SKalle Valo 	WMI_GRP_LPI            = 0x2b,
197d5c65159SKalle Valo 	WMI_GRP_EXTSCAN        = 0x2c,
198d5c65159SKalle Valo 	WMI_GRP_DHCP_OFL       = 0x2d,
199d5c65159SKalle Valo 	WMI_GRP_IPA            = 0x2e,
200d5c65159SKalle Valo 	WMI_GRP_MDNS_OFL       = 0x2f,
201d5c65159SKalle Valo 	WMI_GRP_SAP_OFL        = 0x30,
202d5c65159SKalle Valo 	WMI_GRP_OCB            = 0x31,
203d5c65159SKalle Valo 	WMI_GRP_SOC            = 0x32,
204d5c65159SKalle Valo 	WMI_GRP_PKT_FILTER     = 0x33,
205d5c65159SKalle Valo 	WMI_GRP_MAWC           = 0x34,
206d5c65159SKalle Valo 	WMI_GRP_PMF_OFFLOAD    = 0x35,
207d5c65159SKalle Valo 	WMI_GRP_BPF_OFFLOAD    = 0x36,
208d5c65159SKalle Valo 	WMI_GRP_NAN_DATA       = 0x37,
209d5c65159SKalle Valo 	WMI_GRP_PROTOTYPE      = 0x38,
210d5c65159SKalle Valo 	WMI_GRP_MONITOR        = 0x39,
211d5c65159SKalle Valo 	WMI_GRP_REGULATORY     = 0x3a,
212d5c65159SKalle Valo 	WMI_GRP_HW_DATA_FILTER = 0x3b,
2136d293d44SJohn Crispin 	WMI_GRP_WLM            = 0x3c,
2146d293d44SJohn Crispin 	WMI_GRP_11K_OFFLOAD    = 0x3d,
2156d293d44SJohn Crispin 	WMI_GRP_TWT            = 0x3e,
2163f8be640SJohn Crispin 	WMI_GRP_MOTION_DET     = 0x3f,
2173f8be640SJohn Crispin 	WMI_GRP_SPATIAL_REUSE  = 0x40,
218d5c65159SKalle Valo };
219d5c65159SKalle Valo 
220d5c65159SKalle Valo #define WMI_CMD_GRP(grp_id) (((grp_id) << 12) | 0x1)
221d5c65159SKalle Valo #define WMI_EVT_GRP_START_ID(grp_id) (((grp_id) << 12) | 0x1)
222d5c65159SKalle Valo 
223d5c65159SKalle Valo #define WMI_CMD_UNSUPPORTED 0
224d5c65159SKalle Valo 
225d5c65159SKalle Valo enum wmi_tlv_cmd_id {
226d5c65159SKalle Valo 	WMI_INIT_CMDID = 0x1,
227d5c65159SKalle Valo 	WMI_START_SCAN_CMDID = WMI_TLV_CMD(WMI_GRP_SCAN),
228d5c65159SKalle Valo 	WMI_STOP_SCAN_CMDID,
229d5c65159SKalle Valo 	WMI_SCAN_CHAN_LIST_CMDID,
230d5c65159SKalle Valo 	WMI_SCAN_SCH_PRIO_TBL_CMDID,
231d5c65159SKalle Valo 	WMI_SCAN_UPDATE_REQUEST_CMDID,
232d5c65159SKalle Valo 	WMI_SCAN_PROB_REQ_OUI_CMDID,
233d5c65159SKalle Valo 	WMI_SCAN_ADAPTIVE_DWELL_CONFIG_CMDID,
234d5c65159SKalle Valo 	WMI_PDEV_SET_REGDOMAIN_CMDID = WMI_TLV_CMD(WMI_GRP_PDEV),
235d5c65159SKalle Valo 	WMI_PDEV_SET_CHANNEL_CMDID,
236d5c65159SKalle Valo 	WMI_PDEV_SET_PARAM_CMDID,
237d5c65159SKalle Valo 	WMI_PDEV_PKTLOG_ENABLE_CMDID,
238d5c65159SKalle Valo 	WMI_PDEV_PKTLOG_DISABLE_CMDID,
239d5c65159SKalle Valo 	WMI_PDEV_SET_WMM_PARAMS_CMDID,
240d5c65159SKalle Valo 	WMI_PDEV_SET_HT_CAP_IE_CMDID,
241d5c65159SKalle Valo 	WMI_PDEV_SET_VHT_CAP_IE_CMDID,
242d5c65159SKalle Valo 	WMI_PDEV_SET_DSCP_TID_MAP_CMDID,
243d5c65159SKalle Valo 	WMI_PDEV_SET_QUIET_MODE_CMDID,
244d5c65159SKalle Valo 	WMI_PDEV_GREEN_AP_PS_ENABLE_CMDID,
245d5c65159SKalle Valo 	WMI_PDEV_GET_TPC_CONFIG_CMDID,
246d5c65159SKalle Valo 	WMI_PDEV_SET_BASE_MACADDR_CMDID,
247d5c65159SKalle Valo 	WMI_PDEV_DUMP_CMDID,
248d5c65159SKalle Valo 	WMI_PDEV_SET_LED_CONFIG_CMDID,
249d5c65159SKalle Valo 	WMI_PDEV_GET_TEMPERATURE_CMDID,
250d5c65159SKalle Valo 	WMI_PDEV_SET_LED_FLASHING_CMDID,
251d5c65159SKalle Valo 	WMI_PDEV_SMART_ANT_ENABLE_CMDID,
252d5c65159SKalle Valo 	WMI_PDEV_SMART_ANT_SET_RX_ANTENNA_CMDID,
253d5c65159SKalle Valo 	WMI_PDEV_SET_ANTENNA_SWITCH_TABLE_CMDID,
254d5c65159SKalle Valo 	WMI_PDEV_SET_CTL_TABLE_CMDID,
255d5c65159SKalle Valo 	WMI_PDEV_SET_MIMOGAIN_TABLE_CMDID,
256d5c65159SKalle Valo 	WMI_PDEV_FIPS_CMDID,
257d5c65159SKalle Valo 	WMI_PDEV_GET_ANI_CCK_CONFIG_CMDID,
258d5c65159SKalle Valo 	WMI_PDEV_GET_ANI_OFDM_CONFIG_CMDID,
259d5c65159SKalle Valo 	WMI_PDEV_GET_NFCAL_POWER_CMDID,
260d5c65159SKalle Valo 	WMI_PDEV_GET_TPC_CMDID,
261d5c65159SKalle Valo 	WMI_MIB_STATS_ENABLE_CMDID,
262d5c65159SKalle Valo 	WMI_PDEV_SET_PCL_CMDID,
263d5c65159SKalle Valo 	WMI_PDEV_SET_HW_MODE_CMDID,
264d5c65159SKalle Valo 	WMI_PDEV_SET_MAC_CONFIG_CMDID,
265d5c65159SKalle Valo 	WMI_PDEV_SET_ANTENNA_MODE_CMDID,
266d5c65159SKalle Valo 	WMI_SET_PERIODIC_CHANNEL_STATS_CONFIG_CMDID,
267d5c65159SKalle Valo 	WMI_PDEV_WAL_POWER_DEBUG_CMDID,
268d5c65159SKalle Valo 	WMI_PDEV_SET_REORDER_TIMEOUT_VAL_CMDID,
269d5c65159SKalle Valo 	WMI_PDEV_SET_WAKEUP_CONFIG_CMDID,
270d5c65159SKalle Valo 	WMI_PDEV_GET_ANTDIV_STATUS_CMDID,
271d5c65159SKalle Valo 	WMI_PDEV_GET_CHIP_POWER_STATS_CMDID,
272d5c65159SKalle Valo 	WMI_PDEV_SET_STATS_THRESHOLD_CMDID,
273d5c65159SKalle Valo 	WMI_PDEV_MULTIPLE_VDEV_RESTART_REQUEST_CMDID,
274d5c65159SKalle Valo 	WMI_PDEV_UPDATE_PKT_ROUTING_CMDID,
275d5c65159SKalle Valo 	WMI_PDEV_CHECK_CAL_VERSION_CMDID,
276d5c65159SKalle Valo 	WMI_PDEV_SET_DIVERSITY_GAIN_CMDID,
277d5c65159SKalle Valo 	WMI_PDEV_DIV_GET_RSSI_ANTID_CMDID,
278d5c65159SKalle Valo 	WMI_PDEV_BSS_CHAN_INFO_REQUEST_CMDID,
279d5c65159SKalle Valo 	WMI_PDEV_UPDATE_PMK_CACHE_CMDID,
280d5c65159SKalle Valo 	WMI_PDEV_UPDATE_FILS_HLP_PKT_CMDID,
281d5c65159SKalle Valo 	WMI_PDEV_UPDATE_CTLTABLE_REQUEST_CMDID,
282d5c65159SKalle Valo 	WMI_PDEV_CONFIG_VENDOR_OUI_ACTION_CMDID,
283d5c65159SKalle Valo 	WMI_PDEV_SET_AC_TX_QUEUE_OPTIMIZED_CMDID,
284d5c65159SKalle Valo 	WMI_PDEV_SET_RX_FILTER_PROMISCUOUS_CMDID,
285d5c65159SKalle Valo 	WMI_PDEV_DMA_RING_CFG_REQ_CMDID,
286d5c65159SKalle Valo 	WMI_PDEV_HE_TB_ACTION_FRM_CMDID,
287d5c65159SKalle Valo 	WMI_PDEV_PKTLOG_FILTER_CMDID,
288b56b08aeSRajkumar Manoharan 	WMI_PDEV_SET_RAP_CONFIG_CMDID,
289b56b08aeSRajkumar Manoharan 	WMI_PDEV_DSM_FILTER_CMDID,
290b56b08aeSRajkumar Manoharan 	WMI_PDEV_FRAME_INJECT_CMDID,
291b56b08aeSRajkumar Manoharan 	WMI_PDEV_TBTT_OFFSET_SYNC_CMDID,
292b56b08aeSRajkumar Manoharan 	WMI_PDEV_SET_SRG_BSS_COLOR_BITMAP_CMDID,
293b56b08aeSRajkumar Manoharan 	WMI_PDEV_SET_SRG_PARTIAL_BSSID_BITMAP_CMDID,
294b56b08aeSRajkumar Manoharan 	WMI_PDEV_SET_SRG_OBSS_COLOR_ENABLE_BITMAP_CMDID,
295b56b08aeSRajkumar Manoharan 	WMI_PDEV_SET_SRG_OBSS_BSSID_ENABLE_BITMAP_CMDID,
296b56b08aeSRajkumar Manoharan 	WMI_PDEV_SET_NON_SRG_OBSS_COLOR_ENABLE_BITMAP_CMDID,
297b56b08aeSRajkumar Manoharan 	WMI_PDEV_SET_NON_SRG_OBSS_BSSID_ENABLE_BITMAP_CMDID,
298652f69edSBaochen Qiang 	WMI_PDEV_GET_TPC_STATS_CMDID,
299652f69edSBaochen Qiang 	WMI_PDEV_ENABLE_DURATION_BASED_TX_MODE_SELECTION_CMDID,
300652f69edSBaochen Qiang 	WMI_PDEV_GET_DPD_STATUS_CMDID,
301652f69edSBaochen Qiang 	WMI_PDEV_SET_BIOS_SAR_TABLE_CMDID,
302652f69edSBaochen Qiang 	WMI_PDEV_SET_BIOS_GEO_TABLE_CMDID,
303d5c65159SKalle Valo 	WMI_VDEV_CREATE_CMDID = WMI_TLV_CMD(WMI_GRP_VDEV),
304d5c65159SKalle Valo 	WMI_VDEV_DELETE_CMDID,
305d5c65159SKalle Valo 	WMI_VDEV_START_REQUEST_CMDID,
306d5c65159SKalle Valo 	WMI_VDEV_RESTART_REQUEST_CMDID,
307d5c65159SKalle Valo 	WMI_VDEV_UP_CMDID,
308d5c65159SKalle Valo 	WMI_VDEV_STOP_CMDID,
309d5c65159SKalle Valo 	WMI_VDEV_DOWN_CMDID,
310d5c65159SKalle Valo 	WMI_VDEV_SET_PARAM_CMDID,
311d5c65159SKalle Valo 	WMI_VDEV_INSTALL_KEY_CMDID,
312d5c65159SKalle Valo 	WMI_VDEV_WNM_SLEEPMODE_CMDID,
313d5c65159SKalle Valo 	WMI_VDEV_WMM_ADDTS_CMDID,
314d5c65159SKalle Valo 	WMI_VDEV_WMM_DELTS_CMDID,
315d5c65159SKalle Valo 	WMI_VDEV_SET_WMM_PARAMS_CMDID,
316d5c65159SKalle Valo 	WMI_VDEV_SET_GTX_PARAMS_CMDID,
317d5c65159SKalle Valo 	WMI_VDEV_IPSEC_NATKEEPALIVE_FILTER_CMDID,
318d5c65159SKalle Valo 	WMI_VDEV_PLMREQ_START_CMDID,
319d5c65159SKalle Valo 	WMI_VDEV_PLMREQ_STOP_CMDID,
320d5c65159SKalle Valo 	WMI_VDEV_TSF_TSTAMP_ACTION_CMDID,
321d5c65159SKalle Valo 	WMI_VDEV_SET_IE_CMDID,
322d5c65159SKalle Valo 	WMI_VDEV_RATEMASK_CMDID,
323d5c65159SKalle Valo 	WMI_VDEV_ATF_REQUEST_CMDID,
324d5c65159SKalle Valo 	WMI_VDEV_SET_DSCP_TID_MAP_CMDID,
325d5c65159SKalle Valo 	WMI_VDEV_FILTER_NEIGHBOR_RX_PACKETS_CMDID,
326d5c65159SKalle Valo 	WMI_VDEV_SET_QUIET_MODE_CMDID,
327d5c65159SKalle Valo 	WMI_VDEV_SET_CUSTOM_AGGR_SIZE_CMDID,
328d5c65159SKalle Valo 	WMI_VDEV_ENCRYPT_DECRYPT_DATA_REQ_CMDID,
329d5c65159SKalle Valo 	WMI_VDEV_ADD_MAC_ADDR_TO_RX_FILTER_CMDID,
330d5c65159SKalle Valo 	WMI_PEER_CREATE_CMDID = WMI_TLV_CMD(WMI_GRP_PEER),
331d5c65159SKalle Valo 	WMI_PEER_DELETE_CMDID,
332d5c65159SKalle Valo 	WMI_PEER_FLUSH_TIDS_CMDID,
333d5c65159SKalle Valo 	WMI_PEER_SET_PARAM_CMDID,
334d5c65159SKalle Valo 	WMI_PEER_ASSOC_CMDID,
335d5c65159SKalle Valo 	WMI_PEER_ADD_WDS_ENTRY_CMDID,
336d5c65159SKalle Valo 	WMI_PEER_REMOVE_WDS_ENTRY_CMDID,
337d5c65159SKalle Valo 	WMI_PEER_MCAST_GROUP_CMDID,
338d5c65159SKalle Valo 	WMI_PEER_INFO_REQ_CMDID,
339d5c65159SKalle Valo 	WMI_PEER_GET_ESTIMATED_LINKSPEED_CMDID,
340d5c65159SKalle Valo 	WMI_PEER_SET_RATE_REPORT_CONDITION_CMDID,
341d5c65159SKalle Valo 	WMI_PEER_UPDATE_WDS_ENTRY_CMDID,
342d5c65159SKalle Valo 	WMI_PEER_ADD_PROXY_STA_ENTRY_CMDID,
343d5c65159SKalle Valo 	WMI_PEER_SMART_ANT_SET_TX_ANTENNA_CMDID,
344d5c65159SKalle Valo 	WMI_PEER_SMART_ANT_SET_TRAIN_INFO_CMDID,
345d5c65159SKalle Valo 	WMI_PEER_SMART_ANT_SET_NODE_CONFIG_OPS_CMDID,
346d5c65159SKalle Valo 	WMI_PEER_ATF_REQUEST_CMDID,
347d5c65159SKalle Valo 	WMI_PEER_BWF_REQUEST_CMDID,
348d5c65159SKalle Valo 	WMI_PEER_REORDER_QUEUE_SETUP_CMDID,
349d5c65159SKalle Valo 	WMI_PEER_REORDER_QUEUE_REMOVE_CMDID,
350d5c65159SKalle Valo 	WMI_PEER_SET_RX_BLOCKSIZE_CMDID,
351d5c65159SKalle Valo 	WMI_PEER_ANTDIV_INFO_REQ_CMDID,
352d5c65159SKalle Valo 	WMI_BCN_TX_CMDID = WMI_TLV_CMD(WMI_GRP_MGMT),
353d5c65159SKalle Valo 	WMI_PDEV_SEND_BCN_CMDID,
354d5c65159SKalle Valo 	WMI_BCN_TMPL_CMDID,
355d5c65159SKalle Valo 	WMI_BCN_FILTER_RX_CMDID,
356d5c65159SKalle Valo 	WMI_PRB_REQ_FILTER_RX_CMDID,
357d5c65159SKalle Valo 	WMI_MGMT_TX_CMDID,
358d5c65159SKalle Valo 	WMI_PRB_TMPL_CMDID,
359d5c65159SKalle Valo 	WMI_MGMT_TX_SEND_CMDID,
360d5c65159SKalle Valo 	WMI_OFFCHAN_DATA_TX_SEND_CMDID,
361d5c65159SKalle Valo 	WMI_PDEV_SEND_FD_CMDID,
362d5c65159SKalle Valo 	WMI_BCN_OFFLOAD_CTRL_CMDID,
363d5c65159SKalle Valo 	WMI_BSS_COLOR_CHANGE_ENABLE_CMDID,
364d5c65159SKalle Valo 	WMI_VDEV_BCN_OFFLOAD_QUIET_CONFIG_CMDID,
365047679e3SAloka Dixit 	WMI_FILS_DISCOVERY_TMPL_CMDID,
366d5c65159SKalle Valo 	WMI_ADDBA_CLEAR_RESP_CMDID = WMI_TLV_CMD(WMI_GRP_BA_NEG),
367d5c65159SKalle Valo 	WMI_ADDBA_SEND_CMDID,
368d5c65159SKalle Valo 	WMI_ADDBA_STATUS_CMDID,
369d5c65159SKalle Valo 	WMI_DELBA_SEND_CMDID,
370d5c65159SKalle Valo 	WMI_ADDBA_SET_RESP_CMDID,
371d5c65159SKalle Valo 	WMI_SEND_SINGLEAMSDU_CMDID,
372d5c65159SKalle Valo 	WMI_STA_POWERSAVE_MODE_CMDID = WMI_TLV_CMD(WMI_GRP_STA_PS),
373d5c65159SKalle Valo 	WMI_STA_POWERSAVE_PARAM_CMDID,
374d5c65159SKalle Valo 	WMI_STA_MIMO_PS_MODE_CMDID,
375d5c65159SKalle Valo 	WMI_PDEV_DFS_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_DFS),
376d5c65159SKalle Valo 	WMI_PDEV_DFS_DISABLE_CMDID,
377d5c65159SKalle Valo 	WMI_DFS_PHYERR_FILTER_ENA_CMDID,
378d5c65159SKalle Valo 	WMI_DFS_PHYERR_FILTER_DIS_CMDID,
379d5c65159SKalle Valo 	WMI_PDEV_DFS_PHYERR_OFFLOAD_ENABLE_CMDID,
380d5c65159SKalle Valo 	WMI_PDEV_DFS_PHYERR_OFFLOAD_DISABLE_CMDID,
381d5c65159SKalle Valo 	WMI_VDEV_ADFS_CH_CFG_CMDID,
382d5c65159SKalle Valo 	WMI_VDEV_ADFS_OCAC_ABORT_CMDID,
383d5c65159SKalle Valo 	WMI_ROAM_SCAN_MODE = WMI_TLV_CMD(WMI_GRP_ROAM),
384d5c65159SKalle Valo 	WMI_ROAM_SCAN_RSSI_THRESHOLD,
385d5c65159SKalle Valo 	WMI_ROAM_SCAN_PERIOD,
386d5c65159SKalle Valo 	WMI_ROAM_SCAN_RSSI_CHANGE_THRESHOLD,
387d5c65159SKalle Valo 	WMI_ROAM_AP_PROFILE,
388d5c65159SKalle Valo 	WMI_ROAM_CHAN_LIST,
389d5c65159SKalle Valo 	WMI_ROAM_SCAN_CMD,
390d5c65159SKalle Valo 	WMI_ROAM_SYNCH_COMPLETE,
391d5c65159SKalle Valo 	WMI_ROAM_SET_RIC_REQUEST_CMDID,
392d5c65159SKalle Valo 	WMI_ROAM_INVOKE_CMDID,
393d5c65159SKalle Valo 	WMI_ROAM_FILTER_CMDID,
394d5c65159SKalle Valo 	WMI_ROAM_SUBNET_CHANGE_CONFIG_CMDID,
395d5c65159SKalle Valo 	WMI_ROAM_CONFIGURE_MAWC_CMDID,
396d5c65159SKalle Valo 	WMI_ROAM_SET_MBO_PARAM_CMDID,
397d5c65159SKalle Valo 	WMI_ROAM_PER_CONFIG_CMDID,
398047679e3SAloka Dixit 	WMI_ROAM_BTM_CONFIG_CMDID,
399047679e3SAloka Dixit 	WMI_ENABLE_FILS_CMDID,
400d5c65159SKalle Valo 	WMI_OFL_SCAN_ADD_AP_PROFILE = WMI_TLV_CMD(WMI_GRP_OFL_SCAN),
401d5c65159SKalle Valo 	WMI_OFL_SCAN_REMOVE_AP_PROFILE,
402d5c65159SKalle Valo 	WMI_OFL_SCAN_PERIOD,
403d5c65159SKalle Valo 	WMI_P2P_DEV_SET_DEVICE_INFO = WMI_TLV_CMD(WMI_GRP_P2P),
404d5c65159SKalle Valo 	WMI_P2P_DEV_SET_DISCOVERABILITY,
405d5c65159SKalle Valo 	WMI_P2P_GO_SET_BEACON_IE,
406d5c65159SKalle Valo 	WMI_P2P_GO_SET_PROBE_RESP_IE,
407d5c65159SKalle Valo 	WMI_P2P_SET_VENDOR_IE_DATA_CMDID,
408d5c65159SKalle Valo 	WMI_P2P_DISC_OFFLOAD_CONFIG_CMDID,
409d5c65159SKalle Valo 	WMI_P2P_DISC_OFFLOAD_APPIE_CMDID,
410d5c65159SKalle Valo 	WMI_P2P_DISC_OFFLOAD_PATTERN_CMDID,
411d5c65159SKalle Valo 	WMI_P2P_SET_OPPPS_PARAM_CMDID,
412d5c65159SKalle Valo 	WMI_P2P_LISTEN_OFFLOAD_START_CMDID,
413d5c65159SKalle Valo 	WMI_P2P_LISTEN_OFFLOAD_STOP_CMDID,
414d5c65159SKalle Valo 	WMI_AP_PS_PEER_PARAM_CMDID = WMI_TLV_CMD(WMI_GRP_AP_PS),
415d5c65159SKalle Valo 	WMI_AP_PS_PEER_UAPSD_COEX_CMDID,
416d5c65159SKalle Valo 	WMI_AP_PS_EGAP_PARAM_CMDID,
417d5c65159SKalle Valo 	WMI_PEER_RATE_RETRY_SCHED_CMDID = WMI_TLV_CMD(WMI_GRP_RATE_CTRL),
418d5c65159SKalle Valo 	WMI_WLAN_PROFILE_TRIGGER_CMDID = WMI_TLV_CMD(WMI_GRP_PROFILE),
419d5c65159SKalle Valo 	WMI_WLAN_PROFILE_SET_HIST_INTVL_CMDID,
420d5c65159SKalle Valo 	WMI_WLAN_PROFILE_GET_PROFILE_DATA_CMDID,
421d5c65159SKalle Valo 	WMI_WLAN_PROFILE_ENABLE_PROFILE_ID_CMDID,
422d5c65159SKalle Valo 	WMI_WLAN_PROFILE_LIST_PROFILE_ID_CMDID,
423d5c65159SKalle Valo 	WMI_PDEV_SUSPEND_CMDID = WMI_TLV_CMD(WMI_GRP_SUSPEND),
424d5c65159SKalle Valo 	WMI_PDEV_RESUME_CMDID,
425d5c65159SKalle Valo 	WMI_ADD_BCN_FILTER_CMDID = WMI_TLV_CMD(WMI_GRP_BCN_FILTER),
426d5c65159SKalle Valo 	WMI_RMV_BCN_FILTER_CMDID,
427d5c65159SKalle Valo 	WMI_WOW_ADD_WAKE_PATTERN_CMDID = WMI_TLV_CMD(WMI_GRP_WOW),
428d5c65159SKalle Valo 	WMI_WOW_DEL_WAKE_PATTERN_CMDID,
429d5c65159SKalle Valo 	WMI_WOW_ENABLE_DISABLE_WAKE_EVENT_CMDID,
430d5c65159SKalle Valo 	WMI_WOW_ENABLE_CMDID,
431d5c65159SKalle Valo 	WMI_WOW_HOSTWAKEUP_FROM_SLEEP_CMDID,
432d5c65159SKalle Valo 	WMI_WOW_IOAC_ADD_KEEPALIVE_CMDID,
433d5c65159SKalle Valo 	WMI_WOW_IOAC_DEL_KEEPALIVE_CMDID,
434d5c65159SKalle Valo 	WMI_WOW_IOAC_ADD_WAKE_PATTERN_CMDID,
435d5c65159SKalle Valo 	WMI_WOW_IOAC_DEL_WAKE_PATTERN_CMDID,
436d5c65159SKalle Valo 	WMI_D0_WOW_ENABLE_DISABLE_CMDID,
437d5c65159SKalle Valo 	WMI_EXTWOW_ENABLE_CMDID,
438d5c65159SKalle Valo 	WMI_EXTWOW_SET_APP_TYPE1_PARAMS_CMDID,
439d5c65159SKalle Valo 	WMI_EXTWOW_SET_APP_TYPE2_PARAMS_CMDID,
440d5c65159SKalle Valo 	WMI_WOW_ENABLE_ICMPV6_NA_FLT_CMDID,
441d5c65159SKalle Valo 	WMI_WOW_UDP_SVC_OFLD_CMDID,
442d5c65159SKalle Valo 	WMI_WOW_HOSTWAKEUP_GPIO_PIN_PATTERN_CONFIG_CMDID,
443d5c65159SKalle Valo 	WMI_WOW_SET_ACTION_WAKE_UP_CMDID,
444d5c65159SKalle Valo 	WMI_RTT_MEASREQ_CMDID = WMI_TLV_CMD(WMI_GRP_RTT),
445d5c65159SKalle Valo 	WMI_RTT_TSF_CMDID,
446d5c65159SKalle Valo 	WMI_VDEV_SPECTRAL_SCAN_CONFIGURE_CMDID = WMI_TLV_CMD(WMI_GRP_SPECTRAL),
447d5c65159SKalle Valo 	WMI_VDEV_SPECTRAL_SCAN_ENABLE_CMDID,
448d5c65159SKalle Valo 	WMI_REQUEST_STATS_CMDID = WMI_TLV_CMD(WMI_GRP_STATS),
449d5c65159SKalle Valo 	WMI_MCC_SCHED_TRAFFIC_STATS_CMDID,
450d5c65159SKalle Valo 	WMI_REQUEST_STATS_EXT_CMDID,
451d5c65159SKalle Valo 	WMI_REQUEST_LINK_STATS_CMDID,
452d5c65159SKalle Valo 	WMI_START_LINK_STATS_CMDID,
453d5c65159SKalle Valo 	WMI_CLEAR_LINK_STATS_CMDID,
454d5c65159SKalle Valo 	WMI_GET_FW_MEM_DUMP_CMDID,
455d5c65159SKalle Valo 	WMI_DEBUG_MESG_FLUSH_CMDID,
456d5c65159SKalle Valo 	WMI_DIAG_EVENT_LOG_CONFIG_CMDID,
457d5c65159SKalle Valo 	WMI_REQUEST_WLAN_STATS_CMDID,
458d5c65159SKalle Valo 	WMI_REQUEST_RCPI_CMDID,
459d5c65159SKalle Valo 	WMI_REQUEST_PEER_STATS_INFO_CMDID,
460d5c65159SKalle Valo 	WMI_REQUEST_RADIO_CHAN_STATS_CMDID,
461d5c65159SKalle Valo 	WMI_SET_ARP_NS_OFFLOAD_CMDID = WMI_TLV_CMD(WMI_GRP_ARP_NS_OFL),
462d5c65159SKalle Valo 	WMI_ADD_PROACTIVE_ARP_RSP_PATTERN_CMDID,
463d5c65159SKalle Valo 	WMI_DEL_PROACTIVE_ARP_RSP_PATTERN_CMDID,
464d5c65159SKalle Valo 	WMI_NETWORK_LIST_OFFLOAD_CONFIG_CMDID = WMI_TLV_CMD(WMI_GRP_NLO_OFL),
465d5c65159SKalle Valo 	WMI_APFIND_CMDID,
466d5c65159SKalle Valo 	WMI_PASSPOINT_LIST_CONFIG_CMDID,
467d5c65159SKalle Valo 	WMI_NLO_CONFIGURE_MAWC_CMDID,
468d5c65159SKalle Valo 	WMI_GTK_OFFLOAD_CMDID = WMI_TLV_CMD(WMI_GRP_GTK_OFL),
469d5c65159SKalle Valo 	WMI_CSA_OFFLOAD_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_CSA_OFL),
470d5c65159SKalle Valo 	WMI_CSA_OFFLOAD_CHANSWITCH_CMDID,
471d5c65159SKalle Valo 	WMI_CHATTER_SET_MODE_CMDID = WMI_TLV_CMD(WMI_GRP_CHATTER),
472d5c65159SKalle Valo 	WMI_CHATTER_ADD_COALESCING_FILTER_CMDID,
473d5c65159SKalle Valo 	WMI_CHATTER_DELETE_COALESCING_FILTER_CMDID,
474d5c65159SKalle Valo 	WMI_CHATTER_COALESCING_QUERY_CMDID,
475d5c65159SKalle Valo 	WMI_PEER_TID_ADDBA_CMDID = WMI_TLV_CMD(WMI_GRP_TID_ADDBA),
476d5c65159SKalle Valo 	WMI_PEER_TID_DELBA_CMDID,
477d5c65159SKalle Valo 	WMI_STA_DTIM_PS_METHOD_CMDID,
478d5c65159SKalle Valo 	WMI_STA_UAPSD_AUTO_TRIG_CMDID,
479d5c65159SKalle Valo 	WMI_STA_KEEPALIVE_CMDID,
480d5c65159SKalle Valo 	WMI_BA_REQ_SSN_CMDID,
481d5c65159SKalle Valo 	WMI_ECHO_CMDID = WMI_TLV_CMD(WMI_GRP_MISC),
482d5c65159SKalle Valo 	WMI_PDEV_UTF_CMDID,
483d5c65159SKalle Valo 	WMI_DBGLOG_CFG_CMDID,
484d5c65159SKalle Valo 	WMI_PDEV_QVIT_CMDID,
485d5c65159SKalle Valo 	WMI_PDEV_FTM_INTG_CMDID,
486d5c65159SKalle Valo 	WMI_VDEV_SET_KEEPALIVE_CMDID,
487d5c65159SKalle Valo 	WMI_VDEV_GET_KEEPALIVE_CMDID,
488d5c65159SKalle Valo 	WMI_FORCE_FW_HANG_CMDID,
489d5c65159SKalle Valo 	WMI_SET_MCASTBCAST_FILTER_CMDID,
490d5c65159SKalle Valo 	WMI_THERMAL_MGMT_CMDID,
491d5c65159SKalle Valo 	WMI_HOST_AUTO_SHUTDOWN_CFG_CMDID,
492d5c65159SKalle Valo 	WMI_TPC_CHAINMASK_CONFIG_CMDID,
493d5c65159SKalle Valo 	WMI_SET_ANTENNA_DIVERSITY_CMDID,
494d5c65159SKalle Valo 	WMI_OCB_SET_SCHED_CMDID,
495d5c65159SKalle Valo 	WMI_RSSI_BREACH_MONITOR_CONFIG_CMDID,
496d5c65159SKalle Valo 	WMI_LRO_CONFIG_CMDID,
497d5c65159SKalle Valo 	WMI_TRANSFER_DATA_TO_FLASH_CMDID,
498d5c65159SKalle Valo 	WMI_CONFIG_ENHANCED_MCAST_FILTER_CMDID,
499d5c65159SKalle Valo 	WMI_VDEV_WISA_CMDID,
500d5c65159SKalle Valo 	WMI_DBGLOG_TIME_STAMP_SYNC_CMDID,
501d5c65159SKalle Valo 	WMI_SET_MULTIPLE_MCAST_FILTER_CMDID,
502d5c65159SKalle Valo 	WMI_READ_DATA_FROM_FLASH_CMDID,
5032a63bbcaSPradeep Kumar Chitrapu 	WMI_THERM_THROT_SET_CONF_CMDID,
5042a63bbcaSPradeep Kumar Chitrapu 	WMI_RUNTIME_DPD_RECAL_CMDID,
5052a63bbcaSPradeep Kumar Chitrapu 	WMI_GET_TPC_POWER_CMDID,
5062a63bbcaSPradeep Kumar Chitrapu 	WMI_IDLE_TRIGGER_MONITOR_CMDID,
507d5c65159SKalle Valo 	WMI_GPIO_CONFIG_CMDID = WMI_TLV_CMD(WMI_GRP_GPIO),
508d5c65159SKalle Valo 	WMI_GPIO_OUTPUT_CMDID,
509d5c65159SKalle Valo 	WMI_TXBF_CMDID,
510d5c65159SKalle Valo 	WMI_FWTEST_VDEV_MCC_SET_TBTT_MODE_CMDID = WMI_TLV_CMD(WMI_GRP_FWTEST),
511d5c65159SKalle Valo 	WMI_FWTEST_P2P_SET_NOA_PARAM_CMDID,
512d5c65159SKalle Valo 	WMI_UNIT_TEST_CMDID,
513d5c65159SKalle Valo 	WMI_FWTEST_CMDID,
514d5c65159SKalle Valo 	WMI_QBOOST_CFG_CMDID,
515d5c65159SKalle Valo 	WMI_TDLS_SET_STATE_CMDID = WMI_TLV_CMD(WMI_GRP_TDLS),
516d5c65159SKalle Valo 	WMI_TDLS_PEER_UPDATE_CMDID,
517d5c65159SKalle Valo 	WMI_TDLS_SET_OFFCHAN_MODE_CMDID,
518d5c65159SKalle Valo 	WMI_RESMGR_ADAPTIVE_OCS_EN_DIS_CMDID = WMI_TLV_CMD(WMI_GRP_RESMGR),
519d5c65159SKalle Valo 	WMI_RESMGR_SET_CHAN_TIME_QUOTA_CMDID,
520d5c65159SKalle Valo 	WMI_RESMGR_SET_CHAN_LATENCY_CMDID,
521d5c65159SKalle Valo 	WMI_STA_SMPS_FORCE_MODE_CMDID = WMI_TLV_CMD(WMI_GRP_STA_SMPS),
522d5c65159SKalle Valo 	WMI_STA_SMPS_PARAM_CMDID,
523d5c65159SKalle Valo 	WMI_HB_SET_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_WLAN_HB),
524d5c65159SKalle Valo 	WMI_HB_SET_TCP_PARAMS_CMDID,
525d5c65159SKalle Valo 	WMI_HB_SET_TCP_PKT_FILTER_CMDID,
526d5c65159SKalle Valo 	WMI_HB_SET_UDP_PARAMS_CMDID,
527d5c65159SKalle Valo 	WMI_HB_SET_UDP_PKT_FILTER_CMDID,
528d5c65159SKalle Valo 	WMI_RMC_SET_MODE_CMDID = WMI_TLV_CMD(WMI_GRP_RMC),
529d5c65159SKalle Valo 	WMI_RMC_SET_ACTION_PERIOD_CMDID,
530d5c65159SKalle Valo 	WMI_RMC_CONFIG_CMDID,
531d5c65159SKalle Valo 	WMI_RMC_SET_MANUAL_LEADER_CMDID,
532d5c65159SKalle Valo 	WMI_MHF_OFFLOAD_SET_MODE_CMDID = WMI_TLV_CMD(WMI_GRP_MHF_OFL),
533d5c65159SKalle Valo 	WMI_MHF_OFFLOAD_PLUMB_ROUTING_TBL_CMDID,
534d5c65159SKalle Valo 	WMI_BATCH_SCAN_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_LOCATION_SCAN),
535d5c65159SKalle Valo 	WMI_BATCH_SCAN_DISABLE_CMDID,
536d5c65159SKalle Valo 	WMI_BATCH_SCAN_TRIGGER_RESULT_CMDID,
537d5c65159SKalle Valo 	WMI_OEM_REQ_CMDID = WMI_TLV_CMD(WMI_GRP_OEM),
538d5c65159SKalle Valo 	WMI_OEM_REQUEST_CMDID,
539d5c65159SKalle Valo 	WMI_LPI_OEM_REQ_CMDID,
540d5c65159SKalle Valo 	WMI_NAN_CMDID = WMI_TLV_CMD(WMI_GRP_NAN),
541d5c65159SKalle Valo 	WMI_MODEM_POWER_STATE_CMDID = WMI_TLV_CMD(WMI_GRP_COEX),
542d5c65159SKalle Valo 	WMI_CHAN_AVOID_UPDATE_CMDID,
543d5c65159SKalle Valo 	WMI_COEX_CONFIG_CMDID,
544d5c65159SKalle Valo 	WMI_CHAN_AVOID_RPT_ALLOW_CMDID,
545d5c65159SKalle Valo 	WMI_COEX_GET_ANTENNA_ISOLATION_CMDID,
546d5c65159SKalle Valo 	WMI_SAR_LIMITS_CMDID,
547d5c65159SKalle Valo 	WMI_OBSS_SCAN_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_OBSS_OFL),
548d5c65159SKalle Valo 	WMI_OBSS_SCAN_DISABLE_CMDID,
5495a032c8dSJohn Crispin 	WMI_OBSS_COLOR_COLLISION_DET_CONFIG_CMDID,
550d5c65159SKalle Valo 	WMI_LPI_MGMT_SNOOPING_CONFIG_CMDID = WMI_TLV_CMD(WMI_GRP_LPI),
551d5c65159SKalle Valo 	WMI_LPI_START_SCAN_CMDID,
552d5c65159SKalle Valo 	WMI_LPI_STOP_SCAN_CMDID,
553d5c65159SKalle Valo 	WMI_EXTSCAN_START_CMDID = WMI_TLV_CMD(WMI_GRP_EXTSCAN),
554d5c65159SKalle Valo 	WMI_EXTSCAN_STOP_CMDID,
555d5c65159SKalle Valo 	WMI_EXTSCAN_CONFIGURE_WLAN_CHANGE_MONITOR_CMDID,
556d5c65159SKalle Valo 	WMI_EXTSCAN_CONFIGURE_HOTLIST_MONITOR_CMDID,
557d5c65159SKalle Valo 	WMI_EXTSCAN_GET_CACHED_RESULTS_CMDID,
558d5c65159SKalle Valo 	WMI_EXTSCAN_GET_WLAN_CHANGE_RESULTS_CMDID,
559d5c65159SKalle Valo 	WMI_EXTSCAN_SET_CAPABILITIES_CMDID,
560d5c65159SKalle Valo 	WMI_EXTSCAN_GET_CAPABILITIES_CMDID,
561d5c65159SKalle Valo 	WMI_EXTSCAN_CONFIGURE_HOTLIST_SSID_MONITOR_CMDID,
562d5c65159SKalle Valo 	WMI_EXTSCAN_CONFIGURE_MAWC_CMDID,
563d5c65159SKalle Valo 	WMI_SET_DHCP_SERVER_OFFLOAD_CMDID = WMI_TLV_CMD(WMI_GRP_DHCP_OFL),
564d5c65159SKalle Valo 	WMI_IPA_OFFLOAD_ENABLE_DISABLE_CMDID = WMI_TLV_CMD(WMI_GRP_IPA),
565d5c65159SKalle Valo 	WMI_MDNS_OFFLOAD_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_MDNS_OFL),
566d5c65159SKalle Valo 	WMI_MDNS_SET_FQDN_CMDID,
567d5c65159SKalle Valo 	WMI_MDNS_SET_RESPONSE_CMDID,
568d5c65159SKalle Valo 	WMI_MDNS_GET_STATS_CMDID,
569d5c65159SKalle Valo 	WMI_SAP_OFL_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_SAP_OFL),
570d5c65159SKalle Valo 	WMI_SAP_SET_BLACKLIST_PARAM_CMDID,
571d5c65159SKalle Valo 	WMI_OCB_SET_CONFIG_CMDID = WMI_TLV_CMD(WMI_GRP_OCB),
572d5c65159SKalle Valo 	WMI_OCB_SET_UTC_TIME_CMDID,
573d5c65159SKalle Valo 	WMI_OCB_START_TIMING_ADVERT_CMDID,
574d5c65159SKalle Valo 	WMI_OCB_STOP_TIMING_ADVERT_CMDID,
575d5c65159SKalle Valo 	WMI_OCB_GET_TSF_TIMER_CMDID,
576d5c65159SKalle Valo 	WMI_DCC_GET_STATS_CMDID,
577d5c65159SKalle Valo 	WMI_DCC_CLEAR_STATS_CMDID,
578d5c65159SKalle Valo 	WMI_DCC_UPDATE_NDL_CMDID,
579d5c65159SKalle Valo 	WMI_SOC_SET_PCL_CMDID = WMI_TLV_CMD(WMI_GRP_SOC),
580d5c65159SKalle Valo 	WMI_SOC_SET_HW_MODE_CMDID,
581d5c65159SKalle Valo 	WMI_SOC_SET_DUAL_MAC_CONFIG_CMDID,
582d5c65159SKalle Valo 	WMI_SOC_SET_ANTENNA_MODE_CMDID,
583d5c65159SKalle Valo 	WMI_PACKET_FILTER_CONFIG_CMDID = WMI_TLV_CMD(WMI_GRP_PKT_FILTER),
584d5c65159SKalle Valo 	WMI_PACKET_FILTER_ENABLE_CMDID,
585d5c65159SKalle Valo 	WMI_MAWC_SENSOR_REPORT_IND_CMDID = WMI_TLV_CMD(WMI_GRP_MAWC),
586d5c65159SKalle Valo 	WMI_PMF_OFFLOAD_SET_SA_QUERY_CMDID = WMI_TLV_CMD(WMI_GRP_PMF_OFFLOAD),
587d5c65159SKalle Valo 	WMI_BPF_GET_CAPABILITY_CMDID = WMI_TLV_CMD(WMI_GRP_BPF_OFFLOAD),
588d5c65159SKalle Valo 	WMI_BPF_GET_VDEV_STATS_CMDID,
589d5c65159SKalle Valo 	WMI_BPF_SET_VDEV_INSTRUCTIONS_CMDID,
590d5c65159SKalle Valo 	WMI_BPF_DEL_VDEV_INSTRUCTIONS_CMDID,
591d5c65159SKalle Valo 	WMI_BPF_SET_VDEV_ACTIVE_MODE_CMDID,
592d5c65159SKalle Valo 	WMI_MNT_FILTER_CMDID = WMI_TLV_CMD(WMI_GRP_MONITOR),
593d5c65159SKalle Valo 	WMI_SET_CURRENT_COUNTRY_CMDID = WMI_TLV_CMD(WMI_GRP_REGULATORY),
594d5c65159SKalle Valo 	WMI_11D_SCAN_START_CMDID,
595d5c65159SKalle Valo 	WMI_11D_SCAN_STOP_CMDID,
596d5c65159SKalle Valo 	WMI_SET_INIT_COUNTRY_CMDID,
597d5c65159SKalle Valo 	WMI_NDI_GET_CAP_REQ_CMDID = WMI_TLV_CMD(WMI_GRP_PROTOTYPE),
598d5c65159SKalle Valo 	WMI_NDP_INITIATOR_REQ_CMDID,
599d5c65159SKalle Valo 	WMI_NDP_RESPONDER_REQ_CMDID,
600d5c65159SKalle Valo 	WMI_NDP_END_REQ_CMDID,
601d5c65159SKalle Valo 	WMI_HW_DATA_FILTER_CMDID = WMI_TLV_CMD(WMI_GRP_HW_DATA_FILTER),
6026d293d44SJohn Crispin 	WMI_TWT_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_TWT),
6036d293d44SJohn Crispin 	WMI_TWT_DISABLE_CMDID,
6046d293d44SJohn Crispin 	WMI_TWT_ADD_DIALOG_CMDID,
6056d293d44SJohn Crispin 	WMI_TWT_DEL_DIALOG_CMDID,
6066d293d44SJohn Crispin 	WMI_TWT_PAUSE_DIALOG_CMDID,
6076d293d44SJohn Crispin 	WMI_TWT_RESUME_DIALOG_CMDID,
6083f8be640SJohn Crispin 	WMI_PDEV_OBSS_PD_SPATIAL_REUSE_CMDID =
6093f8be640SJohn Crispin 				WMI_TLV_CMD(WMI_GRP_SPATIAL_REUSE),
6103f8be640SJohn Crispin 	WMI_PDEV_OBSS_PD_SPATIAL_REUSE_SET_DEF_OBSS_THRESH_CMDID,
611d5c65159SKalle Valo };
612d5c65159SKalle Valo 
613d5c65159SKalle Valo enum wmi_tlv_event_id {
614d5c65159SKalle Valo 	WMI_SERVICE_READY_EVENTID = 0x1,
615d5c65159SKalle Valo 	WMI_READY_EVENTID,
616d5c65159SKalle Valo 	WMI_SERVICE_AVAILABLE_EVENTID,
617d5c65159SKalle Valo 	WMI_SCAN_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_SCAN),
618d5c65159SKalle Valo 	WMI_PDEV_TPC_CONFIG_EVENTID = WMI_TLV_CMD(WMI_GRP_PDEV),
619d5c65159SKalle Valo 	WMI_CHAN_INFO_EVENTID,
620d5c65159SKalle Valo 	WMI_PHYERR_EVENTID,
621d5c65159SKalle Valo 	WMI_PDEV_DUMP_EVENTID,
622d5c65159SKalle Valo 	WMI_TX_PAUSE_EVENTID,
623d5c65159SKalle Valo 	WMI_DFS_RADAR_EVENTID,
624d5c65159SKalle Valo 	WMI_PDEV_L1SS_TRACK_EVENTID,
625d5c65159SKalle Valo 	WMI_PDEV_TEMPERATURE_EVENTID,
626d5c65159SKalle Valo 	WMI_SERVICE_READY_EXT_EVENTID,
627d5c65159SKalle Valo 	WMI_PDEV_FIPS_EVENTID,
628d5c65159SKalle Valo 	WMI_PDEV_CHANNEL_HOPPING_EVENTID,
629d5c65159SKalle Valo 	WMI_PDEV_ANI_CCK_LEVEL_EVENTID,
630d5c65159SKalle Valo 	WMI_PDEV_ANI_OFDM_LEVEL_EVENTID,
631d5c65159SKalle Valo 	WMI_PDEV_TPC_EVENTID,
632d5c65159SKalle Valo 	WMI_PDEV_NFCAL_POWER_ALL_CHANNELS_EVENTID,
633d5c65159SKalle Valo 	WMI_PDEV_SET_HW_MODE_RESP_EVENTID,
634d5c65159SKalle Valo 	WMI_PDEV_HW_MODE_TRANSITION_EVENTID,
635d5c65159SKalle Valo 	WMI_PDEV_SET_MAC_CONFIG_RESP_EVENTID,
636d5c65159SKalle Valo 	WMI_PDEV_ANTDIV_STATUS_EVENTID,
637d5c65159SKalle Valo 	WMI_PDEV_CHIP_POWER_STATS_EVENTID,
638d5c65159SKalle Valo 	WMI_PDEV_CHIP_POWER_SAVE_FAILURE_DETECTED_EVENTID,
639d5c65159SKalle Valo 	WMI_PDEV_CSA_SWITCH_COUNT_STATUS_EVENTID,
640d5c65159SKalle Valo 	WMI_PDEV_CHECK_CAL_VERSION_EVENTID,
641d5c65159SKalle Valo 	WMI_PDEV_DIV_RSSI_ANTID_EVENTID,
642d5c65159SKalle Valo 	WMI_PDEV_BSS_CHAN_INFO_EVENTID,
643d5c65159SKalle Valo 	WMI_PDEV_UPDATE_CTLTABLE_EVENTID,
644d5c65159SKalle Valo 	WMI_PDEV_DMA_RING_CFG_RSP_EVENTID,
645d5c65159SKalle Valo 	WMI_PDEV_DMA_RING_BUF_RELEASE_EVENTID,
646d5c65159SKalle Valo 	WMI_PDEV_CTL_FAILSAFE_CHECK_EVENTID,
647bd647855SKarthikeyan Periyasamy 	WMI_PDEV_CSC_SWITCH_COUNT_STATUS_EVENTID,
648bd647855SKarthikeyan Periyasamy 	WMI_PDEV_COLD_BOOT_CAL_DATA_EVENTID,
649bd647855SKarthikeyan Periyasamy 	WMI_PDEV_RAP_INFO_EVENTID,
650bd647855SKarthikeyan Periyasamy 	WMI_CHAN_RF_CHARACTERIZATION_INFO_EVENTID,
651bd647855SKarthikeyan Periyasamy 	WMI_SERVICE_READY_EXT2_EVENTID,
652d5c65159SKalle Valo 	WMI_VDEV_START_RESP_EVENTID = WMI_TLV_CMD(WMI_GRP_VDEV),
653d5c65159SKalle Valo 	WMI_VDEV_STOPPED_EVENTID,
654d5c65159SKalle Valo 	WMI_VDEV_INSTALL_KEY_COMPLETE_EVENTID,
655d5c65159SKalle Valo 	WMI_VDEV_MCC_BCN_INTERVAL_CHANGE_REQ_EVENTID,
656d5c65159SKalle Valo 	WMI_VDEV_TSF_REPORT_EVENTID,
657d5c65159SKalle Valo 	WMI_VDEV_DELETE_RESP_EVENTID,
658d5c65159SKalle Valo 	WMI_VDEV_ENCRYPT_DECRYPT_DATA_RESP_EVENTID,
659d5c65159SKalle Valo 	WMI_VDEV_ADD_MAC_ADDR_TO_RX_FILTER_STATUS_EVENTID,
660d5c65159SKalle Valo 	WMI_PEER_STA_KICKOUT_EVENTID = WMI_TLV_CMD(WMI_GRP_PEER),
661d5c65159SKalle Valo 	WMI_PEER_INFO_EVENTID,
662d5c65159SKalle Valo 	WMI_PEER_TX_FAIL_CNT_THR_EVENTID,
663d5c65159SKalle Valo 	WMI_PEER_ESTIMATED_LINKSPEED_EVENTID,
664d5c65159SKalle Valo 	WMI_PEER_STATE_EVENTID,
665d5c65159SKalle Valo 	WMI_PEER_ASSOC_CONF_EVENTID,
666d5c65159SKalle Valo 	WMI_PEER_DELETE_RESP_EVENTID,
667d5c65159SKalle Valo 	WMI_PEER_RATECODE_LIST_EVENTID,
668d5c65159SKalle Valo 	WMI_WDS_PEER_EVENTID,
669d5c65159SKalle Valo 	WMI_PEER_STA_PS_STATECHG_EVENTID,
670d5c65159SKalle Valo 	WMI_PEER_ANTDIV_INFO_EVENTID,
6719cfbae46SJohn Crispin 	WMI_PEER_RESERVED0_EVENTID,
6729cfbae46SJohn Crispin 	WMI_PEER_RESERVED1_EVENTID,
6739cfbae46SJohn Crispin 	WMI_PEER_RESERVED2_EVENTID,
6749cfbae46SJohn Crispin 	WMI_PEER_RESERVED3_EVENTID,
6759cfbae46SJohn Crispin 	WMI_PEER_RESERVED4_EVENTID,
6769cfbae46SJohn Crispin 	WMI_PEER_RESERVED5_EVENTID,
6779cfbae46SJohn Crispin 	WMI_PEER_RESERVED6_EVENTID,
6789cfbae46SJohn Crispin 	WMI_PEER_RESERVED7_EVENTID,
6799cfbae46SJohn Crispin 	WMI_PEER_RESERVED8_EVENTID,
6809cfbae46SJohn Crispin 	WMI_PEER_RESERVED9_EVENTID,
6819cfbae46SJohn Crispin 	WMI_PEER_RESERVED10_EVENTID,
6829cfbae46SJohn Crispin 	WMI_PEER_OPER_MODE_CHANGE_EVENTID,
68394a6df31SP Praneesh 	WMI_PEER_TX_PN_RESPONSE_EVENTID,
68494a6df31SP Praneesh 	WMI_PEER_CFR_CAPTURE_EVENTID,
68594a6df31SP Praneesh 	WMI_PEER_CREATE_CONF_EVENTID,
686d5c65159SKalle Valo 	WMI_MGMT_RX_EVENTID = WMI_TLV_CMD(WMI_GRP_MGMT),
687d5c65159SKalle Valo 	WMI_HOST_SWBA_EVENTID,
688d5c65159SKalle Valo 	WMI_TBTTOFFSET_UPDATE_EVENTID,
689d5c65159SKalle Valo 	WMI_OFFLOAD_BCN_TX_STATUS_EVENTID,
690d5c65159SKalle Valo 	WMI_OFFLOAD_PROB_RESP_TX_STATUS_EVENTID,
691d5c65159SKalle Valo 	WMI_MGMT_TX_COMPLETION_EVENTID,
692d5c65159SKalle Valo 	WMI_MGMT_TX_BUNDLE_COMPLETION_EVENTID,
693d5c65159SKalle Valo 	WMI_TBTTOFFSET_EXT_UPDATE_EVENTID,
694047679e3SAloka Dixit 	WMI_OFFCHAN_DATA_TX_COMPLETION_EVENTID,
695047679e3SAloka Dixit 	WMI_HOST_FILS_DISCOVERY_EVENTID,
696d5c65159SKalle Valo 	WMI_TX_DELBA_COMPLETE_EVENTID = WMI_TLV_CMD(WMI_GRP_BA_NEG),
697d5c65159SKalle Valo 	WMI_TX_ADDBA_COMPLETE_EVENTID,
698d5c65159SKalle Valo 	WMI_BA_RSP_SSN_EVENTID,
699d5c65159SKalle Valo 	WMI_AGGR_STATE_TRIG_EVENTID,
700d5c65159SKalle Valo 	WMI_ROAM_EVENTID = WMI_TLV_CMD(WMI_GRP_ROAM),
701d5c65159SKalle Valo 	WMI_PROFILE_MATCH,
702d5c65159SKalle Valo 	WMI_ROAM_SYNCH_EVENTID,
703d5c65159SKalle Valo 	WMI_P2P_DISC_EVENTID = WMI_TLV_CMD(WMI_GRP_P2P),
704d5c65159SKalle Valo 	WMI_P2P_NOA_EVENTID,
705d5c65159SKalle Valo 	WMI_P2P_LISTEN_OFFLOAD_STOPPED_EVENTID,
706d5c65159SKalle Valo 	WMI_AP_PS_EGAP_INFO_EVENTID = WMI_TLV_CMD(WMI_GRP_AP_PS),
707d5c65159SKalle Valo 	WMI_PDEV_RESUME_EVENTID = WMI_TLV_CMD(WMI_GRP_SUSPEND),
708d5c65159SKalle Valo 	WMI_WOW_WAKEUP_HOST_EVENTID = WMI_TLV_CMD(WMI_GRP_WOW),
709d5c65159SKalle Valo 	WMI_D0_WOW_DISABLE_ACK_EVENTID,
710d5c65159SKalle Valo 	WMI_WOW_INITIAL_WAKEUP_EVENTID,
711d5c65159SKalle Valo 	WMI_RTT_MEASUREMENT_REPORT_EVENTID = WMI_TLV_CMD(WMI_GRP_RTT),
712d5c65159SKalle Valo 	WMI_TSF_MEASUREMENT_REPORT_EVENTID,
713d5c65159SKalle Valo 	WMI_RTT_ERROR_REPORT_EVENTID,
714d5c65159SKalle Valo 	WMI_STATS_EXT_EVENTID = WMI_TLV_CMD(WMI_GRP_STATS),
715d5c65159SKalle Valo 	WMI_IFACE_LINK_STATS_EVENTID,
716d5c65159SKalle Valo 	WMI_PEER_LINK_STATS_EVENTID,
717d5c65159SKalle Valo 	WMI_RADIO_LINK_STATS_EVENTID,
718d5c65159SKalle Valo 	WMI_UPDATE_FW_MEM_DUMP_EVENTID,
719d5c65159SKalle Valo 	WMI_DIAG_EVENT_LOG_SUPPORTED_EVENTID,
720d5c65159SKalle Valo 	WMI_INST_RSSI_STATS_EVENTID,
721d5c65159SKalle Valo 	WMI_RADIO_TX_POWER_LEVEL_STATS_EVENTID,
722d5c65159SKalle Valo 	WMI_REPORT_STATS_EVENTID,
723d5c65159SKalle Valo 	WMI_UPDATE_RCPI_EVENTID,
724d5c65159SKalle Valo 	WMI_PEER_STATS_INFO_EVENTID,
725d5c65159SKalle Valo 	WMI_RADIO_CHAN_STATS_EVENTID,
726d5c65159SKalle Valo 	WMI_NLO_MATCH_EVENTID = WMI_TLV_CMD(WMI_GRP_NLO_OFL),
727d5c65159SKalle Valo 	WMI_NLO_SCAN_COMPLETE_EVENTID,
728d5c65159SKalle Valo 	WMI_APFIND_EVENTID,
729d5c65159SKalle Valo 	WMI_PASSPOINT_MATCH_EVENTID,
730d5c65159SKalle Valo 	WMI_GTK_OFFLOAD_STATUS_EVENTID = WMI_TLV_CMD(WMI_GRP_GTK_OFL),
731d5c65159SKalle Valo 	WMI_GTK_REKEY_FAIL_EVENTID,
732d5c65159SKalle Valo 	WMI_CSA_HANDLING_EVENTID = WMI_TLV_CMD(WMI_GRP_CSA_OFL),
733d5c65159SKalle Valo 	WMI_CHATTER_PC_QUERY_EVENTID = WMI_TLV_CMD(WMI_GRP_CHATTER),
734d5c65159SKalle Valo 	WMI_PDEV_DFS_RADAR_DETECTION_EVENTID = WMI_TLV_CMD(WMI_GRP_DFS),
735d5c65159SKalle Valo 	WMI_VDEV_DFS_CAC_COMPLETE_EVENTID,
736d5c65159SKalle Valo 	WMI_VDEV_ADFS_OCAC_COMPLETE_EVENTID,
737d5c65159SKalle Valo 	WMI_ECHO_EVENTID = WMI_TLV_CMD(WMI_GRP_MISC),
738d5c65159SKalle Valo 	WMI_PDEV_UTF_EVENTID,
739d5c65159SKalle Valo 	WMI_DEBUG_MESG_EVENTID,
740d5c65159SKalle Valo 	WMI_UPDATE_STATS_EVENTID,
741d5c65159SKalle Valo 	WMI_DEBUG_PRINT_EVENTID,
742d5c65159SKalle Valo 	WMI_DCS_INTERFERENCE_EVENTID,
743d5c65159SKalle Valo 	WMI_PDEV_QVIT_EVENTID,
744d5c65159SKalle Valo 	WMI_WLAN_PROFILE_DATA_EVENTID,
745d5c65159SKalle Valo 	WMI_PDEV_FTM_INTG_EVENTID,
746d5c65159SKalle Valo 	WMI_WLAN_FREQ_AVOID_EVENTID,
747d5c65159SKalle Valo 	WMI_VDEV_GET_KEEPALIVE_EVENTID,
748d5c65159SKalle Valo 	WMI_THERMAL_MGMT_EVENTID,
749d5c65159SKalle Valo 	WMI_DIAG_DATA_CONTAINER_EVENTID,
750d5c65159SKalle Valo 	WMI_HOST_AUTO_SHUTDOWN_EVENTID,
751d5c65159SKalle Valo 	WMI_UPDATE_WHAL_MIB_STATS_EVENTID,
752d5c65159SKalle Valo 	WMI_UPDATE_VDEV_RATE_STATS_EVENTID,
753d5c65159SKalle Valo 	WMI_DIAG_EVENTID,
754d5c65159SKalle Valo 	WMI_OCB_SET_SCHED_EVENTID,
755d5c65159SKalle Valo 	WMI_DEBUG_MESG_FLUSH_COMPLETE_EVENTID,
756d5c65159SKalle Valo 	WMI_RSSI_BREACH_EVENTID,
757d5c65159SKalle Valo 	WMI_TRANSFER_DATA_TO_FLASH_COMPLETE_EVENTID,
758d5c65159SKalle Valo 	WMI_PDEV_UTF_SCPC_EVENTID,
759d5c65159SKalle Valo 	WMI_READ_DATA_FROM_FLASH_EVENTID,
760d5c65159SKalle Valo 	WMI_REPORT_RX_AGGR_FAILURE_EVENTID,
761d5c65159SKalle Valo 	WMI_PKGID_EVENTID,
762d5c65159SKalle Valo 	WMI_GPIO_INPUT_EVENTID = WMI_TLV_CMD(WMI_GRP_GPIO),
763d5c65159SKalle Valo 	WMI_UPLOADH_EVENTID,
764d5c65159SKalle Valo 	WMI_CAPTUREH_EVENTID,
765d5c65159SKalle Valo 	WMI_RFKILL_STATE_CHANGE_EVENTID,
766d5c65159SKalle Valo 	WMI_TDLS_PEER_EVENTID = WMI_TLV_CMD(WMI_GRP_TDLS),
767d5c65159SKalle Valo 	WMI_STA_SMPS_FORCE_MODE_COMPL_EVENTID = WMI_TLV_CMD(WMI_GRP_STA_SMPS),
768d5c65159SKalle Valo 	WMI_BATCH_SCAN_ENABLED_EVENTID = WMI_TLV_CMD(WMI_GRP_LOCATION_SCAN),
769d5c65159SKalle Valo 	WMI_BATCH_SCAN_RESULT_EVENTID,
770d5c65159SKalle Valo 	WMI_OEM_CAPABILITY_EVENTID = WMI_TLV_CMD(WMI_GRP_OEM),
771d5c65159SKalle Valo 	WMI_OEM_MEASUREMENT_REPORT_EVENTID,
772d5c65159SKalle Valo 	WMI_OEM_ERROR_REPORT_EVENTID,
773d5c65159SKalle Valo 	WMI_OEM_RESPONSE_EVENTID,
774d5c65159SKalle Valo 	WMI_NAN_EVENTID = WMI_TLV_CMD(WMI_GRP_NAN),
775d5c65159SKalle Valo 	WMI_NAN_DISC_IFACE_CREATED_EVENTID,
776d5c65159SKalle Valo 	WMI_NAN_DISC_IFACE_DELETED_EVENTID,
777d5c65159SKalle Valo 	WMI_NAN_STARTED_CLUSTER_EVENTID,
778d5c65159SKalle Valo 	WMI_NAN_JOINED_CLUSTER_EVENTID,
779d5c65159SKalle Valo 	WMI_COEX_REPORT_ANTENNA_ISOLATION_EVENTID = WMI_TLV_CMD(WMI_GRP_COEX),
780d5c65159SKalle Valo 	WMI_LPI_RESULT_EVENTID = WMI_TLV_CMD(WMI_GRP_LPI),
781d5c65159SKalle Valo 	WMI_LPI_STATUS_EVENTID,
782d5c65159SKalle Valo 	WMI_LPI_HANDOFF_EVENTID,
783d5c65159SKalle Valo 	WMI_EXTSCAN_START_STOP_EVENTID = WMI_TLV_CMD(WMI_GRP_EXTSCAN),
784d5c65159SKalle Valo 	WMI_EXTSCAN_OPERATION_EVENTID,
785d5c65159SKalle Valo 	WMI_EXTSCAN_TABLE_USAGE_EVENTID,
786d5c65159SKalle Valo 	WMI_EXTSCAN_CACHED_RESULTS_EVENTID,
787d5c65159SKalle Valo 	WMI_EXTSCAN_WLAN_CHANGE_RESULTS_EVENTID,
788d5c65159SKalle Valo 	WMI_EXTSCAN_HOTLIST_MATCH_EVENTID,
789d5c65159SKalle Valo 	WMI_EXTSCAN_CAPABILITIES_EVENTID,
790d5c65159SKalle Valo 	WMI_EXTSCAN_HOTLIST_SSID_MATCH_EVENTID,
791d5c65159SKalle Valo 	WMI_MDNS_STATS_EVENTID = WMI_TLV_CMD(WMI_GRP_MDNS_OFL),
792d5c65159SKalle Valo 	WMI_SAP_OFL_ADD_STA_EVENTID = WMI_TLV_CMD(WMI_GRP_SAP_OFL),
793d5c65159SKalle Valo 	WMI_SAP_OFL_DEL_STA_EVENTID,
794886433a9SJohn Crispin 	WMI_OBSS_COLOR_COLLISION_DETECTION_EVENTID =
795886433a9SJohn Crispin 		WMI_EVT_GRP_START_ID(WMI_GRP_OBSS_OFL),
796d5c65159SKalle Valo 	WMI_OCB_SET_CONFIG_RESP_EVENTID = WMI_TLV_CMD(WMI_GRP_OCB),
797d5c65159SKalle Valo 	WMI_OCB_GET_TSF_TIMER_RESP_EVENTID,
798d5c65159SKalle Valo 	WMI_DCC_GET_STATS_RESP_EVENTID,
799d5c65159SKalle Valo 	WMI_DCC_UPDATE_NDL_RESP_EVENTID,
800d5c65159SKalle Valo 	WMI_DCC_STATS_EVENTID,
801d5c65159SKalle Valo 	WMI_SOC_SET_HW_MODE_RESP_EVENTID = WMI_TLV_CMD(WMI_GRP_SOC),
802d5c65159SKalle Valo 	WMI_SOC_HW_MODE_TRANSITION_EVENTID,
803d5c65159SKalle Valo 	WMI_SOC_SET_DUAL_MAC_CONFIG_RESP_EVENTID,
804d5c65159SKalle Valo 	WMI_MAWC_ENABLE_SENSOR_EVENTID = WMI_TLV_CMD(WMI_GRP_MAWC),
805d5c65159SKalle Valo 	WMI_BPF_CAPABILIY_INFO_EVENTID = WMI_TLV_CMD(WMI_GRP_BPF_OFFLOAD),
806d5c65159SKalle Valo 	WMI_BPF_VDEV_STATS_INFO_EVENTID,
807d5c65159SKalle Valo 	WMI_RMC_NEW_LEADER_EVENTID = WMI_TLV_CMD(WMI_GRP_RMC),
808d5c65159SKalle Valo 	WMI_REG_CHAN_LIST_CC_EVENTID = WMI_TLV_CMD(WMI_GRP_REGULATORY),
809d5c65159SKalle Valo 	WMI_11D_NEW_COUNTRY_EVENTID,
81091fa00faSAditya Kumar Singh 	WMI_REG_CHAN_LIST_CC_EXT_EVENTID,
811d5c65159SKalle Valo 	WMI_NDI_CAP_RSP_EVENTID = WMI_TLV_CMD(WMI_GRP_PROTOTYPE),
812d5c65159SKalle Valo 	WMI_NDP_INITIATOR_RSP_EVENTID,
813d5c65159SKalle Valo 	WMI_NDP_RESPONDER_RSP_EVENTID,
814d5c65159SKalle Valo 	WMI_NDP_END_RSP_EVENTID,
815d5c65159SKalle Valo 	WMI_NDP_INDICATION_EVENTID,
816d5c65159SKalle Valo 	WMI_NDP_CONFIRM_EVENTID,
817d5c65159SKalle Valo 	WMI_NDP_END_INDICATION_EVENTID,
8186d293d44SJohn Crispin 
8196d293d44SJohn Crispin 	WMI_TWT_ENABLE_EVENTID = WMI_TLV_CMD(WMI_GRP_TWT),
8206d293d44SJohn Crispin 	WMI_TWT_DISABLE_EVENTID,
8216d293d44SJohn Crispin 	WMI_TWT_ADD_DIALOG_EVENTID,
8226d293d44SJohn Crispin 	WMI_TWT_DEL_DIALOG_EVENTID,
8236d293d44SJohn Crispin 	WMI_TWT_PAUSE_DIALOG_EVENTID,
8246d293d44SJohn Crispin 	WMI_TWT_RESUME_DIALOG_EVENTID,
825d5c65159SKalle Valo };
826d5c65159SKalle Valo 
827d5c65159SKalle Valo enum wmi_tlv_pdev_param {
828d5c65159SKalle Valo 	WMI_PDEV_PARAM_TX_CHAIN_MASK = 0x1,
829d5c65159SKalle Valo 	WMI_PDEV_PARAM_RX_CHAIN_MASK,
830d5c65159SKalle Valo 	WMI_PDEV_PARAM_TXPOWER_LIMIT2G,
831d5c65159SKalle Valo 	WMI_PDEV_PARAM_TXPOWER_LIMIT5G,
832d5c65159SKalle Valo 	WMI_PDEV_PARAM_TXPOWER_SCALE,
833d5c65159SKalle Valo 	WMI_PDEV_PARAM_BEACON_GEN_MODE,
834d5c65159SKalle Valo 	WMI_PDEV_PARAM_BEACON_TX_MODE,
835d5c65159SKalle Valo 	WMI_PDEV_PARAM_RESMGR_OFFCHAN_MODE,
836d5c65159SKalle Valo 	WMI_PDEV_PARAM_PROTECTION_MODE,
837d5c65159SKalle Valo 	WMI_PDEV_PARAM_DYNAMIC_BW,
838d5c65159SKalle Valo 	WMI_PDEV_PARAM_NON_AGG_SW_RETRY_TH,
839d5c65159SKalle Valo 	WMI_PDEV_PARAM_AGG_SW_RETRY_TH,
840d5c65159SKalle Valo 	WMI_PDEV_PARAM_STA_KICKOUT_TH,
841d5c65159SKalle Valo 	WMI_PDEV_PARAM_AC_AGGRSIZE_SCALING,
842d5c65159SKalle Valo 	WMI_PDEV_PARAM_LTR_ENABLE,
843d5c65159SKalle Valo 	WMI_PDEV_PARAM_LTR_AC_LATENCY_BE,
844d5c65159SKalle Valo 	WMI_PDEV_PARAM_LTR_AC_LATENCY_BK,
845d5c65159SKalle Valo 	WMI_PDEV_PARAM_LTR_AC_LATENCY_VI,
846d5c65159SKalle Valo 	WMI_PDEV_PARAM_LTR_AC_LATENCY_VO,
847d5c65159SKalle Valo 	WMI_PDEV_PARAM_LTR_AC_LATENCY_TIMEOUT,
848d5c65159SKalle Valo 	WMI_PDEV_PARAM_LTR_SLEEP_OVERRIDE,
849d5c65159SKalle Valo 	WMI_PDEV_PARAM_LTR_RX_OVERRIDE,
850d5c65159SKalle Valo 	WMI_PDEV_PARAM_LTR_TX_ACTIVITY_TIMEOUT,
851d5c65159SKalle Valo 	WMI_PDEV_PARAM_L1SS_ENABLE,
852d5c65159SKalle Valo 	WMI_PDEV_PARAM_DSLEEP_ENABLE,
853d5c65159SKalle Valo 	WMI_PDEV_PARAM_PCIELP_TXBUF_FLUSH,
854d5c65159SKalle Valo 	WMI_PDEV_PARAM_PCIELP_TXBUF_WATERMARK,
855d5c65159SKalle Valo 	WMI_PDEV_PARAM_PCIELP_TXBUF_TMO_EN,
856d5c65159SKalle Valo 	WMI_PDEV_PARAM_PCIELP_TXBUF_TMO_VALUE,
857d5c65159SKalle Valo 	WMI_PDEV_PARAM_PDEV_STATS_UPDATE_PERIOD,
858d5c65159SKalle Valo 	WMI_PDEV_PARAM_VDEV_STATS_UPDATE_PERIOD,
859d5c65159SKalle Valo 	WMI_PDEV_PARAM_PEER_STATS_UPDATE_PERIOD,
860d5c65159SKalle Valo 	WMI_PDEV_PARAM_BCNFLT_STATS_UPDATE_PERIOD,
861d5c65159SKalle Valo 	WMI_PDEV_PARAM_PMF_QOS,
862d5c65159SKalle Valo 	WMI_PDEV_PARAM_ARP_AC_OVERRIDE,
863d5c65159SKalle Valo 	WMI_PDEV_PARAM_DCS,
864d5c65159SKalle Valo 	WMI_PDEV_PARAM_ANI_ENABLE,
865d5c65159SKalle Valo 	WMI_PDEV_PARAM_ANI_POLL_PERIOD,
866d5c65159SKalle Valo 	WMI_PDEV_PARAM_ANI_LISTEN_PERIOD,
867d5c65159SKalle Valo 	WMI_PDEV_PARAM_ANI_OFDM_LEVEL,
868d5c65159SKalle Valo 	WMI_PDEV_PARAM_ANI_CCK_LEVEL,
869d5c65159SKalle Valo 	WMI_PDEV_PARAM_DYNTXCHAIN,
870d5c65159SKalle Valo 	WMI_PDEV_PARAM_PROXY_STA,
871d5c65159SKalle Valo 	WMI_PDEV_PARAM_IDLE_PS_CONFIG,
872d5c65159SKalle Valo 	WMI_PDEV_PARAM_POWER_GATING_SLEEP,
873d5c65159SKalle Valo 	WMI_PDEV_PARAM_RFKILL_ENABLE,
874d5c65159SKalle Valo 	WMI_PDEV_PARAM_BURST_DUR,
875d5c65159SKalle Valo 	WMI_PDEV_PARAM_BURST_ENABLE,
876d5c65159SKalle Valo 	WMI_PDEV_PARAM_HW_RFKILL_CONFIG,
877d5c65159SKalle Valo 	WMI_PDEV_PARAM_LOW_POWER_RF_ENABLE,
878d5c65159SKalle Valo 	WMI_PDEV_PARAM_L1SS_TRACK,
879d5c65159SKalle Valo 	WMI_PDEV_PARAM_HYST_EN,
880d5c65159SKalle Valo 	WMI_PDEV_PARAM_POWER_COLLAPSE_ENABLE,
881d5c65159SKalle Valo 	WMI_PDEV_PARAM_LED_SYS_STATE,
882d5c65159SKalle Valo 	WMI_PDEV_PARAM_LED_ENABLE,
883d5c65159SKalle Valo 	WMI_PDEV_PARAM_AUDIO_OVER_WLAN_LATENCY,
884d5c65159SKalle Valo 	WMI_PDEV_PARAM_AUDIO_OVER_WLAN_ENABLE,
885d5c65159SKalle Valo 	WMI_PDEV_PARAM_WHAL_MIB_STATS_UPDATE_ENABLE,
886d5c65159SKalle Valo 	WMI_PDEV_PARAM_VDEV_RATE_STATS_UPDATE_PERIOD,
887d5c65159SKalle Valo 	WMI_PDEV_PARAM_CTS_CBW,
888d5c65159SKalle Valo 	WMI_PDEV_PARAM_WNTS_CONFIG,
889d5c65159SKalle Valo 	WMI_PDEV_PARAM_ADAPTIVE_EARLY_RX_ENABLE,
890d5c65159SKalle Valo 	WMI_PDEV_PARAM_ADAPTIVE_EARLY_RX_MIN_SLEEP_SLOP,
891d5c65159SKalle Valo 	WMI_PDEV_PARAM_ADAPTIVE_EARLY_RX_INC_DEC_STEP,
892d5c65159SKalle Valo 	WMI_PDEV_PARAM_EARLY_RX_FIX_SLEEP_SLOP,
893d5c65159SKalle Valo 	WMI_PDEV_PARAM_BMISS_BASED_ADAPTIVE_BTO_ENABLE,
894d5c65159SKalle Valo 	WMI_PDEV_PARAM_BMISS_BTO_MIN_BCN_TIMEOUT,
895d5c65159SKalle Valo 	WMI_PDEV_PARAM_BMISS_BTO_INC_DEC_STEP,
896d5c65159SKalle Valo 	WMI_PDEV_PARAM_BTO_FIX_BCN_TIMEOUT,
897d5c65159SKalle Valo 	WMI_PDEV_PARAM_CE_BASED_ADAPTIVE_BTO_ENABLE,
898d5c65159SKalle Valo 	WMI_PDEV_PARAM_CE_BTO_COMBO_CE_VALUE,
899d5c65159SKalle Valo 	WMI_PDEV_PARAM_TX_CHAIN_MASK_2G,
900d5c65159SKalle Valo 	WMI_PDEV_PARAM_RX_CHAIN_MASK_2G,
901d5c65159SKalle Valo 	WMI_PDEV_PARAM_TX_CHAIN_MASK_5G,
902d5c65159SKalle Valo 	WMI_PDEV_PARAM_RX_CHAIN_MASK_5G,
903d5c65159SKalle Valo 	WMI_PDEV_PARAM_TX_CHAIN_MASK_CCK,
904d5c65159SKalle Valo 	WMI_PDEV_PARAM_TX_CHAIN_MASK_1SS,
905d5c65159SKalle Valo 	WMI_PDEV_PARAM_CTS2SELF_FOR_P2P_GO_CONFIG,
906d5c65159SKalle Valo 	WMI_PDEV_PARAM_TXPOWER_DECR_DB,
907d5c65159SKalle Valo 	WMI_PDEV_PARAM_AGGR_BURST,
908d5c65159SKalle Valo 	WMI_PDEV_PARAM_RX_DECAP_MODE,
909d5c65159SKalle Valo 	WMI_PDEV_PARAM_FAST_CHANNEL_RESET,
910d5c65159SKalle Valo 	WMI_PDEV_PARAM_SMART_ANTENNA_DEFAULT_ANTENNA,
911d5c65159SKalle Valo 	WMI_PDEV_PARAM_ANTENNA_GAIN,
912d5c65159SKalle Valo 	WMI_PDEV_PARAM_RX_FILTER,
913d5c65159SKalle Valo 	WMI_PDEV_SET_MCAST_TO_UCAST_TID,
914d5c65159SKalle Valo 	WMI_PDEV_PARAM_PROXY_STA_MODE,
915d5c65159SKalle Valo 	WMI_PDEV_PARAM_SET_MCAST2UCAST_MODE,
916d5c65159SKalle Valo 	WMI_PDEV_PARAM_SET_MCAST2UCAST_BUFFER,
917d5c65159SKalle Valo 	WMI_PDEV_PARAM_REMOVE_MCAST2UCAST_BUFFER,
918d5c65159SKalle Valo 	WMI_PDEV_PEER_STA_PS_STATECHG_ENABLE,
919d5c65159SKalle Valo 	WMI_PDEV_PARAM_IGMPMLD_AC_OVERRIDE,
920d5c65159SKalle Valo 	WMI_PDEV_PARAM_BLOCK_INTERBSS,
921d5c65159SKalle Valo 	WMI_PDEV_PARAM_SET_DISABLE_RESET_CMDID,
922d5c65159SKalle Valo 	WMI_PDEV_PARAM_SET_MSDU_TTL_CMDID,
923d5c65159SKalle Valo 	WMI_PDEV_PARAM_SET_PPDU_DURATION_CMDID,
924d5c65159SKalle Valo 	WMI_PDEV_PARAM_TXBF_SOUND_PERIOD_CMDID,
925d5c65159SKalle Valo 	WMI_PDEV_PARAM_SET_PROMISC_MODE_CMDID,
926d5c65159SKalle Valo 	WMI_PDEV_PARAM_SET_BURST_MODE_CMDID,
927d5c65159SKalle Valo 	WMI_PDEV_PARAM_EN_STATS,
928d5c65159SKalle Valo 	WMI_PDEV_PARAM_MU_GROUP_POLICY,
929d5c65159SKalle Valo 	WMI_PDEV_PARAM_NOISE_DETECTION,
930d5c65159SKalle Valo 	WMI_PDEV_PARAM_NOISE_THRESHOLD,
931d5c65159SKalle Valo 	WMI_PDEV_PARAM_DPD_ENABLE,
932d5c65159SKalle Valo 	WMI_PDEV_PARAM_SET_MCAST_BCAST_ECHO,
933d5c65159SKalle Valo 	WMI_PDEV_PARAM_ATF_STRICT_SCH,
934d5c65159SKalle Valo 	WMI_PDEV_PARAM_ATF_SCHED_DURATION,
935d5c65159SKalle Valo 	WMI_PDEV_PARAM_ANT_PLZN,
936d5c65159SKalle Valo 	WMI_PDEV_PARAM_MGMT_RETRY_LIMIT,
937d5c65159SKalle Valo 	WMI_PDEV_PARAM_SENSITIVITY_LEVEL,
938d5c65159SKalle Valo 	WMI_PDEV_PARAM_SIGNED_TXPOWER_2G,
939d5c65159SKalle Valo 	WMI_PDEV_PARAM_SIGNED_TXPOWER_5G,
940d5c65159SKalle Valo 	WMI_PDEV_PARAM_ENABLE_PER_TID_AMSDU,
941d5c65159SKalle Valo 	WMI_PDEV_PARAM_ENABLE_PER_TID_AMPDU,
942d5c65159SKalle Valo 	WMI_PDEV_PARAM_CCA_THRESHOLD,
943d5c65159SKalle Valo 	WMI_PDEV_PARAM_RTS_FIXED_RATE,
944d5c65159SKalle Valo 	WMI_PDEV_PARAM_PDEV_RESET,
945d5c65159SKalle Valo 	WMI_PDEV_PARAM_WAPI_MBSSID_OFFSET,
946d5c65159SKalle Valo 	WMI_PDEV_PARAM_ARP_DBG_SRCADDR,
947d5c65159SKalle Valo 	WMI_PDEV_PARAM_ARP_DBG_DSTADDR,
948d5c65159SKalle Valo 	WMI_PDEV_PARAM_ATF_OBSS_NOISE_SCH,
949d5c65159SKalle Valo 	WMI_PDEV_PARAM_ATF_OBSS_NOISE_SCALING_FACTOR,
950d5c65159SKalle Valo 	WMI_PDEV_PARAM_CUST_TXPOWER_SCALE,
951d5c65159SKalle Valo 	WMI_PDEV_PARAM_ATF_DYNAMIC_ENABLE,
952d5c65159SKalle Valo 	WMI_PDEV_PARAM_CTRL_RETRY_LIMIT,
953d5c65159SKalle Valo 	WMI_PDEV_PARAM_PROPAGATION_DELAY,
954d5c65159SKalle Valo 	WMI_PDEV_PARAM_ENA_ANT_DIV,
955d5c65159SKalle Valo 	WMI_PDEV_PARAM_FORCE_CHAIN_ANT,
956d5c65159SKalle Valo 	WMI_PDEV_PARAM_ANT_DIV_SELFTEST,
957d5c65159SKalle Valo 	WMI_PDEV_PARAM_ANT_DIV_SELFTEST_INTVL,
958d5c65159SKalle Valo 	WMI_PDEV_PARAM_STATS_OBSERVATION_PERIOD,
959d5c65159SKalle Valo 	WMI_PDEV_PARAM_TX_PPDU_DELAY_BIN_SIZE_MS,
960d5c65159SKalle Valo 	WMI_PDEV_PARAM_TX_PPDU_DELAY_ARRAY_LEN,
961d5c65159SKalle Valo 	WMI_PDEV_PARAM_TX_MPDU_AGGR_ARRAY_LEN,
962d5c65159SKalle Valo 	WMI_PDEV_PARAM_RX_MPDU_AGGR_ARRAY_LEN,
963d5c65159SKalle Valo 	WMI_PDEV_PARAM_TX_SCH_DELAY,
964d5c65159SKalle Valo 	WMI_PDEV_PARAM_ENABLE_RTS_SIFS_BURSTING,
965d5c65159SKalle Valo 	WMI_PDEV_PARAM_MAX_MPDUS_IN_AMPDU,
966d5c65159SKalle Valo 	WMI_PDEV_PARAM_PEER_STATS_INFO_ENABLE,
967d5c65159SKalle Valo 	WMI_PDEV_PARAM_FAST_PWR_TRANSITION,
968d5c65159SKalle Valo 	WMI_PDEV_PARAM_RADIO_CHAN_STATS_ENABLE,
969d5c65159SKalle Valo 	WMI_PDEV_PARAM_RADIO_DIAGNOSIS_ENABLE,
970d5c65159SKalle Valo 	WMI_PDEV_PARAM_MESH_MCAST_ENABLE,
971b56b08aeSRajkumar Manoharan 	WMI_PDEV_PARAM_SET_CMD_OBSS_PD_THRESHOLD = 0xbc,
972b56b08aeSRajkumar Manoharan 	WMI_PDEV_PARAM_SET_CMD_OBSS_PD_PER_AC = 0xbe,
973b56b08aeSRajkumar Manoharan 	WMI_PDEV_PARAM_ENABLE_SR_PROHIBIT = 0xc6,
974d5c65159SKalle Valo };
975d5c65159SKalle Valo 
976d5c65159SKalle Valo enum wmi_tlv_vdev_param {
977d5c65159SKalle Valo 	WMI_VDEV_PARAM_RTS_THRESHOLD = 0x1,
978d5c65159SKalle Valo 	WMI_VDEV_PARAM_FRAGMENTATION_THRESHOLD,
979d5c65159SKalle Valo 	WMI_VDEV_PARAM_BEACON_INTERVAL,
980d5c65159SKalle Valo 	WMI_VDEV_PARAM_LISTEN_INTERVAL,
981d5c65159SKalle Valo 	WMI_VDEV_PARAM_MULTICAST_RATE,
982d5c65159SKalle Valo 	WMI_VDEV_PARAM_MGMT_TX_RATE,
983d5c65159SKalle Valo 	WMI_VDEV_PARAM_SLOT_TIME,
984d5c65159SKalle Valo 	WMI_VDEV_PARAM_PREAMBLE,
985d5c65159SKalle Valo 	WMI_VDEV_PARAM_SWBA_TIME,
986d5c65159SKalle Valo 	WMI_VDEV_STATS_UPDATE_PERIOD,
987d5c65159SKalle Valo 	WMI_VDEV_PWRSAVE_AGEOUT_TIME,
988d5c65159SKalle Valo 	WMI_VDEV_HOST_SWBA_INTERVAL,
989d5c65159SKalle Valo 	WMI_VDEV_PARAM_DTIM_PERIOD,
990d5c65159SKalle Valo 	WMI_VDEV_OC_SCHEDULER_AIR_TIME_LIMIT,
991d5c65159SKalle Valo 	WMI_VDEV_PARAM_WDS,
992d5c65159SKalle Valo 	WMI_VDEV_PARAM_ATIM_WINDOW,
993d5c65159SKalle Valo 	WMI_VDEV_PARAM_BMISS_COUNT_MAX,
994d5c65159SKalle Valo 	WMI_VDEV_PARAM_BMISS_FIRST_BCNT,
995d5c65159SKalle Valo 	WMI_VDEV_PARAM_BMISS_FINAL_BCNT,
996d5c65159SKalle Valo 	WMI_VDEV_PARAM_FEATURE_WMM,
997d5c65159SKalle Valo 	WMI_VDEV_PARAM_CHWIDTH,
998d5c65159SKalle Valo 	WMI_VDEV_PARAM_CHEXTOFFSET,
999d5c65159SKalle Valo 	WMI_VDEV_PARAM_DISABLE_HTPROTECTION,
1000d5c65159SKalle Valo 	WMI_VDEV_PARAM_STA_QUICKKICKOUT,
1001d5c65159SKalle Valo 	WMI_VDEV_PARAM_MGMT_RATE,
1002d5c65159SKalle Valo 	WMI_VDEV_PARAM_PROTECTION_MODE,
1003d5c65159SKalle Valo 	WMI_VDEV_PARAM_FIXED_RATE,
1004d5c65159SKalle Valo 	WMI_VDEV_PARAM_SGI,
1005d5c65159SKalle Valo 	WMI_VDEV_PARAM_LDPC,
1006d5c65159SKalle Valo 	WMI_VDEV_PARAM_TX_STBC,
1007d5c65159SKalle Valo 	WMI_VDEV_PARAM_RX_STBC,
1008d5c65159SKalle Valo 	WMI_VDEV_PARAM_INTRA_BSS_FWD,
1009d5c65159SKalle Valo 	WMI_VDEV_PARAM_DEF_KEYID,
1010d5c65159SKalle Valo 	WMI_VDEV_PARAM_NSS,
1011d5c65159SKalle Valo 	WMI_VDEV_PARAM_BCAST_DATA_RATE,
1012d5c65159SKalle Valo 	WMI_VDEV_PARAM_MCAST_DATA_RATE,
1013d5c65159SKalle Valo 	WMI_VDEV_PARAM_MCAST_INDICATE,
1014d5c65159SKalle Valo 	WMI_VDEV_PARAM_DHCP_INDICATE,
1015d5c65159SKalle Valo 	WMI_VDEV_PARAM_UNKNOWN_DEST_INDICATE,
1016d5c65159SKalle Valo 	WMI_VDEV_PARAM_AP_KEEPALIVE_MIN_IDLE_INACTIVE_TIME_SECS,
1017d5c65159SKalle Valo 	WMI_VDEV_PARAM_AP_KEEPALIVE_MAX_IDLE_INACTIVE_TIME_SECS,
1018d5c65159SKalle Valo 	WMI_VDEV_PARAM_AP_KEEPALIVE_MAX_UNRESPONSIVE_TIME_SECS,
1019d5c65159SKalle Valo 	WMI_VDEV_PARAM_AP_ENABLE_NAWDS,
1020d5c65159SKalle Valo 	WMI_VDEV_PARAM_ENABLE_RTSCTS,
1021d5c65159SKalle Valo 	WMI_VDEV_PARAM_TXBF,
1022d5c65159SKalle Valo 	WMI_VDEV_PARAM_PACKET_POWERSAVE,
1023d5c65159SKalle Valo 	WMI_VDEV_PARAM_DROP_UNENCRY,
1024d5c65159SKalle Valo 	WMI_VDEV_PARAM_TX_ENCAP_TYPE,
1025d5c65159SKalle Valo 	WMI_VDEV_PARAM_AP_DETECT_OUT_OF_SYNC_SLEEPING_STA_TIME_SECS,
1026d5c65159SKalle Valo 	WMI_VDEV_PARAM_EARLY_RX_ADJUST_ENABLE,
1027d5c65159SKalle Valo 	WMI_VDEV_PARAM_EARLY_RX_TGT_BMISS_NUM,
1028d5c65159SKalle Valo 	WMI_VDEV_PARAM_EARLY_RX_BMISS_SAMPLE_CYCLE,
1029d5c65159SKalle Valo 	WMI_VDEV_PARAM_EARLY_RX_SLOP_STEP,
1030d5c65159SKalle Valo 	WMI_VDEV_PARAM_EARLY_RX_INIT_SLOP,
1031d5c65159SKalle Valo 	WMI_VDEV_PARAM_EARLY_RX_ADJUST_PAUSE,
1032d5c65159SKalle Valo 	WMI_VDEV_PARAM_TX_PWRLIMIT,
1033d5c65159SKalle Valo 	WMI_VDEV_PARAM_SNR_NUM_FOR_CAL,
1034d5c65159SKalle Valo 	WMI_VDEV_PARAM_ROAM_FW_OFFLOAD,
1035d5c65159SKalle Valo 	WMI_VDEV_PARAM_ENABLE_RMC,
1036d5c65159SKalle Valo 	WMI_VDEV_PARAM_IBSS_MAX_BCN_LOST_MS,
1037d5c65159SKalle Valo 	WMI_VDEV_PARAM_MAX_RATE,
1038d5c65159SKalle Valo 	WMI_VDEV_PARAM_EARLY_RX_DRIFT_SAMPLE,
1039d5c65159SKalle Valo 	WMI_VDEV_PARAM_SET_IBSS_TX_FAIL_CNT_THR,
1040d5c65159SKalle Valo 	WMI_VDEV_PARAM_EBT_RESYNC_TIMEOUT,
1041d5c65159SKalle Valo 	WMI_VDEV_PARAM_AGGR_TRIG_EVENT_ENABLE,
1042d5c65159SKalle Valo 	WMI_VDEV_PARAM_IS_IBSS_POWER_SAVE_ALLOWED,
1043d5c65159SKalle Valo 	WMI_VDEV_PARAM_IS_POWER_COLLAPSE_ALLOWED,
1044d5c65159SKalle Valo 	WMI_VDEV_PARAM_IS_AWAKE_ON_TXRX_ENABLED,
1045d5c65159SKalle Valo 	WMI_VDEV_PARAM_INACTIVITY_CNT,
1046d5c65159SKalle Valo 	WMI_VDEV_PARAM_TXSP_END_INACTIVITY_TIME_MS,
1047d5c65159SKalle Valo 	WMI_VDEV_PARAM_DTIM_POLICY,
1048d5c65159SKalle Valo 	WMI_VDEV_PARAM_IBSS_PS_WARMUP_TIME_SECS,
1049d5c65159SKalle Valo 	WMI_VDEV_PARAM_IBSS_PS_1RX_CHAIN_IN_ATIM_WINDOW_ENABLE,
1050d5c65159SKalle Valo 	WMI_VDEV_PARAM_RX_LEAK_WINDOW,
1051d5c65159SKalle Valo 	WMI_VDEV_PARAM_STATS_AVG_FACTOR,
1052d5c65159SKalle Valo 	WMI_VDEV_PARAM_DISCONNECT_TH,
1053d5c65159SKalle Valo 	WMI_VDEV_PARAM_RTSCTS_RATE,
1054d5c65159SKalle Valo 	WMI_VDEV_PARAM_MCC_RTSCTS_PROTECTION_ENABLE,
1055d5c65159SKalle Valo 	WMI_VDEV_PARAM_MCC_BROADCAST_PROBE_ENABLE,
1056d5c65159SKalle Valo 	WMI_VDEV_PARAM_TXPOWER_SCALE,
1057d5c65159SKalle Valo 	WMI_VDEV_PARAM_TXPOWER_SCALE_DECR_DB,
1058d5c65159SKalle Valo 	WMI_VDEV_PARAM_MCAST2UCAST_SET,
1059d5c65159SKalle Valo 	WMI_VDEV_PARAM_RC_NUM_RETRIES,
1060d5c65159SKalle Valo 	WMI_VDEV_PARAM_CABQ_MAXDUR,
1061d5c65159SKalle Valo 	WMI_VDEV_PARAM_MFPTEST_SET,
1062d5c65159SKalle Valo 	WMI_VDEV_PARAM_RTS_FIXED_RATE,
1063d5c65159SKalle Valo 	WMI_VDEV_PARAM_VHT_SGIMASK,
1064d5c65159SKalle Valo 	WMI_VDEV_PARAM_VHT80_RATEMASK,
1065d5c65159SKalle Valo 	WMI_VDEV_PARAM_PROXY_STA,
1066d5c65159SKalle Valo 	WMI_VDEV_PARAM_VIRTUAL_CELL_MODE,
1067d5c65159SKalle Valo 	WMI_VDEV_PARAM_RX_DECAP_TYPE,
1068d5c65159SKalle Valo 	WMI_VDEV_PARAM_BW_NSS_RATEMASK,
1069d5c65159SKalle Valo 	WMI_VDEV_PARAM_SENSOR_AP,
1070d5c65159SKalle Valo 	WMI_VDEV_PARAM_BEACON_RATE,
1071d5c65159SKalle Valo 	WMI_VDEV_PARAM_DTIM_ENABLE_CTS,
1072d5c65159SKalle Valo 	WMI_VDEV_PARAM_STA_KICKOUT,
1073d5c65159SKalle Valo 	WMI_VDEV_PARAM_CAPABILITIES,
1074d5c65159SKalle Valo 	WMI_VDEV_PARAM_TSF_INCREMENT,
1075d5c65159SKalle Valo 	WMI_VDEV_PARAM_AMPDU_PER_AC,
1076d5c65159SKalle Valo 	WMI_VDEV_PARAM_RX_FILTER,
1077d5c65159SKalle Valo 	WMI_VDEV_PARAM_MGMT_TX_POWER,
1078d5c65159SKalle Valo 	WMI_VDEV_PARAM_NON_AGG_SW_RETRY_TH,
1079d5c65159SKalle Valo 	WMI_VDEV_PARAM_AGG_SW_RETRY_TH,
1080d5c65159SKalle Valo 	WMI_VDEV_PARAM_DISABLE_DYN_BW_RTS,
1081d5c65159SKalle Valo 	WMI_VDEV_PARAM_ATF_SSID_SCHED_POLICY,
1082d5c65159SKalle Valo 	WMI_VDEV_PARAM_HE_DCM,
1083d5c65159SKalle Valo 	WMI_VDEV_PARAM_HE_RANGE_EXT,
1084d5c65159SKalle Valo 	WMI_VDEV_PARAM_ENABLE_BCAST_PROBE_RESPONSE,
1085d5c65159SKalle Valo 	WMI_VDEV_PARAM_FILS_MAX_CHANNEL_GUARD_TIME,
108661fe43e7SMiles Hu 	WMI_VDEV_PARAM_HE_LTF = 0x74,
1087a27c6a58SSowmiya Sree Elavalagan 	WMI_VDEV_PARAM_ENABLE_DISABLE_RTT_RESPONDER_ROLE = 0x7d,
1088aacb4622SPradeep Kumar Chitrapu 	WMI_VDEV_PARAM_BA_MODE = 0x7e,
108961fe43e7SMiles Hu 	WMI_VDEV_PARAM_AUTORATE_MISC_CFG = 0x80,
1090d5c65159SKalle Valo 	WMI_VDEV_PARAM_SET_HE_SOUNDING_MODE = 0x87,
109191270d70SPradeep Kumar Chitrapu 	WMI_VDEV_PARAM_6GHZ_PARAMS = 0x99,
1092d5c65159SKalle Valo 	WMI_VDEV_PARAM_PROTOTYPE = 0x8000,
1093d5c65159SKalle Valo 	WMI_VDEV_PARAM_BSS_COLOR,
1094d5c65159SKalle Valo 	WMI_VDEV_PARAM_SET_HEMU_MODE,
1095f0049043SPradeep Kumar Chitrapu 	WMI_VDEV_PARAM_HEOPS_0_31 = 0x8003,
1096d5c65159SKalle Valo };
1097d5c65159SKalle Valo 
1098d5c65159SKalle Valo enum wmi_tlv_peer_flags {
1099d5c65159SKalle Valo 	WMI_TLV_PEER_AUTH = 0x00000001,
1100d5c65159SKalle Valo 	WMI_TLV_PEER_QOS = 0x00000002,
1101d5c65159SKalle Valo 	WMI_TLV_PEER_NEED_PTK_4_WAY = 0x00000004,
1102d5c65159SKalle Valo 	WMI_TLV_PEER_NEED_GTK_2_WAY = 0x00000010,
1103d5c65159SKalle Valo 	WMI_TLV_PEER_APSD = 0x00000800,
1104d5c65159SKalle Valo 	WMI_TLV_PEER_HT = 0x00001000,
1105d5c65159SKalle Valo 	WMI_TLV_PEER_40MHZ = 0x00002000,
1106d5c65159SKalle Valo 	WMI_TLV_PEER_STBC = 0x00008000,
1107d5c65159SKalle Valo 	WMI_TLV_PEER_LDPC = 0x00010000,
1108d5c65159SKalle Valo 	WMI_TLV_PEER_DYN_MIMOPS = 0x00020000,
1109d5c65159SKalle Valo 	WMI_TLV_PEER_STATIC_MIMOPS = 0x00040000,
1110d5c65159SKalle Valo 	WMI_TLV_PEER_SPATIAL_MUX = 0x00200000,
1111d5c65159SKalle Valo 	WMI_TLV_PEER_VHT = 0x02000000,
1112d5c65159SKalle Valo 	WMI_TLV_PEER_80MHZ = 0x04000000,
1113d5c65159SKalle Valo 	WMI_TLV_PEER_PMF = 0x08000000,
1114d5c65159SKalle Valo 	WMI_PEER_IS_P2P_CAPABLE = 0x20000000,
1115d5c65159SKalle Valo 	WMI_PEER_160MHZ         = 0x40000000,
1116d5c65159SKalle Valo 	WMI_PEER_SAFEMODE_EN    = 0x80000000,
1117d5c65159SKalle Valo 
1118d5c65159SKalle Valo };
1119d5c65159SKalle Valo 
1120d5c65159SKalle Valo /** Enum list of TLV Tags for each parameter structure type. */
1121d5c65159SKalle Valo enum wmi_tlv_tag {
1122d5c65159SKalle Valo 	WMI_TAG_LAST_RESERVED = 15,
1123d5c65159SKalle Valo 	WMI_TAG_FIRST_ARRAY_ENUM,
1124d5c65159SKalle Valo 	WMI_TAG_ARRAY_UINT32 = WMI_TAG_FIRST_ARRAY_ENUM,
1125d5c65159SKalle Valo 	WMI_TAG_ARRAY_BYTE,
1126d5c65159SKalle Valo 	WMI_TAG_ARRAY_STRUCT,
1127d5c65159SKalle Valo 	WMI_TAG_ARRAY_FIXED_STRUCT,
1128d5c65159SKalle Valo 	WMI_TAG_LAST_ARRAY_ENUM = 31,
1129d5c65159SKalle Valo 	WMI_TAG_SERVICE_READY_EVENT,
1130d5c65159SKalle Valo 	WMI_TAG_HAL_REG_CAPABILITIES,
1131d5c65159SKalle Valo 	WMI_TAG_WLAN_HOST_MEM_REQ,
1132d5c65159SKalle Valo 	WMI_TAG_READY_EVENT,
1133d5c65159SKalle Valo 	WMI_TAG_SCAN_EVENT,
1134d5c65159SKalle Valo 	WMI_TAG_PDEV_TPC_CONFIG_EVENT,
1135d5c65159SKalle Valo 	WMI_TAG_CHAN_INFO_EVENT,
1136d5c65159SKalle Valo 	WMI_TAG_COMB_PHYERR_RX_HDR,
1137d5c65159SKalle Valo 	WMI_TAG_VDEV_START_RESPONSE_EVENT,
1138d5c65159SKalle Valo 	WMI_TAG_VDEV_STOPPED_EVENT,
1139d5c65159SKalle Valo 	WMI_TAG_VDEV_INSTALL_KEY_COMPLETE_EVENT,
1140d5c65159SKalle Valo 	WMI_TAG_PEER_STA_KICKOUT_EVENT,
1141d5c65159SKalle Valo 	WMI_TAG_MGMT_RX_HDR,
1142d5c65159SKalle Valo 	WMI_TAG_TBTT_OFFSET_EVENT,
1143d5c65159SKalle Valo 	WMI_TAG_TX_DELBA_COMPLETE_EVENT,
1144d5c65159SKalle Valo 	WMI_TAG_TX_ADDBA_COMPLETE_EVENT,
1145d5c65159SKalle Valo 	WMI_TAG_ROAM_EVENT,
1146d5c65159SKalle Valo 	WMI_TAG_WOW_EVENT_INFO,
1147d5c65159SKalle Valo 	WMI_TAG_WOW_EVENT_INFO_SECTION_BITMAP,
1148d5c65159SKalle Valo 	WMI_TAG_RTT_EVENT_HEADER,
1149d5c65159SKalle Valo 	WMI_TAG_RTT_ERROR_REPORT_EVENT,
1150d5c65159SKalle Valo 	WMI_TAG_RTT_MEAS_EVENT,
1151d5c65159SKalle Valo 	WMI_TAG_ECHO_EVENT,
1152d5c65159SKalle Valo 	WMI_TAG_FTM_INTG_EVENT,
1153d5c65159SKalle Valo 	WMI_TAG_VDEV_GET_KEEPALIVE_EVENT,
1154d5c65159SKalle Valo 	WMI_TAG_GPIO_INPUT_EVENT,
1155d5c65159SKalle Valo 	WMI_TAG_CSA_EVENT,
1156d5c65159SKalle Valo 	WMI_TAG_GTK_OFFLOAD_STATUS_EVENT,
1157d5c65159SKalle Valo 	WMI_TAG_IGTK_INFO,
1158d5c65159SKalle Valo 	WMI_TAG_DCS_INTERFERENCE_EVENT,
1159d5c65159SKalle Valo 	WMI_TAG_ATH_DCS_CW_INT,
1160d5c65159SKalle Valo 	WMI_TAG_WLAN_DCS_CW_INT = /* ALIAS */
1161d5c65159SKalle Valo 		WMI_TAG_ATH_DCS_CW_INT,
1162d5c65159SKalle Valo 	WMI_TAG_ATH_DCS_WLAN_INT_STAT,
1163d5c65159SKalle Valo 	WMI_TAG_WLAN_DCS_IM_TGT_STATS_T = /* ALIAS */
1164d5c65159SKalle Valo 		WMI_TAG_ATH_DCS_WLAN_INT_STAT,
1165d5c65159SKalle Valo 	WMI_TAG_WLAN_PROFILE_CTX_T,
1166d5c65159SKalle Valo 	WMI_TAG_WLAN_PROFILE_T,
1167d5c65159SKalle Valo 	WMI_TAG_PDEV_QVIT_EVENT,
1168d5c65159SKalle Valo 	WMI_TAG_HOST_SWBA_EVENT,
1169d5c65159SKalle Valo 	WMI_TAG_TIM_INFO,
1170d5c65159SKalle Valo 	WMI_TAG_P2P_NOA_INFO,
1171d5c65159SKalle Valo 	WMI_TAG_STATS_EVENT,
1172d5c65159SKalle Valo 	WMI_TAG_AVOID_FREQ_RANGES_EVENT,
1173d5c65159SKalle Valo 	WMI_TAG_AVOID_FREQ_RANGE_DESC,
1174d5c65159SKalle Valo 	WMI_TAG_GTK_REKEY_FAIL_EVENT,
1175d5c65159SKalle Valo 	WMI_TAG_INIT_CMD,
1176d5c65159SKalle Valo 	WMI_TAG_RESOURCE_CONFIG,
1177d5c65159SKalle Valo 	WMI_TAG_WLAN_HOST_MEMORY_CHUNK,
1178d5c65159SKalle Valo 	WMI_TAG_START_SCAN_CMD,
1179d5c65159SKalle Valo 	WMI_TAG_STOP_SCAN_CMD,
1180d5c65159SKalle Valo 	WMI_TAG_SCAN_CHAN_LIST_CMD,
1181d5c65159SKalle Valo 	WMI_TAG_CHANNEL,
1182d5c65159SKalle Valo 	WMI_TAG_PDEV_SET_REGDOMAIN_CMD,
1183d5c65159SKalle Valo 	WMI_TAG_PDEV_SET_PARAM_CMD,
1184d5c65159SKalle Valo 	WMI_TAG_PDEV_SET_WMM_PARAMS_CMD,
1185d5c65159SKalle Valo 	WMI_TAG_WMM_PARAMS,
1186d5c65159SKalle Valo 	WMI_TAG_PDEV_SET_QUIET_CMD,
1187d5c65159SKalle Valo 	WMI_TAG_VDEV_CREATE_CMD,
1188d5c65159SKalle Valo 	WMI_TAG_VDEV_DELETE_CMD,
1189d5c65159SKalle Valo 	WMI_TAG_VDEV_START_REQUEST_CMD,
1190d5c65159SKalle Valo 	WMI_TAG_P2P_NOA_DESCRIPTOR,
1191d5c65159SKalle Valo 	WMI_TAG_P2P_GO_SET_BEACON_IE,
1192d5c65159SKalle Valo 	WMI_TAG_GTK_OFFLOAD_CMD,
1193d5c65159SKalle Valo 	WMI_TAG_VDEV_UP_CMD,
1194d5c65159SKalle Valo 	WMI_TAG_VDEV_STOP_CMD,
1195d5c65159SKalle Valo 	WMI_TAG_VDEV_DOWN_CMD,
1196d5c65159SKalle Valo 	WMI_TAG_VDEV_SET_PARAM_CMD,
1197d5c65159SKalle Valo 	WMI_TAG_VDEV_INSTALL_KEY_CMD,
1198d5c65159SKalle Valo 	WMI_TAG_PEER_CREATE_CMD,
1199d5c65159SKalle Valo 	WMI_TAG_PEER_DELETE_CMD,
1200d5c65159SKalle Valo 	WMI_TAG_PEER_FLUSH_TIDS_CMD,
1201d5c65159SKalle Valo 	WMI_TAG_PEER_SET_PARAM_CMD,
1202d5c65159SKalle Valo 	WMI_TAG_PEER_ASSOC_COMPLETE_CMD,
1203d5c65159SKalle Valo 	WMI_TAG_VHT_RATE_SET,
1204d5c65159SKalle Valo 	WMI_TAG_BCN_TMPL_CMD,
1205d5c65159SKalle Valo 	WMI_TAG_PRB_TMPL_CMD,
1206d5c65159SKalle Valo 	WMI_TAG_BCN_PRB_INFO,
1207d5c65159SKalle Valo 	WMI_TAG_PEER_TID_ADDBA_CMD,
1208d5c65159SKalle Valo 	WMI_TAG_PEER_TID_DELBA_CMD,
1209d5c65159SKalle Valo 	WMI_TAG_STA_POWERSAVE_MODE_CMD,
1210d5c65159SKalle Valo 	WMI_TAG_STA_POWERSAVE_PARAM_CMD,
1211d5c65159SKalle Valo 	WMI_TAG_STA_DTIM_PS_METHOD_CMD,
1212d5c65159SKalle Valo 	WMI_TAG_ROAM_SCAN_MODE,
1213d5c65159SKalle Valo 	WMI_TAG_ROAM_SCAN_RSSI_THRESHOLD,
1214d5c65159SKalle Valo 	WMI_TAG_ROAM_SCAN_PERIOD,
1215d5c65159SKalle Valo 	WMI_TAG_ROAM_SCAN_RSSI_CHANGE_THRESHOLD,
1216d5c65159SKalle Valo 	WMI_TAG_PDEV_SUSPEND_CMD,
1217d5c65159SKalle Valo 	WMI_TAG_PDEV_RESUME_CMD,
1218d5c65159SKalle Valo 	WMI_TAG_ADD_BCN_FILTER_CMD,
1219d5c65159SKalle Valo 	WMI_TAG_RMV_BCN_FILTER_CMD,
1220d5c65159SKalle Valo 	WMI_TAG_WOW_ENABLE_CMD,
1221d5c65159SKalle Valo 	WMI_TAG_WOW_HOSTWAKEUP_FROM_SLEEP_CMD,
1222d5c65159SKalle Valo 	WMI_TAG_STA_UAPSD_AUTO_TRIG_CMD,
1223d5c65159SKalle Valo 	WMI_TAG_STA_UAPSD_AUTO_TRIG_PARAM,
1224d5c65159SKalle Valo 	WMI_TAG_SET_ARP_NS_OFFLOAD_CMD,
1225d5c65159SKalle Valo 	WMI_TAG_ARP_OFFLOAD_TUPLE,
1226d5c65159SKalle Valo 	WMI_TAG_NS_OFFLOAD_TUPLE,
1227d5c65159SKalle Valo 	WMI_TAG_FTM_INTG_CMD,
1228d5c65159SKalle Valo 	WMI_TAG_STA_KEEPALIVE_CMD,
1229b7b6f861SBaochen Qiang 	WMI_TAG_STA_KEEPALIVE_ARP_RESPONSE,
1230d5c65159SKalle Valo 	WMI_TAG_P2P_SET_VENDOR_IE_DATA_CMD,
1231d5c65159SKalle Valo 	WMI_TAG_AP_PS_PEER_CMD,
1232d5c65159SKalle Valo 	WMI_TAG_PEER_RATE_RETRY_SCHED_CMD,
1233d5c65159SKalle Valo 	WMI_TAG_WLAN_PROFILE_TRIGGER_CMD,
1234d5c65159SKalle Valo 	WMI_TAG_WLAN_PROFILE_SET_HIST_INTVL_CMD,
1235d5c65159SKalle Valo 	WMI_TAG_WLAN_PROFILE_GET_PROF_DATA_CMD,
1236d5c65159SKalle Valo 	WMI_TAG_WLAN_PROFILE_ENABLE_PROFILE_ID_CMD,
1237d5c65159SKalle Valo 	WMI_TAG_WOW_DEL_PATTERN_CMD,
1238d5c65159SKalle Valo 	WMI_TAG_WOW_ADD_DEL_EVT_CMD,
1239d5c65159SKalle Valo 	WMI_TAG_RTT_MEASREQ_HEAD,
1240d5c65159SKalle Valo 	WMI_TAG_RTT_MEASREQ_BODY,
1241d5c65159SKalle Valo 	WMI_TAG_RTT_TSF_CMD,
1242d5c65159SKalle Valo 	WMI_TAG_VDEV_SPECTRAL_CONFIGURE_CMD,
1243d5c65159SKalle Valo 	WMI_TAG_VDEV_SPECTRAL_ENABLE_CMD,
1244d5c65159SKalle Valo 	WMI_TAG_REQUEST_STATS_CMD,
1245d5c65159SKalle Valo 	WMI_TAG_NLO_CONFIG_CMD,
1246d5c65159SKalle Valo 	WMI_TAG_NLO_CONFIGURED_PARAMETERS,
1247d5c65159SKalle Valo 	WMI_TAG_CSA_OFFLOAD_ENABLE_CMD,
1248d5c65159SKalle Valo 	WMI_TAG_CSA_OFFLOAD_CHANSWITCH_CMD,
1249d5c65159SKalle Valo 	WMI_TAG_CHATTER_SET_MODE_CMD,
1250d5c65159SKalle Valo 	WMI_TAG_ECHO_CMD,
1251d5c65159SKalle Valo 	WMI_TAG_VDEV_SET_KEEPALIVE_CMD,
1252d5c65159SKalle Valo 	WMI_TAG_VDEV_GET_KEEPALIVE_CMD,
1253d5c65159SKalle Valo 	WMI_TAG_FORCE_FW_HANG_CMD,
1254d5c65159SKalle Valo 	WMI_TAG_GPIO_CONFIG_CMD,
1255d5c65159SKalle Valo 	WMI_TAG_GPIO_OUTPUT_CMD,
1256d5c65159SKalle Valo 	WMI_TAG_PEER_ADD_WDS_ENTRY_CMD,
1257d5c65159SKalle Valo 	WMI_TAG_PEER_REMOVE_WDS_ENTRY_CMD,
1258d5c65159SKalle Valo 	WMI_TAG_BCN_TX_HDR,
1259d5c65159SKalle Valo 	WMI_TAG_BCN_SEND_FROM_HOST_CMD,
1260d5c65159SKalle Valo 	WMI_TAG_MGMT_TX_HDR,
1261d5c65159SKalle Valo 	WMI_TAG_ADDBA_CLEAR_RESP_CMD,
1262d5c65159SKalle Valo 	WMI_TAG_ADDBA_SEND_CMD,
1263d5c65159SKalle Valo 	WMI_TAG_DELBA_SEND_CMD,
1264d5c65159SKalle Valo 	WMI_TAG_ADDBA_SETRESPONSE_CMD,
1265d5c65159SKalle Valo 	WMI_TAG_SEND_SINGLEAMSDU_CMD,
1266d5c65159SKalle Valo 	WMI_TAG_PDEV_PKTLOG_ENABLE_CMD,
1267d5c65159SKalle Valo 	WMI_TAG_PDEV_PKTLOG_DISABLE_CMD,
1268d5c65159SKalle Valo 	WMI_TAG_PDEV_SET_HT_IE_CMD,
1269d5c65159SKalle Valo 	WMI_TAG_PDEV_SET_VHT_IE_CMD,
1270d5c65159SKalle Valo 	WMI_TAG_PDEV_SET_DSCP_TID_MAP_CMD,
1271d5c65159SKalle Valo 	WMI_TAG_PDEV_GREEN_AP_PS_ENABLE_CMD,
1272d5c65159SKalle Valo 	WMI_TAG_PDEV_GET_TPC_CONFIG_CMD,
1273d5c65159SKalle Valo 	WMI_TAG_PDEV_SET_BASE_MACADDR_CMD,
1274d5c65159SKalle Valo 	WMI_TAG_PEER_MCAST_GROUP_CMD,
1275d5c65159SKalle Valo 	WMI_TAG_ROAM_AP_PROFILE,
1276d5c65159SKalle Valo 	WMI_TAG_AP_PROFILE,
1277d5c65159SKalle Valo 	WMI_TAG_SCAN_SCH_PRIORITY_TABLE_CMD,
1278d5c65159SKalle Valo 	WMI_TAG_PDEV_DFS_ENABLE_CMD,
1279d5c65159SKalle Valo 	WMI_TAG_PDEV_DFS_DISABLE_CMD,
1280d5c65159SKalle Valo 	WMI_TAG_WOW_ADD_PATTERN_CMD,
1281d5c65159SKalle Valo 	WMI_TAG_WOW_BITMAP_PATTERN_T,
1282d5c65159SKalle Valo 	WMI_TAG_WOW_IPV4_SYNC_PATTERN_T,
1283d5c65159SKalle Valo 	WMI_TAG_WOW_IPV6_SYNC_PATTERN_T,
1284d5c65159SKalle Valo 	WMI_TAG_WOW_MAGIC_PATTERN_CMD,
1285d5c65159SKalle Valo 	WMI_TAG_SCAN_UPDATE_REQUEST_CMD,
1286d5c65159SKalle Valo 	WMI_TAG_CHATTER_PKT_COALESCING_FILTER,
1287d5c65159SKalle Valo 	WMI_TAG_CHATTER_COALESCING_ADD_FILTER_CMD,
1288d5c65159SKalle Valo 	WMI_TAG_CHATTER_COALESCING_DELETE_FILTER_CMD,
1289d5c65159SKalle Valo 	WMI_TAG_CHATTER_COALESCING_QUERY_CMD,
1290d5c65159SKalle Valo 	WMI_TAG_TXBF_CMD,
1291d5c65159SKalle Valo 	WMI_TAG_DEBUG_LOG_CONFIG_CMD,
1292d5c65159SKalle Valo 	WMI_TAG_NLO_EVENT,
1293d5c65159SKalle Valo 	WMI_TAG_CHATTER_QUERY_REPLY_EVENT,
1294d5c65159SKalle Valo 	WMI_TAG_UPLOAD_H_HDR,
1295d5c65159SKalle Valo 	WMI_TAG_CAPTURE_H_EVENT_HDR,
1296d5c65159SKalle Valo 	WMI_TAG_VDEV_WNM_SLEEPMODE_CMD,
1297d5c65159SKalle Valo 	WMI_TAG_VDEV_IPSEC_NATKEEPALIVE_FILTER_CMD,
1298d5c65159SKalle Valo 	WMI_TAG_VDEV_WMM_ADDTS_CMD,
1299d5c65159SKalle Valo 	WMI_TAG_VDEV_WMM_DELTS_CMD,
1300d5c65159SKalle Valo 	WMI_TAG_VDEV_SET_WMM_PARAMS_CMD,
1301d5c65159SKalle Valo 	WMI_TAG_TDLS_SET_STATE_CMD,
1302d5c65159SKalle Valo 	WMI_TAG_TDLS_PEER_UPDATE_CMD,
1303d5c65159SKalle Valo 	WMI_TAG_TDLS_PEER_EVENT,
1304d5c65159SKalle Valo 	WMI_TAG_TDLS_PEER_CAPABILITIES,
1305d5c65159SKalle Valo 	WMI_TAG_VDEV_MCC_SET_TBTT_MODE_CMD,
1306d5c65159SKalle Valo 	WMI_TAG_ROAM_CHAN_LIST,
1307d5c65159SKalle Valo 	WMI_TAG_VDEV_MCC_BCN_INTVL_CHANGE_EVENT,
1308d5c65159SKalle Valo 	WMI_TAG_RESMGR_ADAPTIVE_OCS_ENABLE_DISABLE_CMD,
1309d5c65159SKalle Valo 	WMI_TAG_RESMGR_SET_CHAN_TIME_QUOTA_CMD,
1310d5c65159SKalle Valo 	WMI_TAG_RESMGR_SET_CHAN_LATENCY_CMD,
1311d5c65159SKalle Valo 	WMI_TAG_BA_REQ_SSN_CMD,
1312d5c65159SKalle Valo 	WMI_TAG_BA_RSP_SSN_EVENT,
1313d5c65159SKalle Valo 	WMI_TAG_STA_SMPS_FORCE_MODE_CMD,
1314d5c65159SKalle Valo 	WMI_TAG_SET_MCASTBCAST_FILTER_CMD,
1315d5c65159SKalle Valo 	WMI_TAG_P2P_SET_OPPPS_CMD,
1316d5c65159SKalle Valo 	WMI_TAG_P2P_SET_NOA_CMD,
1317d5c65159SKalle Valo 	WMI_TAG_BA_REQ_SSN_CMD_SUB_STRUCT_PARAM,
1318d5c65159SKalle Valo 	WMI_TAG_BA_REQ_SSN_EVENT_SUB_STRUCT_PARAM,
1319d5c65159SKalle Valo 	WMI_TAG_STA_SMPS_PARAM_CMD,
1320d5c65159SKalle Valo 	WMI_TAG_VDEV_SET_GTX_PARAMS_CMD,
1321d5c65159SKalle Valo 	WMI_TAG_MCC_SCHED_TRAFFIC_STATS_CMD,
1322d5c65159SKalle Valo 	WMI_TAG_MCC_SCHED_STA_TRAFFIC_STATS,
1323d5c65159SKalle Valo 	WMI_TAG_OFFLOAD_BCN_TX_STATUS_EVENT,
1324d5c65159SKalle Valo 	WMI_TAG_P2P_NOA_EVENT,
1325d5c65159SKalle Valo 	WMI_TAG_HB_SET_ENABLE_CMD,
1326d5c65159SKalle Valo 	WMI_TAG_HB_SET_TCP_PARAMS_CMD,
1327d5c65159SKalle Valo 	WMI_TAG_HB_SET_TCP_PKT_FILTER_CMD,
1328d5c65159SKalle Valo 	WMI_TAG_HB_SET_UDP_PARAMS_CMD,
1329d5c65159SKalle Valo 	WMI_TAG_HB_SET_UDP_PKT_FILTER_CMD,
1330d5c65159SKalle Valo 	WMI_TAG_HB_IND_EVENT,
1331d5c65159SKalle Valo 	WMI_TAG_TX_PAUSE_EVENT,
1332d5c65159SKalle Valo 	WMI_TAG_RFKILL_EVENT,
1333d5c65159SKalle Valo 	WMI_TAG_DFS_RADAR_EVENT,
1334d5c65159SKalle Valo 	WMI_TAG_DFS_PHYERR_FILTER_ENA_CMD,
1335d5c65159SKalle Valo 	WMI_TAG_DFS_PHYERR_FILTER_DIS_CMD,
1336d5c65159SKalle Valo 	WMI_TAG_BATCH_SCAN_RESULT_SCAN_LIST,
1337d5c65159SKalle Valo 	WMI_TAG_BATCH_SCAN_RESULT_NETWORK_INFO,
1338d5c65159SKalle Valo 	WMI_TAG_BATCH_SCAN_ENABLE_CMD,
1339d5c65159SKalle Valo 	WMI_TAG_BATCH_SCAN_DISABLE_CMD,
1340d5c65159SKalle Valo 	WMI_TAG_BATCH_SCAN_TRIGGER_RESULT_CMD,
1341d5c65159SKalle Valo 	WMI_TAG_BATCH_SCAN_ENABLED_EVENT,
1342d5c65159SKalle Valo 	WMI_TAG_BATCH_SCAN_RESULT_EVENT,
1343d5c65159SKalle Valo 	WMI_TAG_VDEV_PLMREQ_START_CMD,
1344d5c65159SKalle Valo 	WMI_TAG_VDEV_PLMREQ_STOP_CMD,
1345d5c65159SKalle Valo 	WMI_TAG_THERMAL_MGMT_CMD,
1346d5c65159SKalle Valo 	WMI_TAG_THERMAL_MGMT_EVENT,
1347d5c65159SKalle Valo 	WMI_TAG_PEER_INFO_REQ_CMD,
1348d5c65159SKalle Valo 	WMI_TAG_PEER_INFO_EVENT,
1349d5c65159SKalle Valo 	WMI_TAG_PEER_INFO,
1350d5c65159SKalle Valo 	WMI_TAG_PEER_TX_FAIL_CNT_THR_EVENT,
1351d5c65159SKalle Valo 	WMI_TAG_RMC_SET_MODE_CMD,
1352d5c65159SKalle Valo 	WMI_TAG_RMC_SET_ACTION_PERIOD_CMD,
1353d5c65159SKalle Valo 	WMI_TAG_RMC_CONFIG_CMD,
1354d5c65159SKalle Valo 	WMI_TAG_MHF_OFFLOAD_SET_MODE_CMD,
1355d5c65159SKalle Valo 	WMI_TAG_MHF_OFFLOAD_PLUMB_ROUTING_TABLE_CMD,
1356d5c65159SKalle Valo 	WMI_TAG_ADD_PROACTIVE_ARP_RSP_PATTERN_CMD,
1357d5c65159SKalle Valo 	WMI_TAG_DEL_PROACTIVE_ARP_RSP_PATTERN_CMD,
1358d5c65159SKalle Valo 	WMI_TAG_NAN_CMD_PARAM,
1359d5c65159SKalle Valo 	WMI_TAG_NAN_EVENT_HDR,
1360d5c65159SKalle Valo 	WMI_TAG_PDEV_L1SS_TRACK_EVENT,
1361d5c65159SKalle Valo 	WMI_TAG_DIAG_DATA_CONTAINER_EVENT,
1362d5c65159SKalle Valo 	WMI_TAG_MODEM_POWER_STATE_CMD_PARAM,
1363d5c65159SKalle Valo 	WMI_TAG_PEER_GET_ESTIMATED_LINKSPEED_CMD,
1364d5c65159SKalle Valo 	WMI_TAG_PEER_ESTIMATED_LINKSPEED_EVENT,
1365d5c65159SKalle Valo 	WMI_TAG_AGGR_STATE_TRIG_EVENT,
1366d5c65159SKalle Valo 	WMI_TAG_MHF_OFFLOAD_ROUTING_TABLE_ENTRY,
1367d5c65159SKalle Valo 	WMI_TAG_ROAM_SCAN_CMD,
1368d5c65159SKalle Valo 	WMI_TAG_REQ_STATS_EXT_CMD,
1369d5c65159SKalle Valo 	WMI_TAG_STATS_EXT_EVENT,
1370d5c65159SKalle Valo 	WMI_TAG_OBSS_SCAN_ENABLE_CMD,
1371d5c65159SKalle Valo 	WMI_TAG_OBSS_SCAN_DISABLE_CMD,
1372d5c65159SKalle Valo 	WMI_TAG_OFFLOAD_PRB_RSP_TX_STATUS_EVENT,
1373d5c65159SKalle Valo 	WMI_TAG_PDEV_SET_LED_CONFIG_CMD,
1374d5c65159SKalle Valo 	WMI_TAG_HOST_AUTO_SHUTDOWN_CFG_CMD,
1375d5c65159SKalle Valo 	WMI_TAG_HOST_AUTO_SHUTDOWN_EVENT,
1376d5c65159SKalle Valo 	WMI_TAG_UPDATE_WHAL_MIB_STATS_EVENT,
1377d5c65159SKalle Valo 	WMI_TAG_CHAN_AVOID_UPDATE_CMD_PARAM,
1378d5c65159SKalle Valo 	WMI_TAG_WOW_IOAC_PKT_PATTERN_T,
1379d5c65159SKalle Valo 	WMI_TAG_WOW_IOAC_TMR_PATTERN_T,
1380d5c65159SKalle Valo 	WMI_TAG_WOW_IOAC_ADD_KEEPALIVE_CMD,
1381d5c65159SKalle Valo 	WMI_TAG_WOW_IOAC_DEL_KEEPALIVE_CMD,
1382d5c65159SKalle Valo 	WMI_TAG_WOW_IOAC_KEEPALIVE_T,
1383d5c65159SKalle Valo 	WMI_TAG_WOW_IOAC_ADD_PATTERN_CMD,
1384d5c65159SKalle Valo 	WMI_TAG_WOW_IOAC_DEL_PATTERN_CMD,
1385d5c65159SKalle Valo 	WMI_TAG_START_LINK_STATS_CMD,
1386d5c65159SKalle Valo 	WMI_TAG_CLEAR_LINK_STATS_CMD,
1387d5c65159SKalle Valo 	WMI_TAG_REQUEST_LINK_STATS_CMD,
1388d5c65159SKalle Valo 	WMI_TAG_IFACE_LINK_STATS_EVENT,
1389d5c65159SKalle Valo 	WMI_TAG_RADIO_LINK_STATS_EVENT,
1390d5c65159SKalle Valo 	WMI_TAG_PEER_STATS_EVENT,
1391d5c65159SKalle Valo 	WMI_TAG_CHANNEL_STATS,
1392d5c65159SKalle Valo 	WMI_TAG_RADIO_LINK_STATS,
1393d5c65159SKalle Valo 	WMI_TAG_RATE_STATS,
1394d5c65159SKalle Valo 	WMI_TAG_PEER_LINK_STATS,
1395d5c65159SKalle Valo 	WMI_TAG_WMM_AC_STATS,
1396d5c65159SKalle Valo 	WMI_TAG_IFACE_LINK_STATS,
1397d5c65159SKalle Valo 	WMI_TAG_LPI_MGMT_SNOOPING_CONFIG_CMD,
1398d5c65159SKalle Valo 	WMI_TAG_LPI_START_SCAN_CMD,
1399d5c65159SKalle Valo 	WMI_TAG_LPI_STOP_SCAN_CMD,
1400d5c65159SKalle Valo 	WMI_TAG_LPI_RESULT_EVENT,
1401d5c65159SKalle Valo 	WMI_TAG_PEER_STATE_EVENT,
1402d5c65159SKalle Valo 	WMI_TAG_EXTSCAN_BUCKET_CMD,
1403d5c65159SKalle Valo 	WMI_TAG_EXTSCAN_BUCKET_CHANNEL_EVENT,
1404d5c65159SKalle Valo 	WMI_TAG_EXTSCAN_START_CMD,
1405d5c65159SKalle Valo 	WMI_TAG_EXTSCAN_STOP_CMD,
1406d5c65159SKalle Valo 	WMI_TAG_EXTSCAN_CONFIGURE_WLAN_CHANGE_MONITOR_CMD,
1407d5c65159SKalle Valo 	WMI_TAG_EXTSCAN_WLAN_CHANGE_BSSID_PARAM_CMD,
1408d5c65159SKalle Valo 	WMI_TAG_EXTSCAN_CONFIGURE_HOTLIST_MONITOR_CMD,
1409d5c65159SKalle Valo 	WMI_TAG_EXTSCAN_GET_CACHED_RESULTS_CMD,
1410d5c65159SKalle Valo 	WMI_TAG_EXTSCAN_GET_WLAN_CHANGE_RESULTS_CMD,
1411d5c65159SKalle Valo 	WMI_TAG_EXTSCAN_SET_CAPABILITIES_CMD,
1412d5c65159SKalle Valo 	WMI_TAG_EXTSCAN_GET_CAPABILITIES_CMD,
1413d5c65159SKalle Valo 	WMI_TAG_EXTSCAN_OPERATION_EVENT,
1414d5c65159SKalle Valo 	WMI_TAG_EXTSCAN_START_STOP_EVENT,
1415d5c65159SKalle Valo 	WMI_TAG_EXTSCAN_TABLE_USAGE_EVENT,
1416d5c65159SKalle Valo 	WMI_TAG_EXTSCAN_WLAN_DESCRIPTOR_EVENT,
1417d5c65159SKalle Valo 	WMI_TAG_EXTSCAN_RSSI_INFO_EVENT,
1418d5c65159SKalle Valo 	WMI_TAG_EXTSCAN_CACHED_RESULTS_EVENT,
1419d5c65159SKalle Valo 	WMI_TAG_EXTSCAN_WLAN_CHANGE_RESULTS_EVENT,
1420d5c65159SKalle Valo 	WMI_TAG_EXTSCAN_WLAN_CHANGE_RESULT_BSSID_EVENT,
1421d5c65159SKalle Valo 	WMI_TAG_EXTSCAN_HOTLIST_MATCH_EVENT,
1422d5c65159SKalle Valo 	WMI_TAG_EXTSCAN_CAPABILITIES_EVENT,
1423d5c65159SKalle Valo 	WMI_TAG_EXTSCAN_CACHE_CAPABILITIES_EVENT,
1424d5c65159SKalle Valo 	WMI_TAG_EXTSCAN_WLAN_CHANGE_MONITOR_CAPABILITIES_EVENT,
1425d5c65159SKalle Valo 	WMI_TAG_EXTSCAN_HOTLIST_MONITOR_CAPABILITIES_EVENT,
1426d5c65159SKalle Valo 	WMI_TAG_D0_WOW_ENABLE_DISABLE_CMD,
1427d5c65159SKalle Valo 	WMI_TAG_D0_WOW_DISABLE_ACK_EVENT,
1428d5c65159SKalle Valo 	WMI_TAG_UNIT_TEST_CMD,
1429d5c65159SKalle Valo 	WMI_TAG_ROAM_OFFLOAD_TLV_PARAM,
1430d5c65159SKalle Valo 	WMI_TAG_ROAM_11I_OFFLOAD_TLV_PARAM,
1431d5c65159SKalle Valo 	WMI_TAG_ROAM_11R_OFFLOAD_TLV_PARAM,
1432d5c65159SKalle Valo 	WMI_TAG_ROAM_ESE_OFFLOAD_TLV_PARAM,
1433d5c65159SKalle Valo 	WMI_TAG_ROAM_SYNCH_EVENT,
1434d5c65159SKalle Valo 	WMI_TAG_ROAM_SYNCH_COMPLETE,
1435d5c65159SKalle Valo 	WMI_TAG_EXTWOW_ENABLE_CMD,
1436d5c65159SKalle Valo 	WMI_TAG_EXTWOW_SET_APP_TYPE1_PARAMS_CMD,
1437d5c65159SKalle Valo 	WMI_TAG_EXTWOW_SET_APP_TYPE2_PARAMS_CMD,
1438d5c65159SKalle Valo 	WMI_TAG_LPI_STATUS_EVENT,
1439d5c65159SKalle Valo 	WMI_TAG_LPI_HANDOFF_EVENT,
1440d5c65159SKalle Valo 	WMI_TAG_VDEV_RATE_STATS_EVENT,
1441d5c65159SKalle Valo 	WMI_TAG_VDEV_RATE_HT_INFO,
1442d5c65159SKalle Valo 	WMI_TAG_RIC_REQUEST,
1443d5c65159SKalle Valo 	WMI_TAG_PDEV_GET_TEMPERATURE_CMD,
1444d5c65159SKalle Valo 	WMI_TAG_PDEV_TEMPERATURE_EVENT,
1445d5c65159SKalle Valo 	WMI_TAG_SET_DHCP_SERVER_OFFLOAD_CMD,
1446d5c65159SKalle Valo 	WMI_TAG_TPC_CHAINMASK_CONFIG_CMD,
1447d5c65159SKalle Valo 	WMI_TAG_RIC_TSPEC,
1448d5c65159SKalle Valo 	WMI_TAG_TPC_CHAINMASK_CONFIG,
1449d5c65159SKalle Valo 	WMI_TAG_IPA_OFFLOAD_ENABLE_DISABLE_CMD,
1450d5c65159SKalle Valo 	WMI_TAG_SCAN_PROB_REQ_OUI_CMD,
1451d5c65159SKalle Valo 	WMI_TAG_KEY_MATERIAL,
1452d5c65159SKalle Valo 	WMI_TAG_TDLS_SET_OFFCHAN_MODE_CMD,
1453d5c65159SKalle Valo 	WMI_TAG_SET_LED_FLASHING_CMD,
1454d5c65159SKalle Valo 	WMI_TAG_MDNS_OFFLOAD_CMD,
1455d5c65159SKalle Valo 	WMI_TAG_MDNS_SET_FQDN_CMD,
1456d5c65159SKalle Valo 	WMI_TAG_MDNS_SET_RESP_CMD,
1457d5c65159SKalle Valo 	WMI_TAG_MDNS_GET_STATS_CMD,
1458d5c65159SKalle Valo 	WMI_TAG_MDNS_STATS_EVENT,
1459d5c65159SKalle Valo 	WMI_TAG_ROAM_INVOKE_CMD,
1460d5c65159SKalle Valo 	WMI_TAG_PDEV_RESUME_EVENT,
1461d5c65159SKalle Valo 	WMI_TAG_PDEV_SET_ANTENNA_DIVERSITY_CMD,
1462d5c65159SKalle Valo 	WMI_TAG_SAP_OFL_ENABLE_CMD,
1463d5c65159SKalle Valo 	WMI_TAG_SAP_OFL_ADD_STA_EVENT,
1464d5c65159SKalle Valo 	WMI_TAG_SAP_OFL_DEL_STA_EVENT,
1465d5c65159SKalle Valo 	WMI_TAG_APFIND_CMD_PARAM,
1466d5c65159SKalle Valo 	WMI_TAG_APFIND_EVENT_HDR,
1467d5c65159SKalle Valo 	WMI_TAG_OCB_SET_SCHED_CMD,
1468d5c65159SKalle Valo 	WMI_TAG_OCB_SET_SCHED_EVENT,
1469d5c65159SKalle Valo 	WMI_TAG_OCB_SET_CONFIG_CMD,
1470d5c65159SKalle Valo 	WMI_TAG_OCB_SET_CONFIG_RESP_EVENT,
1471d5c65159SKalle Valo 	WMI_TAG_OCB_SET_UTC_TIME_CMD,
1472d5c65159SKalle Valo 	WMI_TAG_OCB_START_TIMING_ADVERT_CMD,
1473d5c65159SKalle Valo 	WMI_TAG_OCB_STOP_TIMING_ADVERT_CMD,
1474d5c65159SKalle Valo 	WMI_TAG_OCB_GET_TSF_TIMER_CMD,
1475d5c65159SKalle Valo 	WMI_TAG_OCB_GET_TSF_TIMER_RESP_EVENT,
1476d5c65159SKalle Valo 	WMI_TAG_DCC_GET_STATS_CMD,
1477d5c65159SKalle Valo 	WMI_TAG_DCC_CHANNEL_STATS_REQUEST,
1478d5c65159SKalle Valo 	WMI_TAG_DCC_GET_STATS_RESP_EVENT,
1479d5c65159SKalle Valo 	WMI_TAG_DCC_CLEAR_STATS_CMD,
1480d5c65159SKalle Valo 	WMI_TAG_DCC_UPDATE_NDL_CMD,
1481d5c65159SKalle Valo 	WMI_TAG_DCC_UPDATE_NDL_RESP_EVENT,
1482d5c65159SKalle Valo 	WMI_TAG_DCC_STATS_EVENT,
1483d5c65159SKalle Valo 	WMI_TAG_OCB_CHANNEL,
1484d5c65159SKalle Valo 	WMI_TAG_OCB_SCHEDULE_ELEMENT,
1485d5c65159SKalle Valo 	WMI_TAG_DCC_NDL_STATS_PER_CHANNEL,
1486d5c65159SKalle Valo 	WMI_TAG_DCC_NDL_CHAN,
1487d5c65159SKalle Valo 	WMI_TAG_QOS_PARAMETER,
1488d5c65159SKalle Valo 	WMI_TAG_DCC_NDL_ACTIVE_STATE_CONFIG,
1489d5c65159SKalle Valo 	WMI_TAG_ROAM_SCAN_EXTENDED_THRESHOLD_PARAM,
1490d5c65159SKalle Valo 	WMI_TAG_ROAM_FILTER,
1491d5c65159SKalle Valo 	WMI_TAG_PASSPOINT_CONFIG_CMD,
1492d5c65159SKalle Valo 	WMI_TAG_PASSPOINT_EVENT_HDR,
1493d5c65159SKalle Valo 	WMI_TAG_EXTSCAN_CONFIGURE_HOTLIST_SSID_MONITOR_CMD,
1494d5c65159SKalle Valo 	WMI_TAG_EXTSCAN_HOTLIST_SSID_MATCH_EVENT,
1495d5c65159SKalle Valo 	WMI_TAG_VDEV_TSF_TSTAMP_ACTION_CMD,
1496d5c65159SKalle Valo 	WMI_TAG_VDEV_TSF_REPORT_EVENT,
1497d5c65159SKalle Valo 	WMI_TAG_GET_FW_MEM_DUMP,
1498d5c65159SKalle Valo 	WMI_TAG_UPDATE_FW_MEM_DUMP,
1499d5c65159SKalle Valo 	WMI_TAG_FW_MEM_DUMP_PARAMS,
1500d5c65159SKalle Valo 	WMI_TAG_DEBUG_MESG_FLUSH,
1501d5c65159SKalle Valo 	WMI_TAG_DEBUG_MESG_FLUSH_COMPLETE,
1502d5c65159SKalle Valo 	WMI_TAG_PEER_SET_RATE_REPORT_CONDITION,
1503d5c65159SKalle Valo 	WMI_TAG_ROAM_SUBNET_CHANGE_CONFIG,
1504d5c65159SKalle Valo 	WMI_TAG_VDEV_SET_IE_CMD,
1505d5c65159SKalle Valo 	WMI_TAG_RSSI_BREACH_MONITOR_CONFIG,
1506d5c65159SKalle Valo 	WMI_TAG_RSSI_BREACH_EVENT,
1507d5c65159SKalle Valo 	WMI_TAG_WOW_EVENT_INITIAL_WAKEUP,
1508d5c65159SKalle Valo 	WMI_TAG_SOC_SET_PCL_CMD,
1509d5c65159SKalle Valo 	WMI_TAG_SOC_SET_HW_MODE_CMD,
1510d5c65159SKalle Valo 	WMI_TAG_SOC_SET_HW_MODE_RESPONSE_EVENT,
1511d5c65159SKalle Valo 	WMI_TAG_SOC_HW_MODE_TRANSITION_EVENT,
1512d5c65159SKalle Valo 	WMI_TAG_VDEV_TXRX_STREAMS,
1513d5c65159SKalle Valo 	WMI_TAG_SOC_SET_HW_MODE_RESPONSE_VDEV_MAC_ENTRY,
1514d5c65159SKalle Valo 	WMI_TAG_SOC_SET_DUAL_MAC_CONFIG_CMD,
1515d5c65159SKalle Valo 	WMI_TAG_SOC_SET_DUAL_MAC_CONFIG_RESPONSE_EVENT,
1516d5c65159SKalle Valo 	WMI_TAG_WOW_IOAC_SOCK_PATTERN_T,
1517d5c65159SKalle Valo 	WMI_TAG_WOW_ENABLE_ICMPV6_NA_FLT_CMD,
1518d5c65159SKalle Valo 	WMI_TAG_DIAG_EVENT_LOG_CONFIG,
1519d5c65159SKalle Valo 	WMI_TAG_DIAG_EVENT_LOG_SUPPORTED_EVENT_FIXED_PARAMS,
1520d5c65159SKalle Valo 	WMI_TAG_PACKET_FILTER_CONFIG,
1521d5c65159SKalle Valo 	WMI_TAG_PACKET_FILTER_ENABLE,
1522d5c65159SKalle Valo 	WMI_TAG_SAP_SET_BLACKLIST_PARAM_CMD,
1523d5c65159SKalle Valo 	WMI_TAG_MGMT_TX_SEND_CMD,
1524d5c65159SKalle Valo 	WMI_TAG_MGMT_TX_COMPL_EVENT,
1525d5c65159SKalle Valo 	WMI_TAG_SOC_SET_ANTENNA_MODE_CMD,
1526d5c65159SKalle Valo 	WMI_TAG_WOW_UDP_SVC_OFLD_CMD,
1527d5c65159SKalle Valo 	WMI_TAG_LRO_INFO_CMD,
1528d5c65159SKalle Valo 	WMI_TAG_ROAM_EARLYSTOP_RSSI_THRES_PARAM,
1529d5c65159SKalle Valo 	WMI_TAG_SERVICE_READY_EXT_EVENT,
1530d5c65159SKalle Valo 	WMI_TAG_MAWC_SENSOR_REPORT_IND_CMD,
1531d5c65159SKalle Valo 	WMI_TAG_MAWC_ENABLE_SENSOR_EVENT,
1532d5c65159SKalle Valo 	WMI_TAG_ROAM_CONFIGURE_MAWC_CMD,
1533d5c65159SKalle Valo 	WMI_TAG_NLO_CONFIGURE_MAWC_CMD,
1534d5c65159SKalle Valo 	WMI_TAG_EXTSCAN_CONFIGURE_MAWC_CMD,
1535d5c65159SKalle Valo 	WMI_TAG_PEER_ASSOC_CONF_EVENT,
1536d5c65159SKalle Valo 	WMI_TAG_WOW_HOSTWAKEUP_GPIO_PIN_PATTERN_CONFIG_CMD,
1537d5c65159SKalle Valo 	WMI_TAG_AP_PS_EGAP_PARAM_CMD,
1538d5c65159SKalle Valo 	WMI_TAG_AP_PS_EGAP_INFO_EVENT,
1539d5c65159SKalle Valo 	WMI_TAG_PMF_OFFLOAD_SET_SA_QUERY_CMD,
1540d5c65159SKalle Valo 	WMI_TAG_TRANSFER_DATA_TO_FLASH_CMD,
1541d5c65159SKalle Valo 	WMI_TAG_TRANSFER_DATA_TO_FLASH_COMPLETE_EVENT,
1542d5c65159SKalle Valo 	WMI_TAG_SCPC_EVENT,
1543d5c65159SKalle Valo 	WMI_TAG_AP_PS_EGAP_INFO_CHAINMASK_LIST,
1544d5c65159SKalle Valo 	WMI_TAG_STA_SMPS_FORCE_MODE_COMPLETE_EVENT,
1545d5c65159SKalle Valo 	WMI_TAG_BPF_GET_CAPABILITY_CMD,
1546d5c65159SKalle Valo 	WMI_TAG_BPF_CAPABILITY_INFO_EVT,
1547d5c65159SKalle Valo 	WMI_TAG_BPF_GET_VDEV_STATS_CMD,
1548d5c65159SKalle Valo 	WMI_TAG_BPF_VDEV_STATS_INFO_EVT,
1549d5c65159SKalle Valo 	WMI_TAG_BPF_SET_VDEV_INSTRUCTIONS_CMD,
1550d5c65159SKalle Valo 	WMI_TAG_BPF_DEL_VDEV_INSTRUCTIONS_CMD,
1551d5c65159SKalle Valo 	WMI_TAG_VDEV_DELETE_RESP_EVENT,
1552d5c65159SKalle Valo 	WMI_TAG_PEER_DELETE_RESP_EVENT,
1553d5c65159SKalle Valo 	WMI_TAG_ROAM_DENSE_THRES_PARAM,
1554d5c65159SKalle Valo 	WMI_TAG_ENLO_CANDIDATE_SCORE_PARAM,
1555d5c65159SKalle Valo 	WMI_TAG_PEER_UPDATE_WDS_ENTRY_CMD,
1556d5c65159SKalle Valo 	WMI_TAG_VDEV_CONFIG_RATEMASK,
1557d5c65159SKalle Valo 	WMI_TAG_PDEV_FIPS_CMD,
1558d5c65159SKalle Valo 	WMI_TAG_PDEV_SMART_ANT_ENABLE_CMD,
1559d5c65159SKalle Valo 	WMI_TAG_PDEV_SMART_ANT_SET_RX_ANTENNA_CMD,
1560d5c65159SKalle Valo 	WMI_TAG_PEER_SMART_ANT_SET_TX_ANTENNA_CMD,
1561d5c65159SKalle Valo 	WMI_TAG_PEER_SMART_ANT_SET_TRAIN_ANTENNA_CMD,
1562d5c65159SKalle Valo 	WMI_TAG_PEER_SMART_ANT_SET_NODE_CONFIG_OPS_CMD,
1563d5c65159SKalle Valo 	WMI_TAG_PDEV_SET_ANT_SWITCH_TBL_CMD,
1564d5c65159SKalle Valo 	WMI_TAG_PDEV_SET_CTL_TABLE_CMD,
1565d5c65159SKalle Valo 	WMI_TAG_PDEV_SET_MIMOGAIN_TABLE_CMD,
1566d5c65159SKalle Valo 	WMI_TAG_FWTEST_SET_PARAM_CMD,
1567d5c65159SKalle Valo 	WMI_TAG_PEER_ATF_REQUEST,
1568d5c65159SKalle Valo 	WMI_TAG_VDEV_ATF_REQUEST,
1569d5c65159SKalle Valo 	WMI_TAG_PDEV_GET_ANI_CCK_CONFIG_CMD,
1570d5c65159SKalle Valo 	WMI_TAG_PDEV_GET_ANI_OFDM_CONFIG_CMD,
1571d5c65159SKalle Valo 	WMI_TAG_INST_RSSI_STATS_RESP,
1572d5c65159SKalle Valo 	WMI_TAG_MED_UTIL_REPORT_EVENT,
1573d5c65159SKalle Valo 	WMI_TAG_PEER_STA_PS_STATECHANGE_EVENT,
1574d5c65159SKalle Valo 	WMI_TAG_WDS_ADDR_EVENT,
1575d5c65159SKalle Valo 	WMI_TAG_PEER_RATECODE_LIST_EVENT,
1576d5c65159SKalle Valo 	WMI_TAG_PDEV_NFCAL_POWER_ALL_CHANNELS_EVENT,
1577d5c65159SKalle Valo 	WMI_TAG_PDEV_TPC_EVENT,
1578d5c65159SKalle Valo 	WMI_TAG_ANI_OFDM_EVENT,
1579d5c65159SKalle Valo 	WMI_TAG_ANI_CCK_EVENT,
1580d5c65159SKalle Valo 	WMI_TAG_PDEV_CHANNEL_HOPPING_EVENT,
1581d5c65159SKalle Valo 	WMI_TAG_PDEV_FIPS_EVENT,
1582d5c65159SKalle Valo 	WMI_TAG_ATF_PEER_INFO,
1583d5c65159SKalle Valo 	WMI_TAG_PDEV_GET_TPC_CMD,
1584d5c65159SKalle Valo 	WMI_TAG_VDEV_FILTER_NRP_CONFIG_CMD,
1585d5c65159SKalle Valo 	WMI_TAG_QBOOST_CFG_CMD,
1586d5c65159SKalle Valo 	WMI_TAG_PDEV_SMART_ANT_GPIO_HANDLE,
1587d5c65159SKalle Valo 	WMI_TAG_PEER_SMART_ANT_SET_TX_ANTENNA_SERIES,
1588d5c65159SKalle Valo 	WMI_TAG_PEER_SMART_ANT_SET_TRAIN_ANTENNA_PARAM,
1589d5c65159SKalle Valo 	WMI_TAG_PDEV_SET_ANT_CTRL_CHAIN,
1590d5c65159SKalle Valo 	WMI_TAG_PEER_CCK_OFDM_RATE_INFO,
1591d5c65159SKalle Valo 	WMI_TAG_PEER_MCS_RATE_INFO,
1592d5c65159SKalle Valo 	WMI_TAG_PDEV_NFCAL_POWER_ALL_CHANNELS_NFDBR,
1593d5c65159SKalle Valo 	WMI_TAG_PDEV_NFCAL_POWER_ALL_CHANNELS_NFDBM,
1594d5c65159SKalle Valo 	WMI_TAG_PDEV_NFCAL_POWER_ALL_CHANNELS_FREQNUM,
1595d5c65159SKalle Valo 	WMI_TAG_MU_REPORT_TOTAL_MU,
1596d5c65159SKalle Valo 	WMI_TAG_VDEV_SET_DSCP_TID_MAP_CMD,
1597d5c65159SKalle Valo 	WMI_TAG_ROAM_SET_MBO,
1598d5c65159SKalle Valo 	WMI_TAG_MIB_STATS_ENABLE_CMD,
1599d5c65159SKalle Valo 	WMI_TAG_NAN_DISC_IFACE_CREATED_EVENT,
1600d5c65159SKalle Valo 	WMI_TAG_NAN_DISC_IFACE_DELETED_EVENT,
1601d5c65159SKalle Valo 	WMI_TAG_NAN_STARTED_CLUSTER_EVENT,
1602d5c65159SKalle Valo 	WMI_TAG_NAN_JOINED_CLUSTER_EVENT,
1603d5c65159SKalle Valo 	WMI_TAG_NDI_GET_CAP_REQ,
1604d5c65159SKalle Valo 	WMI_TAG_NDP_INITIATOR_REQ,
1605d5c65159SKalle Valo 	WMI_TAG_NDP_RESPONDER_REQ,
1606d5c65159SKalle Valo 	WMI_TAG_NDP_END_REQ,
1607d5c65159SKalle Valo 	WMI_TAG_NDI_CAP_RSP_EVENT,
1608d5c65159SKalle Valo 	WMI_TAG_NDP_INITIATOR_RSP_EVENT,
1609d5c65159SKalle Valo 	WMI_TAG_NDP_RESPONDER_RSP_EVENT,
1610d5c65159SKalle Valo 	WMI_TAG_NDP_END_RSP_EVENT,
1611d5c65159SKalle Valo 	WMI_TAG_NDP_INDICATION_EVENT,
1612d5c65159SKalle Valo 	WMI_TAG_NDP_CONFIRM_EVENT,
1613d5c65159SKalle Valo 	WMI_TAG_NDP_END_INDICATION_EVENT,
1614d5c65159SKalle Valo 	WMI_TAG_VDEV_SET_QUIET_CMD,
1615d5c65159SKalle Valo 	WMI_TAG_PDEV_SET_PCL_CMD,
1616d5c65159SKalle Valo 	WMI_TAG_PDEV_SET_HW_MODE_CMD,
1617d5c65159SKalle Valo 	WMI_TAG_PDEV_SET_MAC_CONFIG_CMD,
1618d5c65159SKalle Valo 	WMI_TAG_PDEV_SET_ANTENNA_MODE_CMD,
1619d5c65159SKalle Valo 	WMI_TAG_PDEV_SET_HW_MODE_RESPONSE_EVENT,
1620d5c65159SKalle Valo 	WMI_TAG_PDEV_HW_MODE_TRANSITION_EVENT,
1621d5c65159SKalle Valo 	WMI_TAG_PDEV_SET_HW_MODE_RESPONSE_VDEV_MAC_ENTRY,
1622d5c65159SKalle Valo 	WMI_TAG_PDEV_SET_MAC_CONFIG_RESPONSE_EVENT,
1623d5c65159SKalle Valo 	WMI_TAG_COEX_CONFIG_CMD,
1624d5c65159SKalle Valo 	WMI_TAG_CONFIG_ENHANCED_MCAST_FILTER,
1625d5c65159SKalle Valo 	WMI_TAG_CHAN_AVOID_RPT_ALLOW_CMD,
1626d5c65159SKalle Valo 	WMI_TAG_SET_PERIODIC_CHANNEL_STATS_CONFIG,
1627d5c65159SKalle Valo 	WMI_TAG_VDEV_SET_CUSTOM_AGGR_SIZE_CMD,
1628d5c65159SKalle Valo 	WMI_TAG_PDEV_WAL_POWER_DEBUG_CMD,
1629d5c65159SKalle Valo 	WMI_TAG_MAC_PHY_CAPABILITIES,
1630d5c65159SKalle Valo 	WMI_TAG_HW_MODE_CAPABILITIES,
1631d5c65159SKalle Valo 	WMI_TAG_SOC_MAC_PHY_HW_MODE_CAPS,
1632d5c65159SKalle Valo 	WMI_TAG_HAL_REG_CAPABILITIES_EXT,
1633d5c65159SKalle Valo 	WMI_TAG_SOC_HAL_REG_CAPABILITIES,
1634d5c65159SKalle Valo 	WMI_TAG_VDEV_WISA_CMD,
1635d5c65159SKalle Valo 	WMI_TAG_TX_POWER_LEVEL_STATS_EVT,
1636d5c65159SKalle Valo 	WMI_TAG_SCAN_ADAPTIVE_DWELL_PARAMETERS_TLV,
1637d5c65159SKalle Valo 	WMI_TAG_SCAN_ADAPTIVE_DWELL_CONFIG,
1638d5c65159SKalle Valo 	WMI_TAG_WOW_SET_ACTION_WAKE_UP_CMD,
1639d5c65159SKalle Valo 	WMI_TAG_NDP_END_RSP_PER_NDI,
1640d5c65159SKalle Valo 	WMI_TAG_PEER_BWF_REQUEST,
1641d5c65159SKalle Valo 	WMI_TAG_BWF_PEER_INFO,
1642d5c65159SKalle Valo 	WMI_TAG_DBGLOG_TIME_STAMP_SYNC_CMD,
1643d5c65159SKalle Valo 	WMI_TAG_RMC_SET_LEADER_CMD,
1644d5c65159SKalle Valo 	WMI_TAG_RMC_MANUAL_LEADER_EVENT,
1645d5c65159SKalle Valo 	WMI_TAG_PER_CHAIN_RSSI_STATS,
1646d5c65159SKalle Valo 	WMI_TAG_RSSI_STATS,
1647d5c65159SKalle Valo 	WMI_TAG_P2P_LO_START_CMD,
1648d5c65159SKalle Valo 	WMI_TAG_P2P_LO_STOP_CMD,
1649d5c65159SKalle Valo 	WMI_TAG_P2P_LO_STOPPED_EVENT,
1650d5c65159SKalle Valo 	WMI_TAG_REORDER_QUEUE_SETUP_CMD,
1651d5c65159SKalle Valo 	WMI_TAG_REORDER_QUEUE_REMOVE_CMD,
1652d5c65159SKalle Valo 	WMI_TAG_SET_MULTIPLE_MCAST_FILTER_CMD,
1653d5c65159SKalle Valo 	WMI_TAG_MGMT_TX_COMPL_BUNDLE_EVENT,
1654d5c65159SKalle Valo 	WMI_TAG_READ_DATA_FROM_FLASH_CMD,
1655d5c65159SKalle Valo 	WMI_TAG_READ_DATA_FROM_FLASH_EVENT,
1656d5c65159SKalle Valo 	WMI_TAG_PDEV_SET_REORDER_TIMEOUT_VAL_CMD,
1657d5c65159SKalle Valo 	WMI_TAG_PEER_SET_RX_BLOCKSIZE_CMD,
1658d5c65159SKalle Valo 	WMI_TAG_PDEV_SET_WAKEUP_CONFIG_CMDID,
1659d5c65159SKalle Valo 	WMI_TAG_TLV_BUF_LEN_PARAM,
1660d5c65159SKalle Valo 	WMI_TAG_SERVICE_AVAILABLE_EVENT,
1661d5c65159SKalle Valo 	WMI_TAG_PEER_ANTDIV_INFO_REQ_CMD,
1662d5c65159SKalle Valo 	WMI_TAG_PEER_ANTDIV_INFO_EVENT,
1663d5c65159SKalle Valo 	WMI_TAG_PEER_ANTDIV_INFO,
1664d5c65159SKalle Valo 	WMI_TAG_PDEV_GET_ANTDIV_STATUS_CMD,
1665d5c65159SKalle Valo 	WMI_TAG_PDEV_ANTDIV_STATUS_EVENT,
1666d5c65159SKalle Valo 	WMI_TAG_MNT_FILTER_CMD,
1667d5c65159SKalle Valo 	WMI_TAG_GET_CHIP_POWER_STATS_CMD,
1668d5c65159SKalle Valo 	WMI_TAG_PDEV_CHIP_POWER_STATS_EVENT,
1669d5c65159SKalle Valo 	WMI_TAG_COEX_GET_ANTENNA_ISOLATION_CMD,
1670d5c65159SKalle Valo 	WMI_TAG_COEX_REPORT_ISOLATION_EVENT,
1671d5c65159SKalle Valo 	WMI_TAG_CHAN_CCA_STATS,
1672d5c65159SKalle Valo 	WMI_TAG_PEER_SIGNAL_STATS,
1673d5c65159SKalle Valo 	WMI_TAG_TX_STATS,
1674d5c65159SKalle Valo 	WMI_TAG_PEER_AC_TX_STATS,
1675d5c65159SKalle Valo 	WMI_TAG_RX_STATS,
1676d5c65159SKalle Valo 	WMI_TAG_PEER_AC_RX_STATS,
1677d5c65159SKalle Valo 	WMI_TAG_REPORT_STATS_EVENT,
1678d5c65159SKalle Valo 	WMI_TAG_CHAN_CCA_STATS_THRESH,
1679d5c65159SKalle Valo 	WMI_TAG_PEER_SIGNAL_STATS_THRESH,
1680d5c65159SKalle Valo 	WMI_TAG_TX_STATS_THRESH,
1681d5c65159SKalle Valo 	WMI_TAG_RX_STATS_THRESH,
1682d5c65159SKalle Valo 	WMI_TAG_PDEV_SET_STATS_THRESHOLD_CMD,
1683d5c65159SKalle Valo 	WMI_TAG_REQUEST_WLAN_STATS_CMD,
1684d5c65159SKalle Valo 	WMI_TAG_RX_AGGR_FAILURE_EVENT,
1685d5c65159SKalle Valo 	WMI_TAG_RX_AGGR_FAILURE_INFO,
1686d5c65159SKalle Valo 	WMI_TAG_VDEV_ENCRYPT_DECRYPT_DATA_REQ_CMD,
1687d5c65159SKalle Valo 	WMI_TAG_VDEV_ENCRYPT_DECRYPT_DATA_RESP_EVENT,
1688d5c65159SKalle Valo 	WMI_TAG_PDEV_BAND_TO_MAC,
1689d5c65159SKalle Valo 	WMI_TAG_TBTT_OFFSET_INFO,
1690d5c65159SKalle Valo 	WMI_TAG_TBTT_OFFSET_EXT_EVENT,
1691d5c65159SKalle Valo 	WMI_TAG_SAR_LIMITS_CMD,
1692d5c65159SKalle Valo 	WMI_TAG_SAR_LIMIT_CMD_ROW,
1693d5c65159SKalle Valo 	WMI_TAG_PDEV_DFS_PHYERR_OFFLOAD_ENABLE_CMD,
1694d5c65159SKalle Valo 	WMI_TAG_PDEV_DFS_PHYERR_OFFLOAD_DISABLE_CMD,
1695d5c65159SKalle Valo 	WMI_TAG_VDEV_ADFS_CH_CFG_CMD,
1696d5c65159SKalle Valo 	WMI_TAG_VDEV_ADFS_OCAC_ABORT_CMD,
1697d5c65159SKalle Valo 	WMI_TAG_PDEV_DFS_RADAR_DETECTION_EVENT,
1698d5c65159SKalle Valo 	WMI_TAG_VDEV_ADFS_OCAC_COMPLETE_EVENT,
1699d5c65159SKalle Valo 	WMI_TAG_VDEV_DFS_CAC_COMPLETE_EVENT,
1700d5c65159SKalle Valo 	WMI_TAG_VENDOR_OUI,
1701d5c65159SKalle Valo 	WMI_TAG_REQUEST_RCPI_CMD,
1702d5c65159SKalle Valo 	WMI_TAG_UPDATE_RCPI_EVENT,
1703d5c65159SKalle Valo 	WMI_TAG_REQUEST_PEER_STATS_INFO_CMD,
1704d5c65159SKalle Valo 	WMI_TAG_PEER_STATS_INFO,
1705d5c65159SKalle Valo 	WMI_TAG_PEER_STATS_INFO_EVENT,
1706d5c65159SKalle Valo 	WMI_TAG_PKGID_EVENT,
1707d5c65159SKalle Valo 	WMI_TAG_CONNECTED_NLO_RSSI_PARAMS,
1708d5c65159SKalle Valo 	WMI_TAG_SET_CURRENT_COUNTRY_CMD,
1709d5c65159SKalle Valo 	WMI_TAG_REGULATORY_RULE_STRUCT,
1710d5c65159SKalle Valo 	WMI_TAG_REG_CHAN_LIST_CC_EVENT,
1711d5c65159SKalle Valo 	WMI_TAG_11D_SCAN_START_CMD,
1712d5c65159SKalle Valo 	WMI_TAG_11D_SCAN_STOP_CMD,
1713d5c65159SKalle Valo 	WMI_TAG_11D_NEW_COUNTRY_EVENT,
1714d5c65159SKalle Valo 	WMI_TAG_REQUEST_RADIO_CHAN_STATS_CMD,
1715d5c65159SKalle Valo 	WMI_TAG_RADIO_CHAN_STATS,
1716d5c65159SKalle Valo 	WMI_TAG_RADIO_CHAN_STATS_EVENT,
1717d5c65159SKalle Valo 	WMI_TAG_ROAM_PER_CONFIG,
1718d5c65159SKalle Valo 	WMI_TAG_VDEV_ADD_MAC_ADDR_TO_RX_FILTER_CMD,
1719d5c65159SKalle Valo 	WMI_TAG_VDEV_ADD_MAC_ADDR_TO_RX_FILTER_STATUS_EVENT,
1720d5c65159SKalle Valo 	WMI_TAG_BPF_SET_VDEV_ACTIVE_MODE_CMD,
1721d5c65159SKalle Valo 	WMI_TAG_HW_DATA_FILTER_CMD,
1722d5c65159SKalle Valo 	WMI_TAG_CONNECTED_NLO_BSS_BAND_RSSI_PREF,
1723d5c65159SKalle Valo 	WMI_TAG_PEER_OPER_MODE_CHANGE_EVENT,
1724d5c65159SKalle Valo 	WMI_TAG_CHIP_POWER_SAVE_FAILURE_DETECTED,
1725d5c65159SKalle Valo 	WMI_TAG_PDEV_MULTIPLE_VDEV_RESTART_REQUEST_CMD,
1726d5c65159SKalle Valo 	WMI_TAG_PDEV_CSA_SWITCH_COUNT_STATUS_EVENT,
1727d5c65159SKalle Valo 	WMI_TAG_PDEV_UPDATE_PKT_ROUTING_CMD,
1728d5c65159SKalle Valo 	WMI_TAG_PDEV_CHECK_CAL_VERSION_CMD,
1729d5c65159SKalle Valo 	WMI_TAG_PDEV_CHECK_CAL_VERSION_EVENT,
1730d5c65159SKalle Valo 	WMI_TAG_PDEV_SET_DIVERSITY_GAIN_CMD,
1731d5c65159SKalle Valo 	WMI_TAG_MAC_PHY_CHAINMASK_COMBO,
1732d5c65159SKalle Valo 	WMI_TAG_MAC_PHY_CHAINMASK_CAPABILITY,
1733d5c65159SKalle Valo 	WMI_TAG_VDEV_SET_ARP_STATS_CMD,
1734d5c65159SKalle Valo 	WMI_TAG_VDEV_GET_ARP_STATS_CMD,
1735d5c65159SKalle Valo 	WMI_TAG_VDEV_GET_ARP_STATS_EVENT,
1736d5c65159SKalle Valo 	WMI_TAG_IFACE_OFFLOAD_STATS,
1737d5c65159SKalle Valo 	WMI_TAG_REQUEST_STATS_CMD_SUB_STRUCT_PARAM,
1738d5c65159SKalle Valo 	WMI_TAG_RSSI_CTL_EXT,
1739d5c65159SKalle Valo 	WMI_TAG_SINGLE_PHYERR_EXT_RX_HDR,
1740d5c65159SKalle Valo 	WMI_TAG_COEX_BT_ACTIVITY_EVENT,
1741d5c65159SKalle Valo 	WMI_TAG_VDEV_GET_TX_POWER_CMD,
1742d5c65159SKalle Valo 	WMI_TAG_VDEV_TX_POWER_EVENT,
1743d5c65159SKalle Valo 	WMI_TAG_OFFCHAN_DATA_TX_COMPL_EVENT,
1744d5c65159SKalle Valo 	WMI_TAG_OFFCHAN_DATA_TX_SEND_CMD,
1745d5c65159SKalle Valo 	WMI_TAG_TX_SEND_PARAMS,
1746d5c65159SKalle Valo 	WMI_TAG_HE_RATE_SET,
1747d5c65159SKalle Valo 	WMI_TAG_CONGESTION_STATS,
1748d5c65159SKalle Valo 	WMI_TAG_SET_INIT_COUNTRY_CMD,
1749d5c65159SKalle Valo 	WMI_TAG_SCAN_DBS_DUTY_CYCLE,
1750d5c65159SKalle Valo 	WMI_TAG_SCAN_DBS_DUTY_CYCLE_PARAM_TLV,
1751d5c65159SKalle Valo 	WMI_TAG_PDEV_DIV_GET_RSSI_ANTID,
1752d5c65159SKalle Valo 	WMI_TAG_THERM_THROT_CONFIG_REQUEST,
1753d5c65159SKalle Valo 	WMI_TAG_THERM_THROT_LEVEL_CONFIG_INFO,
1754d5c65159SKalle Valo 	WMI_TAG_THERM_THROT_STATS_EVENT,
1755d5c65159SKalle Valo 	WMI_TAG_THERM_THROT_LEVEL_STATS_INFO,
1756d5c65159SKalle Valo 	WMI_TAG_PDEV_DIV_RSSI_ANTID_EVENT,
1757d5c65159SKalle Valo 	WMI_TAG_OEM_DMA_RING_CAPABILITIES,
1758d5c65159SKalle Valo 	WMI_TAG_OEM_DMA_RING_CFG_REQ,
1759d5c65159SKalle Valo 	WMI_TAG_OEM_DMA_RING_CFG_RSP,
1760d5c65159SKalle Valo 	WMI_TAG_OEM_INDIRECT_DATA,
1761d5c65159SKalle Valo 	WMI_TAG_OEM_DMA_BUF_RELEASE,
1762d5c65159SKalle Valo 	WMI_TAG_OEM_DMA_BUF_RELEASE_ENTRY,
1763d5c65159SKalle Valo 	WMI_TAG_PDEV_BSS_CHAN_INFO_REQUEST,
1764d5c65159SKalle Valo 	WMI_TAG_PDEV_BSS_CHAN_INFO_EVENT,
1765d5c65159SKalle Valo 	WMI_TAG_ROAM_LCA_DISALLOW_CONFIG,
1766d5c65159SKalle Valo 	WMI_TAG_VDEV_LIMIT_OFFCHAN_CMD,
1767d5c65159SKalle Valo 	WMI_TAG_ROAM_RSSI_REJECTION_OCE_CONFIG,
1768d5c65159SKalle Valo 	WMI_TAG_UNIT_TEST_EVENT,
1769d5c65159SKalle Valo 	WMI_TAG_ROAM_FILS_OFFLOAD,
1770d5c65159SKalle Valo 	WMI_TAG_PDEV_UPDATE_PMK_CACHE_CMD,
1771d5c65159SKalle Valo 	WMI_TAG_PMK_CACHE,
1772d5c65159SKalle Valo 	WMI_TAG_PDEV_UPDATE_FILS_HLP_PKT_CMD,
1773d5c65159SKalle Valo 	WMI_TAG_ROAM_FILS_SYNCH,
1774d5c65159SKalle Valo 	WMI_TAG_GTK_OFFLOAD_EXTENDED,
1775d5c65159SKalle Valo 	WMI_TAG_ROAM_BG_SCAN_ROAMING,
1776d5c65159SKalle Valo 	WMI_TAG_OIC_PING_OFFLOAD_PARAMS_CMD,
1777d5c65159SKalle Valo 	WMI_TAG_OIC_PING_OFFLOAD_SET_ENABLE_CMD,
1778d5c65159SKalle Valo 	WMI_TAG_OIC_PING_HANDOFF_EVENT,
1779d5c65159SKalle Valo 	WMI_TAG_DHCP_LEASE_RENEW_OFFLOAD_CMD,
1780d5c65159SKalle Valo 	WMI_TAG_DHCP_LEASE_RENEW_EVENT,
1781d5c65159SKalle Valo 	WMI_TAG_BTM_CONFIG,
1782d5c65159SKalle Valo 	WMI_TAG_DEBUG_MESG_FW_DATA_STALL,
1783d5c65159SKalle Valo 	WMI_TAG_WLM_CONFIG_CMD,
1784d5c65159SKalle Valo 	WMI_TAG_PDEV_UPDATE_CTLTABLE_REQUEST,
1785d5c65159SKalle Valo 	WMI_TAG_PDEV_UPDATE_CTLTABLE_EVENT,
1786d5c65159SKalle Valo 	WMI_TAG_ROAM_CND_SCORING_PARAM,
1787d5c65159SKalle Valo 	WMI_TAG_PDEV_CONFIG_VENDOR_OUI_ACTION,
1788d5c65159SKalle Valo 	WMI_TAG_VENDOR_OUI_EXT,
1789d5c65159SKalle Valo 	WMI_TAG_ROAM_SYNCH_FRAME_EVENT,
1790d5c65159SKalle Valo 	WMI_TAG_FD_SEND_FROM_HOST_CMD,
1791d5c65159SKalle Valo 	WMI_TAG_ENABLE_FILS_CMD,
1792d5c65159SKalle Valo 	WMI_TAG_HOST_SWFDA_EVENT,
1793d5c65159SKalle Valo 	WMI_TAG_BCN_OFFLOAD_CTRL_CMD,
1794d5c65159SKalle Valo 	WMI_TAG_PDEV_SET_AC_TX_QUEUE_OPTIMIZED_CMD,
1795d5c65159SKalle Valo 	WMI_TAG_STATS_PERIOD,
1796d5c65159SKalle Valo 	WMI_TAG_NDL_SCHEDULE_UPDATE,
1797d5c65159SKalle Valo 	WMI_TAG_PEER_TID_MSDUQ_QDEPTH_THRESH_UPDATE_CMD,
1798d5c65159SKalle Valo 	WMI_TAG_MSDUQ_QDEPTH_THRESH_UPDATE,
1799d5c65159SKalle Valo 	WMI_TAG_PDEV_SET_RX_FILTER_PROMISCUOUS_CMD,
1800d5c65159SKalle Valo 	WMI_TAG_SAR2_RESULT_EVENT,
1801d5c65159SKalle Valo 	WMI_TAG_SAR_CAPABILITIES,
1802d5c65159SKalle Valo 	WMI_TAG_SAP_OBSS_DETECTION_CFG_CMD,
1803d5c65159SKalle Valo 	WMI_TAG_SAP_OBSS_DETECTION_INFO_EVT,
1804d5c65159SKalle Valo 	WMI_TAG_DMA_RING_CAPABILITIES,
1805d5c65159SKalle Valo 	WMI_TAG_DMA_RING_CFG_REQ,
1806d5c65159SKalle Valo 	WMI_TAG_DMA_RING_CFG_RSP,
1807d5c65159SKalle Valo 	WMI_TAG_DMA_BUF_RELEASE,
1808d5c65159SKalle Valo 	WMI_TAG_DMA_BUF_RELEASE_ENTRY,
1809d5c65159SKalle Valo 	WMI_TAG_SAR_GET_LIMITS_CMD,
1810d5c65159SKalle Valo 	WMI_TAG_SAR_GET_LIMITS_EVENT,
1811d5c65159SKalle Valo 	WMI_TAG_SAR_GET_LIMITS_EVENT_ROW,
1812d5c65159SKalle Valo 	WMI_TAG_OFFLOAD_11K_REPORT,
1813d5c65159SKalle Valo 	WMI_TAG_INVOKE_NEIGHBOR_REPORT,
1814d5c65159SKalle Valo 	WMI_TAG_NEIGHBOR_REPORT_OFFLOAD,
1815d5c65159SKalle Valo 	WMI_TAG_VDEV_SET_CONNECTIVITY_CHECK_STATS,
1816d5c65159SKalle Valo 	WMI_TAG_VDEV_GET_CONNECTIVITY_CHECK_STATS,
1817d5c65159SKalle Valo 	WMI_TAG_BPF_SET_VDEV_ENABLE_CMD,
1818d5c65159SKalle Valo 	WMI_TAG_BPF_SET_VDEV_WORK_MEMORY_CMD,
1819d5c65159SKalle Valo 	WMI_TAG_BPF_GET_VDEV_WORK_MEMORY_CMD,
1820d5c65159SKalle Valo 	WMI_TAG_BPF_GET_VDEV_WORK_MEMORY_RESP_EVT,
1821d5c65159SKalle Valo 	WMI_TAG_PDEV_GET_NFCAL_POWER,
1822d5c65159SKalle Valo 	WMI_TAG_BSS_COLOR_CHANGE_ENABLE,
1823d5c65159SKalle Valo 	WMI_TAG_OBSS_COLOR_COLLISION_DET_CONFIG,
1824d5c65159SKalle Valo 	WMI_TAG_OBSS_COLOR_COLLISION_EVT,
1825d5c65159SKalle Valo 	WMI_TAG_RUNTIME_DPD_RECAL_CMD,
1826d5c65159SKalle Valo 	WMI_TAG_TWT_ENABLE_CMD,
1827d5c65159SKalle Valo 	WMI_TAG_TWT_DISABLE_CMD,
1828d5c65159SKalle Valo 	WMI_TAG_TWT_ADD_DIALOG_CMD,
1829d5c65159SKalle Valo 	WMI_TAG_TWT_DEL_DIALOG_CMD,
1830d5c65159SKalle Valo 	WMI_TAG_TWT_PAUSE_DIALOG_CMD,
1831d5c65159SKalle Valo 	WMI_TAG_TWT_RESUME_DIALOG_CMD,
1832d5c65159SKalle Valo 	WMI_TAG_TWT_ENABLE_COMPLETE_EVENT,
1833d5c65159SKalle Valo 	WMI_TAG_TWT_DISABLE_COMPLETE_EVENT,
1834d5c65159SKalle Valo 	WMI_TAG_TWT_ADD_DIALOG_COMPLETE_EVENT,
1835d5c65159SKalle Valo 	WMI_TAG_TWT_DEL_DIALOG_COMPLETE_EVENT,
1836d5c65159SKalle Valo 	WMI_TAG_TWT_PAUSE_DIALOG_COMPLETE_EVENT,
1837d5c65159SKalle Valo 	WMI_TAG_TWT_RESUME_DIALOG_COMPLETE_EVENT,
1838d5c65159SKalle Valo 	WMI_TAG_REQUEST_ROAM_SCAN_STATS_CMD,
1839d5c65159SKalle Valo 	WMI_TAG_ROAM_SCAN_STATS_EVENT,
1840d5c65159SKalle Valo 	WMI_TAG_PEER_TID_CONFIGURATIONS_CMD,
1841d5c65159SKalle Valo 	WMI_TAG_VDEV_SET_CUSTOM_SW_RETRY_TH_CMD,
1842d5c65159SKalle Valo 	WMI_TAG_GET_TPC_POWER_CMD,
1843d5c65159SKalle Valo 	WMI_TAG_GET_TPC_POWER_EVENT,
1844d5c65159SKalle Valo 	WMI_TAG_DMA_BUF_RELEASE_SPECTRAL_META_DATA,
1845d5c65159SKalle Valo 	WMI_TAG_MOTION_DET_CONFIG_PARAMS_CMD,
1846d5c65159SKalle Valo 	WMI_TAG_MOTION_DET_BASE_LINE_CONFIG_PARAMS_CMD,
1847d5c65159SKalle Valo 	WMI_TAG_MOTION_DET_START_STOP_CMD,
1848d5c65159SKalle Valo 	WMI_TAG_MOTION_DET_BASE_LINE_START_STOP_CMD,
1849d5c65159SKalle Valo 	WMI_TAG_MOTION_DET_EVENT,
1850d5c65159SKalle Valo 	WMI_TAG_MOTION_DET_BASE_LINE_EVENT,
1851d5c65159SKalle Valo 	WMI_TAG_NDP_TRANSPORT_IP,
1852d5c65159SKalle Valo 	WMI_TAG_OBSS_SPATIAL_REUSE_SET_CMD,
1853d5c65159SKalle Valo 	WMI_TAG_ESP_ESTIMATE_EVENT,
1854d5c65159SKalle Valo 	WMI_TAG_NAN_HOST_CONFIG,
1855d5c65159SKalle Valo 	WMI_TAG_SPECTRAL_BIN_SCALING_PARAMS,
1856d5c65159SKalle Valo 	WMI_TAG_PEER_CFR_CAPTURE_CMD,
1857d5c65159SKalle Valo 	WMI_TAG_PEER_CHAN_WIDTH_SWITCH_CMD,
1858d5c65159SKalle Valo 	WMI_TAG_CHAN_WIDTH_PEER_LIST,
1859d5c65159SKalle Valo 	WMI_TAG_OBSS_SPATIAL_REUSE_SET_DEF_OBSS_THRESH_CMD,
1860d5c65159SKalle Valo 	WMI_TAG_PDEV_HE_TB_ACTION_FRM_CMD,
1861d5c65159SKalle Valo 	WMI_TAG_PEER_EXTD2_STATS,
1862d5c65159SKalle Valo 	WMI_TAG_HPCS_PULSE_START_CMD,
1863d5c65159SKalle Valo 	WMI_TAG_PDEV_CTL_FAILSAFE_CHECK_EVENT,
1864d5c65159SKalle Valo 	WMI_TAG_VDEV_CHAINMASK_CONFIG_CMD,
1865d5c65159SKalle Valo 	WMI_TAG_VDEV_BCN_OFFLOAD_QUIET_CONFIG_CMD,
1866d5c65159SKalle Valo 	WMI_TAG_NAN_EVENT_INFO,
1867d5c65159SKalle Valo 	WMI_TAG_NDP_CHANNEL_INFO,
1868d5c65159SKalle Valo 	WMI_TAG_NDP_CMD,
1869d5c65159SKalle Valo 	WMI_TAG_NDP_EVENT,
1870d5c65159SKalle Valo 	WMI_TAG_PDEV_PEER_PKTLOG_FILTER_CMD = 0x301,
1871d5c65159SKalle Valo 	WMI_TAG_PDEV_PEER_PKTLOG_FILTER_INFO,
1872047679e3SAloka Dixit 	WMI_TAG_FILS_DISCOVERY_TMPL_CMD = 0x344,
1873b56b08aeSRajkumar Manoharan 	WMI_TAG_PDEV_SRG_BSS_COLOR_BITMAP_CMD = 0x37b,
1874b56b08aeSRajkumar Manoharan 	WMI_TAG_PDEV_SRG_PARTIAL_BSSID_BITMAP_CMD,
1875b56b08aeSRajkumar Manoharan 	WMI_TAG_PDEV_SRG_OBSS_COLOR_ENABLE_BITMAP_CMD = 0x381,
1876b56b08aeSRajkumar Manoharan 	WMI_TAG_PDEV_SRG_OBSS_BSSID_ENABLE_BITMAP_CMD,
1877b56b08aeSRajkumar Manoharan 	WMI_TAG_PDEV_NON_SRG_OBSS_COLOR_ENABLE_BITMAP_CMD,
1878b56b08aeSRajkumar Manoharan 	WMI_TAG_PDEV_NON_SRG_OBSS_BSSID_ENABLE_BITMAP_CMD,
187991fa00faSAditya Kumar Singh 	WMI_TAG_REGULATORY_RULE_EXT_STRUCT = 0x3A9,
188091fa00faSAditya Kumar Singh 	WMI_TAG_REG_CHAN_LIST_CC_EXT_EVENT,
1881652f69edSBaochen Qiang 	WMI_TAG_PDEV_SET_BIOS_SAR_TABLE_CMD = 0x3D8,
1882652f69edSBaochen Qiang 	WMI_TAG_PDEV_SET_BIOS_GEO_TABLE_CMD,
1883d5c65159SKalle Valo 	WMI_TAG_MAX
1884d5c65159SKalle Valo };
1885d5c65159SKalle Valo 
1886d5c65159SKalle Valo enum wmi_tlv_service {
1887d5c65159SKalle Valo 	WMI_TLV_SERVICE_BEACON_OFFLOAD = 0,
1888d5c65159SKalle Valo 	WMI_TLV_SERVICE_SCAN_OFFLOAD = 1,
1889d5c65159SKalle Valo 	WMI_TLV_SERVICE_ROAM_SCAN_OFFLOAD = 2,
1890d5c65159SKalle Valo 	WMI_TLV_SERVICE_BCN_MISS_OFFLOAD = 3,
1891d5c65159SKalle Valo 	WMI_TLV_SERVICE_STA_PWRSAVE = 4,
1892d5c65159SKalle Valo 	WMI_TLV_SERVICE_STA_ADVANCED_PWRSAVE = 5,
1893d5c65159SKalle Valo 	WMI_TLV_SERVICE_AP_UAPSD = 6,
1894d5c65159SKalle Valo 	WMI_TLV_SERVICE_AP_DFS = 7,
1895d5c65159SKalle Valo 	WMI_TLV_SERVICE_11AC = 8,
1896d5c65159SKalle Valo 	WMI_TLV_SERVICE_BLOCKACK = 9,
1897d5c65159SKalle Valo 	WMI_TLV_SERVICE_PHYERR = 10,
1898d5c65159SKalle Valo 	WMI_TLV_SERVICE_BCN_FILTER = 11,
1899d5c65159SKalle Valo 	WMI_TLV_SERVICE_RTT = 12,
1900d5c65159SKalle Valo 	WMI_TLV_SERVICE_WOW = 13,
1901d5c65159SKalle Valo 	WMI_TLV_SERVICE_RATECTRL_CACHE = 14,
1902d5c65159SKalle Valo 	WMI_TLV_SERVICE_IRAM_TIDS = 15,
1903d5c65159SKalle Valo 	WMI_TLV_SERVICE_ARPNS_OFFLOAD = 16,
1904d5c65159SKalle Valo 	WMI_TLV_SERVICE_NLO = 17,
1905d5c65159SKalle Valo 	WMI_TLV_SERVICE_GTK_OFFLOAD = 18,
1906d5c65159SKalle Valo 	WMI_TLV_SERVICE_SCAN_SCH = 19,
1907d5c65159SKalle Valo 	WMI_TLV_SERVICE_CSA_OFFLOAD = 20,
1908d5c65159SKalle Valo 	WMI_TLV_SERVICE_CHATTER = 21,
1909d5c65159SKalle Valo 	WMI_TLV_SERVICE_COEX_FREQAVOID = 22,
1910d5c65159SKalle Valo 	WMI_TLV_SERVICE_PACKET_POWER_SAVE = 23,
1911d5c65159SKalle Valo 	WMI_TLV_SERVICE_FORCE_FW_HANG = 24,
1912d5c65159SKalle Valo 	WMI_TLV_SERVICE_GPIO = 25,
1913d5c65159SKalle Valo 	WMI_TLV_SERVICE_STA_DTIM_PS_MODULATED_DTIM = 26,
1914d5c65159SKalle Valo 	WMI_STA_UAPSD_BASIC_AUTO_TRIG = 27,
1915d5c65159SKalle Valo 	WMI_STA_UAPSD_VAR_AUTO_TRIG = 28,
1916d5c65159SKalle Valo 	WMI_TLV_SERVICE_STA_KEEP_ALIVE = 29,
1917d5c65159SKalle Valo 	WMI_TLV_SERVICE_TX_ENCAP = 30,
1918d5c65159SKalle Valo 	WMI_TLV_SERVICE_AP_PS_DETECT_OUT_OF_SYNC = 31,
1919d5c65159SKalle Valo 	WMI_TLV_SERVICE_EARLY_RX = 32,
1920d5c65159SKalle Valo 	WMI_TLV_SERVICE_STA_SMPS = 33,
1921d5c65159SKalle Valo 	WMI_TLV_SERVICE_FWTEST = 34,
1922d5c65159SKalle Valo 	WMI_TLV_SERVICE_STA_WMMAC = 35,
1923d5c65159SKalle Valo 	WMI_TLV_SERVICE_TDLS = 36,
1924d5c65159SKalle Valo 	WMI_TLV_SERVICE_BURST = 37,
1925d5c65159SKalle Valo 	WMI_TLV_SERVICE_MCC_BCN_INTERVAL_CHANGE = 38,
1926d5c65159SKalle Valo 	WMI_TLV_SERVICE_ADAPTIVE_OCS = 39,
1927d5c65159SKalle Valo 	WMI_TLV_SERVICE_BA_SSN_SUPPORT = 40,
1928d5c65159SKalle Valo 	WMI_TLV_SERVICE_FILTER_IPSEC_NATKEEPALIVE = 41,
1929d5c65159SKalle Valo 	WMI_TLV_SERVICE_WLAN_HB = 42,
1930d5c65159SKalle Valo 	WMI_TLV_SERVICE_LTE_ANT_SHARE_SUPPORT = 43,
1931d5c65159SKalle Valo 	WMI_TLV_SERVICE_BATCH_SCAN = 44,
1932d5c65159SKalle Valo 	WMI_TLV_SERVICE_QPOWER = 45,
1933d5c65159SKalle Valo 	WMI_TLV_SERVICE_PLMREQ = 46,
1934d5c65159SKalle Valo 	WMI_TLV_SERVICE_THERMAL_MGMT = 47,
1935d5c65159SKalle Valo 	WMI_TLV_SERVICE_RMC = 48,
1936d5c65159SKalle Valo 	WMI_TLV_SERVICE_MHF_OFFLOAD = 49,
1937d5c65159SKalle Valo 	WMI_TLV_SERVICE_COEX_SAR = 50,
1938d5c65159SKalle Valo 	WMI_TLV_SERVICE_BCN_TXRATE_OVERRIDE = 51,
1939d5c65159SKalle Valo 	WMI_TLV_SERVICE_NAN = 52,
1940d5c65159SKalle Valo 	WMI_TLV_SERVICE_L1SS_STAT = 53,
1941d5c65159SKalle Valo 	WMI_TLV_SERVICE_ESTIMATE_LINKSPEED = 54,
1942d5c65159SKalle Valo 	WMI_TLV_SERVICE_OBSS_SCAN = 55,
1943d5c65159SKalle Valo 	WMI_TLV_SERVICE_TDLS_OFFCHAN = 56,
1944d5c65159SKalle Valo 	WMI_TLV_SERVICE_TDLS_UAPSD_BUFFER_STA = 57,
1945d5c65159SKalle Valo 	WMI_TLV_SERVICE_TDLS_UAPSD_SLEEP_STA = 58,
1946d5c65159SKalle Valo 	WMI_TLV_SERVICE_IBSS_PWRSAVE = 59,
1947d5c65159SKalle Valo 	WMI_TLV_SERVICE_LPASS = 60,
1948d5c65159SKalle Valo 	WMI_TLV_SERVICE_EXTSCAN = 61,
1949d5c65159SKalle Valo 	WMI_TLV_SERVICE_D0WOW = 62,
1950d5c65159SKalle Valo 	WMI_TLV_SERVICE_HSOFFLOAD = 63,
1951d5c65159SKalle Valo 	WMI_TLV_SERVICE_ROAM_HO_OFFLOAD = 64,
1952d5c65159SKalle Valo 	WMI_TLV_SERVICE_RX_FULL_REORDER = 65,
1953d5c65159SKalle Valo 	WMI_TLV_SERVICE_DHCP_OFFLOAD = 66,
1954d5c65159SKalle Valo 	WMI_TLV_SERVICE_STA_RX_IPA_OFFLOAD_SUPPORT = 67,
1955d5c65159SKalle Valo 	WMI_TLV_SERVICE_MDNS_OFFLOAD = 68,
1956d5c65159SKalle Valo 	WMI_TLV_SERVICE_SAP_AUTH_OFFLOAD = 69,
1957d5c65159SKalle Valo 	WMI_TLV_SERVICE_DUAL_BAND_SIMULTANEOUS_SUPPORT = 70,
1958d5c65159SKalle Valo 	WMI_TLV_SERVICE_OCB = 71,
1959d5c65159SKalle Valo 	WMI_TLV_SERVICE_AP_ARPNS_OFFLOAD = 72,
1960d5c65159SKalle Valo 	WMI_TLV_SERVICE_PER_BAND_CHAINMASK_SUPPORT = 73,
1961d5c65159SKalle Valo 	WMI_TLV_SERVICE_PACKET_FILTER_OFFLOAD = 74,
1962d5c65159SKalle Valo 	WMI_TLV_SERVICE_MGMT_TX_HTT = 75,
1963d5c65159SKalle Valo 	WMI_TLV_SERVICE_MGMT_TX_WMI = 76,
1964d5c65159SKalle Valo 	WMI_TLV_SERVICE_EXT_MSG = 77,
1965d5c65159SKalle Valo 	WMI_TLV_SERVICE_MAWC = 78,
1966d5c65159SKalle Valo 	WMI_TLV_SERVICE_PEER_ASSOC_CONF = 79,
1967d5c65159SKalle Valo 	WMI_TLV_SERVICE_EGAP = 80,
1968d5c65159SKalle Valo 	WMI_TLV_SERVICE_STA_PMF_OFFLOAD = 81,
1969d5c65159SKalle Valo 	WMI_TLV_SERVICE_UNIFIED_WOW_CAPABILITY = 82,
1970d5c65159SKalle Valo 	WMI_TLV_SERVICE_ENHANCED_PROXY_STA = 83,
1971d5c65159SKalle Valo 	WMI_TLV_SERVICE_ATF = 84,
1972d5c65159SKalle Valo 	WMI_TLV_SERVICE_COEX_GPIO = 85,
1973d5c65159SKalle Valo 	WMI_TLV_SERVICE_AUX_SPECTRAL_INTF = 86,
1974d5c65159SKalle Valo 	WMI_TLV_SERVICE_AUX_CHAN_LOAD_INTF = 87,
1975d5c65159SKalle Valo 	WMI_TLV_SERVICE_BSS_CHANNEL_INFO_64 = 88,
1976d5c65159SKalle Valo 	WMI_TLV_SERVICE_ENTERPRISE_MESH = 89,
1977d5c65159SKalle Valo 	WMI_TLV_SERVICE_RESTRT_CHNL_SUPPORT = 90,
1978d5c65159SKalle Valo 	WMI_TLV_SERVICE_BPF_OFFLOAD = 91,
1979d5c65159SKalle Valo 	WMI_TLV_SERVICE_SYNC_DELETE_CMDS = 92,
1980d5c65159SKalle Valo 	WMI_TLV_SERVICE_SMART_ANTENNA_SW_SUPPORT = 93,
1981d5c65159SKalle Valo 	WMI_TLV_SERVICE_SMART_ANTENNA_HW_SUPPORT = 94,
1982d5c65159SKalle Valo 	WMI_TLV_SERVICE_RATECTRL_LIMIT_MAX_MIN_RATES = 95,
1983d5c65159SKalle Valo 	WMI_TLV_SERVICE_NAN_DATA = 96,
1984d5c65159SKalle Valo 	WMI_TLV_SERVICE_NAN_RTT = 97,
1985d5c65159SKalle Valo 	WMI_TLV_SERVICE_11AX = 98,
1986d5c65159SKalle Valo 	WMI_TLV_SERVICE_DEPRECATED_REPLACE = 99,
1987d5c65159SKalle Valo 	WMI_TLV_SERVICE_TDLS_CONN_TRACKER_IN_HOST_MODE = 100,
1988d5c65159SKalle Valo 	WMI_TLV_SERVICE_ENHANCED_MCAST_FILTER = 101,
1989d5c65159SKalle Valo 	WMI_TLV_SERVICE_PERIODIC_CHAN_STAT_SUPPORT = 102,
1990d5c65159SKalle Valo 	WMI_TLV_SERVICE_MESH_11S = 103,
1991d5c65159SKalle Valo 	WMI_TLV_SERVICE_HALF_RATE_QUARTER_RATE_SUPPORT = 104,
1992d5c65159SKalle Valo 	WMI_TLV_SERVICE_VDEV_RX_FILTER = 105,
1993d5c65159SKalle Valo 	WMI_TLV_SERVICE_P2P_LISTEN_OFFLOAD_SUPPORT = 106,
1994d5c65159SKalle Valo 	WMI_TLV_SERVICE_MARK_FIRST_WAKEUP_PACKET = 107,
1995d5c65159SKalle Valo 	WMI_TLV_SERVICE_MULTIPLE_MCAST_FILTER_SET = 108,
1996d5c65159SKalle Valo 	WMI_TLV_SERVICE_HOST_MANAGED_RX_REORDER = 109,
1997d5c65159SKalle Valo 	WMI_TLV_SERVICE_FLASH_RDWR_SUPPORT = 110,
1998d5c65159SKalle Valo 	WMI_TLV_SERVICE_WLAN_STATS_REPORT = 111,
1999d5c65159SKalle Valo 	WMI_TLV_SERVICE_TX_MSDU_ID_NEW_PARTITION_SUPPORT = 112,
2000d5c65159SKalle Valo 	WMI_TLV_SERVICE_DFS_PHYERR_OFFLOAD = 113,
2001d5c65159SKalle Valo 	WMI_TLV_SERVICE_RCPI_SUPPORT = 114,
2002d5c65159SKalle Valo 	WMI_TLV_SERVICE_FW_MEM_DUMP_SUPPORT = 115,
2003d5c65159SKalle Valo 	WMI_TLV_SERVICE_PEER_STATS_INFO = 116,
2004d5c65159SKalle Valo 	WMI_TLV_SERVICE_REGULATORY_DB = 117,
2005d5c65159SKalle Valo 	WMI_TLV_SERVICE_11D_OFFLOAD = 118,
2006d5c65159SKalle Valo 	WMI_TLV_SERVICE_HW_DATA_FILTERING = 119,
2007d5c65159SKalle Valo 	WMI_TLV_SERVICE_MULTIPLE_VDEV_RESTART = 120,
2008d5c65159SKalle Valo 	WMI_TLV_SERVICE_PKT_ROUTING = 121,
2009d5c65159SKalle Valo 	WMI_TLV_SERVICE_CHECK_CAL_VERSION = 122,
2010d5c65159SKalle Valo 	WMI_TLV_SERVICE_OFFCHAN_TX_WMI = 123,
2011d5c65159SKalle Valo 	WMI_TLV_SERVICE_8SS_TX_BFEE  =  124,
2012d5c65159SKalle Valo 	WMI_TLV_SERVICE_EXTENDED_NSS_SUPPORT = 125,
2013d5c65159SKalle Valo 	WMI_TLV_SERVICE_ACK_TIMEOUT = 126,
2014d5c65159SKalle Valo 	WMI_TLV_SERVICE_PDEV_BSS_CHANNEL_INFO_64 = 127,
2015d5c65159SKalle Valo 
2016e2e23a79SWen Gong 	/* The first 128 bits */
2017d5c65159SKalle Valo 	WMI_MAX_SERVICE = 128,
2018d5c65159SKalle Valo 
2019d5c65159SKalle Valo 	WMI_TLV_SERVICE_CHAN_LOAD_INFO = 128,
2020d5c65159SKalle Valo 	WMI_TLV_SERVICE_TX_PPDU_INFO_STATS_SUPPORT = 129,
2021d5c65159SKalle Valo 	WMI_TLV_SERVICE_VDEV_LIMIT_OFFCHAN_SUPPORT = 130,
2022d5c65159SKalle Valo 	WMI_TLV_SERVICE_FILS_SUPPORT = 131,
2023d5c65159SKalle Valo 	WMI_TLV_SERVICE_WLAN_OIC_PING_OFFLOAD = 132,
2024d5c65159SKalle Valo 	WMI_TLV_SERVICE_WLAN_DHCP_RENEW = 133,
2025d5c65159SKalle Valo 	WMI_TLV_SERVICE_MAWC_SUPPORT = 134,
2026d5c65159SKalle Valo 	WMI_TLV_SERVICE_VDEV_LATENCY_CONFIG = 135,
2027d5c65159SKalle Valo 	WMI_TLV_SERVICE_PDEV_UPDATE_CTLTABLE_SUPPORT = 136,
2028d5c65159SKalle Valo 	WMI_TLV_SERVICE_PKTLOG_SUPPORT_OVER_HTT = 137,
2029d5c65159SKalle Valo 	WMI_TLV_SERVICE_VDEV_MULTI_GROUP_KEY_SUPPORT = 138,
2030d5c65159SKalle Valo 	WMI_TLV_SERVICE_SCAN_PHYMODE_SUPPORT = 139,
2031d5c65159SKalle Valo 	WMI_TLV_SERVICE_THERM_THROT = 140,
2032d5c65159SKalle Valo 	WMI_TLV_SERVICE_BCN_OFFLOAD_START_STOP_SUPPORT = 141,
2033d5c65159SKalle Valo 	WMI_TLV_SERVICE_WOW_WAKEUP_BY_TIMER_PATTERN = 142,
2034d5c65159SKalle Valo 	WMI_TLV_SERVICE_PEER_MAP_UNMAP_V2_SUPPORT = 143,
2035d5c65159SKalle Valo 	WMI_TLV_SERVICE_OFFCHAN_DATA_TID_SUPPORT = 144,
2036d5c65159SKalle Valo 	WMI_TLV_SERVICE_RX_PROMISC_ENABLE_SUPPORT = 145,
2037d5c65159SKalle Valo 	WMI_TLV_SERVICE_SUPPORT_DIRECT_DMA = 146,
2038d5c65159SKalle Valo 	WMI_TLV_SERVICE_AP_OBSS_DETECTION_OFFLOAD = 147,
2039d5c65159SKalle Valo 	WMI_TLV_SERVICE_11K_NEIGHBOUR_REPORT_SUPPORT = 148,
2040d5c65159SKalle Valo 	WMI_TLV_SERVICE_LISTEN_INTERVAL_OFFLOAD_SUPPORT = 149,
2041d5c65159SKalle Valo 	WMI_TLV_SERVICE_BSS_COLOR_OFFLOAD = 150,
2042d5c65159SKalle Valo 	WMI_TLV_SERVICE_RUNTIME_DPD_RECAL = 151,
2043d5c65159SKalle Valo 	WMI_TLV_SERVICE_STA_TWT = 152,
2044d5c65159SKalle Valo 	WMI_TLV_SERVICE_AP_TWT = 153,
2045d5c65159SKalle Valo 	WMI_TLV_SERVICE_GMAC_OFFLOAD_SUPPORT = 154,
2046d5c65159SKalle Valo 	WMI_TLV_SERVICE_SPOOF_MAC_SUPPORT = 155,
2047d5c65159SKalle Valo 	WMI_TLV_SERVICE_PEER_TID_CONFIGS_SUPPORT = 156,
2048d5c65159SKalle Valo 	WMI_TLV_SERVICE_VDEV_SWRETRY_PER_AC_CONFIG_SUPPORT = 157,
2049d5c65159SKalle Valo 	WMI_TLV_SERVICE_DUAL_BEACON_ON_SINGLE_MAC_SCC_SUPPORT = 158,
2050d5c65159SKalle Valo 	WMI_TLV_SERVICE_DUAL_BEACON_ON_SINGLE_MAC_MCC_SUPPORT = 159,
2051d5c65159SKalle Valo 	WMI_TLV_SERVICE_MOTION_DET = 160,
2052d5c65159SKalle Valo 	WMI_TLV_SERVICE_INFRA_MBSSID = 161,
2053d5c65159SKalle Valo 	WMI_TLV_SERVICE_OBSS_SPATIAL_REUSE = 162,
2054d5c65159SKalle Valo 	WMI_TLV_SERVICE_VDEV_DIFFERENT_BEACON_INTERVAL_SUPPORT = 163,
2055d5c65159SKalle Valo 	WMI_TLV_SERVICE_NAN_DBS_SUPPORT = 164,
2056d5c65159SKalle Valo 	WMI_TLV_SERVICE_NDI_DBS_SUPPORT = 165,
2057d5c65159SKalle Valo 	WMI_TLV_SERVICE_NAN_SAP_SUPPORT = 166,
2058d5c65159SKalle Valo 	WMI_TLV_SERVICE_NDI_SAP_SUPPORT = 167,
2059d5c65159SKalle Valo 	WMI_TLV_SERVICE_CFR_CAPTURE_SUPPORT = 168,
2060d5c65159SKalle Valo 	WMI_TLV_SERVICE_CFR_CAPTURE_IND_MSG_TYPE_1 = 169,
2061d5c65159SKalle Valo 	WMI_TLV_SERVICE_ESP_SUPPORT = 170,
2062d5c65159SKalle Valo 	WMI_TLV_SERVICE_PEER_CHWIDTH_CHANGE = 171,
2063d5c65159SKalle Valo 	WMI_TLV_SERVICE_WLAN_HPCS_PULSE = 172,
2064d5c65159SKalle Valo 	WMI_TLV_SERVICE_PER_VDEV_CHAINMASK_CONFIG_SUPPORT = 173,
2065d5c65159SKalle Valo 	WMI_TLV_SERVICE_TX_DATA_MGMT_ACK_RSSI = 174,
2066d5c65159SKalle Valo 	WMI_TLV_SERVICE_NAN_DISABLE_SUPPORT = 175,
2067d5c65159SKalle Valo 	WMI_TLV_SERVICE_HTT_H2T_NO_HTC_HDR_LEN_IN_MSG_LEN = 176,
2068559ef68fSAshok Raj Nagarajan 	WMI_TLV_SERVICE_COEX_SUPPORT_UNEQUAL_ISOLATION = 177,
2069559ef68fSAshok Raj Nagarajan 	WMI_TLV_SERVICE_HW_DB2DBM_CONVERSION_SUPPORT = 178,
2070559ef68fSAshok Raj Nagarajan 	WMI_TLV_SERVICE_SUPPORT_EXTEND_ADDRESS = 179,
2071559ef68fSAshok Raj Nagarajan 	WMI_TLV_SERVICE_BEACON_RECEPTION_STATS = 180,
2072559ef68fSAshok Raj Nagarajan 	WMI_TLV_SERVICE_FETCH_TX_PN = 181,
2073559ef68fSAshok Raj Nagarajan 	WMI_TLV_SERVICE_PEER_UNMAP_RESPONSE_SUPPORT = 182,
2074559ef68fSAshok Raj Nagarajan 	WMI_TLV_SERVICE_TX_PER_PEER_AMPDU_SIZE = 183,
2075559ef68fSAshok Raj Nagarajan 	WMI_TLV_SERVICE_BSS_COLOR_SWITCH_COUNT = 184,
2076559ef68fSAshok Raj Nagarajan 	WMI_TLV_SERVICE_HTT_PEER_STATS_SUPPORT = 185,
2077559ef68fSAshok Raj Nagarajan 	WMI_TLV_SERVICE_UL_RU26_ALLOWED = 186,
2078559ef68fSAshok Raj Nagarajan 	WMI_TLV_SERVICE_GET_MWS_COEX_STATE = 187,
2079559ef68fSAshok Raj Nagarajan 	WMI_TLV_SERVICE_GET_MWS_DPWB_STATE = 188,
2080559ef68fSAshok Raj Nagarajan 	WMI_TLV_SERVICE_GET_MWS_TDM_STATE = 189,
2081559ef68fSAshok Raj Nagarajan 	WMI_TLV_SERVICE_GET_MWS_IDRX_STATE = 190,
2082559ef68fSAshok Raj Nagarajan 	WMI_TLV_SERVICE_GET_MWS_ANTENNA_SHARING_STATE = 191,
2083559ef68fSAshok Raj Nagarajan 	WMI_TLV_SERVICE_ENHANCED_TPC_CONFIG_EVENT = 192,
2084559ef68fSAshok Raj Nagarajan 	WMI_TLV_SERVICE_WLM_STATS_REQUEST = 193,
2085559ef68fSAshok Raj Nagarajan 	WMI_TLV_SERVICE_EXT_PEER_TID_CONFIGS_SUPPORT = 194,
2086559ef68fSAshok Raj Nagarajan 	WMI_TLV_SERVICE_WPA3_FT_SAE_SUPPORT = 195,
2087559ef68fSAshok Raj Nagarajan 	WMI_TLV_SERVICE_WPA3_FT_SUITE_B_SUPPORT = 196,
2088559ef68fSAshok Raj Nagarajan 	WMI_TLV_SERVICE_VOW_ENABLE = 197,
2089559ef68fSAshok Raj Nagarajan 	WMI_TLV_SERVICE_CFR_CAPTURE_IND_EVT_TYPE_1 = 198,
2090559ef68fSAshok Raj Nagarajan 	WMI_TLV_SERVICE_BROADCAST_TWT = 199,
2091559ef68fSAshok Raj Nagarajan 	WMI_TLV_SERVICE_RAP_DETECTION_SUPPORT = 200,
2092559ef68fSAshok Raj Nagarajan 	WMI_TLV_SERVICE_PS_TDCC = 201,
2093559ef68fSAshok Raj Nagarajan 	WMI_TLV_SERVICE_THREE_WAY_COEX_CONFIG_LEGACY   = 202,
2094559ef68fSAshok Raj Nagarajan 	WMI_TLV_SERVICE_THREE_WAY_COEX_CONFIG_OVERRIDE = 203,
2095559ef68fSAshok Raj Nagarajan 	WMI_TLV_SERVICE_TX_PWR_PER_PEER = 204,
2096559ef68fSAshok Raj Nagarajan 	WMI_TLV_SERVICE_STA_PLUS_STA_SUPPORT = 205,
2097559ef68fSAshok Raj Nagarajan 	WMI_TLV_SERVICE_WPA3_FT_FILS = 206,
2098559ef68fSAshok Raj Nagarajan 	WMI_TLV_SERVICE_ADAPTIVE_11R_ROAM = 207,
2099559ef68fSAshok Raj Nagarajan 	WMI_TLV_SERVICE_CHAN_RF_CHARACTERIZATION_INFO = 208,
2100559ef68fSAshok Raj Nagarajan 	WMI_TLV_SERVICE_FW_IFACE_COMBINATION_SUPPORT = 209,
2101559ef68fSAshok Raj Nagarajan 	WMI_TLV_SERVICE_TX_COMPL_TSF64 = 210,
2102559ef68fSAshok Raj Nagarajan 	WMI_TLV_SERVICE_DSM_ROAM_FILTER = 211,
2103559ef68fSAshok Raj Nagarajan 	WMI_TLV_SERVICE_PACKET_CAPTURE_SUPPORT = 212,
2104559ef68fSAshok Raj Nagarajan 	WMI_TLV_SERVICE_PER_PEER_HTT_STATS_RESET = 213,
21059d11b7bfSKarthikeyan Periyasamy 	WMI_TLV_SERVICE_FREQINFO_IN_METADATA = 219,
2106bd647855SKarthikeyan Periyasamy 	WMI_TLV_SERVICE_EXT2_MSG = 220,
2107710a95f9SVenkateswara Naralasetty 	WMI_TLV_SERVICE_PEER_POWER_SAVE_DURATION_SUPPORT = 246,
2108b56b08aeSRajkumar Manoharan 	WMI_TLV_SERVICE_SRG_SRP_SPATIAL_REUSE_SUPPORT = 249,
21095a81610aSAloka Dixit 	WMI_TLV_SERVICE_MBSS_PARAM_IN_VDEV_START_SUPPORT = 253,
2110cf8f3d4dSTamizh Chelvam Raja 	WMI_TLV_SERVICE_PASSIVE_SCAN_START_TIME_ENHANCE = 263,
2111d5c65159SKalle Valo 
2112e2e23a79SWen Gong 	/* The second 128 bits */
2113e2e23a79SWen Gong 	WMI_MAX_EXT_SERVICE = 256,
21148b4d2f08SManikanta Pubbisetty 	WMI_TLV_SERVICE_SCAN_CONFIG_PER_CHANNEL = 265,
211591fa00faSAditya Kumar Singh 	WMI_TLV_SERVICE_REG_CC_EXT_EVENT_SUPPORT = 281,
2116652f69edSBaochen Qiang 	WMI_TLV_SERVICE_BIOS_SAR_SUPPORT = 326,
2117e89a51aeSManikanta Pubbisetty 	WMI_TLV_SERVICE_SUPPORT_11D_FOR_HOST_SCAN = 357,
2118e2e23a79SWen Gong 
2119e2e23a79SWen Gong 	/* The third 128 bits */
2120e2e23a79SWen Gong 	WMI_MAX_EXT2_SERVICE = 384
2121d5c65159SKalle Valo };
2122d5c65159SKalle Valo 
2123d5c65159SKalle Valo enum {
2124d5c65159SKalle Valo 	WMI_SMPS_FORCED_MODE_NONE = 0,
2125d5c65159SKalle Valo 	WMI_SMPS_FORCED_MODE_DISABLED,
2126d5c65159SKalle Valo 	WMI_SMPS_FORCED_MODE_STATIC,
2127d5c65159SKalle Valo 	WMI_SMPS_FORCED_MODE_DYNAMIC
2128d5c65159SKalle Valo };
2129d5c65159SKalle Valo 
2130d5c65159SKalle Valo #define WMI_TPC_CHAINMASK_CONFIG_BAND_2G      0
2131d5c65159SKalle Valo #define WMI_TPC_CHAINMASK_CONFIG_BAND_5G      1
2132d5c65159SKalle Valo #define WMI_NUM_SUPPORTED_BAND_MAX 2
2133d5c65159SKalle Valo 
2134d5c65159SKalle Valo #define WMI_PEER_MIMO_PS_STATE                          0x1
2135d5c65159SKalle Valo #define WMI_PEER_AMPDU                                  0x2
2136d5c65159SKalle Valo #define WMI_PEER_AUTHORIZE                              0x3
2137d5c65159SKalle Valo #define WMI_PEER_CHWIDTH                                0x4
2138d5c65159SKalle Valo #define WMI_PEER_NSS                                    0x5
2139d5c65159SKalle Valo #define WMI_PEER_USE_4ADDR                              0x6
2140d5c65159SKalle Valo #define WMI_PEER_MEMBERSHIP                             0x7
2141d5c65159SKalle Valo #define WMI_PEER_USERPOS                                0x8
2142d5c65159SKalle Valo #define WMI_PEER_CRIT_PROTO_HINT_ENABLED                0x9
2143d5c65159SKalle Valo #define WMI_PEER_TX_FAIL_CNT_THR                        0xA
2144d5c65159SKalle Valo #define WMI_PEER_SET_HW_RETRY_CTS2S                     0xB
2145d5c65159SKalle Valo #define WMI_PEER_IBSS_ATIM_WINDOW_LENGTH                0xC
2146d5c65159SKalle Valo #define WMI_PEER_PHYMODE                                0xD
2147d5c65159SKalle Valo #define WMI_PEER_USE_FIXED_PWR                          0xE
2148d5c65159SKalle Valo #define WMI_PEER_PARAM_FIXED_RATE                       0xF
2149d5c65159SKalle Valo #define WMI_PEER_SET_MU_WHITELIST                       0x10
2150d5c65159SKalle Valo #define WMI_PEER_SET_MAX_TX_RATE                        0x11
2151d5c65159SKalle Valo #define WMI_PEER_SET_MIN_TX_RATE                        0x12
2152d5c65159SKalle Valo #define WMI_PEER_SET_DEFAULT_ROUTING                    0x13
2153d5c65159SKalle Valo 
2154d5c65159SKalle Valo /* slot time long */
2155d5c65159SKalle Valo #define WMI_VDEV_SLOT_TIME_LONG         0x1
2156d5c65159SKalle Valo /* slot time short */
2157d5c65159SKalle Valo #define WMI_VDEV_SLOT_TIME_SHORT        0x2
2158d5c65159SKalle Valo /* preablbe long */
2159d5c65159SKalle Valo #define WMI_VDEV_PREAMBLE_LONG          0x1
2160d5c65159SKalle Valo /* preablbe short */
2161d5c65159SKalle Valo #define WMI_VDEV_PREAMBLE_SHORT         0x2
2162d5c65159SKalle Valo 
2163d5c65159SKalle Valo enum wmi_peer_smps_state {
2164d5c65159SKalle Valo 	WMI_PEER_SMPS_PS_NONE = 0x0,
2165d5c65159SKalle Valo 	WMI_PEER_SMPS_STATIC  = 0x1,
2166d5c65159SKalle Valo 	WMI_PEER_SMPS_DYNAMIC = 0x2
2167d5c65159SKalle Valo };
2168d5c65159SKalle Valo 
2169d5c65159SKalle Valo enum wmi_peer_chwidth {
2170d5c65159SKalle Valo 	WMI_PEER_CHWIDTH_20MHZ = 0,
2171d5c65159SKalle Valo 	WMI_PEER_CHWIDTH_40MHZ = 1,
2172d5c65159SKalle Valo 	WMI_PEER_CHWIDTH_80MHZ = 2,
2173d5c65159SKalle Valo 	WMI_PEER_CHWIDTH_160MHZ = 3,
2174d5c65159SKalle Valo };
2175d5c65159SKalle Valo 
2176d5c65159SKalle Valo enum wmi_beacon_gen_mode {
2177d5c65159SKalle Valo 	WMI_BEACON_STAGGERED_MODE = 0,
2178d5c65159SKalle Valo 	WMI_BEACON_BURST_MODE = 1
2179d5c65159SKalle Valo };
2180d5c65159SKalle Valo 
2181bd647855SKarthikeyan Periyasamy enum wmi_direct_buffer_module {
2182bd647855SKarthikeyan Periyasamy 	WMI_DIRECT_BUF_SPECTRAL = 0,
2183bd647855SKarthikeyan Periyasamy 	WMI_DIRECT_BUF_CFR = 1,
2184bd647855SKarthikeyan Periyasamy 
2185bd647855SKarthikeyan Periyasamy 	/* keep it last */
2186bd647855SKarthikeyan Periyasamy 	WMI_DIRECT_BUF_MAX
2187bd647855SKarthikeyan Periyasamy };
2188bd647855SKarthikeyan Periyasamy 
2189f552d6fdSP Praneesh /* enum wmi_nss_ratio - NSS ratio received from FW during service ready ext
2190f552d6fdSP Praneesh  *			event
2191f552d6fdSP Praneesh  * WMI_NSS_RATIO_1BY2_NSS -Max nss of 160MHz is equals to half of the max nss
2192f552d6fdSP Praneesh  *			   of 80MHz
2193f552d6fdSP Praneesh  * WMI_NSS_RATIO_3BY4_NSS - Max nss of 160MHz is equals to 3/4 of the max nss
2194f552d6fdSP Praneesh  *			    of 80MHz
2195f552d6fdSP Praneesh  * WMI_NSS_RATIO_1_NSS - Max nss of 160MHz is equals to the max nss of 80MHz
2196f552d6fdSP Praneesh  * WMI_NSS_RATIO_2_NSS - Max nss of 160MHz is equals to two times the max
2197f552d6fdSP Praneesh  *			 nss of 80MHz
2198f552d6fdSP Praneesh  */
2199f552d6fdSP Praneesh 
2200f552d6fdSP Praneesh enum wmi_nss_ratio {
2201f552d6fdSP Praneesh 	WMI_NSS_RATIO_1BY2_NSS = 0x0,
2202f552d6fdSP Praneesh 	WMI_NSS_RATIO_3BY4_NSS = 0x1,
2203f552d6fdSP Praneesh 	WMI_NSS_RATIO_1_NSS = 0x2,
2204f552d6fdSP Praneesh 	WMI_NSS_RATIO_2_NSS = 0x3,
2205f552d6fdSP Praneesh };
2206f552d6fdSP Praneesh 
220755e18e5aSCarl Huang enum wmi_dtim_policy {
220855e18e5aSCarl Huang 	WMI_DTIM_POLICY_IGNORE = 1,
220955e18e5aSCarl Huang 	WMI_DTIM_POLICY_NORMAL = 2,
221055e18e5aSCarl Huang 	WMI_DTIM_POLICY_STICK  = 3,
221155e18e5aSCarl Huang 	WMI_DTIM_POLICY_AUTO   = 4,
221255e18e5aSCarl Huang };
221355e18e5aSCarl Huang 
2214d5c65159SKalle Valo struct wmi_host_pdev_band_to_mac {
2215d5c65159SKalle Valo 	u32 pdev_id;
2216d5c65159SKalle Valo 	u32 start_freq;
2217d5c65159SKalle Valo 	u32 end_freq;
2218d5c65159SKalle Valo };
2219d5c65159SKalle Valo 
2220d5c65159SKalle Valo struct ath11k_ppe_threshold {
2221d5c65159SKalle Valo 	u32 numss_m1;
2222d5c65159SKalle Valo 	u32 ru_bit_mask;
2223d5c65159SKalle Valo 	u32 ppet16_ppet8_ru3_ru0[PSOC_HOST_MAX_NUM_SS];
2224d5c65159SKalle Valo };
2225d5c65159SKalle Valo 
2226d5c65159SKalle Valo struct ath11k_service_ext_param {
2227d5c65159SKalle Valo 	u32 default_conc_scan_config_bits;
2228d5c65159SKalle Valo 	u32 default_fw_config_bits;
2229d5c65159SKalle Valo 	struct ath11k_ppe_threshold ppet;
2230d5c65159SKalle Valo 	u32 he_cap_info;
2231d5c65159SKalle Valo 	u32 mpdu_density;
2232d5c65159SKalle Valo 	u32 max_bssid_rx_filters;
2233d5c65159SKalle Valo 	u32 num_hw_modes;
2234d5c65159SKalle Valo 	u32 num_phy;
2235d5c65159SKalle Valo };
2236d5c65159SKalle Valo 
2237d5c65159SKalle Valo struct ath11k_hw_mode_caps {
2238d5c65159SKalle Valo 	u32 hw_mode_id;
2239d5c65159SKalle Valo 	u32 phy_id_map;
2240d5c65159SKalle Valo 	u32 hw_mode_config_type;
2241d5c65159SKalle Valo };
2242d5c65159SKalle Valo 
2243d5c65159SKalle Valo #define PSOC_HOST_MAX_PHY_SIZE (3)
2244d5c65159SKalle Valo #define ATH11K_11B_SUPPORT                 BIT(0)
2245d5c65159SKalle Valo #define ATH11K_11G_SUPPORT                 BIT(1)
2246d5c65159SKalle Valo #define ATH11K_11A_SUPPORT                 BIT(2)
2247d5c65159SKalle Valo #define ATH11K_11N_SUPPORT                 BIT(3)
2248d5c65159SKalle Valo #define ATH11K_11AC_SUPPORT                BIT(4)
2249d5c65159SKalle Valo #define ATH11K_11AX_SUPPORT                BIT(5)
2250d5c65159SKalle Valo 
2251d5c65159SKalle Valo struct ath11k_hal_reg_capabilities_ext {
2252d5c65159SKalle Valo 	u32 phy_id;
2253d5c65159SKalle Valo 	u32 eeprom_reg_domain;
2254d5c65159SKalle Valo 	u32 eeprom_reg_domain_ext;
2255d5c65159SKalle Valo 	u32 regcap1;
2256d5c65159SKalle Valo 	u32 regcap2;
2257d5c65159SKalle Valo 	u32 wireless_modes;
2258d5c65159SKalle Valo 	u32 low_2ghz_chan;
2259d5c65159SKalle Valo 	u32 high_2ghz_chan;
2260d5c65159SKalle Valo 	u32 low_5ghz_chan;
2261d5c65159SKalle Valo 	u32 high_5ghz_chan;
2262d5c65159SKalle Valo };
2263d5c65159SKalle Valo 
2264d5c65159SKalle Valo #define WMI_HOST_MAX_PDEV 3
2265d5c65159SKalle Valo 
2266d5c65159SKalle Valo struct wlan_host_mem_chunk {
2267d5c65159SKalle Valo 	u32 tlv_header;
2268d5c65159SKalle Valo 	u32 req_id;
2269d5c65159SKalle Valo 	u32 ptr;
2270d5c65159SKalle Valo 	u32 size;
2271d5c65159SKalle Valo } __packed;
2272d5c65159SKalle Valo 
2273d5c65159SKalle Valo struct wmi_host_mem_chunk {
2274d5c65159SKalle Valo 	void *vaddr;
2275d5c65159SKalle Valo 	dma_addr_t paddr;
2276d5c65159SKalle Valo 	u32 len;
2277d5c65159SKalle Valo 	u32 req_id;
2278d5c65159SKalle Valo };
2279d5c65159SKalle Valo 
2280d5c65159SKalle Valo struct wmi_init_cmd_param {
2281d5c65159SKalle Valo 	u32 tlv_header;
2282d5c65159SKalle Valo 	struct target_resource_config *res_cfg;
2283d5c65159SKalle Valo 	u8 num_mem_chunks;
2284d5c65159SKalle Valo 	struct wmi_host_mem_chunk *mem_chunks;
2285d5c65159SKalle Valo 	u32 hw_mode_id;
2286d5c65159SKalle Valo 	u32 num_band_to_mac;
2287d5c65159SKalle Valo 	struct wmi_host_pdev_band_to_mac band_to_mac[WMI_HOST_MAX_PDEV];
2288d5c65159SKalle Valo };
2289d5c65159SKalle Valo 
2290d5c65159SKalle Valo struct wmi_pdev_band_to_mac {
2291d5c65159SKalle Valo 	u32 tlv_header;
2292d5c65159SKalle Valo 	u32 pdev_id;
2293d5c65159SKalle Valo 	u32 start_freq;
2294d5c65159SKalle Valo 	u32 end_freq;
2295d5c65159SKalle Valo } __packed;
2296d5c65159SKalle Valo 
2297d5c65159SKalle Valo struct wmi_pdev_set_hw_mode_cmd_param {
2298d5c65159SKalle Valo 	u32 tlv_header;
2299d5c65159SKalle Valo 	u32 pdev_id;
2300d5c65159SKalle Valo 	u32 hw_mode_index;
2301d5c65159SKalle Valo 	u32 num_band_to_mac;
2302d5c65159SKalle Valo } __packed;
2303d5c65159SKalle Valo 
2304d5c65159SKalle Valo struct wmi_ppe_threshold {
2305d5c65159SKalle Valo 	u32 numss_m1; /** NSS - 1*/
2306d5c65159SKalle Valo 	union {
2307d5c65159SKalle Valo 		u32 ru_count;
2308d5c65159SKalle Valo 		u32 ru_mask;
2309d5c65159SKalle Valo 	} __packed;
2310d5c65159SKalle Valo 	u32 ppet16_ppet8_ru3_ru0[WMI_MAX_NUM_SS];
2311d5c65159SKalle Valo } __packed;
2312d5c65159SKalle Valo 
2313d5c65159SKalle Valo #define HW_BD_INFO_SIZE       5
2314d5c65159SKalle Valo 
2315d5c65159SKalle Valo struct wmi_abi_version {
2316d5c65159SKalle Valo 	u32 abi_version_0;
2317d5c65159SKalle Valo 	u32 abi_version_1;
2318d5c65159SKalle Valo 	u32 abi_version_ns_0;
2319d5c65159SKalle Valo 	u32 abi_version_ns_1;
2320d5c65159SKalle Valo 	u32 abi_version_ns_2;
2321d5c65159SKalle Valo 	u32 abi_version_ns_3;
2322d5c65159SKalle Valo } __packed;
2323d5c65159SKalle Valo 
2324d5c65159SKalle Valo struct wmi_init_cmd {
2325d5c65159SKalle Valo 	u32 tlv_header;
2326d5c65159SKalle Valo 	struct wmi_abi_version host_abi_vers;
2327d5c65159SKalle Valo 	u32 num_host_mem_chunks;
2328d5c65159SKalle Valo } __packed;
2329d5c65159SKalle Valo 
23309b4dd38bSSeevalamuthu Mariappan #define WMI_RSRC_CFG_FLAG1_BSS_CHANNEL_INFO_64 BIT(5)
2331a08dbb04SAloka Dixit #define WMI_RSRC_CFG_FLAG2_CALC_NEXT_DTIM_COUNT_SET BIT(9)
233201c6c9fcSAbinaya Kalaiselvan #define WMI_RSRC_CFG_FLAG1_ACK_RSSI BIT(18)
23339b4dd38bSSeevalamuthu Mariappan 
233491fa00faSAditya Kumar Singh #define WMI_CFG_HOST_SERVICE_FLAG_REG_CC_EXT 4
233591fa00faSAditya Kumar Singh 
2336d5c65159SKalle Valo struct wmi_resource_config {
2337d5c65159SKalle Valo 	u32 tlv_header;
2338d5c65159SKalle Valo 	u32 num_vdevs;
2339d5c65159SKalle Valo 	u32 num_peers;
2340d5c65159SKalle Valo 	u32 num_offload_peers;
2341d5c65159SKalle Valo 	u32 num_offload_reorder_buffs;
2342d5c65159SKalle Valo 	u32 num_peer_keys;
2343d5c65159SKalle Valo 	u32 num_tids;
2344d5c65159SKalle Valo 	u32 ast_skid_limit;
2345d5c65159SKalle Valo 	u32 tx_chain_mask;
2346d5c65159SKalle Valo 	u32 rx_chain_mask;
2347d5c65159SKalle Valo 	u32 rx_timeout_pri[4];
2348d5c65159SKalle Valo 	u32 rx_decap_mode;
2349d5c65159SKalle Valo 	u32 scan_max_pending_req;
2350d5c65159SKalle Valo 	u32 bmiss_offload_max_vdev;
2351d5c65159SKalle Valo 	u32 roam_offload_max_vdev;
2352d5c65159SKalle Valo 	u32 roam_offload_max_ap_profiles;
2353d5c65159SKalle Valo 	u32 num_mcast_groups;
2354d5c65159SKalle Valo 	u32 num_mcast_table_elems;
2355d5c65159SKalle Valo 	u32 mcast2ucast_mode;
2356d5c65159SKalle Valo 	u32 tx_dbg_log_size;
2357d5c65159SKalle Valo 	u32 num_wds_entries;
2358d5c65159SKalle Valo 	u32 dma_burst_size;
2359d5c65159SKalle Valo 	u32 mac_aggr_delim;
2360d5c65159SKalle Valo 	u32 rx_skip_defrag_timeout_dup_detection_check;
2361d5c65159SKalle Valo 	u32 vow_config;
2362d5c65159SKalle Valo 	u32 gtk_offload_max_vdev;
2363d5c65159SKalle Valo 	u32 num_msdu_desc;
2364d5c65159SKalle Valo 	u32 max_frag_entries;
2365d5c65159SKalle Valo 	u32 num_tdls_vdevs;
2366d5c65159SKalle Valo 	u32 num_tdls_conn_table_entries;
2367d5c65159SKalle Valo 	u32 beacon_tx_offload_max_vdev;
2368d5c65159SKalle Valo 	u32 num_multicast_filter_entries;
2369d5c65159SKalle Valo 	u32 num_wow_filters;
2370d5c65159SKalle Valo 	u32 num_keep_alive_pattern;
2371d5c65159SKalle Valo 	u32 keep_alive_pattern_size;
2372d5c65159SKalle Valo 	u32 max_tdls_concurrent_sleep_sta;
2373d5c65159SKalle Valo 	u32 max_tdls_concurrent_buffer_sta;
2374d5c65159SKalle Valo 	u32 wmi_send_separate;
2375d5c65159SKalle Valo 	u32 num_ocb_vdevs;
2376d5c65159SKalle Valo 	u32 num_ocb_channels;
2377d5c65159SKalle Valo 	u32 num_ocb_schedules;
2378d5c65159SKalle Valo 	u32 flag1;
2379d5c65159SKalle Valo 	u32 smart_ant_cap;
2380d5c65159SKalle Valo 	u32 bk_minfree;
2381d5c65159SKalle Valo 	u32 be_minfree;
2382d5c65159SKalle Valo 	u32 vi_minfree;
2383d5c65159SKalle Valo 	u32 vo_minfree;
2384d5c65159SKalle Valo 	u32 alloc_frag_desc_for_data_pkt;
2385d5c65159SKalle Valo 	u32 num_ns_ext_tuples_cfg;
2386d5c65159SKalle Valo 	u32 bpf_instruction_size;
2387d5c65159SKalle Valo 	u32 max_bssid_rx_filters;
2388d5c65159SKalle Valo 	u32 use_pdev_id;
2389d5c65159SKalle Valo 	u32 max_num_dbs_scan_duty_cycle;
2390d5c65159SKalle Valo 	u32 max_num_group_keys;
2391d5c65159SKalle Valo 	u32 peer_map_unmap_v2_support;
23926d293d44SJohn Crispin 	u32 sched_params;
23936d293d44SJohn Crispin 	u32 twt_ap_pdev_count;
23946d293d44SJohn Crispin 	u32 twt_ap_sta_count;
239591fa00faSAditya Kumar Singh 	u32 max_nlo_ssids;
239691fa00faSAditya Kumar Singh 	u32 num_pkt_filters;
239791fa00faSAditya Kumar Singh 	u32 num_max_sta_vdevs;
239891fa00faSAditya Kumar Singh 	u32 max_bssid_indicator;
239991fa00faSAditya Kumar Singh 	u32 ul_resp_config;
240091fa00faSAditya Kumar Singh 	u32 msdu_flow_override_config0;
240191fa00faSAditya Kumar Singh 	u32 msdu_flow_override_config1;
240291fa00faSAditya Kumar Singh 	u32 flags2;
240391fa00faSAditya Kumar Singh 	u32 host_service_flags;
2404a08dbb04SAloka Dixit 	u32 max_rnr_neighbours;
2405a08dbb04SAloka Dixit 	u32 ema_max_vap_cnt;
2406a08dbb04SAloka Dixit 	u32 ema_max_profile_period;
2407d5c65159SKalle Valo } __packed;
2408d5c65159SKalle Valo 
2409d5c65159SKalle Valo struct wmi_service_ready_event {
2410d5c65159SKalle Valo 	u32 fw_build_vers;
2411d5c65159SKalle Valo 	struct wmi_abi_version fw_abi_vers;
2412d5c65159SKalle Valo 	u32 phy_capability;
2413d5c65159SKalle Valo 	u32 max_frag_entry;
2414d5c65159SKalle Valo 	u32 num_rf_chains;
2415d5c65159SKalle Valo 	u32 ht_cap_info;
2416d5c65159SKalle Valo 	u32 vht_cap_info;
2417d5c65159SKalle Valo 	u32 vht_supp_mcs;
2418d5c65159SKalle Valo 	u32 hw_min_tx_power;
2419d5c65159SKalle Valo 	u32 hw_max_tx_power;
2420d5c65159SKalle Valo 	u32 sys_cap_info;
2421d5c65159SKalle Valo 	u32 min_pkt_size_enable;
2422d5c65159SKalle Valo 	u32 max_bcn_ie_size;
2423d5c65159SKalle Valo 	u32 num_mem_reqs;
2424d5c65159SKalle Valo 	u32 max_num_scan_channels;
2425d5c65159SKalle Valo 	u32 hw_bd_id;
2426d5c65159SKalle Valo 	u32 hw_bd_info[HW_BD_INFO_SIZE];
2427d5c65159SKalle Valo 	u32 max_supported_macs;
2428d5c65159SKalle Valo 	u32 wmi_fw_sub_feat_caps;
2429d5c65159SKalle Valo 	u32 num_dbs_hw_modes;
2430d5c65159SKalle Valo 	/* txrx_chainmask
2431d5c65159SKalle Valo 	 *    [7:0]   - 2G band tx chain mask
2432d5c65159SKalle Valo 	 *    [15:8]  - 2G band rx chain mask
2433d5c65159SKalle Valo 	 *    [23:16] - 5G band tx chain mask
2434d5c65159SKalle Valo 	 *    [31:24] - 5G band rx chain mask
2435d5c65159SKalle Valo 	 */
2436d5c65159SKalle Valo 	u32 txrx_chainmask;
2437d5c65159SKalle Valo 	u32 default_dbs_hw_mode_index;
2438d5c65159SKalle Valo 	u32 num_msdu_desc;
2439d5c65159SKalle Valo } __packed;
2440d5c65159SKalle Valo 
2441d5c65159SKalle Valo #define WMI_SERVICE_BM_SIZE	((WMI_MAX_SERVICE + sizeof(u32) - 1) / sizeof(u32))
2442d5c65159SKalle Valo 
2443d5c65159SKalle Valo #define WMI_SERVICE_SEGMENT_BM_SIZE32 4 /* 4x u32 = 128 bits */
2444d5c65159SKalle Valo #define WMI_SERVICE_EXT_BM_SIZE (WMI_SERVICE_SEGMENT_BM_SIZE32 * sizeof(u32))
2445d5c65159SKalle Valo #define WMI_AVAIL_SERVICE_BITS_IN_SIZE32 32
2446d5c65159SKalle Valo #define WMI_SERVICE_BITS_IN_SIZE32 4
2447d5c65159SKalle Valo 
2448d5c65159SKalle Valo struct wmi_service_ready_ext_event {
2449d5c65159SKalle Valo 	u32 default_conc_scan_config_bits;
2450d5c65159SKalle Valo 	u32 default_fw_config_bits;
2451d5c65159SKalle Valo 	struct wmi_ppe_threshold ppet;
2452d5c65159SKalle Valo 	u32 he_cap_info;
2453d5c65159SKalle Valo 	u32 mpdu_density;
2454d5c65159SKalle Valo 	u32 max_bssid_rx_filters;
2455d5c65159SKalle Valo 	u32 fw_build_vers_ext;
2456d5c65159SKalle Valo 	u32 max_nlo_ssids;
2457d5c65159SKalle Valo 	u32 max_bssid_indicator;
2458d5c65159SKalle Valo 	u32 he_cap_info_ext;
2459d5c65159SKalle Valo } __packed;
2460d5c65159SKalle Valo 
2461d5c65159SKalle Valo struct wmi_soc_mac_phy_hw_mode_caps {
2462d5c65159SKalle Valo 	u32 num_hw_modes;
2463d5c65159SKalle Valo 	u32 num_chainmask_tables;
2464d5c65159SKalle Valo } __packed;
2465d5c65159SKalle Valo 
2466d5c65159SKalle Valo struct wmi_hw_mode_capabilities {
2467d5c65159SKalle Valo 	u32 tlv_header;
2468d5c65159SKalle Valo 	u32 hw_mode_id;
2469d5c65159SKalle Valo 	u32 phy_id_map;
2470d5c65159SKalle Valo 	u32 hw_mode_config_type;
2471d5c65159SKalle Valo } __packed;
2472d5c65159SKalle Valo 
2473d5c65159SKalle Valo #define WMI_MAX_HECAP_PHY_SIZE                 (3)
2474f552d6fdSP Praneesh #define WMI_NSS_RATIO_ENABLE_DISABLE_BITPOS    BIT(0)
2475f552d6fdSP Praneesh #define WMI_NSS_RATIO_ENABLE_DISABLE_GET(_val) \
2476f552d6fdSP Praneesh 	FIELD_GET(WMI_NSS_RATIO_ENABLE_DISABLE_BITPOS, _val)
2477f552d6fdSP Praneesh #define WMI_NSS_RATIO_INFO_BITPOS              GENMASK(4, 1)
2478f552d6fdSP Praneesh #define WMI_NSS_RATIO_INFO_GET(_val) \
2479f552d6fdSP Praneesh 	FIELD_GET(WMI_NSS_RATIO_INFO_BITPOS, _val)
2480d5c65159SKalle Valo 
2481d5c65159SKalle Valo struct wmi_mac_phy_capabilities {
2482d5c65159SKalle Valo 	u32 hw_mode_id;
2483d5c65159SKalle Valo 	u32 pdev_id;
2484d5c65159SKalle Valo 	u32 phy_id;
2485d5c65159SKalle Valo 	u32 supported_flags;
2486d5c65159SKalle Valo 	u32 supported_bands;
2487d5c65159SKalle Valo 	u32 ampdu_density;
2488d5c65159SKalle Valo 	u32 max_bw_supported_2g;
2489d5c65159SKalle Valo 	u32 ht_cap_info_2g;
2490d5c65159SKalle Valo 	u32 vht_cap_info_2g;
2491d5c65159SKalle Valo 	u32 vht_supp_mcs_2g;
2492d5c65159SKalle Valo 	u32 he_cap_info_2g;
2493d5c65159SKalle Valo 	u32 he_supp_mcs_2g;
2494d5c65159SKalle Valo 	u32 tx_chain_mask_2g;
2495d5c65159SKalle Valo 	u32 rx_chain_mask_2g;
2496d5c65159SKalle Valo 	u32 max_bw_supported_5g;
2497d5c65159SKalle Valo 	u32 ht_cap_info_5g;
2498d5c65159SKalle Valo 	u32 vht_cap_info_5g;
2499d5c65159SKalle Valo 	u32 vht_supp_mcs_5g;
2500d5c65159SKalle Valo 	u32 he_cap_info_5g;
2501d5c65159SKalle Valo 	u32 he_supp_mcs_5g;
2502d5c65159SKalle Valo 	u32 tx_chain_mask_5g;
2503d5c65159SKalle Valo 	u32 rx_chain_mask_5g;
2504d5c65159SKalle Valo 	u32 he_cap_phy_info_2g[WMI_MAX_HECAP_PHY_SIZE];
2505d5c65159SKalle Valo 	u32 he_cap_phy_info_5g[WMI_MAX_HECAP_PHY_SIZE];
2506d5c65159SKalle Valo 	struct wmi_ppe_threshold he_ppet2g;
2507d5c65159SKalle Valo 	struct wmi_ppe_threshold he_ppet5g;
2508d5c65159SKalle Valo 	u32 chainmask_table_id;
2509d5c65159SKalle Valo 	u32 lmac_id;
2510d5c65159SKalle Valo 	u32 he_cap_info_2g_ext;
2511d5c65159SKalle Valo 	u32 he_cap_info_5g_ext;
2512d5c65159SKalle Valo 	u32 he_cap_info_internal;
2513f552d6fdSP Praneesh 	u32 wireless_modes;
2514f552d6fdSP Praneesh 	u32 low_2ghz_chan_freq;
2515f552d6fdSP Praneesh 	u32 high_2ghz_chan_freq;
2516f552d6fdSP Praneesh 	u32 low_5ghz_chan_freq;
2517f552d6fdSP Praneesh 	u32 high_5ghz_chan_freq;
2518f552d6fdSP Praneesh 	u32 nss_ratio;
2519d5c65159SKalle Valo } __packed;
2520d5c65159SKalle Valo 
2521d5c65159SKalle Valo struct wmi_hal_reg_capabilities_ext {
2522d5c65159SKalle Valo 	u32 tlv_header;
2523d5c65159SKalle Valo 	u32 phy_id;
2524d5c65159SKalle Valo 	u32 eeprom_reg_domain;
2525d5c65159SKalle Valo 	u32 eeprom_reg_domain_ext;
2526d5c65159SKalle Valo 	u32 regcap1;
2527d5c65159SKalle Valo 	u32 regcap2;
2528d5c65159SKalle Valo 	u32 wireless_modes;
2529d5c65159SKalle Valo 	u32 low_2ghz_chan;
2530d5c65159SKalle Valo 	u32 high_2ghz_chan;
2531d5c65159SKalle Valo 	u32 low_5ghz_chan;
2532d5c65159SKalle Valo 	u32 high_5ghz_chan;
2533d5c65159SKalle Valo } __packed;
2534d5c65159SKalle Valo 
2535d5c65159SKalle Valo struct wmi_soc_hal_reg_capabilities {
2536d5c65159SKalle Valo 	u32 num_phy;
2537d5c65159SKalle Valo } __packed;
2538d5c65159SKalle Valo 
2539d5c65159SKalle Valo /* 2 word representation of MAC addr */
2540d5c65159SKalle Valo struct wmi_mac_addr {
2541d5c65159SKalle Valo 	union {
2542d5c65159SKalle Valo 		u8 addr[6];
2543d5c65159SKalle Valo 		struct {
2544d5c65159SKalle Valo 			u32 word0;
2545d5c65159SKalle Valo 			u32 word1;
2546d5c65159SKalle Valo 		} __packed;
2547d5c65159SKalle Valo 	} __packed;
2548d5c65159SKalle Valo } __packed;
2549d5c65159SKalle Valo 
2550bd647855SKarthikeyan Periyasamy struct wmi_dma_ring_capabilities {
2551bd647855SKarthikeyan Periyasamy 	u32 tlv_header;
2552bd647855SKarthikeyan Periyasamy 	u32 pdev_id;
2553bd647855SKarthikeyan Periyasamy 	u32 module_id;
2554bd647855SKarthikeyan Periyasamy 	u32 min_elem;
2555bd647855SKarthikeyan Periyasamy 	u32 min_buf_sz;
2556bd647855SKarthikeyan Periyasamy 	u32 min_buf_align;
2557bd647855SKarthikeyan Periyasamy } __packed;
2558bd647855SKarthikeyan Periyasamy 
255921c1b063SMaharaja Kennadyrajan struct wmi_ready_event_min {
2560d5c65159SKalle Valo 	struct wmi_abi_version fw_abi_vers;
2561d5c65159SKalle Valo 	struct wmi_mac_addr mac_addr;
2562d5c65159SKalle Valo 	u32 status;
2563d5c65159SKalle Valo 	u32 num_dscp_table;
2564d5c65159SKalle Valo 	u32 num_extra_mac_addr;
2565d5c65159SKalle Valo 	u32 num_total_peers;
2566d5c65159SKalle Valo 	u32 num_extra_peers;
2567d5c65159SKalle Valo } __packed;
2568d5c65159SKalle Valo 
256921c1b063SMaharaja Kennadyrajan struct wmi_ready_event {
257021c1b063SMaharaja Kennadyrajan 	struct wmi_ready_event_min ready_event_min;
257121c1b063SMaharaja Kennadyrajan 	u32 max_ast_index;
257221c1b063SMaharaja Kennadyrajan 	u32 pktlog_defs_checksum;
257321c1b063SMaharaja Kennadyrajan } __packed;
257421c1b063SMaharaja Kennadyrajan 
2575d5c65159SKalle Valo struct wmi_service_available_event {
2576d5c65159SKalle Valo 	u32 wmi_service_segment_offset;
2577d5c65159SKalle Valo 	u32 wmi_service_segment_bitmap[WMI_SERVICE_SEGMENT_BM_SIZE32];
2578d5c65159SKalle Valo } __packed;
2579d5c65159SKalle Valo 
2580d5c65159SKalle Valo struct ath11k_pdev_wmi {
25816bc9d6f7SJohn Crispin 	struct ath11k_wmi_base *wmi_ab;
2582d5c65159SKalle Valo 	enum ath11k_htc_ep_id eid;
2583d5c65159SKalle Valo 	const struct wmi_peer_flags_map *peer_flags;
2584d5c65159SKalle Valo 	u32 rx_decap_mode;
2585f951380aSP Praneesh 	wait_queue_head_t tx_ce_desc_wq;
2586d5c65159SKalle Valo };
2587d5c65159SKalle Valo 
2588d5c65159SKalle Valo struct vdev_create_params {
2589d5c65159SKalle Valo 	u8 if_id;
2590d5c65159SKalle Valo 	u32 type;
2591d5c65159SKalle Valo 	u32 subtype;
2592d5c65159SKalle Valo 	struct {
2593d5c65159SKalle Valo 		u8 tx;
2594d5c65159SKalle Valo 		u8 rx;
2595d5c65159SKalle Valo 	} chains[NUM_NL80211_BANDS];
2596d5c65159SKalle Valo 	u32 pdev_id;
25975a81610aSAloka Dixit 	u32 mbssid_flags;
25985a81610aSAloka Dixit 	u32 mbssid_tx_vdev_id;
2599d5c65159SKalle Valo };
2600d5c65159SKalle Valo 
2601d5c65159SKalle Valo struct wmi_vdev_create_cmd {
2602d5c65159SKalle Valo 	u32 tlv_header;
2603d5c65159SKalle Valo 	u32 vdev_id;
2604d5c65159SKalle Valo 	u32 vdev_type;
2605d5c65159SKalle Valo 	u32 vdev_subtype;
2606d5c65159SKalle Valo 	struct wmi_mac_addr vdev_macaddr;
2607d5c65159SKalle Valo 	u32 num_cfg_txrx_streams;
2608d5c65159SKalle Valo 	u32 pdev_id;
26095a81610aSAloka Dixit 	u32 mbssid_flags;
26105a81610aSAloka Dixit 	u32 mbssid_tx_vdev_id;
2611d5c65159SKalle Valo } __packed;
2612d5c65159SKalle Valo 
2613d5c65159SKalle Valo struct wmi_vdev_txrx_streams {
2614d5c65159SKalle Valo 	u32 tlv_header;
2615d5c65159SKalle Valo 	u32 band;
2616d5c65159SKalle Valo 	u32 supported_tx_streams;
2617d5c65159SKalle Valo 	u32 supported_rx_streams;
2618d5c65159SKalle Valo } __packed;
2619d5c65159SKalle Valo 
2620d5c65159SKalle Valo struct wmi_vdev_delete_cmd {
2621d5c65159SKalle Valo 	u32 tlv_header;
2622d5c65159SKalle Valo 	u32 vdev_id;
2623d5c65159SKalle Valo } __packed;
2624d5c65159SKalle Valo 
2625d5c65159SKalle Valo struct wmi_vdev_up_cmd {
2626d5c65159SKalle Valo 	u32 tlv_header;
2627d5c65159SKalle Valo 	u32 vdev_id;
2628d5c65159SKalle Valo 	u32 vdev_assoc_id;
2629d5c65159SKalle Valo 	struct wmi_mac_addr vdev_bssid;
2630cf604e72SAloka Dixit 	struct wmi_mac_addr tx_vdev_bssid;
2631cf604e72SAloka Dixit 	u32 nontx_profile_idx;
2632cf604e72SAloka Dixit 	u32 nontx_profile_cnt;
2633d5c65159SKalle Valo } __packed;
2634d5c65159SKalle Valo 
2635d5c65159SKalle Valo struct wmi_vdev_stop_cmd {
2636d5c65159SKalle Valo 	u32 tlv_header;
2637d5c65159SKalle Valo 	u32 vdev_id;
2638d5c65159SKalle Valo } __packed;
2639d5c65159SKalle Valo 
2640d5c65159SKalle Valo struct wmi_vdev_down_cmd {
2641d5c65159SKalle Valo 	u32 tlv_header;
2642d5c65159SKalle Valo 	u32 vdev_id;
2643d5c65159SKalle Valo } __packed;
2644d5c65159SKalle Valo 
2645d5c65159SKalle Valo #define WMI_VDEV_START_HIDDEN_SSID  BIT(0)
2646d5c65159SKalle Valo #define WMI_VDEV_START_PMF_ENABLED  BIT(1)
2647d5c65159SKalle Valo #define WMI_VDEV_START_LDPC_RX_ENABLED BIT(3)
26488717db7eSSeevalamuthu Mariappan #define WMI_VDEV_START_HW_ENCRYPTION_DISABLED BIT(4)
2649d5c65159SKalle Valo 
2650d5c65159SKalle Valo struct wmi_ssid {
2651d5c65159SKalle Valo 	u32 ssid_len;
2652d5c65159SKalle Valo 	u32 ssid[8];
2653d5c65159SKalle Valo } __packed;
2654d5c65159SKalle Valo 
2655d5c65159SKalle Valo #define ATH11K_VDEV_SETUP_TIMEOUT_HZ (1 * HZ)
2656d5c65159SKalle Valo 
2657d5c65159SKalle Valo struct wmi_vdev_start_request_cmd {
2658d5c65159SKalle Valo 	u32 tlv_header;
2659d5c65159SKalle Valo 	u32 vdev_id;
2660d5c65159SKalle Valo 	u32 requestor_id;
2661d5c65159SKalle Valo 	u32 beacon_interval;
2662d5c65159SKalle Valo 	u32 dtim_period;
2663d5c65159SKalle Valo 	u32 flags;
2664d5c65159SKalle Valo 	struct wmi_ssid ssid;
2665d5c65159SKalle Valo 	u32 bcn_tx_rate;
2666d5c65159SKalle Valo 	u32 bcn_txpower;
2667d5c65159SKalle Valo 	u32 num_noa_descriptors;
2668d5c65159SKalle Valo 	u32 disable_hw_ack;
2669d5c65159SKalle Valo 	u32 preferred_tx_streams;
2670d5c65159SKalle Valo 	u32 preferred_rx_streams;
2671d5c65159SKalle Valo 	u32 he_ops;
2672d5c65159SKalle Valo 	u32 cac_duration_ms;
2673d5c65159SKalle Valo 	u32 regdomain;
26745a81610aSAloka Dixit 	u32 min_data_rate;
26755a81610aSAloka Dixit 	u32 mbssid_flags;
26765a81610aSAloka Dixit 	u32 mbssid_tx_vdev_id;
2677d5c65159SKalle Valo } __packed;
2678d5c65159SKalle Valo 
2679d5c65159SKalle Valo #define MGMT_TX_DL_FRM_LEN		     64
2680d5c65159SKalle Valo #define WMI_MAC_MAX_SSID_LENGTH              32
2681d5c65159SKalle Valo struct mac_ssid {
2682d5c65159SKalle Valo 	u8 length;
2683d5c65159SKalle Valo 	u8 mac_ssid[WMI_MAC_MAX_SSID_LENGTH];
2684d5c65159SKalle Valo } __packed;
2685d5c65159SKalle Valo 
2686d5c65159SKalle Valo struct wmi_p2p_noa_descriptor {
2687d5c65159SKalle Valo 	u32 type_count;
2688d5c65159SKalle Valo 	u32 duration;
2689d5c65159SKalle Valo 	u32 interval;
2690d5c65159SKalle Valo 	u32 start_time;
2691d5c65159SKalle Valo };
2692d5c65159SKalle Valo 
2693d5c65159SKalle Valo struct channel_param {
2694d5c65159SKalle Valo 	u8 chan_id;
2695d5c65159SKalle Valo 	u8 pwr;
2696d5c65159SKalle Valo 	u32 mhz;
2697d5c65159SKalle Valo 	u32 half_rate:1,
2698d5c65159SKalle Valo 	    quarter_rate:1,
2699d5c65159SKalle Valo 	    dfs_set:1,
2700d5c65159SKalle Valo 	    dfs_set_cfreq2:1,
2701d5c65159SKalle Valo 	    is_chan_passive:1,
2702d5c65159SKalle Valo 	    allow_ht:1,
2703d5c65159SKalle Valo 	    allow_vht:1,
27049f056ed8SJohn Crispin 	    allow_he:1,
2705d387503dSPradeep Kumar Chitrapu 	    set_agile:1,
2706d387503dSPradeep Kumar Chitrapu 	    psc_channel:1;
2707d5c65159SKalle Valo 	u32 phy_mode;
2708d5c65159SKalle Valo 	u32 cfreq1;
2709d5c65159SKalle Valo 	u32 cfreq2;
2710d5c65159SKalle Valo 	char   maxpower;
2711d5c65159SKalle Valo 	char   minpower;
2712d5c65159SKalle Valo 	char   maxregpower;
2713d5c65159SKalle Valo 	u8  antennamax;
2714d5c65159SKalle Valo 	u8  reg_class_id;
2715d5c65159SKalle Valo } __packed;
2716d5c65159SKalle Valo 
2717d5c65159SKalle Valo enum wmi_phy_mode {
2718d5c65159SKalle Valo 	MODE_11A        = 0,
2719d5c65159SKalle Valo 	MODE_11G        = 1,   /* 11b/g Mode */
2720d5c65159SKalle Valo 	MODE_11B        = 2,   /* 11b Mode */
2721d5c65159SKalle Valo 	MODE_11GONLY    = 3,   /* 11g only Mode */
2722d5c65159SKalle Valo 	MODE_11NA_HT20   = 4,
2723d5c65159SKalle Valo 	MODE_11NG_HT20   = 5,
2724d5c65159SKalle Valo 	MODE_11NA_HT40   = 6,
2725d5c65159SKalle Valo 	MODE_11NG_HT40   = 7,
2726d5c65159SKalle Valo 	MODE_11AC_VHT20 = 8,
2727d5c65159SKalle Valo 	MODE_11AC_VHT40 = 9,
2728d5c65159SKalle Valo 	MODE_11AC_VHT80 = 10,
2729d5c65159SKalle Valo 	MODE_11AC_VHT20_2G = 11,
2730d5c65159SKalle Valo 	MODE_11AC_VHT40_2G = 12,
2731d5c65159SKalle Valo 	MODE_11AC_VHT80_2G = 13,
2732d5c65159SKalle Valo 	MODE_11AC_VHT80_80 = 14,
2733d5c65159SKalle Valo 	MODE_11AC_VHT160 = 15,
2734d5c65159SKalle Valo 	MODE_11AX_HE20 = 16,
2735d5c65159SKalle Valo 	MODE_11AX_HE40 = 17,
2736d5c65159SKalle Valo 	MODE_11AX_HE80 = 18,
2737d5c65159SKalle Valo 	MODE_11AX_HE80_80 = 19,
2738d5c65159SKalle Valo 	MODE_11AX_HE160 = 20,
2739d5c65159SKalle Valo 	MODE_11AX_HE20_2G = 21,
2740d5c65159SKalle Valo 	MODE_11AX_HE40_2G = 22,
2741d5c65159SKalle Valo 	MODE_11AX_HE80_2G = 23,
2742d5c65159SKalle Valo 	MODE_UNKNOWN = 24,
2743d5c65159SKalle Valo 	MODE_MAX = 24
2744d5c65159SKalle Valo };
2745d5c65159SKalle Valo 
ath11k_wmi_phymode_str(enum wmi_phy_mode mode)2746d5c65159SKalle Valo static inline const char *ath11k_wmi_phymode_str(enum wmi_phy_mode mode)
2747d5c65159SKalle Valo {
2748d5c65159SKalle Valo 	switch (mode) {
2749d5c65159SKalle Valo 	case MODE_11A:
2750d5c65159SKalle Valo 		return "11a";
2751d5c65159SKalle Valo 	case MODE_11G:
2752d5c65159SKalle Valo 		return "11g";
2753d5c65159SKalle Valo 	case MODE_11B:
2754d5c65159SKalle Valo 		return "11b";
2755d5c65159SKalle Valo 	case MODE_11GONLY:
2756d5c65159SKalle Valo 		return "11gonly";
2757d5c65159SKalle Valo 	case MODE_11NA_HT20:
2758d5c65159SKalle Valo 		return "11na-ht20";
2759d5c65159SKalle Valo 	case MODE_11NG_HT20:
2760d5c65159SKalle Valo 		return "11ng-ht20";
2761d5c65159SKalle Valo 	case MODE_11NA_HT40:
2762d5c65159SKalle Valo 		return "11na-ht40";
2763d5c65159SKalle Valo 	case MODE_11NG_HT40:
2764d5c65159SKalle Valo 		return "11ng-ht40";
2765d5c65159SKalle Valo 	case MODE_11AC_VHT20:
2766d5c65159SKalle Valo 		return "11ac-vht20";
2767d5c65159SKalle Valo 	case MODE_11AC_VHT40:
2768d5c65159SKalle Valo 		return "11ac-vht40";
2769d5c65159SKalle Valo 	case MODE_11AC_VHT80:
2770d5c65159SKalle Valo 		return "11ac-vht80";
2771d5c65159SKalle Valo 	case MODE_11AC_VHT160:
2772d5c65159SKalle Valo 		return "11ac-vht160";
2773d5c65159SKalle Valo 	case MODE_11AC_VHT80_80:
2774d5c65159SKalle Valo 		return "11ac-vht80+80";
2775d5c65159SKalle Valo 	case MODE_11AC_VHT20_2G:
2776d5c65159SKalle Valo 		return "11ac-vht20-2g";
2777d5c65159SKalle Valo 	case MODE_11AC_VHT40_2G:
2778d5c65159SKalle Valo 		return "11ac-vht40-2g";
2779d5c65159SKalle Valo 	case MODE_11AC_VHT80_2G:
2780d5c65159SKalle Valo 		return "11ac-vht80-2g";
2781d5c65159SKalle Valo 	case MODE_11AX_HE20:
2782d5c65159SKalle Valo 		return "11ax-he20";
2783d5c65159SKalle Valo 	case MODE_11AX_HE40:
2784d5c65159SKalle Valo 		return "11ax-he40";
2785d5c65159SKalle Valo 	case MODE_11AX_HE80:
2786d5c65159SKalle Valo 		return "11ax-he80";
2787d5c65159SKalle Valo 	case MODE_11AX_HE80_80:
2788d5c65159SKalle Valo 		return "11ax-he80+80";
2789d5c65159SKalle Valo 	case MODE_11AX_HE160:
2790d5c65159SKalle Valo 		return "11ax-he160";
2791d5c65159SKalle Valo 	case MODE_11AX_HE20_2G:
2792d5c65159SKalle Valo 		return "11ax-he20-2g";
2793d5c65159SKalle Valo 	case MODE_11AX_HE40_2G:
2794d5c65159SKalle Valo 		return "11ax-he40-2g";
2795d5c65159SKalle Valo 	case MODE_11AX_HE80_2G:
2796d5c65159SKalle Valo 		return "11ax-he80-2g";
2797d5c65159SKalle Valo 	case MODE_UNKNOWN:
2798d5c65159SKalle Valo 		/* skip */
2799d5c65159SKalle Valo 		break;
2800d5c65159SKalle Valo 
2801d5c65159SKalle Valo 		/* no default handler to allow compiler to check that the
2802d5c65159SKalle Valo 		 * enum is fully handled
2803d5c65159SKalle Valo 		 */
2804d1389e19Szhengbin 	}
2805d5c65159SKalle Valo 
2806d5c65159SKalle Valo 	return "<unknown>";
2807d5c65159SKalle Valo }
2808d5c65159SKalle Valo 
2809d5c65159SKalle Valo struct wmi_channel_arg {
2810d5c65159SKalle Valo 	u32 freq;
2811d5c65159SKalle Valo 	u32 band_center_freq1;
2812d5c65159SKalle Valo 	u32 band_center_freq2;
2813d5c65159SKalle Valo 	bool passive;
2814d5c65159SKalle Valo 	bool allow_ibss;
2815d5c65159SKalle Valo 	bool allow_ht;
2816d5c65159SKalle Valo 	bool allow_vht;
2817d5c65159SKalle Valo 	bool ht40plus;
2818d5c65159SKalle Valo 	bool chan_radar;
2819d5c65159SKalle Valo 	bool freq2_radar;
2820d5c65159SKalle Valo 	bool allow_he;
2821d5c65159SKalle Valo 	u32 min_power;
2822d5c65159SKalle Valo 	u32 max_power;
2823d5c65159SKalle Valo 	u32 max_reg_power;
2824d5c65159SKalle Valo 	u32 max_antenna_gain;
2825d5c65159SKalle Valo 	enum wmi_phy_mode mode;
2826d5c65159SKalle Valo };
2827d5c65159SKalle Valo 
2828d5c65159SKalle Valo struct wmi_vdev_start_req_arg {
2829d5c65159SKalle Valo 	u32 vdev_id;
2830d5c65159SKalle Valo 	struct wmi_channel_arg channel;
2831d5c65159SKalle Valo 	u32 bcn_intval;
2832d5c65159SKalle Valo 	u32 dtim_period;
2833d5c65159SKalle Valo 	u8 *ssid;
2834d5c65159SKalle Valo 	u32 ssid_len;
2835d5c65159SKalle Valo 	u32 bcn_tx_rate;
2836d5c65159SKalle Valo 	u32 bcn_tx_power;
2837d5c65159SKalle Valo 	bool disable_hw_ack;
2838d5c65159SKalle Valo 	bool hidden_ssid;
2839d5c65159SKalle Valo 	bool pmf_enabled;
2840d5c65159SKalle Valo 	u32 he_ops;
2841d5c65159SKalle Valo 	u32 cac_duration_ms;
2842d5c65159SKalle Valo 	u32 regdomain;
2843d5c65159SKalle Valo 	u32 pref_rx_streams;
2844d5c65159SKalle Valo 	u32 pref_tx_streams;
2845d5c65159SKalle Valo 	u32 num_noa_descriptors;
28465a81610aSAloka Dixit 	u32 min_data_rate;
28475a81610aSAloka Dixit 	u32 mbssid_flags;
28485a81610aSAloka Dixit 	u32 mbssid_tx_vdev_id;
2849d5c65159SKalle Valo };
2850d5c65159SKalle Valo 
2851d5c65159SKalle Valo struct peer_create_params {
2852d5c65159SKalle Valo 	const u8 *peer_addr;
2853d5c65159SKalle Valo 	u32 peer_type;
2854d5c65159SKalle Valo 	u32 vdev_id;
2855d5c65159SKalle Valo };
2856d5c65159SKalle Valo 
2857d5c65159SKalle Valo struct peer_delete_params {
2858d5c65159SKalle Valo 	u8 vdev_id;
2859d5c65159SKalle Valo };
2860d5c65159SKalle Valo 
2861d5c65159SKalle Valo struct peer_flush_params {
2862d5c65159SKalle Valo 	u32 peer_tid_bitmap;
2863d5c65159SKalle Valo 	u8 vdev_id;
2864d5c65159SKalle Valo };
2865d5c65159SKalle Valo 
2866d5c65159SKalle Valo struct pdev_set_regdomain_params {
2867d5c65159SKalle Valo 	u16 current_rd_in_use;
2868d5c65159SKalle Valo 	u16 current_rd_2g;
2869d5c65159SKalle Valo 	u16 current_rd_5g;
2870d5c65159SKalle Valo 	u32 ctl_2g;
2871d5c65159SKalle Valo 	u32 ctl_5g;
2872d5c65159SKalle Valo 	u8 dfs_domain;
2873d5c65159SKalle Valo 	u32 pdev_id;
2874d5c65159SKalle Valo };
2875d5c65159SKalle Valo 
2876d5c65159SKalle Valo struct rx_reorder_queue_remove_params {
2877d5c65159SKalle Valo 	u8 *peer_macaddr;
2878d5c65159SKalle Valo 	u16 vdev_id;
2879d5c65159SKalle Valo 	u32 peer_tid_bitmap;
2880d5c65159SKalle Valo };
2881d5c65159SKalle Valo 
2882d5c65159SKalle Valo #define WMI_HOST_PDEV_ID_SOC 0xFF
2883d5c65159SKalle Valo #define WMI_HOST_PDEV_ID_0   0
2884d5c65159SKalle Valo #define WMI_HOST_PDEV_ID_1   1
2885d5c65159SKalle Valo #define WMI_HOST_PDEV_ID_2   2
2886d5c65159SKalle Valo 
2887d5c65159SKalle Valo #define WMI_PDEV_ID_SOC         0
2888d5c65159SKalle Valo #define WMI_PDEV_ID_1ST         1
2889d5c65159SKalle Valo #define WMI_PDEV_ID_2ND         2
2890d5c65159SKalle Valo #define WMI_PDEV_ID_3RD         3
2891d5c65159SKalle Valo 
2892d5c65159SKalle Valo /* Freq units in MHz */
2893d5c65159SKalle Valo #define REG_RULE_START_FREQ			0x0000ffff
2894d5c65159SKalle Valo #define REG_RULE_END_FREQ			0xffff0000
2895d5c65159SKalle Valo #define REG_RULE_FLAGS				0x0000ffff
2896d5c65159SKalle Valo #define REG_RULE_MAX_BW				0x0000ffff
2897d5c65159SKalle Valo #define REG_RULE_REG_PWR			0x00ff0000
2898d5c65159SKalle Valo #define REG_RULE_ANT_GAIN			0xff000000
289991fa00faSAditya Kumar Singh #define REG_RULE_PSD_INFO			BIT(0)
290091fa00faSAditya Kumar Singh #define REG_RULE_PSD_EIRP			0xff0000
2901d5c65159SKalle Valo 
2902d5c65159SKalle Valo #define WMI_VDEV_PARAM_TXBF_SU_TX_BFEE BIT(0)
2903d5c65159SKalle Valo #define WMI_VDEV_PARAM_TXBF_MU_TX_BFEE BIT(1)
2904d5c65159SKalle Valo #define WMI_VDEV_PARAM_TXBF_SU_TX_BFER BIT(2)
2905d5c65159SKalle Valo #define WMI_VDEV_PARAM_TXBF_MU_TX_BFER BIT(3)
2906d5c65159SKalle Valo 
2907a96f1042SMuna Sinada #define HE_PHYCAP_BYTE_0	0
2908a96f1042SMuna Sinada #define HE_PHYCAP_BYTE_1	1
2909a96f1042SMuna Sinada #define HE_PHYCAP_BYTE_2	2
2910a96f1042SMuna Sinada #define HE_PHYCAP_BYTE_3	3
2911a96f1042SMuna Sinada #define HE_PHYCAP_BYTE_4	4
2912d5c65159SKalle Valo 
2913a96f1042SMuna Sinada #define HECAP_PHY_SU_BFER		BIT(7)
2914d5c65159SKalle Valo #define HECAP_PHY_SU_BFEE		BIT(0)
2915d5c65159SKalle Valo #define HECAP_PHY_MU_BFER		BIT(1)
2916a96f1042SMuna Sinada #define HECAP_PHY_UL_MUMIMO		BIT(6)
2917a96f1042SMuna Sinada #define HECAP_PHY_UL_MUOFDMA		BIT(7)
2918d5c65159SKalle Valo 
2919d5c65159SKalle Valo #define HECAP_PHY_SUBFMR_GET(hecap_phy) \
2920a96f1042SMuna Sinada 	FIELD_GET(HECAP_PHY_SU_BFER, hecap_phy[HE_PHYCAP_BYTE_3])
2921d5c65159SKalle Valo 
2922d5c65159SKalle Valo #define HECAP_PHY_SUBFME_GET(hecap_phy) \
2923a96f1042SMuna Sinada 	FIELD_GET(HECAP_PHY_SU_BFEE, hecap_phy[HE_PHYCAP_BYTE_4])
2924d5c65159SKalle Valo 
2925d5c65159SKalle Valo #define HECAP_PHY_MUBFMR_GET(hecap_phy) \
2926a96f1042SMuna Sinada 	FIELD_GET(HECAP_PHY_MU_BFER, hecap_phy[HE_PHYCAP_BYTE_4])
2927d5c65159SKalle Valo 
2928d5c65159SKalle Valo #define HECAP_PHY_ULMUMIMO_GET(hecap_phy) \
2929a96f1042SMuna Sinada 	FIELD_GET(HECAP_PHY_UL_MUMIMO, hecap_phy[HE_PHYCAP_BYTE_2])
2930d5c65159SKalle Valo 
2931d5c65159SKalle Valo #define HECAP_PHY_ULOFDMA_GET(hecap_phy) \
2932a96f1042SMuna Sinada 	FIELD_GET(HECAP_PHY_UL_MUOFDMA, hecap_phy[HE_PHYCAP_BYTE_2])
2933d5c65159SKalle Valo 
2934d5c65159SKalle Valo #define HE_MODE_SU_TX_BFEE	BIT(0)
2935d5c65159SKalle Valo #define HE_MODE_SU_TX_BFER	BIT(1)
2936d5c65159SKalle Valo #define HE_MODE_MU_TX_BFEE	BIT(2)
2937d5c65159SKalle Valo #define HE_MODE_MU_TX_BFER	BIT(3)
2938d5c65159SKalle Valo #define HE_MODE_DL_OFDMA	BIT(4)
2939d5c65159SKalle Valo #define HE_MODE_UL_OFDMA	BIT(5)
2940d5c65159SKalle Valo #define HE_MODE_UL_MUMIMO	BIT(6)
2941d5c65159SKalle Valo 
2942d5c65159SKalle Valo #define HE_DL_MUOFDMA_ENABLE	1
2943d5c65159SKalle Valo #define HE_UL_MUOFDMA_ENABLE	1
2944d5c65159SKalle Valo #define HE_DL_MUMIMO_ENABLE	1
294538dfe775SMuna Sinada #define HE_UL_MUMIMO_ENABLE	1
2946d5c65159SKalle Valo #define HE_MU_BFEE_ENABLE	1
2947d5c65159SKalle Valo #define HE_SU_BFEE_ENABLE	1
294838dfe775SMuna Sinada #define HE_MU_BFER_ENABLE	1
294938dfe775SMuna Sinada #define HE_SU_BFER_ENABLE	1
2950d5c65159SKalle Valo 
2951d5c65159SKalle Valo #define HE_VHT_SOUNDING_MODE_ENABLE		1
2952d5c65159SKalle Valo #define HE_SU_MU_SOUNDING_MODE_ENABLE		1
2953d5c65159SKalle Valo #define HE_TRIG_NONTRIG_SOUNDING_MODE_ENABLE	1
2954d5c65159SKalle Valo 
2955d5c65159SKalle Valo /* HE or VHT Sounding */
2956d5c65159SKalle Valo #define HE_VHT_SOUNDING_MODE		BIT(0)
2957d5c65159SKalle Valo /* SU or MU Sounding */
2958d5c65159SKalle Valo #define HE_SU_MU_SOUNDING_MODE		BIT(2)
2959d5c65159SKalle Valo /* Trig or Non-Trig Sounding */
2960d5c65159SKalle Valo #define HE_TRIG_NONTRIG_SOUNDING_MODE	BIT(3)
2961d5c65159SKalle Valo 
2962d5c65159SKalle Valo #define WMI_TXBF_STS_CAP_OFFSET_LSB	4
2963d5c65159SKalle Valo #define WMI_TXBF_STS_CAP_OFFSET_MASK	0x70
2964d5c65159SKalle Valo #define WMI_BF_SOUND_DIM_OFFSET_LSB	8
2965d5c65159SKalle Valo #define WMI_BF_SOUND_DIM_OFFSET_MASK	0x700
2966d5c65159SKalle Valo 
2967d5c65159SKalle Valo struct pdev_params {
2968d5c65159SKalle Valo 	u32 param_id;
2969d5c65159SKalle Valo 	u32 param_value;
2970d5c65159SKalle Valo };
2971d5c65159SKalle Valo 
2972d5c65159SKalle Valo enum wmi_peer_type {
2973d5c65159SKalle Valo 	WMI_PEER_TYPE_DEFAULT = 0,
2974d5c65159SKalle Valo 	WMI_PEER_TYPE_BSS = 1,
2975d5c65159SKalle Valo 	WMI_PEER_TYPE_TDLS = 2,
2976d5c65159SKalle Valo };
2977d5c65159SKalle Valo 
2978d5c65159SKalle Valo struct wmi_peer_create_cmd {
2979d5c65159SKalle Valo 	u32 tlv_header;
2980d5c65159SKalle Valo 	u32 vdev_id;
2981d5c65159SKalle Valo 	struct wmi_mac_addr peer_macaddr;
2982d5c65159SKalle Valo 	u32 peer_type;
2983d5c65159SKalle Valo } __packed;
2984d5c65159SKalle Valo 
2985d5c65159SKalle Valo struct wmi_peer_delete_cmd {
2986d5c65159SKalle Valo 	u32 tlv_header;
2987d5c65159SKalle Valo 	u32 vdev_id;
2988d5c65159SKalle Valo 	struct wmi_mac_addr peer_macaddr;
2989d5c65159SKalle Valo } __packed;
2990d5c65159SKalle Valo 
2991d5c65159SKalle Valo struct wmi_peer_reorder_queue_setup_cmd {
2992d5c65159SKalle Valo 	u32 tlv_header;
2993d5c65159SKalle Valo 	u32 vdev_id;
2994d5c65159SKalle Valo 	struct wmi_mac_addr peer_macaddr;
2995d5c65159SKalle Valo 	u32 tid;
2996d5c65159SKalle Valo 	u32 queue_ptr_lo;
2997d5c65159SKalle Valo 	u32 queue_ptr_hi;
2998d5c65159SKalle Valo 	u32 queue_no;
2999d5c65159SKalle Valo 	u32 ba_window_size_valid;
3000d5c65159SKalle Valo 	u32 ba_window_size;
3001d5c65159SKalle Valo } __packed;
3002d5c65159SKalle Valo 
3003d5c65159SKalle Valo struct wmi_peer_reorder_queue_remove_cmd {
3004d5c65159SKalle Valo 	u32 tlv_header;
3005d5c65159SKalle Valo 	u32 vdev_id;
3006d5c65159SKalle Valo 	struct wmi_mac_addr peer_macaddr;
3007d5c65159SKalle Valo 	u32 tid_mask;
3008d5c65159SKalle Valo } __packed;
3009d5c65159SKalle Valo 
3010d5c65159SKalle Valo struct gpio_config_params {
3011d5c65159SKalle Valo 	u32 gpio_num;
3012d5c65159SKalle Valo 	u32 input;
3013d5c65159SKalle Valo 	u32 pull_type;
3014d5c65159SKalle Valo 	u32 intr_mode;
3015d5c65159SKalle Valo };
3016d5c65159SKalle Valo 
3017d5c65159SKalle Valo enum wmi_gpio_type {
3018d5c65159SKalle Valo 	WMI_GPIO_PULL_NONE,
3019d5c65159SKalle Valo 	WMI_GPIO_PULL_UP,
3020d5c65159SKalle Valo 	WMI_GPIO_PULL_DOWN
3021d5c65159SKalle Valo };
3022d5c65159SKalle Valo 
3023d5c65159SKalle Valo enum wmi_gpio_intr_type {
3024d5c65159SKalle Valo 	WMI_GPIO_INTTYPE_DISABLE,
3025d5c65159SKalle Valo 	WMI_GPIO_INTTYPE_RISING_EDGE,
3026d5c65159SKalle Valo 	WMI_GPIO_INTTYPE_FALLING_EDGE,
3027d5c65159SKalle Valo 	WMI_GPIO_INTTYPE_BOTH_EDGE,
3028d5c65159SKalle Valo 	WMI_GPIO_INTTYPE_LEVEL_LOW,
3029d5c65159SKalle Valo 	WMI_GPIO_INTTYPE_LEVEL_HIGH
3030d5c65159SKalle Valo };
3031d5c65159SKalle Valo 
3032d5c65159SKalle Valo enum wmi_bss_chan_info_req_type {
3033d5c65159SKalle Valo 	WMI_BSS_SURVEY_REQ_TYPE_READ = 1,
3034d5c65159SKalle Valo 	WMI_BSS_SURVEY_REQ_TYPE_READ_CLEAR,
3035d5c65159SKalle Valo };
3036d5c65159SKalle Valo 
3037d5c65159SKalle Valo struct wmi_gpio_config_cmd_param {
3038d5c65159SKalle Valo 	u32 tlv_header;
3039d5c65159SKalle Valo 	u32 gpio_num;
3040d5c65159SKalle Valo 	u32 input;
3041d5c65159SKalle Valo 	u32 pull_type;
3042d5c65159SKalle Valo 	u32 intr_mode;
3043d5c65159SKalle Valo };
3044d5c65159SKalle Valo 
3045d5c65159SKalle Valo struct gpio_output_params {
3046d5c65159SKalle Valo 	u32 gpio_num;
3047d5c65159SKalle Valo 	u32 set;
3048d5c65159SKalle Valo };
3049d5c65159SKalle Valo 
3050d5c65159SKalle Valo struct wmi_gpio_output_cmd_param {
3051d5c65159SKalle Valo 	u32 tlv_header;
3052d5c65159SKalle Valo 	u32 gpio_num;
3053d5c65159SKalle Valo 	u32 set;
3054d5c65159SKalle Valo };
3055d5c65159SKalle Valo 
3056d5c65159SKalle Valo struct set_fwtest_params {
3057d5c65159SKalle Valo 	u32 arg;
3058d5c65159SKalle Valo 	u32 value;
3059d5c65159SKalle Valo };
3060d5c65159SKalle Valo 
3061d5c65159SKalle Valo struct wmi_fwtest_set_param_cmd_param {
3062d5c65159SKalle Valo 	u32 tlv_header;
3063d5c65159SKalle Valo 	u32 param_id;
3064d5c65159SKalle Valo 	u32 param_value;
3065d5c65159SKalle Valo };
3066d5c65159SKalle Valo 
3067d5c65159SKalle Valo struct wmi_pdev_set_param_cmd {
3068d5c65159SKalle Valo 	u32 tlv_header;
3069d5c65159SKalle Valo 	u32 pdev_id;
3070d5c65159SKalle Valo 	u32 param_id;
3071d5c65159SKalle Valo 	u32 param_value;
3072d5c65159SKalle Valo } __packed;
3073d5c65159SKalle Valo 
307497c63746SJohn Crispin struct wmi_pdev_set_ps_mode_cmd {
307597c63746SJohn Crispin 	u32 tlv_header;
307697c63746SJohn Crispin 	u32 vdev_id;
307797c63746SJohn Crispin 	u32 sta_ps_mode;
307897c63746SJohn Crispin } __packed;
307997c63746SJohn Crispin 
3080d5c65159SKalle Valo struct wmi_pdev_suspend_cmd {
3081d5c65159SKalle Valo 	u32 tlv_header;
3082d5c65159SKalle Valo 	u32 pdev_id;
3083d5c65159SKalle Valo 	u32 suspend_opt;
3084d5c65159SKalle Valo } __packed;
3085d5c65159SKalle Valo 
3086d5c65159SKalle Valo struct wmi_pdev_resume_cmd {
3087d5c65159SKalle Valo 	u32 tlv_header;
3088d5c65159SKalle Valo 	u32 pdev_id;
3089d5c65159SKalle Valo } __packed;
3090d5c65159SKalle Valo 
3091d5c65159SKalle Valo struct wmi_pdev_bss_chan_info_req_cmd {
3092d5c65159SKalle Valo 	u32 tlv_header;
3093d5c65159SKalle Valo 	/* ref wmi_bss_chan_info_req_type */
3094d5c65159SKalle Valo 	u32 req_type;
3095feab5bb8SSeevalamuthu Mariappan 	u32 pdev_id;
3096d5c65159SKalle Valo } __packed;
3097d5c65159SKalle Valo 
3098d5c65159SKalle Valo struct wmi_ap_ps_peer_cmd {
3099d5c65159SKalle Valo 	u32 tlv_header;
3100d5c65159SKalle Valo 	u32 vdev_id;
3101d5c65159SKalle Valo 	struct wmi_mac_addr peer_macaddr;
3102d5c65159SKalle Valo 	u32 param;
3103d5c65159SKalle Valo 	u32 value;
3104d5c65159SKalle Valo } __packed;
3105d5c65159SKalle Valo 
3106d5c65159SKalle Valo struct wmi_sta_powersave_param_cmd {
3107d5c65159SKalle Valo 	u32 tlv_header;
3108d5c65159SKalle Valo 	u32 vdev_id;
3109d5c65159SKalle Valo 	u32 param;
3110d5c65159SKalle Valo 	u32 value;
3111d5c65159SKalle Valo } __packed;
3112d5c65159SKalle Valo 
3113d5c65159SKalle Valo struct wmi_pdev_set_regdomain_cmd {
3114d5c65159SKalle Valo 	u32 tlv_header;
3115d5c65159SKalle Valo 	u32 pdev_id;
3116d5c65159SKalle Valo 	u32 reg_domain;
3117d5c65159SKalle Valo 	u32 reg_domain_2g;
3118d5c65159SKalle Valo 	u32 reg_domain_5g;
3119d5c65159SKalle Valo 	u32 conformance_test_limit_2g;
3120d5c65159SKalle Valo 	u32 conformance_test_limit_5g;
3121d5c65159SKalle Valo 	u32 dfs_domain;
3122d5c65159SKalle Valo } __packed;
3123d5c65159SKalle Valo 
3124d5c65159SKalle Valo struct wmi_peer_set_param_cmd {
3125d5c65159SKalle Valo 	u32 tlv_header;
3126d5c65159SKalle Valo 	u32 vdev_id;
3127d5c65159SKalle Valo 	struct wmi_mac_addr peer_macaddr;
3128d5c65159SKalle Valo 	u32 param_id;
3129d5c65159SKalle Valo 	u32 param_value;
3130d5c65159SKalle Valo } __packed;
3131d5c65159SKalle Valo 
3132d5c65159SKalle Valo struct wmi_peer_flush_tids_cmd {
3133d5c65159SKalle Valo 	u32 tlv_header;
3134d5c65159SKalle Valo 	u32 vdev_id;
3135d5c65159SKalle Valo 	struct wmi_mac_addr peer_macaddr;
3136d5c65159SKalle Valo 	u32 peer_tid_bitmap;
3137d5c65159SKalle Valo } __packed;
3138d5c65159SKalle Valo 
3139d5c65159SKalle Valo struct wmi_dfs_phyerr_offload_cmd {
3140d5c65159SKalle Valo 	u32 tlv_header;
3141d5c65159SKalle Valo 	u32 pdev_id;
3142d5c65159SKalle Valo } __packed;
3143d5c65159SKalle Valo 
3144d5c65159SKalle Valo struct wmi_bcn_offload_ctrl_cmd {
3145d5c65159SKalle Valo 	u32 tlv_header;
3146d5c65159SKalle Valo 	u32 vdev_id;
3147d5c65159SKalle Valo 	u32 bcn_ctrl_op;
3148d5c65159SKalle Valo } __packed;
3149d5c65159SKalle Valo 
3150d5c65159SKalle Valo enum scan_dwelltime_adaptive_mode {
3151d5c65159SKalle Valo 	SCAN_DWELL_MODE_DEFAULT = 0,
3152d5c65159SKalle Valo 	SCAN_DWELL_MODE_CONSERVATIVE = 1,
3153d5c65159SKalle Valo 	SCAN_DWELL_MODE_MODERATE = 2,
3154d5c65159SKalle Valo 	SCAN_DWELL_MODE_AGGRESSIVE = 3,
3155d5c65159SKalle Valo 	SCAN_DWELL_MODE_STATIC = 4
3156d5c65159SKalle Valo };
3157d5c65159SKalle Valo 
3158d5c65159SKalle Valo #define WLAN_SSID_MAX_LEN 32
3159d5c65159SKalle Valo 
3160d5c65159SKalle Valo struct element_info {
3161d5c65159SKalle Valo 	u32 len;
3162d5c65159SKalle Valo 	u8 *ptr;
3163d5c65159SKalle Valo };
3164d5c65159SKalle Valo 
3165d5c65159SKalle Valo struct wlan_ssid {
3166d5c65159SKalle Valo 	u8 length;
3167d5c65159SKalle Valo 	u8 ssid[WLAN_SSID_MAX_LEN];
3168d5c65159SKalle Valo };
3169d5c65159SKalle Valo 
3170d5c65159SKalle Valo #define WMI_IE_BITMAP_SIZE             8
3171d5c65159SKalle Valo 
3172d5c65159SKalle Valo /* prefix used by scan requestor ids on the host */
3173d5c65159SKalle Valo #define WMI_HOST_SCAN_REQUESTOR_ID_PREFIX 0xA000
3174d5c65159SKalle Valo 
3175d5c65159SKalle Valo /* prefix used by scan request ids generated on the host */
3176d5c65159SKalle Valo /* host cycles through the lower 12 bits to generate ids */
3177d5c65159SKalle Valo #define WMI_HOST_SCAN_REQ_ID_PREFIX 0xA000
3178d5c65159SKalle Valo 
3179d5c65159SKalle Valo /* Values lower than this may be refused by some firmware revisions with a scan
3180d5c65159SKalle Valo  * completion with a timedout reason.
3181d5c65159SKalle Valo  */
3182d5c65159SKalle Valo #define WMI_SCAN_CHAN_MIN_TIME_MSEC 40
3183d5c65159SKalle Valo 
3184d5c65159SKalle Valo /* Scan priority numbers must be sequential, starting with 0 */
3185d5c65159SKalle Valo enum wmi_scan_priority {
3186d5c65159SKalle Valo 	WMI_SCAN_PRIORITY_VERY_LOW = 0,
3187d5c65159SKalle Valo 	WMI_SCAN_PRIORITY_LOW,
3188d5c65159SKalle Valo 	WMI_SCAN_PRIORITY_MEDIUM,
3189d5c65159SKalle Valo 	WMI_SCAN_PRIORITY_HIGH,
3190d5c65159SKalle Valo 	WMI_SCAN_PRIORITY_VERY_HIGH,
3191d5c65159SKalle Valo 	WMI_SCAN_PRIORITY_COUNT   /* number of priorities supported */
3192d5c65159SKalle Valo };
3193d5c65159SKalle Valo 
3194d5c65159SKalle Valo enum wmi_scan_event_type {
3195d5c65159SKalle Valo 	WMI_SCAN_EVENT_STARTED              = BIT(0),
3196d5c65159SKalle Valo 	WMI_SCAN_EVENT_COMPLETED            = BIT(1),
3197d5c65159SKalle Valo 	WMI_SCAN_EVENT_BSS_CHANNEL          = BIT(2),
3198d5c65159SKalle Valo 	WMI_SCAN_EVENT_FOREIGN_CHAN         = BIT(3),
3199d5c65159SKalle Valo 	WMI_SCAN_EVENT_DEQUEUED             = BIT(4),
3200d5c65159SKalle Valo 	/* possibly by high-prio scan */
3201d5c65159SKalle Valo 	WMI_SCAN_EVENT_PREEMPTED            = BIT(5),
3202d5c65159SKalle Valo 	WMI_SCAN_EVENT_START_FAILED         = BIT(6),
3203d5c65159SKalle Valo 	WMI_SCAN_EVENT_RESTARTED            = BIT(7),
3204d5c65159SKalle Valo 	WMI_SCAN_EVENT_FOREIGN_CHAN_EXIT    = BIT(8),
3205d5c65159SKalle Valo 	WMI_SCAN_EVENT_SUSPENDED            = BIT(9),
3206d5c65159SKalle Valo 	WMI_SCAN_EVENT_RESUMED              = BIT(10),
3207d5c65159SKalle Valo 	WMI_SCAN_EVENT_MAX                  = BIT(15),
3208d5c65159SKalle Valo };
3209d5c65159SKalle Valo 
3210d5c65159SKalle Valo enum wmi_scan_completion_reason {
3211d5c65159SKalle Valo 	WMI_SCAN_REASON_COMPLETED,
3212d5c65159SKalle Valo 	WMI_SCAN_REASON_CANCELLED,
3213d5c65159SKalle Valo 	WMI_SCAN_REASON_PREEMPTED,
3214d5c65159SKalle Valo 	WMI_SCAN_REASON_TIMEDOUT,
3215d5c65159SKalle Valo 	WMI_SCAN_REASON_INTERNAL_FAILURE,
3216d5c65159SKalle Valo 	WMI_SCAN_REASON_MAX,
3217d5c65159SKalle Valo };
3218d5c65159SKalle Valo 
3219d5c65159SKalle Valo struct  wmi_start_scan_cmd {
3220d5c65159SKalle Valo 	u32 tlv_header;
3221d5c65159SKalle Valo 	u32 scan_id;
3222d5c65159SKalle Valo 	u32 scan_req_id;
3223d5c65159SKalle Valo 	u32 vdev_id;
3224d5c65159SKalle Valo 	u32 scan_priority;
3225d5c65159SKalle Valo 	u32 notify_scan_events;
3226d5c65159SKalle Valo 	u32 dwell_time_active;
3227d5c65159SKalle Valo 	u32 dwell_time_passive;
3228d5c65159SKalle Valo 	u32 min_rest_time;
3229d5c65159SKalle Valo 	u32 max_rest_time;
3230d5c65159SKalle Valo 	u32 repeat_probe_time;
3231d5c65159SKalle Valo 	u32 probe_spacing_time;
3232d5c65159SKalle Valo 	u32 idle_time;
3233d5c65159SKalle Valo 	u32 max_scan_time;
3234d5c65159SKalle Valo 	u32 probe_delay;
3235d5c65159SKalle Valo 	u32 scan_ctrl_flags;
3236d5c65159SKalle Valo 	u32 burst_duration;
3237d5c65159SKalle Valo 	u32 num_chan;
3238d5c65159SKalle Valo 	u32 num_bssid;
3239d5c65159SKalle Valo 	u32 num_ssids;
3240d5c65159SKalle Valo 	u32 ie_len;
3241d5c65159SKalle Valo 	u32 n_probes;
3242d5c65159SKalle Valo 	struct wmi_mac_addr mac_addr;
3243d5c65159SKalle Valo 	struct wmi_mac_addr mac_mask;
3244d5c65159SKalle Valo 	u32 ie_bitmap[WMI_IE_BITMAP_SIZE];
3245d5c65159SKalle Valo 	u32 num_vendor_oui;
3246d5c65159SKalle Valo 	u32 scan_ctrl_flags_ext;
3247d5c65159SKalle Valo 	u32 dwell_time_active_2g;
3248194b8ea1SPradeep Kumar Chitrapu 	u32 dwell_time_active_6g;
3249194b8ea1SPradeep Kumar Chitrapu 	u32 dwell_time_passive_6g;
3250194b8ea1SPradeep Kumar Chitrapu 	u32 scan_start_offset;
3251d5c65159SKalle Valo } __packed;
3252d5c65159SKalle Valo 
3253d5c65159SKalle Valo #define WMI_SCAN_FLAG_PASSIVE        0x1
3254d5c65159SKalle Valo #define WMI_SCAN_ADD_BCAST_PROBE_REQ 0x2
3255d5c65159SKalle Valo #define WMI_SCAN_ADD_CCK_RATES       0x4
3256d5c65159SKalle Valo #define WMI_SCAN_ADD_OFDM_RATES      0x8
3257d5c65159SKalle Valo #define WMI_SCAN_CHAN_STAT_EVENT     0x10
3258d5c65159SKalle Valo #define WMI_SCAN_FILTER_PROBE_REQ    0x20
3259d5c65159SKalle Valo #define WMI_SCAN_BYPASS_DFS_CHN      0x40
3260d5c65159SKalle Valo #define WMI_SCAN_CONTINUE_ON_ERROR   0x80
3261d5c65159SKalle Valo #define WMI_SCAN_FILTER_PROMISCUOS   0x100
3262d5c65159SKalle Valo #define WMI_SCAN_FLAG_FORCE_ACTIVE_ON_DFS 0x200
3263d5c65159SKalle Valo #define WMI_SCAN_ADD_TPC_IE_IN_PROBE_REQ  0x400
3264d5c65159SKalle Valo #define WMI_SCAN_ADD_DS_IE_IN_PROBE_REQ   0x800
3265d5c65159SKalle Valo #define WMI_SCAN_ADD_SPOOF_MAC_IN_PROBE_REQ   0x1000
3266d5c65159SKalle Valo #define WMI_SCAN_OFFCHAN_MGMT_TX    0x2000
3267d5c65159SKalle Valo #define WMI_SCAN_OFFCHAN_DATA_TX    0x4000
3268d5c65159SKalle Valo #define WMI_SCAN_CAPTURE_PHY_ERROR  0x8000
3269d5c65159SKalle Valo #define WMI_SCAN_FLAG_STRICT_PASSIVE_ON_PCHN 0x10000
3270d5c65159SKalle Valo #define WMI_SCAN_FLAG_HALF_RATE_SUPPORT      0x20000
3271d5c65159SKalle Valo #define WMI_SCAN_FLAG_QUARTER_RATE_SUPPORT   0x40000
3272d5c65159SKalle Valo #define WMI_SCAN_RANDOM_SEQ_NO_IN_PROBE_REQ 0x80000
3273d5c65159SKalle Valo #define WMI_SCAN_ENABLE_IE_WHTELIST_IN_PROBE_REQ 0x100000
3274d5c65159SKalle Valo 
3275d5c65159SKalle Valo #define WMI_SCAN_DWELL_MODE_MASK 0x00E00000
3276d5c65159SKalle Valo #define WMI_SCAN_DWELL_MODE_SHIFT        21
3277cf8f3d4dSTamizh Chelvam Raja #define WMI_SCAN_FLAG_EXT_PASSIVE_SCAN_START_TIME_ENHANCE   0x00000800
3278d5c65159SKalle Valo 
32798b4d2f08SManikanta Pubbisetty #define WMI_SCAN_CONFIG_PER_CHANNEL_MASK	GENMASK(19, 0)
32808b4d2f08SManikanta Pubbisetty #define WMI_SCAN_CH_FLAG_SCAN_ONLY_IF_RNR_FOUND	BIT(20)
32818b4d2f08SManikanta Pubbisetty 
3282d5c65159SKalle Valo enum {
3283d5c65159SKalle Valo 	WMI_SCAN_DWELL_MODE_DEFAULT      = 0,
3284d5c65159SKalle Valo 	WMI_SCAN_DWELL_MODE_CONSERVATIVE = 1,
3285d5c65159SKalle Valo 	WMI_SCAN_DWELL_MODE_MODERATE     = 2,
3286d5c65159SKalle Valo 	WMI_SCAN_DWELL_MODE_AGGRESSIVE   = 3,
3287d5c65159SKalle Valo 	WMI_SCAN_DWELL_MODE_STATIC       = 4,
3288d5c65159SKalle Valo };
3289d5c65159SKalle Valo 
3290d5c65159SKalle Valo #define WMI_SCAN_SET_DWELL_MODE(flag, mode) \
3291d5c65159SKalle Valo 	((flag) |= (((mode) << WMI_SCAN_DWELL_MODE_SHIFT) & \
3292d5c65159SKalle Valo 		    WMI_SCAN_DWELL_MODE_MASK))
3293d5c65159SKalle Valo 
329474601ecfSPradeep Kumar Chitrapu struct hint_short_ssid {
329574601ecfSPradeep Kumar Chitrapu 	u32 freq_flags;
329674601ecfSPradeep Kumar Chitrapu 	u32 short_ssid;
329774601ecfSPradeep Kumar Chitrapu };
329874601ecfSPradeep Kumar Chitrapu 
329974601ecfSPradeep Kumar Chitrapu struct hint_bssid {
330074601ecfSPradeep Kumar Chitrapu 	u32 freq_flags;
330174601ecfSPradeep Kumar Chitrapu 	struct wmi_mac_addr bssid;
330274601ecfSPradeep Kumar Chitrapu };
330374601ecfSPradeep Kumar Chitrapu 
3304d5c65159SKalle Valo struct scan_req_params {
3305d5c65159SKalle Valo 	u32 scan_id;
3306d5c65159SKalle Valo 	u32 scan_req_id;
3307d5c65159SKalle Valo 	u32 vdev_id;
3308d5c65159SKalle Valo 	u32 pdev_id;
3309509421acSNathan Chancellor 	enum wmi_scan_priority scan_priority;
3310d5c65159SKalle Valo 	union {
3311d5c65159SKalle Valo 		struct {
3312d5c65159SKalle Valo 			u32 scan_ev_started:1,
3313d5c65159SKalle Valo 			    scan_ev_completed:1,
3314d5c65159SKalle Valo 			    scan_ev_bss_chan:1,
3315d5c65159SKalle Valo 			    scan_ev_foreign_chan:1,
3316d5c65159SKalle Valo 			    scan_ev_dequeued:1,
3317d5c65159SKalle Valo 			    scan_ev_preempted:1,
3318d5c65159SKalle Valo 			    scan_ev_start_failed:1,
3319d5c65159SKalle Valo 			    scan_ev_restarted:1,
3320d5c65159SKalle Valo 			    scan_ev_foreign_chn_exit:1,
3321d5c65159SKalle Valo 			    scan_ev_invalid:1,
3322d5c65159SKalle Valo 			    scan_ev_gpio_timeout:1,
3323d5c65159SKalle Valo 			    scan_ev_suspended:1,
3324d5c65159SKalle Valo 			    scan_ev_resumed:1;
3325d5c65159SKalle Valo 		};
3326d5c65159SKalle Valo 		u32 scan_events;
3327d5c65159SKalle Valo 	};
3328cf8f3d4dSTamizh Chelvam Raja 	u32 scan_ctrl_flags_ext;
3329d5c65159SKalle Valo 	u32 dwell_time_active;
3330d5c65159SKalle Valo 	u32 dwell_time_active_2g;
3331d5c65159SKalle Valo 	u32 dwell_time_passive;
3332194b8ea1SPradeep Kumar Chitrapu 	u32 dwell_time_active_6g;
3333194b8ea1SPradeep Kumar Chitrapu 	u32 dwell_time_passive_6g;
3334d5c65159SKalle Valo 	u32 min_rest_time;
3335d5c65159SKalle Valo 	u32 max_rest_time;
3336d5c65159SKalle Valo 	u32 repeat_probe_time;
3337d5c65159SKalle Valo 	u32 probe_spacing_time;
3338d5c65159SKalle Valo 	u32 idle_time;
3339d5c65159SKalle Valo 	u32 max_scan_time;
3340d5c65159SKalle Valo 	u32 probe_delay;
3341d5c65159SKalle Valo 	union {
3342d5c65159SKalle Valo 		struct {
3343d5c65159SKalle Valo 			u32 scan_f_passive:1,
3344d5c65159SKalle Valo 			    scan_f_bcast_probe:1,
3345d5c65159SKalle Valo 			    scan_f_cck_rates:1,
3346d5c65159SKalle Valo 			    scan_f_ofdm_rates:1,
3347d5c65159SKalle Valo 			    scan_f_chan_stat_evnt:1,
3348d5c65159SKalle Valo 			    scan_f_filter_prb_req:1,
3349d5c65159SKalle Valo 			    scan_f_bypass_dfs_chn:1,
3350d5c65159SKalle Valo 			    scan_f_continue_on_err:1,
3351d5c65159SKalle Valo 			    scan_f_offchan_mgmt_tx:1,
3352d5c65159SKalle Valo 			    scan_f_offchan_data_tx:1,
3353d5c65159SKalle Valo 			    scan_f_promisc_mode:1,
3354d5c65159SKalle Valo 			    scan_f_capture_phy_err:1,
3355d5c65159SKalle Valo 			    scan_f_strict_passive_pch:1,
3356d5c65159SKalle Valo 			    scan_f_half_rate:1,
3357d5c65159SKalle Valo 			    scan_f_quarter_rate:1,
3358d5c65159SKalle Valo 			    scan_f_force_active_dfs_chn:1,
3359d5c65159SKalle Valo 			    scan_f_add_tpc_ie_in_probe:1,
3360d5c65159SKalle Valo 			    scan_f_add_ds_ie_in_probe:1,
3361d5c65159SKalle Valo 			    scan_f_add_spoofed_mac_in_probe:1,
3362d5c65159SKalle Valo 			    scan_f_add_rand_seq_in_probe:1,
3363d5c65159SKalle Valo 			    scan_f_en_ie_whitelist_in_probe:1,
3364d5c65159SKalle Valo 			    scan_f_forced:1,
3365d5c65159SKalle Valo 			    scan_f_2ghz:1,
3366d5c65159SKalle Valo 			    scan_f_5ghz:1,
3367d5c65159SKalle Valo 			    scan_f_80mhz:1;
3368d5c65159SKalle Valo 		};
3369d5c65159SKalle Valo 		u32 scan_flags;
3370d5c65159SKalle Valo 	};
3371d5c65159SKalle Valo 	enum scan_dwelltime_adaptive_mode adaptive_dwell_time_mode;
3372d5c65159SKalle Valo 	u32 burst_duration;
3373d5c65159SKalle Valo 	u32 num_chan;
3374d5c65159SKalle Valo 	u32 num_bssid;
3375d5c65159SKalle Valo 	u32 num_ssids;
3376d5c65159SKalle Valo 	u32 n_probes;
3377cea7f78dSWen Gong 	u32 *chan_list;
3378d5c65159SKalle Valo 	u32 notify_scan_events;
337950dc9ce9SKarthikeyan Kathirvel 	struct wlan_ssid ssid[WLAN_SCAN_PARAMS_MAX_SSID];
338050dc9ce9SKarthikeyan Kathirvel 	struct wmi_mac_addr bssid_list[WLAN_SCAN_PARAMS_MAX_BSSID];
3381d5c65159SKalle Valo 	struct element_info extraie;
3382d5c65159SKalle Valo 	struct element_info htcap;
3383d5c65159SKalle Valo 	struct element_info vhtcap;
338474601ecfSPradeep Kumar Chitrapu 	u32 num_hint_s_ssid;
338574601ecfSPradeep Kumar Chitrapu 	u32 num_hint_bssid;
338674601ecfSPradeep Kumar Chitrapu 	struct hint_short_ssid hint_s_ssid[WLAN_SCAN_MAX_HINT_S_SSID];
338774601ecfSPradeep Kumar Chitrapu 	struct hint_bssid hint_bssid[WLAN_SCAN_MAX_HINT_BSSID];
33889cbd7fc9SCarl Huang 	struct wmi_mac_addr mac_addr;
33899cbd7fc9SCarl Huang 	struct wmi_mac_addr mac_mask;
3390d5c65159SKalle Valo };
3391d5c65159SKalle Valo 
3392d5c65159SKalle Valo struct wmi_ssid_arg {
3393d5c65159SKalle Valo 	int len;
3394d5c65159SKalle Valo 	const u8 *ssid;
3395d5c65159SKalle Valo };
3396d5c65159SKalle Valo 
3397d5c65159SKalle Valo struct wmi_bssid_arg {
3398d5c65159SKalle Valo 	const u8 *bssid;
3399d5c65159SKalle Valo };
3400d5c65159SKalle Valo 
3401d5c65159SKalle Valo struct wmi_start_scan_arg {
3402d5c65159SKalle Valo 	u32 scan_id;
3403d5c65159SKalle Valo 	u32 scan_req_id;
3404d5c65159SKalle Valo 	u32 vdev_id;
3405d5c65159SKalle Valo 	u32 scan_priority;
3406d5c65159SKalle Valo 	u32 notify_scan_events;
3407d5c65159SKalle Valo 	u32 dwell_time_active;
3408d5c65159SKalle Valo 	u32 dwell_time_passive;
3409d5c65159SKalle Valo 	u32 min_rest_time;
3410d5c65159SKalle Valo 	u32 max_rest_time;
3411d5c65159SKalle Valo 	u32 repeat_probe_time;
3412d5c65159SKalle Valo 	u32 probe_spacing_time;
3413d5c65159SKalle Valo 	u32 idle_time;
3414d5c65159SKalle Valo 	u32 max_scan_time;
3415d5c65159SKalle Valo 	u32 probe_delay;
3416d5c65159SKalle Valo 	u32 scan_ctrl_flags;
3417d5c65159SKalle Valo 
3418d5c65159SKalle Valo 	u32 ie_len;
3419d5c65159SKalle Valo 	u32 n_channels;
3420d5c65159SKalle Valo 	u32 n_ssids;
3421d5c65159SKalle Valo 	u32 n_bssids;
3422d5c65159SKalle Valo 
3423d5c65159SKalle Valo 	u8 ie[WLAN_SCAN_PARAMS_MAX_IE_LEN];
3424d5c65159SKalle Valo 	u32 channels[64];
3425d5c65159SKalle Valo 	struct wmi_ssid_arg ssids[WLAN_SCAN_PARAMS_MAX_SSID];
3426d5c65159SKalle Valo 	struct wmi_bssid_arg bssids[WLAN_SCAN_PARAMS_MAX_BSSID];
3427d5c65159SKalle Valo };
3428d5c65159SKalle Valo 
3429d5c65159SKalle Valo #define WMI_SCAN_STOP_ONE       0x00000000
3430d5c65159SKalle Valo #define WMI_SCN_STOP_VAP_ALL    0x01000000
3431d5c65159SKalle Valo #define WMI_SCAN_STOP_ALL       0x04000000
3432d5c65159SKalle Valo 
3433d5c65159SKalle Valo /* Prefix 0xA000 indicates that the scan request
3434d5c65159SKalle Valo  * is trigger by HOST
3435d5c65159SKalle Valo  */
3436d5c65159SKalle Valo #define ATH11K_SCAN_ID          0xA000
3437d5c65159SKalle Valo 
3438d5c65159SKalle Valo enum scan_cancel_req_type {
3439d5c65159SKalle Valo 	WLAN_SCAN_CANCEL_SINGLE = 1,
3440d5c65159SKalle Valo 	WLAN_SCAN_CANCEL_VDEV_ALL,
3441d5c65159SKalle Valo 	WLAN_SCAN_CANCEL_PDEV_ALL,
3442d5c65159SKalle Valo };
3443d5c65159SKalle Valo 
3444d5c65159SKalle Valo struct scan_cancel_param {
3445d5c65159SKalle Valo 	u32 requester;
3446d5c65159SKalle Valo 	u32 scan_id;
3447d5c65159SKalle Valo 	enum scan_cancel_req_type req_type;
3448d5c65159SKalle Valo 	u32 vdev_id;
3449d5c65159SKalle Valo 	u32 pdev_id;
3450d5c65159SKalle Valo };
3451d5c65159SKalle Valo 
3452d5c65159SKalle Valo struct  wmi_bcn_send_from_host_cmd {
3453d5c65159SKalle Valo 	u32 tlv_header;
3454d5c65159SKalle Valo 	u32 vdev_id;
3455d5c65159SKalle Valo 	u32 data_len;
3456d5c65159SKalle Valo 	union {
3457d5c65159SKalle Valo 		u32 frag_ptr;
3458d5c65159SKalle Valo 		u32 frag_ptr_lo;
3459d5c65159SKalle Valo 	};
3460d5c65159SKalle Valo 	u32 frame_ctrl;
3461d5c65159SKalle Valo 	u32 dtim_flag;
3462d5c65159SKalle Valo 	u32 bcn_antenna;
3463d5c65159SKalle Valo 	u32 frag_ptr_hi;
3464d5c65159SKalle Valo };
3465d5c65159SKalle Valo 
3466d5c65159SKalle Valo #define WMI_CHAN_INFO_MODE		GENMASK(5, 0)
3467d5c65159SKalle Valo #define WMI_CHAN_INFO_HT40_PLUS		BIT(6)
3468d5c65159SKalle Valo #define WMI_CHAN_INFO_PASSIVE		BIT(7)
3469d5c65159SKalle Valo #define WMI_CHAN_INFO_ADHOC_ALLOWED	BIT(8)
3470d5c65159SKalle Valo #define WMI_CHAN_INFO_AP_DISABLED	BIT(9)
3471d5c65159SKalle Valo #define WMI_CHAN_INFO_DFS		BIT(10)
3472d5c65159SKalle Valo #define WMI_CHAN_INFO_ALLOW_HT		BIT(11)
3473d5c65159SKalle Valo #define WMI_CHAN_INFO_ALLOW_VHT		BIT(12)
3474d5c65159SKalle Valo #define WMI_CHAN_INFO_CHAN_CHANGE_CAUSE_CSA	BIT(13)
3475d5c65159SKalle Valo #define WMI_CHAN_INFO_HALF_RATE		BIT(14)
3476d5c65159SKalle Valo #define WMI_CHAN_INFO_QUARTER_RATE	BIT(15)
3477d5c65159SKalle Valo #define WMI_CHAN_INFO_DFS_FREQ2		BIT(16)
3478d5c65159SKalle Valo #define WMI_CHAN_INFO_ALLOW_HE		BIT(17)
3479bff621fdSPradeep Kumar Chitrapu #define WMI_CHAN_INFO_PSC		BIT(18)
3480d5c65159SKalle Valo 
3481d5c65159SKalle Valo #define WMI_CHAN_REG_INFO1_MIN_PWR	GENMASK(7, 0)
3482d5c65159SKalle Valo #define WMI_CHAN_REG_INFO1_MAX_PWR	GENMASK(15, 8)
3483d5c65159SKalle Valo #define WMI_CHAN_REG_INFO1_MAX_REG_PWR	GENMASK(23, 16)
3484d5c65159SKalle Valo #define WMI_CHAN_REG_INFO1_REG_CLS	GENMASK(31, 24)
3485d5c65159SKalle Valo 
3486d5c65159SKalle Valo #define WMI_CHAN_REG_INFO2_ANT_MAX	GENMASK(7, 0)
3487d5c65159SKalle Valo #define WMI_CHAN_REG_INFO2_MAX_TX_PWR	GENMASK(15, 8)
3488d5c65159SKalle Valo 
3489d5c65159SKalle Valo struct wmi_channel {
3490d5c65159SKalle Valo 	u32 tlv_header;
3491d5c65159SKalle Valo 	u32 mhz;
3492d5c65159SKalle Valo 	u32 band_center_freq1;
3493d5c65159SKalle Valo 	u32 band_center_freq2;
3494d5c65159SKalle Valo 	u32 info;
3495d5c65159SKalle Valo 	u32 reg_info_1;
3496d5c65159SKalle Valo 	u32 reg_info_2;
3497d5c65159SKalle Valo } __packed;
3498d5c65159SKalle Valo 
3499d5c65159SKalle Valo struct wmi_mgmt_params {
3500d5c65159SKalle Valo 	void *tx_frame;
3501d5c65159SKalle Valo 	u16 frm_len;
3502d5c65159SKalle Valo 	u8 vdev_id;
3503d5c65159SKalle Valo 	u16 chanfreq;
3504d5c65159SKalle Valo 	void *pdata;
3505d5c65159SKalle Valo 	u16 desc_id;
3506d5c65159SKalle Valo 	u8 *macaddr;
3507d5c65159SKalle Valo };
3508d5c65159SKalle Valo 
3509d5c65159SKalle Valo enum wmi_sta_ps_mode {
3510d5c65159SKalle Valo 	WMI_STA_PS_MODE_DISABLED = 0,
3511d5c65159SKalle Valo 	WMI_STA_PS_MODE_ENABLED = 1,
3512d5c65159SKalle Valo };
3513d5c65159SKalle Valo 
3514d5c65159SKalle Valo #define WMI_SMPS_MASK_LOWER_16BITS 0xFF
3515d5c65159SKalle Valo #define WMI_SMPS_MASK_UPPER_3BITS 0x7
3516d5c65159SKalle Valo #define WMI_SMPS_PARAM_VALUE_SHIFT 29
3517d5c65159SKalle Valo 
3518d5c65159SKalle Valo #define ATH11K_WMI_FW_HANG_ASSERT_TYPE 1
3519d5c65159SKalle Valo #define ATH11K_WMI_FW_HANG_DELAY 0
3520d5c65159SKalle Valo 
3521d5c65159SKalle Valo /* type, 0:unused 1: ASSERT 2: not respond detect command
3522d5c65159SKalle Valo  * delay_time_ms, the simulate will delay time
3523d5c65159SKalle Valo  */
3524d5c65159SKalle Valo 
3525d5c65159SKalle Valo struct wmi_force_fw_hang_cmd {
3526d5c65159SKalle Valo 	u32 tlv_header;
3527d5c65159SKalle Valo 	u32 type;
3528d5c65159SKalle Valo 	u32 delay_time_ms;
3529d5c65159SKalle Valo };
3530d5c65159SKalle Valo 
3531d5c65159SKalle Valo struct wmi_vdev_set_param_cmd {
3532d5c65159SKalle Valo 	u32 tlv_header;
3533d5c65159SKalle Valo 	u32 vdev_id;
3534d5c65159SKalle Valo 	u32 param_id;
3535d5c65159SKalle Valo 	u32 param_value;
3536d5c65159SKalle Valo } __packed;
3537d5c65159SKalle Valo 
3538d5c65159SKalle Valo enum wmi_stats_id {
3539d5c65159SKalle Valo 	WMI_REQUEST_PEER_STAT			= BIT(0),
3540d5c65159SKalle Valo 	WMI_REQUEST_AP_STAT			= BIT(1),
3541d5c65159SKalle Valo 	WMI_REQUEST_PDEV_STAT			= BIT(2),
3542d5c65159SKalle Valo 	WMI_REQUEST_VDEV_STAT			= BIT(3),
3543d5c65159SKalle Valo 	WMI_REQUEST_BCNFLT_STAT			= BIT(4),
3544d5c65159SKalle Valo 	WMI_REQUEST_VDEV_RATE_STAT		= BIT(5),
3545d5c65159SKalle Valo 	WMI_REQUEST_INST_STAT			= BIT(6),
3546d5c65159SKalle Valo 	WMI_REQUEST_MIB_STAT			= BIT(7),
3547d5c65159SKalle Valo 	WMI_REQUEST_RSSI_PER_CHAIN_STAT		= BIT(8),
3548d5c65159SKalle Valo 	WMI_REQUEST_CONGESTION_STAT		= BIT(9),
3549d5c65159SKalle Valo 	WMI_REQUEST_PEER_EXTD_STAT		= BIT(10),
3550d5c65159SKalle Valo 	WMI_REQUEST_BCN_STAT			= BIT(11),
3551d5c65159SKalle Valo 	WMI_REQUEST_BCN_STAT_RESET		= BIT(12),
3552d5c65159SKalle Valo 	WMI_REQUEST_PEER_EXTD2_STAT		= BIT(13),
3553d5c65159SKalle Valo };
3554d5c65159SKalle Valo 
3555d5c65159SKalle Valo struct wmi_request_stats_cmd {
3556d5c65159SKalle Valo 	u32 tlv_header;
3557d5c65159SKalle Valo 	enum wmi_stats_id stats_id;
3558d5c65159SKalle Valo 	u32 vdev_id;
3559d5c65159SKalle Valo 	struct wmi_mac_addr peer_macaddr;
3560d5c65159SKalle Valo 	u32 pdev_id;
3561d5c65159SKalle Valo } __packed;
3562d5c65159SKalle Valo 
3563a41d1034SPradeep Kumar Chitrapu struct wmi_get_pdev_temperature_cmd {
3564a41d1034SPradeep Kumar Chitrapu 	u32 tlv_header;
3565a41d1034SPradeep Kumar Chitrapu 	u32 param;
3566a41d1034SPradeep Kumar Chitrapu 	u32 pdev_id;
3567a41d1034SPradeep Kumar Chitrapu } __packed;
3568a41d1034SPradeep Kumar Chitrapu 
3569b43310e4SGovindaraj Saminathan struct wmi_ftm_seg_hdr {
3570b43310e4SGovindaraj Saminathan 	u32 len;
3571b43310e4SGovindaraj Saminathan 	u32 msgref;
3572b43310e4SGovindaraj Saminathan 	u32 segmentinfo;
3573b43310e4SGovindaraj Saminathan 	u32 pdev_id;
3574b43310e4SGovindaraj Saminathan } __packed;
3575b43310e4SGovindaraj Saminathan 
3576b43310e4SGovindaraj Saminathan struct wmi_ftm_cmd {
3577b43310e4SGovindaraj Saminathan 	u32 tlv_header;
3578b43310e4SGovindaraj Saminathan 	struct wmi_ftm_seg_hdr seg_hdr;
3579b43310e4SGovindaraj Saminathan 	u8 data[];
3580b43310e4SGovindaraj Saminathan } __packed;
3581b43310e4SGovindaraj Saminathan 
3582b43310e4SGovindaraj Saminathan struct wmi_ftm_event_msg {
3583b43310e4SGovindaraj Saminathan 	struct wmi_ftm_seg_hdr seg_hdr;
3584b43310e4SGovindaraj Saminathan 	u8 data[];
3585b43310e4SGovindaraj Saminathan } __packed;
3586b43310e4SGovindaraj Saminathan 
3587d5c65159SKalle Valo #define WMI_BEACON_TX_BUFFER_SIZE	512
3588d5c65159SKalle Valo 
358987bd4011SAloka Dixit #define WMI_EMA_TMPL_IDX_SHIFT            8
359087bd4011SAloka Dixit #define WMI_EMA_FIRST_TMPL_SHIFT          16
359187bd4011SAloka Dixit #define WMI_EMA_LAST_TMPL_SHIFT           24
359287bd4011SAloka Dixit 
3593d5c65159SKalle Valo struct wmi_bcn_tmpl_cmd {
3594d5c65159SKalle Valo 	u32 tlv_header;
3595d5c65159SKalle Valo 	u32 vdev_id;
3596d5c65159SKalle Valo 	u32 tim_ie_offset;
3597d5c65159SKalle Valo 	u32 buf_len;
3598d5c65159SKalle Valo 	u32 csa_switch_count_offset;
3599d5c65159SKalle Valo 	u32 ext_csa_switch_count_offset;
3600d5c65159SKalle Valo 	u32 csa_event_bitmap;
3601d5c65159SKalle Valo 	u32 mbssid_ie_offset;
3602d5c65159SKalle Valo 	u32 esp_ie_offset;
360387bd4011SAloka Dixit 	u32 csc_switch_count_offset;
360487bd4011SAloka Dixit 	u32 csc_event_bitmap;
360587bd4011SAloka Dixit 	u32 mu_edca_ie_offset;
360687bd4011SAloka Dixit 	u32 feature_enable_bitmap;
360787bd4011SAloka Dixit 	u32 ema_params;
3608d5c65159SKalle Valo } __packed;
3609d5c65159SKalle Valo 
3610d5c65159SKalle Valo struct wmi_key_seq_counter {
3611d5c65159SKalle Valo 	u32 key_seq_counter_l;
3612d5c65159SKalle Valo 	u32 key_seq_counter_h;
3613d5c65159SKalle Valo } __packed;
3614d5c65159SKalle Valo 
3615d5c65159SKalle Valo struct wmi_vdev_install_key_cmd {
3616d5c65159SKalle Valo 	u32 tlv_header;
3617d5c65159SKalle Valo 	u32 vdev_id;
3618d5c65159SKalle Valo 	struct wmi_mac_addr peer_macaddr;
3619d5c65159SKalle Valo 	u32 key_idx;
3620d5c65159SKalle Valo 	u32 key_flags;
3621d5c65159SKalle Valo 	u32 key_cipher;
3622d5c65159SKalle Valo 	struct wmi_key_seq_counter key_rsc_counter;
3623d5c65159SKalle Valo 	struct wmi_key_seq_counter key_global_rsc_counter;
3624d5c65159SKalle Valo 	struct wmi_key_seq_counter key_tsc_counter;
3625d5c65159SKalle Valo 	u8 wpi_key_rsc_counter[16];
3626d5c65159SKalle Valo 	u8 wpi_key_tsc_counter[16];
3627d5c65159SKalle Valo 	u32 key_len;
3628d5c65159SKalle Valo 	u32 key_txmic_len;
3629d5c65159SKalle Valo 	u32 key_rxmic_len;
3630d5c65159SKalle Valo 	u32 is_group_key_id_valid;
3631d5c65159SKalle Valo 	u32 group_key_id;
3632d5c65159SKalle Valo 
3633d5c65159SKalle Valo 	/* Followed by key_data containing key followed by
3634d5c65159SKalle Valo 	 * tx mic and then rx mic
3635d5c65159SKalle Valo 	 */
3636d5c65159SKalle Valo } __packed;
3637d5c65159SKalle Valo 
3638d5c65159SKalle Valo struct wmi_vdev_install_key_arg {
3639d5c65159SKalle Valo 	u32 vdev_id;
3640d5c65159SKalle Valo 	const u8 *macaddr;
3641d5c65159SKalle Valo 	u32 key_idx;
3642d5c65159SKalle Valo 	u32 key_flags;
3643d5c65159SKalle Valo 	u32 key_cipher;
3644d5c65159SKalle Valo 	u32 key_len;
3645d5c65159SKalle Valo 	u32 key_txmic_len;
3646d5c65159SKalle Valo 	u32 key_rxmic_len;
3647d5c65159SKalle Valo 	u64 key_rsc_counter;
3648d5c65159SKalle Valo 	const void *key_data;
3649d5c65159SKalle Valo };
3650d5c65159SKalle Valo 
3651d5c65159SKalle Valo #define WMI_MAX_SUPPORTED_RATES			128
3652d5c65159SKalle Valo #define WMI_HOST_MAX_HECAP_PHY_SIZE		3
36539f056ed8SJohn Crispin #define WMI_HOST_MAX_HE_RATE_SET		3
36549f056ed8SJohn Crispin #define WMI_HECAP_TXRX_MCS_NSS_IDX_80		0
36559f056ed8SJohn Crispin #define WMI_HECAP_TXRX_MCS_NSS_IDX_160		1
36569f056ed8SJohn Crispin #define WMI_HECAP_TXRX_MCS_NSS_IDX_80_80	2
3657d5c65159SKalle Valo 
3658d5c65159SKalle Valo struct wmi_rate_set_arg {
3659d5c65159SKalle Valo 	u32 num_rates;
3660d5c65159SKalle Valo 	u8 rates[WMI_MAX_SUPPORTED_RATES];
3661d5c65159SKalle Valo };
3662d5c65159SKalle Valo 
3663d5c65159SKalle Valo struct peer_assoc_params {
3664d5c65159SKalle Valo 	struct wmi_mac_addr peer_macaddr;
3665d5c65159SKalle Valo 	u32 vdev_id;
3666d5c65159SKalle Valo 	u32 peer_new_assoc;
3667d5c65159SKalle Valo 	u32 peer_associd;
3668d5c65159SKalle Valo 	u32 peer_flags;
3669d5c65159SKalle Valo 	u32 peer_caps;
3670d5c65159SKalle Valo 	u32 peer_listen_intval;
3671d5c65159SKalle Valo 	u32 peer_ht_caps;
3672d5c65159SKalle Valo 	u32 peer_max_mpdu;
3673d5c65159SKalle Valo 	u32 peer_mpdu_density;
3674d5c65159SKalle Valo 	u32 peer_rate_caps;
3675d5c65159SKalle Valo 	u32 peer_nss;
3676d5c65159SKalle Valo 	u32 peer_vht_caps;
3677d5c65159SKalle Valo 	u32 peer_phymode;
3678d5c65159SKalle Valo 	u32 peer_ht_info[2];
3679d5c65159SKalle Valo 	struct wmi_rate_set_arg peer_legacy_rates;
3680d5c65159SKalle Valo 	struct wmi_rate_set_arg peer_ht_rates;
3681d5c65159SKalle Valo 	u32 rx_max_rate;
3682d5c65159SKalle Valo 	u32 rx_mcs_set;
3683d5c65159SKalle Valo 	u32 tx_max_rate;
3684d5c65159SKalle Valo 	u32 tx_mcs_set;
3685d5c65159SKalle Valo 	u8 vht_capable;
368691270d70SPradeep Kumar Chitrapu 	u8 min_data_rate;
3687d5c65159SKalle Valo 	u32 tx_max_mcs_nss;
3688d5c65159SKalle Valo 	u32 peer_bw_rxnss_override;
3689d5c65159SKalle Valo 	bool is_pmf_enabled;
3690d5c65159SKalle Valo 	bool is_wme_set;
3691d5c65159SKalle Valo 	bool qos_flag;
3692d5c65159SKalle Valo 	bool apsd_flag;
3693d5c65159SKalle Valo 	bool ht_flag;
3694d5c65159SKalle Valo 	bool bw_40;
3695d5c65159SKalle Valo 	bool bw_80;
3696d5c65159SKalle Valo 	bool bw_160;
3697d5c65159SKalle Valo 	bool stbc_flag;
3698d5c65159SKalle Valo 	bool ldpc_flag;
3699d5c65159SKalle Valo 	bool static_mimops_flag;
3700d5c65159SKalle Valo 	bool dynamic_mimops_flag;
3701d5c65159SKalle Valo 	bool spatial_mux_flag;
3702d5c65159SKalle Valo 	bool vht_flag;
3703d5c65159SKalle Valo 	bool vht_ng_flag;
3704d5c65159SKalle Valo 	bool need_ptk_4_way;
3705d5c65159SKalle Valo 	bool need_gtk_2_way;
3706d5c65159SKalle Valo 	bool auth_flag;
3707d5c65159SKalle Valo 	bool safe_mode_enabled;
3708d5c65159SKalle Valo 	bool amsdu_disable;
3709d5c65159SKalle Valo 	/* Use common structure */
3710d5c65159SKalle Valo 	u8 peer_mac[ETH_ALEN];
3711d5c65159SKalle Valo 
3712d5c65159SKalle Valo 	bool he_flag;
3713d5c65159SKalle Valo 	u32 peer_he_cap_macinfo[2];
3714d5c65159SKalle Valo 	u32 peer_he_cap_macinfo_internal;
371591270d70SPradeep Kumar Chitrapu 	u32 peer_he_caps_6ghz;
3716d5c65159SKalle Valo 	u32 peer_he_ops;
3717d5c65159SKalle Valo 	u32 peer_he_cap_phyinfo[WMI_HOST_MAX_HECAP_PHY_SIZE];
3718d5c65159SKalle Valo 	u32 peer_he_mcs_count;
3719d5c65159SKalle Valo 	u32 peer_he_rx_mcs_set[WMI_HOST_MAX_HE_RATE_SET];
3720d5c65159SKalle Valo 	u32 peer_he_tx_mcs_set[WMI_HOST_MAX_HE_RATE_SET];
37216d293d44SJohn Crispin 	bool twt_responder;
37226d293d44SJohn Crispin 	bool twt_requester;
3723c802b6d7SRameshkumar Sundaram 	bool is_assoc;
3724d5c65159SKalle Valo 	struct ath11k_ppe_threshold peer_ppet;
3725d5c65159SKalle Valo };
3726d5c65159SKalle Valo 
3727d5c65159SKalle Valo struct  wmi_peer_assoc_complete_cmd {
3728d5c65159SKalle Valo 	u32 tlv_header;
3729d5c65159SKalle Valo 	struct wmi_mac_addr peer_macaddr;
3730d5c65159SKalle Valo 	u32 vdev_id;
3731d5c65159SKalle Valo 	u32 peer_new_assoc;
3732d5c65159SKalle Valo 	u32 peer_associd;
3733d5c65159SKalle Valo 	u32 peer_flags;
3734d5c65159SKalle Valo 	u32 peer_caps;
3735d5c65159SKalle Valo 	u32 peer_listen_intval;
3736d5c65159SKalle Valo 	u32 peer_ht_caps;
3737d5c65159SKalle Valo 	u32 peer_max_mpdu;
3738d5c65159SKalle Valo 	u32 peer_mpdu_density;
3739d5c65159SKalle Valo 	u32 peer_rate_caps;
3740d5c65159SKalle Valo 	u32 peer_nss;
3741d5c65159SKalle Valo 	u32 peer_vht_caps;
3742d5c65159SKalle Valo 	u32 peer_phymode;
3743d5c65159SKalle Valo 	u32 peer_ht_info[2];
3744d5c65159SKalle Valo 	u32 num_peer_legacy_rates;
3745d5c65159SKalle Valo 	u32 num_peer_ht_rates;
3746d5c65159SKalle Valo 	u32 peer_bw_rxnss_override;
3747d5c65159SKalle Valo 	struct  wmi_ppe_threshold peer_ppet;
3748d5c65159SKalle Valo 	u32 peer_he_cap_info;
3749d5c65159SKalle Valo 	u32 peer_he_ops;
3750d5c65159SKalle Valo 	u32 peer_he_cap_phy[WMI_MAX_HECAP_PHY_SIZE];
3751d5c65159SKalle Valo 	u32 peer_he_mcs;
3752d5c65159SKalle Valo 	u32 peer_he_cap_info_ext;
3753d5c65159SKalle Valo 	u32 peer_he_cap_info_internal;
375491270d70SPradeep Kumar Chitrapu 	u32 min_data_rate;
375591270d70SPradeep Kumar Chitrapu 	u32 peer_he_caps_6ghz;
3756d5c65159SKalle Valo } __packed;
3757d5c65159SKalle Valo 
3758d5c65159SKalle Valo struct wmi_stop_scan_cmd {
3759d5c65159SKalle Valo 	u32 tlv_header;
3760d5c65159SKalle Valo 	u32 requestor;
3761d5c65159SKalle Valo 	u32 scan_id;
3762d5c65159SKalle Valo 	u32 req_type;
3763d5c65159SKalle Valo 	u32 vdev_id;
3764d5c65159SKalle Valo 	u32 pdev_id;
3765d5c65159SKalle Valo };
3766d5c65159SKalle Valo 
3767d5c65159SKalle Valo struct scan_chan_list_params {
3768d5c65159SKalle Valo 	u32 pdev_id;
3769d5c65159SKalle Valo 	u16 nallchans;
3770b2549465SGustavo A. R. Silva 	struct channel_param ch_param[];
3771d5c65159SKalle Valo };
3772d5c65159SKalle Valo 
3773d5c65159SKalle Valo struct wmi_scan_chan_list_cmd {
3774d5c65159SKalle Valo 	u32 tlv_header;
3775d5c65159SKalle Valo 	u32 num_scan_chans;
3776d5c65159SKalle Valo 	u32 flags;
3777d5c65159SKalle Valo 	u32 pdev_id;
3778d5c65159SKalle Valo } __packed;
3779d5c65159SKalle Valo 
37809cbd7fc9SCarl Huang struct wmi_scan_prob_req_oui_cmd {
37819cbd7fc9SCarl Huang 	u32 tlv_header;
37829cbd7fc9SCarl Huang 	u32 prob_req_oui;
37839cbd7fc9SCarl Huang }  __packed;
37849cbd7fc9SCarl Huang 
3785d5c65159SKalle Valo #define WMI_MGMT_SEND_DOWNLD_LEN	64
3786d5c65159SKalle Valo 
3787d5c65159SKalle Valo #define WMI_TX_PARAMS_DWORD0_POWER		GENMASK(7, 0)
3788d5c65159SKalle Valo #define WMI_TX_PARAMS_DWORD0_MCS_MASK		GENMASK(19, 8)
3789d5c65159SKalle Valo #define WMI_TX_PARAMS_DWORD0_NSS_MASK		GENMASK(27, 20)
3790d5c65159SKalle Valo #define WMI_TX_PARAMS_DWORD0_RETRY_LIMIT	GENMASK(31, 28)
3791d5c65159SKalle Valo 
3792d5c65159SKalle Valo #define WMI_TX_PARAMS_DWORD1_CHAIN_MASK		GENMASK(7, 0)
3793d5c65159SKalle Valo #define WMI_TX_PARAMS_DWORD1_BW_MASK		GENMASK(14, 8)
3794d5c65159SKalle Valo #define WMI_TX_PARAMS_DWORD1_PREAMBLE_TYPE	GENMASK(19, 15)
3795d5c65159SKalle Valo #define WMI_TX_PARAMS_DWORD1_FRAME_TYPE		BIT(20)
3796d5c65159SKalle Valo #define WMI_TX_PARAMS_DWORD1_RSVD		GENMASK(31, 21)
3797d5c65159SKalle Valo 
3798d5c65159SKalle Valo struct wmi_mgmt_send_params {
3799d5c65159SKalle Valo 	u32 tlv_header;
3800d5c65159SKalle Valo 	u32 tx_params_dword0;
3801d5c65159SKalle Valo 	u32 tx_params_dword1;
3802d5c65159SKalle Valo };
3803d5c65159SKalle Valo 
3804d5c65159SKalle Valo struct wmi_mgmt_send_cmd {
3805d5c65159SKalle Valo 	u32 tlv_header;
3806d5c65159SKalle Valo 	u32 vdev_id;
3807d5c65159SKalle Valo 	u32 desc_id;
3808d5c65159SKalle Valo 	u32 chanfreq;
3809d5c65159SKalle Valo 	u32 paddr_lo;
3810d5c65159SKalle Valo 	u32 paddr_hi;
3811d5c65159SKalle Valo 	u32 frame_len;
3812d5c65159SKalle Valo 	u32 buf_len;
3813d5c65159SKalle Valo 	u32 tx_params_valid;
3814d5c65159SKalle Valo 
3815d5c65159SKalle Valo 	/* This TLV is followed by struct wmi_mgmt_frame */
3816d5c65159SKalle Valo 
3817d5c65159SKalle Valo 	/* Followed by struct wmi_mgmt_send_params */
3818d5c65159SKalle Valo } __packed;
3819d5c65159SKalle Valo 
3820d5c65159SKalle Valo struct wmi_sta_powersave_mode_cmd {
3821d5c65159SKalle Valo 	u32 tlv_header;
3822d5c65159SKalle Valo 	u32 vdev_id;
3823d5c65159SKalle Valo 	u32 sta_ps_mode;
3824d5c65159SKalle Valo };
3825d5c65159SKalle Valo 
3826d5c65159SKalle Valo struct wmi_sta_smps_force_mode_cmd {
3827d5c65159SKalle Valo 	u32 tlv_header;
3828d5c65159SKalle Valo 	u32 vdev_id;
3829d5c65159SKalle Valo 	u32 forced_mode;
3830d5c65159SKalle Valo };
3831d5c65159SKalle Valo 
3832d5c65159SKalle Valo struct wmi_sta_smps_param_cmd {
3833d5c65159SKalle Valo 	u32 tlv_header;
3834d5c65159SKalle Valo 	u32 vdev_id;
3835d5c65159SKalle Valo 	u32 param;
3836d5c65159SKalle Valo 	u32 value;
3837d5c65159SKalle Valo };
3838d5c65159SKalle Valo 
3839d5c65159SKalle Valo struct wmi_bcn_prb_info {
3840d5c65159SKalle Valo 	u32 tlv_header;
3841d5c65159SKalle Valo 	u32 caps;
3842d5c65159SKalle Valo 	u32 erp;
3843d5c65159SKalle Valo } __packed;
3844d5c65159SKalle Valo 
3845d5c65159SKalle Valo enum {
3846d5c65159SKalle Valo 	WMI_PDEV_SUSPEND,
3847d5c65159SKalle Valo 	WMI_PDEV_SUSPEND_AND_DISABLE_INTR,
3848d5c65159SKalle Valo };
3849d5c65159SKalle Valo 
3850d5c65159SKalle Valo struct green_ap_ps_params {
3851d5c65159SKalle Valo 	u32 value;
3852d5c65159SKalle Valo };
3853d5c65159SKalle Valo 
3854d5c65159SKalle Valo struct wmi_pdev_green_ap_ps_enable_cmd_param {
3855d5c65159SKalle Valo 	u32 tlv_header;
3856d5c65159SKalle Valo 	u32 pdev_id;
3857d5c65159SKalle Valo 	u32 enable;
3858d5c65159SKalle Valo };
3859d5c65159SKalle Valo 
3860d5c65159SKalle Valo struct ap_ps_params {
3861d5c65159SKalle Valo 	u32 vdev_id;
3862d5c65159SKalle Valo 	u32 param;
3863d5c65159SKalle Valo 	u32 value;
3864d5c65159SKalle Valo };
3865d5c65159SKalle Valo 
3866d5c65159SKalle Valo struct vdev_set_params {
3867d5c65159SKalle Valo 	u32 if_id;
3868d5c65159SKalle Valo 	u32 param_id;
3869d5c65159SKalle Valo 	u32 param_value;
3870d5c65159SKalle Valo };
3871d5c65159SKalle Valo 
3872d5c65159SKalle Valo struct stats_request_params {
3873d5c65159SKalle Valo 	u32 stats_id;
3874d5c65159SKalle Valo 	u32 vdev_id;
3875d5c65159SKalle Valo 	u32 pdev_id;
3876d5c65159SKalle Valo };
3877d5c65159SKalle Valo 
38780b05ddadSWen Gong struct wmi_set_current_country_params {
38790b05ddadSWen Gong 	u8 alpha2[3];
38800b05ddadSWen Gong };
38810b05ddadSWen Gong 
38820b05ddadSWen Gong struct wmi_set_current_country_cmd {
38830b05ddadSWen Gong 	u32 tlv_header;
38840b05ddadSWen Gong 	u32 pdev_id;
38850b05ddadSWen Gong 	u32 new_alpha2;
38860b05ddadSWen Gong } __packed;
38870b05ddadSWen Gong 
3888d5c65159SKalle Valo enum set_init_cc_type {
3889d5c65159SKalle Valo 	WMI_COUNTRY_INFO_TYPE_ALPHA,
3890d5c65159SKalle Valo 	WMI_COUNTRY_INFO_TYPE_COUNTRY_CODE,
3891d5c65159SKalle Valo 	WMI_COUNTRY_INFO_TYPE_REGDOMAIN,
3892d5c65159SKalle Valo };
3893d5c65159SKalle Valo 
3894d5c65159SKalle Valo enum set_init_cc_flags {
3895d5c65159SKalle Valo 	INVALID_CC,
3896d5c65159SKalle Valo 	CC_IS_SET,
3897d5c65159SKalle Valo 	REGDMN_IS_SET,
3898d5c65159SKalle Valo 	ALPHA_IS_SET,
3899d5c65159SKalle Valo };
3900d5c65159SKalle Valo 
3901d5c65159SKalle Valo struct wmi_init_country_params {
3902d5c65159SKalle Valo 	union {
3903d5c65159SKalle Valo 		u16 country_code;
3904d5c65159SKalle Valo 		u16 regdom_id;
3905d5c65159SKalle Valo 		u8 alpha2[3];
3906d5c65159SKalle Valo 	} cc_info;
3907d5c65159SKalle Valo 	enum set_init_cc_flags flags;
3908d5c65159SKalle Valo };
3909d5c65159SKalle Valo 
3910d5c65159SKalle Valo struct wmi_init_country_cmd {
3911d5c65159SKalle Valo 	u32 tlv_header;
3912d5c65159SKalle Valo 	u32 pdev_id;
3913d5c65159SKalle Valo 	u32 init_cc_type;
3914d5c65159SKalle Valo 	union {
3915d5c65159SKalle Valo 		u32 country_code;
3916d5c65159SKalle Valo 		u32 regdom_id;
3917d5c65159SKalle Valo 		u32 alpha2;
3918d5c65159SKalle Valo 	} cc_info;
3919d5c65159SKalle Valo } __packed;
3920d5c65159SKalle Valo 
39219dcf6808SWen Gong struct wmi_11d_scan_start_params {
39229dcf6808SWen Gong 	u32 vdev_id;
39239dcf6808SWen Gong 	u32 scan_period_msec;
39249dcf6808SWen Gong 	u32 start_interval_msec;
39259dcf6808SWen Gong };
39269dcf6808SWen Gong 
39279dcf6808SWen Gong struct wmi_11d_scan_start_cmd {
39289dcf6808SWen Gong 	u32 tlv_header;
39299dcf6808SWen Gong 	u32 vdev_id;
39309dcf6808SWen Gong 	u32 scan_period_msec;
39319dcf6808SWen Gong 	u32 start_interval_msec;
39329dcf6808SWen Gong } __packed;
39339dcf6808SWen Gong 
39349dcf6808SWen Gong struct wmi_11d_scan_stop_cmd {
39359dcf6808SWen Gong 	u32 tlv_header;
39369dcf6808SWen Gong 	u32 vdev_id;
39379dcf6808SWen Gong } __packed;
39389dcf6808SWen Gong 
39399dcf6808SWen Gong struct wmi_11d_new_cc_ev {
39409dcf6808SWen Gong 	u32 new_alpha2;
39419dcf6808SWen Gong } __packed;
39429dcf6808SWen Gong 
39432a63bbcaSPradeep Kumar Chitrapu #define THERMAL_LEVELS  1
39442a63bbcaSPradeep Kumar Chitrapu struct tt_level_config {
39452a63bbcaSPradeep Kumar Chitrapu 	u32 tmplwm;
39462a63bbcaSPradeep Kumar Chitrapu 	u32 tmphwm;
39472a63bbcaSPradeep Kumar Chitrapu 	u32 dcoffpercent;
39482a63bbcaSPradeep Kumar Chitrapu 	u32 priority;
39492a63bbcaSPradeep Kumar Chitrapu };
39502a63bbcaSPradeep Kumar Chitrapu 
39512a63bbcaSPradeep Kumar Chitrapu struct thermal_mitigation_params {
39522a63bbcaSPradeep Kumar Chitrapu 	u32 pdev_id;
39532a63bbcaSPradeep Kumar Chitrapu 	u32 enable;
39542a63bbcaSPradeep Kumar Chitrapu 	u32 dc;
39552a63bbcaSPradeep Kumar Chitrapu 	u32 dc_per_event;
39562a63bbcaSPradeep Kumar Chitrapu 	struct tt_level_config levelconf[THERMAL_LEVELS];
39572a63bbcaSPradeep Kumar Chitrapu };
39582a63bbcaSPradeep Kumar Chitrapu 
39592a63bbcaSPradeep Kumar Chitrapu struct wmi_therm_throt_config_request_cmd {
39602a63bbcaSPradeep Kumar Chitrapu 	u32 tlv_header;
39612a63bbcaSPradeep Kumar Chitrapu 	u32 pdev_id;
39622a63bbcaSPradeep Kumar Chitrapu 	u32 enable;
39632a63bbcaSPradeep Kumar Chitrapu 	u32 dc;
39642a63bbcaSPradeep Kumar Chitrapu 	u32 dc_per_event;
39652a63bbcaSPradeep Kumar Chitrapu 	u32 therm_throt_levels;
39662a63bbcaSPradeep Kumar Chitrapu } __packed;
39672a63bbcaSPradeep Kumar Chitrapu 
39682a63bbcaSPradeep Kumar Chitrapu struct wmi_therm_throt_level_config_info {
39692a63bbcaSPradeep Kumar Chitrapu 	u32 tlv_header;
39702a63bbcaSPradeep Kumar Chitrapu 	u32 temp_lwm;
39712a63bbcaSPradeep Kumar Chitrapu 	u32 temp_hwm;
39722a63bbcaSPradeep Kumar Chitrapu 	u32 dc_off_percent;
39732a63bbcaSPradeep Kumar Chitrapu 	u32 prio;
39742a63bbcaSPradeep Kumar Chitrapu } __packed;
39752a63bbcaSPradeep Kumar Chitrapu 
39769556dfa2SMaharaja Kennadyrajan struct wmi_delba_send_cmd {
39779556dfa2SMaharaja Kennadyrajan 	u32 tlv_header;
39789556dfa2SMaharaja Kennadyrajan 	u32 vdev_id;
39799556dfa2SMaharaja Kennadyrajan 	struct wmi_mac_addr peer_macaddr;
39809556dfa2SMaharaja Kennadyrajan 	u32 tid;
39819556dfa2SMaharaja Kennadyrajan 	u32 initiator;
39829556dfa2SMaharaja Kennadyrajan 	u32 reasoncode;
39839556dfa2SMaharaja Kennadyrajan } __packed;
39849556dfa2SMaharaja Kennadyrajan 
39859556dfa2SMaharaja Kennadyrajan struct wmi_addba_setresponse_cmd {
39869556dfa2SMaharaja Kennadyrajan 	u32 tlv_header;
39879556dfa2SMaharaja Kennadyrajan 	u32 vdev_id;
39889556dfa2SMaharaja Kennadyrajan 	struct wmi_mac_addr peer_macaddr;
39899556dfa2SMaharaja Kennadyrajan 	u32 tid;
39909556dfa2SMaharaja Kennadyrajan 	u32 statuscode;
39919556dfa2SMaharaja Kennadyrajan } __packed;
39929556dfa2SMaharaja Kennadyrajan 
39939556dfa2SMaharaja Kennadyrajan struct wmi_addba_send_cmd {
39949556dfa2SMaharaja Kennadyrajan 	u32 tlv_header;
39959556dfa2SMaharaja Kennadyrajan 	u32 vdev_id;
39969556dfa2SMaharaja Kennadyrajan 	struct wmi_mac_addr peer_macaddr;
39979556dfa2SMaharaja Kennadyrajan 	u32 tid;
39989556dfa2SMaharaja Kennadyrajan 	u32 buffersize;
39999556dfa2SMaharaja Kennadyrajan } __packed;
40009556dfa2SMaharaja Kennadyrajan 
40019556dfa2SMaharaja Kennadyrajan struct wmi_addba_clear_resp_cmd {
40029556dfa2SMaharaja Kennadyrajan 	u32 tlv_header;
40039556dfa2SMaharaja Kennadyrajan 	u32 vdev_id;
40049556dfa2SMaharaja Kennadyrajan 	struct wmi_mac_addr peer_macaddr;
40059556dfa2SMaharaja Kennadyrajan } __packed;
40069556dfa2SMaharaja Kennadyrajan 
4007d5c65159SKalle Valo struct wmi_pdev_pktlog_filter_info {
4008d5c65159SKalle Valo 	u32 tlv_header;
4009d5c65159SKalle Valo 	struct wmi_mac_addr peer_macaddr;
4010d5c65159SKalle Valo } __packed;
4011d5c65159SKalle Valo 
4012d5c65159SKalle Valo struct wmi_pdev_pktlog_filter_cmd {
4013d5c65159SKalle Valo 	u32 tlv_header;
4014d5c65159SKalle Valo 	u32 pdev_id;
4015d5c65159SKalle Valo 	u32 enable;
4016d5c65159SKalle Valo 	u32 filter_type;
4017d5c65159SKalle Valo 	u32 num_mac;
4018d5c65159SKalle Valo } __packed;
4019d5c65159SKalle Valo 
4020d5c65159SKalle Valo enum ath11k_wmi_pktlog_enable {
4021d5c65159SKalle Valo 	ATH11K_WMI_PKTLOG_ENABLE_AUTO  = 0,
4022d5c65159SKalle Valo 	ATH11K_WMI_PKTLOG_ENABLE_FORCE = 1,
4023d5c65159SKalle Valo };
4024d5c65159SKalle Valo 
4025d5c65159SKalle Valo struct wmi_pktlog_enable_cmd {
4026d5c65159SKalle Valo 	u32 tlv_header;
4027d5c65159SKalle Valo 	u32 pdev_id;
4028d5c65159SKalle Valo 	u32 evlist; /* WMI_PKTLOG_EVENT */
4029d5c65159SKalle Valo 	u32 enable;
4030d5c65159SKalle Valo } __packed;
4031d5c65159SKalle Valo 
4032d5c65159SKalle Valo struct wmi_pktlog_disable_cmd {
4033d5c65159SKalle Valo 	u32 tlv_header;
4034d5c65159SKalle Valo 	u32 pdev_id;
4035d5c65159SKalle Valo } __packed;
4036d5c65159SKalle Valo 
4037d5c65159SKalle Valo #define DFS_PHYERR_UNIT_TEST_CMD 0
4038d5c65159SKalle Valo #define DFS_UNIT_TEST_MODULE	0x2b
4039d5c65159SKalle Valo #define DFS_UNIT_TEST_TOKEN	0xAA
4040d5c65159SKalle Valo 
4041d5c65159SKalle Valo enum dfs_test_args_idx {
4042d5c65159SKalle Valo 	DFS_TEST_CMDID = 0,
4043d5c65159SKalle Valo 	DFS_TEST_PDEV_ID,
4044d5c65159SKalle Valo 	DFS_TEST_RADAR_PARAM,
4045d5c65159SKalle Valo 	DFS_MAX_TEST_ARGS,
4046d5c65159SKalle Valo };
4047d5c65159SKalle Valo 
4048d5c65159SKalle Valo struct wmi_dfs_unit_test_arg {
4049d5c65159SKalle Valo 	u32 cmd_id;
4050d5c65159SKalle Valo 	u32 pdev_id;
4051d5c65159SKalle Valo 	u32 radar_param;
4052d5c65159SKalle Valo };
4053d5c65159SKalle Valo 
4054d5c65159SKalle Valo struct wmi_unit_test_cmd {
4055d5c65159SKalle Valo 	u32 tlv_header;
4056d5c65159SKalle Valo 	u32 vdev_id;
4057d5c65159SKalle Valo 	u32 module_id;
4058d5c65159SKalle Valo 	u32 num_args;
4059d5c65159SKalle Valo 	u32 diag_token;
4060d5c65159SKalle Valo 	/* Followed by test args*/
4061d5c65159SKalle Valo } __packed;
4062d5c65159SKalle Valo 
4063d5c65159SKalle Valo #define MAX_SUPPORTED_RATES 128
4064d5c65159SKalle Valo 
4065d5c65159SKalle Valo #define WMI_PEER_AUTH		0x00000001
4066d5c65159SKalle Valo #define WMI_PEER_QOS		0x00000002
4067d5c65159SKalle Valo #define WMI_PEER_NEED_PTK_4_WAY	0x00000004
4068d5c65159SKalle Valo #define WMI_PEER_NEED_GTK_2_WAY	0x00000010
4069d5c65159SKalle Valo #define WMI_PEER_HE		0x00000400
4070d5c65159SKalle Valo #define WMI_PEER_APSD		0x00000800
4071d5c65159SKalle Valo #define WMI_PEER_HT		0x00001000
4072d5c65159SKalle Valo #define WMI_PEER_40MHZ		0x00002000
4073d5c65159SKalle Valo #define WMI_PEER_STBC		0x00008000
4074d5c65159SKalle Valo #define WMI_PEER_LDPC		0x00010000
4075d5c65159SKalle Valo #define WMI_PEER_DYN_MIMOPS	0x00020000
4076d5c65159SKalle Valo #define WMI_PEER_STATIC_MIMOPS	0x00040000
4077d5c65159SKalle Valo #define WMI_PEER_SPATIAL_MUX	0x00200000
40786d293d44SJohn Crispin #define WMI_PEER_TWT_REQ	0x00400000
40796d293d44SJohn Crispin #define WMI_PEER_TWT_RESP	0x00800000
4080d5c65159SKalle Valo #define WMI_PEER_VHT		0x02000000
4081d5c65159SKalle Valo #define WMI_PEER_80MHZ		0x04000000
4082d5c65159SKalle Valo #define WMI_PEER_PMF		0x08000000
4083d5c65159SKalle Valo /* TODO: Place holder for WLAN_PEER_F_PS_PRESEND_REQUIRED = 0x10000000.
4084d5c65159SKalle Valo  * Need to be cleaned up
4085d5c65159SKalle Valo  */
4086d5c65159SKalle Valo #define WMI_PEER_IS_P2P_CAPABLE	0x20000000
4087d5c65159SKalle Valo #define WMI_PEER_160MHZ		0x40000000
4088d5c65159SKalle Valo #define WMI_PEER_SAFEMODE_EN	0x80000000
4089d5c65159SKalle Valo 
4090d5c65159SKalle Valo struct beacon_tmpl_params {
4091d5c65159SKalle Valo 	u8 vdev_id;
4092d5c65159SKalle Valo 	u32 tim_ie_offset;
4093d5c65159SKalle Valo 	u32 tmpl_len;
4094d5c65159SKalle Valo 	u32 tmpl_len_aligned;
4095d5c65159SKalle Valo 	u32 csa_switch_count_offset;
4096d5c65159SKalle Valo 	u32 ext_csa_switch_count_offset;
4097d5c65159SKalle Valo 	u8 *frm;
4098d5c65159SKalle Valo };
4099d5c65159SKalle Valo 
4100d5c65159SKalle Valo struct wmi_rate_set {
4101d5c65159SKalle Valo 	u32 num_rates;
4102d5c65159SKalle Valo 	u32 rates[(MAX_SUPPORTED_RATES / 4) + 1];
4103d5c65159SKalle Valo };
4104d5c65159SKalle Valo 
4105d5c65159SKalle Valo struct wmi_vht_rate_set {
4106d5c65159SKalle Valo 	u32 tlv_header;
4107d5c65159SKalle Valo 	u32 rx_max_rate;
4108d5c65159SKalle Valo 	u32 rx_mcs_set;
4109d5c65159SKalle Valo 	u32 tx_max_rate;
4110d5c65159SKalle Valo 	u32 tx_mcs_set;
4111d5c65159SKalle Valo 	u32 tx_max_mcs_nss;
4112d5c65159SKalle Valo } __packed;
4113d5c65159SKalle Valo 
4114d5c65159SKalle Valo struct wmi_he_rate_set {
4115d5c65159SKalle Valo 	u32 tlv_header;
411661fe43e7SMiles Hu 
411761fe43e7SMiles Hu 	/* MCS at which the peer can receive */
4118d5c65159SKalle Valo 	u32 rx_mcs_set;
411961fe43e7SMiles Hu 
412061fe43e7SMiles Hu 	/* MCS at which the peer can transmit */
4121d5c65159SKalle Valo 	u32 tx_mcs_set;
4122d5c65159SKalle Valo } __packed;
4123d5c65159SKalle Valo 
4124d5c65159SKalle Valo #define MAX_REG_RULES 10
4125d5c65159SKalle Valo #define REG_ALPHA2_LEN 2
412691fa00faSAditya Kumar Singh #define MAX_6GHZ_REG_RULES 5
4127d5c65159SKalle Valo 
4128d5c65159SKalle Valo enum wmi_start_event_param {
4129d5c65159SKalle Valo 	WMI_VDEV_START_RESP_EVENT = 0,
4130d5c65159SKalle Valo 	WMI_VDEV_RESTART_RESP_EVENT,
4131d5c65159SKalle Valo };
4132d5c65159SKalle Valo 
4133d5c65159SKalle Valo struct wmi_vdev_start_resp_event {
4134d5c65159SKalle Valo 	u32 vdev_id;
4135d5c65159SKalle Valo 	u32 requestor_id;
4136d5c65159SKalle Valo 	enum wmi_start_event_param resp_type;
4137d5c65159SKalle Valo 	u32 status;
4138d5c65159SKalle Valo 	u32 chain_mask;
4139d5c65159SKalle Valo 	u32 smps_mode;
4140d5c65159SKalle Valo 	union {
4141d5c65159SKalle Valo 		u32 mac_id;
4142d5c65159SKalle Valo 		u32 pdev_id;
4143d5c65159SKalle Valo 	};
4144d5c65159SKalle Valo 	u32 cfgd_tx_streams;
4145d5c65159SKalle Valo 	u32 cfgd_rx_streams;
4146d5c65159SKalle Valo } __packed;
4147d5c65159SKalle Valo 
4148d5c65159SKalle Valo /* VDEV start response status codes */
4149d5c65159SKalle Valo enum wmi_vdev_start_resp_status_code {
4150d5c65159SKalle Valo 	WMI_VDEV_START_RESPONSE_STATUS_SUCCESS = 0,
4151d5c65159SKalle Valo 	WMI_VDEV_START_RESPONSE_INVALID_VDEVID = 1,
4152d5c65159SKalle Valo 	WMI_VDEV_START_RESPONSE_NOT_SUPPORTED = 2,
4153d5c65159SKalle Valo 	WMI_VDEV_START_RESPONSE_DFS_VIOLATION = 3,
4154d5c65159SKalle Valo 	WMI_VDEV_START_RESPONSE_INVALID_REGDOMAIN = 4,
4155d5c65159SKalle Valo };
4156d5c65159SKalle Valo 
4157d5c65159SKalle Valo /* Regaulatory Rule Flags Passed by FW */
4158d5c65159SKalle Valo #define REGULATORY_CHAN_DISABLED     BIT(0)
4159d5c65159SKalle Valo #define REGULATORY_CHAN_NO_IR        BIT(1)
4160d5c65159SKalle Valo #define REGULATORY_CHAN_RADAR        BIT(3)
4161d5c65159SKalle Valo #define REGULATORY_CHAN_NO_OFDM      BIT(6)
4162d5c65159SKalle Valo #define REGULATORY_CHAN_INDOOR_ONLY  BIT(9)
4163d5c65159SKalle Valo 
4164d5c65159SKalle Valo #define REGULATORY_CHAN_NO_HT40      BIT(4)
4165d5c65159SKalle Valo #define REGULATORY_CHAN_NO_80MHZ     BIT(7)
4166d5c65159SKalle Valo #define REGULATORY_CHAN_NO_160MHZ    BIT(8)
4167d5c65159SKalle Valo #define REGULATORY_CHAN_NO_20MHZ     BIT(11)
4168d5c65159SKalle Valo #define REGULATORY_CHAN_NO_10MHZ     BIT(12)
4169d5c65159SKalle Valo 
417091fa00faSAditya Kumar Singh enum wmi_reg_chan_list_cmd_type {
417191fa00faSAditya Kumar Singh 	WMI_REG_CHAN_LIST_CC_ID = 0,
417291fa00faSAditya Kumar Singh 	WMI_REG_CHAN_LIST_CC_EXT_ID = 1,
417391fa00faSAditya Kumar Singh };
417491fa00faSAditya Kumar Singh 
417591fa00faSAditya Kumar Singh enum wmi_reg_cc_setting_code {
4176d5c65159SKalle Valo 	WMI_REG_SET_CC_STATUS_PASS = 0,
4177d5c65159SKalle Valo 	WMI_REG_CURRENT_ALPHA2_NOT_FOUND = 1,
4178d5c65159SKalle Valo 	WMI_REG_INIT_ALPHA2_NOT_FOUND = 2,
4179d5c65159SKalle Valo 	WMI_REG_SET_CC_CHANGE_NOT_ALLOWED = 3,
4180d5c65159SKalle Valo 	WMI_REG_SET_CC_STATUS_NO_MEMORY = 4,
4181d5c65159SKalle Valo 	WMI_REG_SET_CC_STATUS_FAIL = 5,
418291fa00faSAditya Kumar Singh 
418391fa00faSAditya Kumar Singh 	/* add new setting code above, update in
418491fa00faSAditya Kumar Singh 	 * @enum cc_setting_code as well.
418591fa00faSAditya Kumar Singh 	 * Also handle it in ath11k_wmi_cc_setting_code_to_reg()
418691fa00faSAditya Kumar Singh 	 */
418791fa00faSAditya Kumar Singh };
418891fa00faSAditya Kumar Singh 
418991fa00faSAditya Kumar Singh enum cc_setting_code {
419091fa00faSAditya Kumar Singh 	REG_SET_CC_STATUS_PASS = 0,
419191fa00faSAditya Kumar Singh 	REG_CURRENT_ALPHA2_NOT_FOUND = 1,
419291fa00faSAditya Kumar Singh 	REG_INIT_ALPHA2_NOT_FOUND = 2,
419391fa00faSAditya Kumar Singh 	REG_SET_CC_CHANGE_NOT_ALLOWED = 3,
419491fa00faSAditya Kumar Singh 	REG_SET_CC_STATUS_NO_MEMORY = 4,
419591fa00faSAditya Kumar Singh 	REG_SET_CC_STATUS_FAIL = 5,
419691fa00faSAditya Kumar Singh 
419791fa00faSAditya Kumar Singh 	/* add new setting code above, update in
419891fa00faSAditya Kumar Singh 	 * @enum wmi_reg_cc_setting_code as well.
4199e238e62bSAditya Kumar Singh 	 * Also handle it in ath11k_cc_status_to_str()
420091fa00faSAditya Kumar Singh 	 */
420191fa00faSAditya Kumar Singh };
420291fa00faSAditya Kumar Singh 
420391fa00faSAditya Kumar Singh static inline enum cc_setting_code
ath11k_wmi_cc_setting_code_to_reg(enum wmi_reg_cc_setting_code status_code)420491fa00faSAditya Kumar Singh ath11k_wmi_cc_setting_code_to_reg(enum wmi_reg_cc_setting_code status_code)
420591fa00faSAditya Kumar Singh {
420691fa00faSAditya Kumar Singh 	switch (status_code) {
420791fa00faSAditya Kumar Singh 	case WMI_REG_SET_CC_STATUS_PASS:
420891fa00faSAditya Kumar Singh 		return REG_SET_CC_STATUS_PASS;
420991fa00faSAditya Kumar Singh 	case WMI_REG_CURRENT_ALPHA2_NOT_FOUND:
421091fa00faSAditya Kumar Singh 		return REG_CURRENT_ALPHA2_NOT_FOUND;
421191fa00faSAditya Kumar Singh 	case WMI_REG_INIT_ALPHA2_NOT_FOUND:
421291fa00faSAditya Kumar Singh 		return REG_INIT_ALPHA2_NOT_FOUND;
421391fa00faSAditya Kumar Singh 	case WMI_REG_SET_CC_CHANGE_NOT_ALLOWED:
421491fa00faSAditya Kumar Singh 		return REG_SET_CC_CHANGE_NOT_ALLOWED;
421591fa00faSAditya Kumar Singh 	case WMI_REG_SET_CC_STATUS_NO_MEMORY:
421691fa00faSAditya Kumar Singh 		return REG_SET_CC_STATUS_NO_MEMORY;
421791fa00faSAditya Kumar Singh 	case WMI_REG_SET_CC_STATUS_FAIL:
421891fa00faSAditya Kumar Singh 		return REG_SET_CC_STATUS_FAIL;
421991fa00faSAditya Kumar Singh 	}
422091fa00faSAditya Kumar Singh 
422191fa00faSAditya Kumar Singh 	return REG_SET_CC_STATUS_FAIL;
422291fa00faSAditya Kumar Singh }
422391fa00faSAditya Kumar Singh 
ath11k_cc_status_to_str(enum cc_setting_code code)4224e238e62bSAditya Kumar Singh static inline const char *ath11k_cc_status_to_str(enum cc_setting_code code)
4225e238e62bSAditya Kumar Singh {
4226e238e62bSAditya Kumar Singh 	switch (code) {
4227e238e62bSAditya Kumar Singh 	case REG_SET_CC_STATUS_PASS:
4228e238e62bSAditya Kumar Singh 		return "REG_SET_CC_STATUS_PASS";
4229e238e62bSAditya Kumar Singh 	case REG_CURRENT_ALPHA2_NOT_FOUND:
4230e238e62bSAditya Kumar Singh 		return "REG_CURRENT_ALPHA2_NOT_FOUND";
4231e238e62bSAditya Kumar Singh 	case REG_INIT_ALPHA2_NOT_FOUND:
4232e238e62bSAditya Kumar Singh 		return "REG_INIT_ALPHA2_NOT_FOUND";
4233e238e62bSAditya Kumar Singh 	case REG_SET_CC_CHANGE_NOT_ALLOWED:
4234e238e62bSAditya Kumar Singh 		return "REG_SET_CC_CHANGE_NOT_ALLOWED";
4235e238e62bSAditya Kumar Singh 	case REG_SET_CC_STATUS_NO_MEMORY:
4236e238e62bSAditya Kumar Singh 		return "REG_SET_CC_STATUS_NO_MEMORY";
4237e238e62bSAditya Kumar Singh 	case REG_SET_CC_STATUS_FAIL:
4238e238e62bSAditya Kumar Singh 		return "REG_SET_CC_STATUS_FAIL";
4239e238e62bSAditya Kumar Singh 	}
4240e238e62bSAditya Kumar Singh 
4241e238e62bSAditya Kumar Singh 	return "Unknown CC status";
4242e238e62bSAditya Kumar Singh }
4243e238e62bSAditya Kumar Singh 
424491fa00faSAditya Kumar Singh enum wmi_reg_6ghz_ap_type {
424591fa00faSAditya Kumar Singh 	WMI_REG_INDOOR_AP = 0,
424691fa00faSAditya Kumar Singh 	WMI_REG_STANDARD_POWER_AP = 1,
424791fa00faSAditya Kumar Singh 	WMI_REG_VERY_LOW_POWER_AP = 2,
424891fa00faSAditya Kumar Singh 
4249e238e62bSAditya Kumar Singh 	/* add AP type above, handle in ath11k_6ghz_ap_type_to_str()
4250e238e62bSAditya Kumar Singh 	 */
425191fa00faSAditya Kumar Singh 	WMI_REG_CURRENT_MAX_AP_TYPE,
425291fa00faSAditya Kumar Singh 	WMI_REG_MAX_AP_TYPE = 7,
425391fa00faSAditya Kumar Singh };
425491fa00faSAditya Kumar Singh 
4255e238e62bSAditya Kumar Singh static inline const char *
ath11k_6ghz_ap_type_to_str(enum wmi_reg_6ghz_ap_type type)4256e238e62bSAditya Kumar Singh ath11k_6ghz_ap_type_to_str(enum wmi_reg_6ghz_ap_type type)
4257e238e62bSAditya Kumar Singh {
4258e238e62bSAditya Kumar Singh 	switch (type) {
4259e238e62bSAditya Kumar Singh 	case WMI_REG_INDOOR_AP:
4260e238e62bSAditya Kumar Singh 		return "INDOOR AP";
4261e238e62bSAditya Kumar Singh 	case WMI_REG_STANDARD_POWER_AP:
4262e238e62bSAditya Kumar Singh 		return "STANDARD POWER AP";
4263e238e62bSAditya Kumar Singh 	case WMI_REG_VERY_LOW_POWER_AP:
4264e238e62bSAditya Kumar Singh 		return "VERY LOW POWER AP";
4265e238e62bSAditya Kumar Singh 	case WMI_REG_CURRENT_MAX_AP_TYPE:
4266e238e62bSAditya Kumar Singh 		return "CURRENT_MAX_AP_TYPE";
4267e238e62bSAditya Kumar Singh 	case WMI_REG_MAX_AP_TYPE:
4268e238e62bSAditya Kumar Singh 		return "MAX_AP_TYPE";
4269e238e62bSAditya Kumar Singh 	}
4270e238e62bSAditya Kumar Singh 
4271e238e62bSAditya Kumar Singh 	return "unknown 6 GHz AP type";
4272e238e62bSAditya Kumar Singh }
4273e238e62bSAditya Kumar Singh 
427491fa00faSAditya Kumar Singh enum wmi_reg_6ghz_client_type {
427591fa00faSAditya Kumar Singh 	WMI_REG_DEFAULT_CLIENT = 0,
427691fa00faSAditya Kumar Singh 	WMI_REG_SUBORDINATE_CLIENT = 1,
427791fa00faSAditya Kumar Singh 	WMI_REG_MAX_CLIENT_TYPE = 2,
4278e238e62bSAditya Kumar Singh 
4279e238e62bSAditya Kumar Singh 	/* add client type above, handle it in
4280e238e62bSAditya Kumar Singh 	 * ath11k_6ghz_client_type_to_str()
4281e238e62bSAditya Kumar Singh 	 */
4282d5c65159SKalle Valo };
4283d5c65159SKalle Valo 
4284e238e62bSAditya Kumar Singh static inline const char *
ath11k_6ghz_client_type_to_str(enum wmi_reg_6ghz_client_type type)4285e238e62bSAditya Kumar Singh ath11k_6ghz_client_type_to_str(enum wmi_reg_6ghz_client_type type)
4286e238e62bSAditya Kumar Singh {
4287e238e62bSAditya Kumar Singh 	switch (type) {
4288e238e62bSAditya Kumar Singh 	case WMI_REG_DEFAULT_CLIENT:
4289e238e62bSAditya Kumar Singh 		return "DEFAULT CLIENT";
4290e238e62bSAditya Kumar Singh 	case WMI_REG_SUBORDINATE_CLIENT:
4291e238e62bSAditya Kumar Singh 		return "SUBORDINATE CLIENT";
4292e238e62bSAditya Kumar Singh 	case WMI_REG_MAX_CLIENT_TYPE:
4293e238e62bSAditya Kumar Singh 		return "MAX_CLIENT_TYPE";
4294e238e62bSAditya Kumar Singh 	}
4295e238e62bSAditya Kumar Singh 
4296e238e62bSAditya Kumar Singh 	return "unknown 6 GHz client type";
4297e238e62bSAditya Kumar Singh }
4298e238e62bSAditya Kumar Singh 
4299e238e62bSAditya Kumar Singh enum reg_subdomains_6ghz {
4300e238e62bSAditya Kumar Singh 	EMPTY_6GHZ = 0x0,
4301e238e62bSAditya Kumar Singh 	FCC1_CLIENT_LPI_REGULAR_6GHZ = 0x01,
4302e238e62bSAditya Kumar Singh 	FCC1_CLIENT_SP_6GHZ = 0x02,
4303e238e62bSAditya Kumar Singh 	FCC1_AP_LPI_6GHZ = 0x03,
4304e238e62bSAditya Kumar Singh 	FCC1_CLIENT_LPI_SUBORDINATE = FCC1_AP_LPI_6GHZ,
4305e238e62bSAditya Kumar Singh 	FCC1_AP_SP_6GHZ = 0x04,
4306e238e62bSAditya Kumar Singh 	ETSI1_LPI_6GHZ = 0x10,
4307e238e62bSAditya Kumar Singh 	ETSI1_VLP_6GHZ = 0x11,
4308e238e62bSAditya Kumar Singh 	ETSI2_LPI_6GHZ = 0x12,
4309e238e62bSAditya Kumar Singh 	ETSI2_VLP_6GHZ = 0x13,
4310e238e62bSAditya Kumar Singh 	APL1_LPI_6GHZ = 0x20,
4311e238e62bSAditya Kumar Singh 	APL1_VLP_6GHZ = 0x21,
4312e238e62bSAditya Kumar Singh 
4313e238e62bSAditya Kumar Singh 	/* add sub-domain above, handle it in
4314e238e62bSAditya Kumar Singh 	 * ath11k_sub_reg_6ghz_to_str()
4315e238e62bSAditya Kumar Singh 	 */
4316e238e62bSAditya Kumar Singh };
4317e238e62bSAditya Kumar Singh 
4318e238e62bSAditya Kumar Singh static inline const char *
ath11k_sub_reg_6ghz_to_str(enum reg_subdomains_6ghz sub_id)4319e238e62bSAditya Kumar Singh ath11k_sub_reg_6ghz_to_str(enum reg_subdomains_6ghz sub_id)
4320e238e62bSAditya Kumar Singh {
4321e238e62bSAditya Kumar Singh 	switch (sub_id) {
4322e238e62bSAditya Kumar Singh 	case EMPTY_6GHZ:
4323e238e62bSAditya Kumar Singh 		return "N/A";
4324e238e62bSAditya Kumar Singh 	case FCC1_CLIENT_LPI_REGULAR_6GHZ:
4325e238e62bSAditya Kumar Singh 		return "FCC1_CLIENT_LPI_REGULAR_6GHZ";
4326e238e62bSAditya Kumar Singh 	case FCC1_CLIENT_SP_6GHZ:
4327e238e62bSAditya Kumar Singh 		return "FCC1_CLIENT_SP_6GHZ";
4328e238e62bSAditya Kumar Singh 	case FCC1_AP_LPI_6GHZ:
4329e238e62bSAditya Kumar Singh 		return "FCC1_AP_LPI_6GHZ/FCC1_CLIENT_LPI_SUBORDINATE";
4330e238e62bSAditya Kumar Singh 	case FCC1_AP_SP_6GHZ:
4331e238e62bSAditya Kumar Singh 		return "FCC1_AP_SP_6GHZ";
4332e238e62bSAditya Kumar Singh 	case ETSI1_LPI_6GHZ:
4333e238e62bSAditya Kumar Singh 		return "ETSI1_LPI_6GHZ";
4334e238e62bSAditya Kumar Singh 	case ETSI1_VLP_6GHZ:
4335e238e62bSAditya Kumar Singh 		return "ETSI1_VLP_6GHZ";
4336e238e62bSAditya Kumar Singh 	case ETSI2_LPI_6GHZ:
4337e238e62bSAditya Kumar Singh 		return "ETSI2_LPI_6GHZ";
4338e238e62bSAditya Kumar Singh 	case ETSI2_VLP_6GHZ:
4339e238e62bSAditya Kumar Singh 		return "ETSI2_VLP_6GHZ";
4340e238e62bSAditya Kumar Singh 	case APL1_LPI_6GHZ:
4341e238e62bSAditya Kumar Singh 		return "APL1_LPI_6GHZ";
4342e238e62bSAditya Kumar Singh 	case APL1_VLP_6GHZ:
4343e238e62bSAditya Kumar Singh 		return "APL1_VLP_6GHZ";
4344e238e62bSAditya Kumar Singh 	}
4345e238e62bSAditya Kumar Singh 
4346e238e62bSAditya Kumar Singh 	return "unknown sub reg id";
4347e238e62bSAditya Kumar Singh }
4348e238e62bSAditya Kumar Singh 
4349e238e62bSAditya Kumar Singh enum reg_super_domain_6ghz {
4350e238e62bSAditya Kumar Singh 	FCC1_6GHZ = 0x01,
4351e238e62bSAditya Kumar Singh 	ETSI1_6GHZ = 0x02,
4352e238e62bSAditya Kumar Singh 	ETSI2_6GHZ = 0x03,
4353e238e62bSAditya Kumar Singh 	APL1_6GHZ = 0x04,
4354e238e62bSAditya Kumar Singh 	FCC1_6GHZ_CL = 0x05,
4355e238e62bSAditya Kumar Singh 
4356e238e62bSAditya Kumar Singh 	/* add super domain above, handle it in
4357e238e62bSAditya Kumar Singh 	 * ath11k_super_reg_6ghz_to_str()
4358e238e62bSAditya Kumar Singh 	 */
4359e238e62bSAditya Kumar Singh };
4360e238e62bSAditya Kumar Singh 
4361e238e62bSAditya Kumar Singh static inline const char *
ath11k_super_reg_6ghz_to_str(enum reg_super_domain_6ghz domain_id)4362e238e62bSAditya Kumar Singh ath11k_super_reg_6ghz_to_str(enum reg_super_domain_6ghz domain_id)
4363e238e62bSAditya Kumar Singh {
4364e238e62bSAditya Kumar Singh 	switch (domain_id) {
4365e238e62bSAditya Kumar Singh 	case FCC1_6GHZ:
4366e238e62bSAditya Kumar Singh 		return "FCC1_6GHZ";
4367e238e62bSAditya Kumar Singh 	case ETSI1_6GHZ:
4368e238e62bSAditya Kumar Singh 		return "ETSI1_6GHZ";
4369e238e62bSAditya Kumar Singh 	case ETSI2_6GHZ:
4370e238e62bSAditya Kumar Singh 		return "ETSI2_6GHZ";
4371e238e62bSAditya Kumar Singh 	case APL1_6GHZ:
4372e238e62bSAditya Kumar Singh 		return "APL1_6GHZ";
4373e238e62bSAditya Kumar Singh 	case FCC1_6GHZ_CL:
4374e238e62bSAditya Kumar Singh 		return "FCC1_6GHZ_CL";
4375e238e62bSAditya Kumar Singh 	}
4376e238e62bSAditya Kumar Singh 
4377e238e62bSAditya Kumar Singh 	return "unknown domain id";
4378e238e62bSAditya Kumar Singh }
4379e238e62bSAditya Kumar Singh 
4380d5c65159SKalle Valo struct cur_reg_rule {
4381d5c65159SKalle Valo 	u16 start_freq;
4382d5c65159SKalle Valo 	u16 end_freq;
4383d5c65159SKalle Valo 	u16 max_bw;
4384d5c65159SKalle Valo 	u8 reg_power;
4385d5c65159SKalle Valo 	u8 ant_gain;
4386d5c65159SKalle Valo 	u16 flags;
438791fa00faSAditya Kumar Singh 	bool psd_flag;
438891fa00faSAditya Kumar Singh 	s8 psd_eirp;
4389d5c65159SKalle Valo };
4390d5c65159SKalle Valo 
4391d5c65159SKalle Valo struct cur_regulatory_info {
4392d5c65159SKalle Valo 	enum cc_setting_code status_code;
4393d5c65159SKalle Valo 	u8 num_phy;
4394d5c65159SKalle Valo 	u8 phy_id;
4395d5c65159SKalle Valo 	u16 reg_dmn_pair;
4396d5c65159SKalle Valo 	u16 ctry_code;
4397d5c65159SKalle Valo 	u8 alpha2[REG_ALPHA2_LEN + 1];
4398d5c65159SKalle Valo 	u32 dfs_region;
4399d5c65159SKalle Valo 	u32 phybitmap;
440025e289e1SAditya Kumar Singh 	u32 min_bw_2ghz;
440125e289e1SAditya Kumar Singh 	u32 max_bw_2ghz;
440225e289e1SAditya Kumar Singh 	u32 min_bw_5ghz;
440325e289e1SAditya Kumar Singh 	u32 max_bw_5ghz;
440425e289e1SAditya Kumar Singh 	u32 num_2ghz_reg_rules;
440525e289e1SAditya Kumar Singh 	u32 num_5ghz_reg_rules;
440625e289e1SAditya Kumar Singh 	struct cur_reg_rule *reg_rules_2ghz_ptr;
440725e289e1SAditya Kumar Singh 	struct cur_reg_rule *reg_rules_5ghz_ptr;
440891fa00faSAditya Kumar Singh 	bool is_ext_reg_event;
440991fa00faSAditya Kumar Singh 	enum wmi_reg_6ghz_client_type client_type;
441091fa00faSAditya Kumar Singh 	bool rnr_tpe_usable;
441191fa00faSAditya Kumar Singh 	bool unspecified_ap_usable;
441291fa00faSAditya Kumar Singh 	u8 domain_code_6ghz_ap[WMI_REG_CURRENT_MAX_AP_TYPE];
441391fa00faSAditya Kumar Singh 	u8 domain_code_6ghz_client[WMI_REG_CURRENT_MAX_AP_TYPE][WMI_REG_MAX_CLIENT_TYPE];
441491fa00faSAditya Kumar Singh 	u32 domain_code_6ghz_super_id;
441591fa00faSAditya Kumar Singh 	u32 min_bw_6ghz_ap[WMI_REG_CURRENT_MAX_AP_TYPE];
441691fa00faSAditya Kumar Singh 	u32 max_bw_6ghz_ap[WMI_REG_CURRENT_MAX_AP_TYPE];
441791fa00faSAditya Kumar Singh 	u32 min_bw_6ghz_client[WMI_REG_CURRENT_MAX_AP_TYPE][WMI_REG_MAX_CLIENT_TYPE];
441891fa00faSAditya Kumar Singh 	u32 max_bw_6ghz_client[WMI_REG_CURRENT_MAX_AP_TYPE][WMI_REG_MAX_CLIENT_TYPE];
441991fa00faSAditya Kumar Singh 	u32 num_6ghz_rules_ap[WMI_REG_CURRENT_MAX_AP_TYPE];
442091fa00faSAditya Kumar Singh 	u32 num_6ghz_rules_client[WMI_REG_CURRENT_MAX_AP_TYPE][WMI_REG_MAX_CLIENT_TYPE];
442191fa00faSAditya Kumar Singh 	struct cur_reg_rule *reg_rules_6ghz_ap_ptr[WMI_REG_CURRENT_MAX_AP_TYPE];
442291fa00faSAditya Kumar Singh 	struct cur_reg_rule *reg_rules_6ghz_client_ptr
442391fa00faSAditya Kumar Singh 		[WMI_REG_CURRENT_MAX_AP_TYPE][WMI_REG_MAX_CLIENT_TYPE];
4424d5c65159SKalle Valo };
4425d5c65159SKalle Valo 
4426d5c65159SKalle Valo struct wmi_reg_chan_list_cc_event {
4427d5c65159SKalle Valo 	u32 status_code;
4428d5c65159SKalle Valo 	u32 phy_id;
4429d5c65159SKalle Valo 	u32 alpha2;
4430d5c65159SKalle Valo 	u32 num_phy;
4431d5c65159SKalle Valo 	u32 country_id;
4432d5c65159SKalle Valo 	u32 domain_code;
4433d5c65159SKalle Valo 	u32 dfs_region;
4434d5c65159SKalle Valo 	u32 phybitmap;
443525e289e1SAditya Kumar Singh 	u32 min_bw_2ghz;
443625e289e1SAditya Kumar Singh 	u32 max_bw_2ghz;
443725e289e1SAditya Kumar Singh 	u32 min_bw_5ghz;
443825e289e1SAditya Kumar Singh 	u32 max_bw_5ghz;
443925e289e1SAditya Kumar Singh 	u32 num_2ghz_reg_rules;
444025e289e1SAditya Kumar Singh 	u32 num_5ghz_reg_rules;
4441d5c65159SKalle Valo } __packed;
4442d5c65159SKalle Valo 
4443d5c65159SKalle Valo struct wmi_regulatory_rule_struct {
4444d5c65159SKalle Valo 	u32  tlv_header;
4445d5c65159SKalle Valo 	u32  freq_info;
4446d5c65159SKalle Valo 	u32  bw_pwr_info;
4447d5c65159SKalle Valo 	u32  flag_info;
4448d5c65159SKalle Valo };
4449d5c65159SKalle Valo 
445091fa00faSAditya Kumar Singh #define WMI_REG_CLIENT_MAX 4
445191fa00faSAditya Kumar Singh 
445291fa00faSAditya Kumar Singh struct wmi_reg_chan_list_cc_ext_event {
445391fa00faSAditya Kumar Singh 	u32 status_code;
445491fa00faSAditya Kumar Singh 	u32 phy_id;
445591fa00faSAditya Kumar Singh 	u32 alpha2;
445691fa00faSAditya Kumar Singh 	u32 num_phy;
445791fa00faSAditya Kumar Singh 	u32 country_id;
445891fa00faSAditya Kumar Singh 	u32 domain_code;
445991fa00faSAditya Kumar Singh 	u32 dfs_region;
446091fa00faSAditya Kumar Singh 	u32 phybitmap;
446191fa00faSAditya Kumar Singh 	u32 min_bw_2ghz;
446291fa00faSAditya Kumar Singh 	u32 max_bw_2ghz;
446391fa00faSAditya Kumar Singh 	u32 min_bw_5ghz;
446491fa00faSAditya Kumar Singh 	u32 max_bw_5ghz;
446591fa00faSAditya Kumar Singh 	u32 num_2ghz_reg_rules;
446691fa00faSAditya Kumar Singh 	u32 num_5ghz_reg_rules;
446791fa00faSAditya Kumar Singh 	u32 client_type;
446891fa00faSAditya Kumar Singh 	u32 rnr_tpe_usable;
446991fa00faSAditya Kumar Singh 	u32 unspecified_ap_usable;
447091fa00faSAditya Kumar Singh 	u32 domain_code_6ghz_ap_lpi;
447191fa00faSAditya Kumar Singh 	u32 domain_code_6ghz_ap_sp;
447291fa00faSAditya Kumar Singh 	u32 domain_code_6ghz_ap_vlp;
447391fa00faSAditya Kumar Singh 	u32 domain_code_6ghz_client_lpi[WMI_REG_CLIENT_MAX];
447491fa00faSAditya Kumar Singh 	u32 domain_code_6ghz_client_sp[WMI_REG_CLIENT_MAX];
447591fa00faSAditya Kumar Singh 	u32 domain_code_6ghz_client_vlp[WMI_REG_CLIENT_MAX];
447691fa00faSAditya Kumar Singh 	u32 domain_code_6ghz_super_id;
447791fa00faSAditya Kumar Singh 	u32 min_bw_6ghz_ap_sp;
447891fa00faSAditya Kumar Singh 	u32 max_bw_6ghz_ap_sp;
447991fa00faSAditya Kumar Singh 	u32 min_bw_6ghz_ap_lpi;
448091fa00faSAditya Kumar Singh 	u32 max_bw_6ghz_ap_lpi;
448191fa00faSAditya Kumar Singh 	u32 min_bw_6ghz_ap_vlp;
448291fa00faSAditya Kumar Singh 	u32 max_bw_6ghz_ap_vlp;
448391fa00faSAditya Kumar Singh 	u32 min_bw_6ghz_client_sp[WMI_REG_CLIENT_MAX];
448491fa00faSAditya Kumar Singh 	u32 max_bw_6ghz_client_sp[WMI_REG_CLIENT_MAX];
448591fa00faSAditya Kumar Singh 	u32 min_bw_6ghz_client_lpi[WMI_REG_CLIENT_MAX];
448691fa00faSAditya Kumar Singh 	u32 max_bw_6ghz_client_lpi[WMI_REG_CLIENT_MAX];
448791fa00faSAditya Kumar Singh 	u32 min_bw_6ghz_client_vlp[WMI_REG_CLIENT_MAX];
448891fa00faSAditya Kumar Singh 	u32 max_bw_6ghz_client_vlp[WMI_REG_CLIENT_MAX];
448991fa00faSAditya Kumar Singh 	u32 num_6ghz_reg_rules_ap_sp;
449091fa00faSAditya Kumar Singh 	u32 num_6ghz_reg_rules_ap_lpi;
449191fa00faSAditya Kumar Singh 	u32 num_6ghz_reg_rules_ap_vlp;
449291fa00faSAditya Kumar Singh 	u32 num_6ghz_reg_rules_client_sp[WMI_REG_CLIENT_MAX];
449391fa00faSAditya Kumar Singh 	u32 num_6ghz_reg_rules_client_lpi[WMI_REG_CLIENT_MAX];
449491fa00faSAditya Kumar Singh 	u32 num_6ghz_reg_rules_client_vlp[WMI_REG_CLIENT_MAX];
449591fa00faSAditya Kumar Singh } __packed;
449691fa00faSAditya Kumar Singh 
449791fa00faSAditya Kumar Singh struct wmi_regulatory_ext_rule {
449891fa00faSAditya Kumar Singh 	u32 tlv_header;
449991fa00faSAditya Kumar Singh 	u32 freq_info;
450091fa00faSAditya Kumar Singh 	u32 bw_pwr_info;
450191fa00faSAditya Kumar Singh 	u32 flag_info;
450291fa00faSAditya Kumar Singh 	u32 psd_power_info;
450391fa00faSAditya Kumar Singh } __packed;
450491fa00faSAditya Kumar Singh 
45053cbbdfbeSRitesh Singh struct wmi_vdev_delete_resp_event {
45063cbbdfbeSRitesh Singh 	u32 vdev_id;
45073cbbdfbeSRitesh Singh } __packed;
45083cbbdfbeSRitesh Singh 
4509d5c65159SKalle Valo struct wmi_peer_delete_resp_event {
4510d5c65159SKalle Valo 	u32 vdev_id;
4511d5c65159SKalle Valo 	struct wmi_mac_addr peer_macaddr;
4512d5c65159SKalle Valo } __packed;
4513d5c65159SKalle Valo 
4514d5c65159SKalle Valo struct wmi_bcn_tx_status_event {
4515d5c65159SKalle Valo 	u32 vdev_id;
4516d5c65159SKalle Valo 	u32 tx_status;
4517d5c65159SKalle Valo } __packed;
4518d5c65159SKalle Valo 
4519d5c65159SKalle Valo struct wmi_vdev_stopped_event {
4520d5c65159SKalle Valo 	u32 vdev_id;
4521d5c65159SKalle Valo } __packed;
4522d5c65159SKalle Valo 
4523d5c65159SKalle Valo struct wmi_pdev_bss_chan_info_event {
4524d5c65159SKalle Valo 	u32 freq;	/* Units in MHz */
4525d5c65159SKalle Valo 	u32 noise_floor;	/* units are dBm */
4526d5c65159SKalle Valo 	/* rx clear - how often the channel was unused */
4527d5c65159SKalle Valo 	u32 rx_clear_count_low;
4528d5c65159SKalle Valo 	u32 rx_clear_count_high;
4529d5c65159SKalle Valo 	/* cycle count - elapsed time during measured period, in clock ticks */
4530d5c65159SKalle Valo 	u32 cycle_count_low;
4531d5c65159SKalle Valo 	u32 cycle_count_high;
4532d5c65159SKalle Valo 	/* tx cycle count - elapsed time spent in tx, in clock ticks */
4533d5c65159SKalle Valo 	u32 tx_cycle_count_low;
4534d5c65159SKalle Valo 	u32 tx_cycle_count_high;
4535d5c65159SKalle Valo 	/* rx cycle count - elapsed time spent in rx, in clock ticks */
4536d5c65159SKalle Valo 	u32 rx_cycle_count_low;
4537d5c65159SKalle Valo 	u32 rx_cycle_count_high;
4538d5c65159SKalle Valo 	/*rx_cycle cnt for my bss in 64bits format */
4539d5c65159SKalle Valo 	u32 rx_bss_cycle_count_low;
4540d5c65159SKalle Valo 	u32 rx_bss_cycle_count_high;
4541feab5bb8SSeevalamuthu Mariappan 	u32 pdev_id;
4542d5c65159SKalle Valo } __packed;
4543d5c65159SKalle Valo 
4544d5c65159SKalle Valo #define WMI_VDEV_INSTALL_KEY_COMPL_STATUS_SUCCESS 0
4545d5c65159SKalle Valo 
4546d5c65159SKalle Valo struct wmi_vdev_install_key_compl_event {
4547d5c65159SKalle Valo 	u32 vdev_id;
4548d5c65159SKalle Valo 	struct wmi_mac_addr peer_macaddr;
4549d5c65159SKalle Valo 	u32 key_idx;
4550d5c65159SKalle Valo 	u32 key_flags;
4551d5c65159SKalle Valo 	u32 status;
4552d5c65159SKalle Valo } __packed;
4553d5c65159SKalle Valo 
4554d5c65159SKalle Valo struct wmi_vdev_install_key_complete_arg {
4555d5c65159SKalle Valo 	u32 vdev_id;
4556d5c65159SKalle Valo 	const u8 *macaddr;
4557d5c65159SKalle Valo 	u32 key_idx;
4558d5c65159SKalle Valo 	u32 key_flags;
4559d5c65159SKalle Valo 	u32 status;
4560d5c65159SKalle Valo };
4561d5c65159SKalle Valo 
4562d5c65159SKalle Valo struct wmi_peer_assoc_conf_event {
4563d5c65159SKalle Valo 	u32 vdev_id;
4564d5c65159SKalle Valo 	struct wmi_mac_addr peer_macaddr;
4565d5c65159SKalle Valo } __packed;
4566d5c65159SKalle Valo 
4567d5c65159SKalle Valo struct wmi_peer_assoc_conf_arg {
4568d5c65159SKalle Valo 	u32 vdev_id;
4569d5c65159SKalle Valo 	const u8 *macaddr;
4570d5c65159SKalle Valo };
4571d5c65159SKalle Valo 
4572047679e3SAloka Dixit struct wmi_fils_discovery_event {
4573047679e3SAloka Dixit 	u32 vdev_id;
4574047679e3SAloka Dixit 	u32 fils_tt;
4575047679e3SAloka Dixit 	u32 tbtt;
4576047679e3SAloka Dixit } __packed;
4577047679e3SAloka Dixit 
4578047679e3SAloka Dixit struct wmi_probe_resp_tx_status_event {
4579047679e3SAloka Dixit 	u32 vdev_id;
4580047679e3SAloka Dixit 	u32 tx_status;
4581047679e3SAloka Dixit } __packed;
4582047679e3SAloka Dixit 
4583d5c65159SKalle Valo /*
4584d5c65159SKalle Valo  * PDEV statistics
4585d5c65159SKalle Valo  */
4586d5c65159SKalle Valo struct wmi_pdev_stats_base {
4587d5c65159SKalle Valo 	s32 chan_nf;
4588d5c65159SKalle Valo 	u32 tx_frame_count; /* Cycles spent transmitting frames */
4589d5c65159SKalle Valo 	u32 rx_frame_count; /* Cycles spent receiving frames */
4590d5c65159SKalle Valo 	u32 rx_clear_count; /* Total channel busy time, evidently */
4591d5c65159SKalle Valo 	u32 cycle_count; /* Total on-channel time */
4592d5c65159SKalle Valo 	u32 phy_err_count;
4593d5c65159SKalle Valo 	u32 chan_tx_pwr;
4594d5c65159SKalle Valo } __packed;
4595d5c65159SKalle Valo 
4596d5c65159SKalle Valo struct wmi_pdev_stats_extra {
4597d5c65159SKalle Valo 	u32 ack_rx_bad;
4598d5c65159SKalle Valo 	u32 rts_bad;
4599d5c65159SKalle Valo 	u32 rts_good;
4600d5c65159SKalle Valo 	u32 fcs_bad;
4601d5c65159SKalle Valo 	u32 no_beacons;
4602d5c65159SKalle Valo 	u32 mib_int_count;
4603d5c65159SKalle Valo } __packed;
4604d5c65159SKalle Valo 
4605d5c65159SKalle Valo struct wmi_pdev_stats_tx {
4606d5c65159SKalle Valo 	/* Num HTT cookies queued to dispatch list */
4607d5c65159SKalle Valo 	s32 comp_queued;
4608d5c65159SKalle Valo 
4609d5c65159SKalle Valo 	/* Num HTT cookies dispatched */
4610d5c65159SKalle Valo 	s32 comp_delivered;
4611d5c65159SKalle Valo 
4612d5c65159SKalle Valo 	/* Num MSDU queued to WAL */
4613d5c65159SKalle Valo 	s32 msdu_enqued;
4614d5c65159SKalle Valo 
4615d5c65159SKalle Valo 	/* Num MPDU queue to WAL */
4616d5c65159SKalle Valo 	s32 mpdu_enqued;
4617d5c65159SKalle Valo 
4618d5c65159SKalle Valo 	/* Num MSDUs dropped by WMM limit */
4619d5c65159SKalle Valo 	s32 wmm_drop;
4620d5c65159SKalle Valo 
4621d5c65159SKalle Valo 	/* Num Local frames queued */
4622d5c65159SKalle Valo 	s32 local_enqued;
4623d5c65159SKalle Valo 
4624d5c65159SKalle Valo 	/* Num Local frames done */
4625d5c65159SKalle Valo 	s32 local_freed;
4626d5c65159SKalle Valo 
4627d5c65159SKalle Valo 	/* Num queued to HW */
4628d5c65159SKalle Valo 	s32 hw_queued;
4629d5c65159SKalle Valo 
4630d5c65159SKalle Valo 	/* Num PPDU reaped from HW */
4631d5c65159SKalle Valo 	s32 hw_reaped;
4632d5c65159SKalle Valo 
4633d5c65159SKalle Valo 	/* Num underruns */
4634d5c65159SKalle Valo 	s32 underrun;
4635d5c65159SKalle Valo 
4636f394e4eaSSriram R 	/* Num hw paused */
4637f394e4eaSSriram R 	u32 hw_paused;
4638f394e4eaSSriram R 
4639d5c65159SKalle Valo 	/* Num PPDUs cleaned up in TX abort */
4640d5c65159SKalle Valo 	s32 tx_abort;
4641d5c65159SKalle Valo 
464217818dfaSColin Ian King 	/* Num MPDUs requeued by SW */
464317818dfaSColin Ian King 	s32 mpdus_requeued;
4644d5c65159SKalle Valo 
4645d5c65159SKalle Valo 	/* excessive retries */
4646d5c65159SKalle Valo 	u32 tx_ko;
4647d5c65159SKalle Valo 
4648f394e4eaSSriram R 	u32 tx_xretry;
4649f394e4eaSSriram R 
4650d5c65159SKalle Valo 	/* data hw rate code */
4651d5c65159SKalle Valo 	u32 data_rc;
4652d5c65159SKalle Valo 
4653d5c65159SKalle Valo 	/* Scheduler self triggers */
4654d5c65159SKalle Valo 	u32 self_triggers;
4655d5c65159SKalle Valo 
4656d5c65159SKalle Valo 	/* frames dropped due to excessive sw retries */
4657d5c65159SKalle Valo 	u32 sw_retry_failure;
4658d5c65159SKalle Valo 
4659d5c65159SKalle Valo 	/* illegal rate phy errors  */
4660d5c65159SKalle Valo 	u32 illgl_rate_phy_err;
4661d5c65159SKalle Valo 
4662d5c65159SKalle Valo 	/* wal pdev continuous xretry */
4663d5c65159SKalle Valo 	u32 pdev_cont_xretry;
4664d5c65159SKalle Valo 
4665d5c65159SKalle Valo 	/* wal pdev tx timeouts */
4666d5c65159SKalle Valo 	u32 pdev_tx_timeout;
4667d5c65159SKalle Valo 
4668d5c65159SKalle Valo 	/* wal pdev resets  */
4669d5c65159SKalle Valo 	u32 pdev_resets;
4670d5c65159SKalle Valo 
4671d5c65159SKalle Valo 	/* frames dropped due to non-availability of stateless TIDs */
4672d5c65159SKalle Valo 	u32 stateless_tid_alloc_failure;
4673d5c65159SKalle Valo 
4674d5c65159SKalle Valo 	/* PhY/BB underrun */
4675d5c65159SKalle Valo 	u32 phy_underrun;
4676d5c65159SKalle Valo 
4677d5c65159SKalle Valo 	/* MPDU is more than txop limit */
4678d5c65159SKalle Valo 	u32 txop_ovf;
4679f394e4eaSSriram R 
4680f394e4eaSSriram R 	/* Num sequences posted */
4681f394e4eaSSriram R 	u32 seq_posted;
4682f394e4eaSSriram R 
4683f394e4eaSSriram R 	/* Num sequences failed in queueing */
4684f394e4eaSSriram R 	u32 seq_failed_queueing;
4685f394e4eaSSriram R 
4686f394e4eaSSriram R 	/* Num sequences completed */
4687f394e4eaSSriram R 	u32 seq_completed;
4688f394e4eaSSriram R 
4689f394e4eaSSriram R 	/* Num sequences restarted */
4690f394e4eaSSriram R 	u32 seq_restarted;
4691f394e4eaSSriram R 
4692f394e4eaSSriram R 	/* Num of MU sequences posted */
4693f394e4eaSSriram R 	u32 mu_seq_posted;
4694f394e4eaSSriram R 
4695f394e4eaSSriram R 	/* Num MPDUs flushed by SW, HWPAUSED, SW TXABORT
4696f394e4eaSSriram R 	 * (Reset,channel change)
4697f394e4eaSSriram R 	 */
4698f394e4eaSSriram R 	s32 mpdus_sw_flush;
4699f394e4eaSSriram R 
4700f394e4eaSSriram R 	/* Num MPDUs filtered by HW, all filter condition (TTL expired) */
4701f394e4eaSSriram R 	s32 mpdus_hw_filter;
4702f394e4eaSSriram R 
4703f394e4eaSSriram R 	/* Num MPDUs truncated by PDG (TXOP, TBTT,
4704f394e4eaSSriram R 	 * PPDU_duration based on rate, dyn_bw)
4705f394e4eaSSriram R 	 */
4706f394e4eaSSriram R 	s32 mpdus_truncated;
4707f394e4eaSSriram R 
4708f394e4eaSSriram R 	/* Num MPDUs that was tried but didn't receive ACK or BA */
4709f394e4eaSSriram R 	s32 mpdus_ack_failed;
4710f394e4eaSSriram R 
4711f394e4eaSSriram R 	/* Num MPDUs that was dropped du to expiry. */
4712f394e4eaSSriram R 	s32 mpdus_expired;
4713d5c65159SKalle Valo } __packed;
4714d5c65159SKalle Valo 
4715d5c65159SKalle Valo struct wmi_pdev_stats_rx {
4716d5c65159SKalle Valo 	/* Cnts any change in ring routing mid-ppdu */
4717d5c65159SKalle Valo 	s32 mid_ppdu_route_change;
4718d5c65159SKalle Valo 
4719d5c65159SKalle Valo 	/* Total number of statuses processed */
4720d5c65159SKalle Valo 	s32 status_rcvd;
4721d5c65159SKalle Valo 
4722d5c65159SKalle Valo 	/* Extra frags on rings 0-3 */
4723d5c65159SKalle Valo 	s32 r0_frags;
4724d5c65159SKalle Valo 	s32 r1_frags;
4725d5c65159SKalle Valo 	s32 r2_frags;
4726d5c65159SKalle Valo 	s32 r3_frags;
4727d5c65159SKalle Valo 
4728d5c65159SKalle Valo 	/* MSDUs / MPDUs delivered to HTT */
4729d5c65159SKalle Valo 	s32 htt_msdus;
4730d5c65159SKalle Valo 	s32 htt_mpdus;
4731d5c65159SKalle Valo 
4732d5c65159SKalle Valo 	/* MSDUs / MPDUs delivered to local stack */
4733d5c65159SKalle Valo 	s32 loc_msdus;
4734d5c65159SKalle Valo 	s32 loc_mpdus;
4735d5c65159SKalle Valo 
4736d5c65159SKalle Valo 	/* AMSDUs that have more MSDUs than the status ring size */
4737d5c65159SKalle Valo 	s32 oversize_amsdu;
4738d5c65159SKalle Valo 
4739d5c65159SKalle Valo 	/* Number of PHY errors */
4740d5c65159SKalle Valo 	s32 phy_errs;
4741d5c65159SKalle Valo 
4742d5c65159SKalle Valo 	/* Number of PHY errors drops */
4743d5c65159SKalle Valo 	s32 phy_err_drop;
4744d5c65159SKalle Valo 
4745d5c65159SKalle Valo 	/* Number of mpdu errors - FCS, MIC, ENC etc. */
4746d5c65159SKalle Valo 	s32 mpdu_errs;
4747f394e4eaSSriram R 
4748f394e4eaSSriram R 	/* Num overflow errors */
4749f394e4eaSSriram R 	s32 rx_ovfl_errs;
4750d5c65159SKalle Valo } __packed;
4751d5c65159SKalle Valo 
4752d5c65159SKalle Valo struct wmi_pdev_stats {
4753d5c65159SKalle Valo 	struct wmi_pdev_stats_base base;
4754d5c65159SKalle Valo 	struct wmi_pdev_stats_tx tx;
4755d5c65159SKalle Valo 	struct wmi_pdev_stats_rx rx;
4756d5c65159SKalle Valo } __packed;
4757d5c65159SKalle Valo 
4758d5c65159SKalle Valo #define WLAN_MAX_AC 4
4759d5c65159SKalle Valo #define MAX_TX_RATE_VALUES 10
4760d5c65159SKalle Valo #define MAX_TX_RATE_VALUES 10
4761d5c65159SKalle Valo 
4762d5c65159SKalle Valo struct wmi_vdev_stats {
4763d5c65159SKalle Valo 	u32 vdev_id;
4764d5c65159SKalle Valo 	u32 beacon_snr;
4765d5c65159SKalle Valo 	u32 data_snr;
4766d5c65159SKalle Valo 	u32 num_tx_frames[WLAN_MAX_AC];
4767d5c65159SKalle Valo 	u32 num_rx_frames;
4768d5c65159SKalle Valo 	u32 num_tx_frames_retries[WLAN_MAX_AC];
4769d5c65159SKalle Valo 	u32 num_tx_frames_failures[WLAN_MAX_AC];
4770d5c65159SKalle Valo 	u32 num_rts_fail;
4771d5c65159SKalle Valo 	u32 num_rts_success;
4772d5c65159SKalle Valo 	u32 num_rx_err;
4773d5c65159SKalle Valo 	u32 num_rx_discard;
4774d5c65159SKalle Valo 	u32 num_tx_not_acked;
4775d5c65159SKalle Valo 	u32 tx_rate_history[MAX_TX_RATE_VALUES];
4776d5c65159SKalle Valo 	u32 beacon_rssi_history[MAX_TX_RATE_VALUES];
4777d5c65159SKalle Valo } __packed;
4778d5c65159SKalle Valo 
4779d5c65159SKalle Valo struct wmi_bcn_stats {
4780d5c65159SKalle Valo 	u32 vdev_id;
4781d5c65159SKalle Valo 	u32 tx_bcn_succ_cnt;
4782d5c65159SKalle Valo 	u32 tx_bcn_outage_cnt;
4783d5c65159SKalle Valo } __packed;
4784d5c65159SKalle Valo 
4785d5c65159SKalle Valo struct wmi_stats_event {
4786d5c65159SKalle Valo 	u32 stats_id;
4787d5c65159SKalle Valo 	u32 num_pdev_stats;
4788d5c65159SKalle Valo 	u32 num_vdev_stats;
4789d5c65159SKalle Valo 	u32 num_peer_stats;
4790d5c65159SKalle Valo 	u32 num_bcnflt_stats;
4791d5c65159SKalle Valo 	u32 num_chan_stats;
4792d5c65159SKalle Valo 	u32 num_mib_stats;
4793d5c65159SKalle Valo 	u32 pdev_id;
4794d5c65159SKalle Valo 	u32 num_bcn_stats;
4795d5c65159SKalle Valo 	u32 num_peer_extd_stats;
4796d5c65159SKalle Valo 	u32 num_peer_extd2_stats;
4797d5c65159SKalle Valo } __packed;
4798d5c65159SKalle Valo 
4799b488c766SWen Gong struct wmi_rssi_stats {
4800b488c766SWen Gong 	u32 vdev_id;
4801b488c766SWen Gong 	u32 rssi_avg_beacon[WMI_MAX_CHAINS];
4802b488c766SWen Gong 	u32 rssi_avg_data[WMI_MAX_CHAINS];
4803b488c766SWen Gong 	struct wmi_mac_addr peer_macaddr;
4804b488c766SWen Gong } __packed;
4805b488c766SWen Gong 
4806b488c766SWen Gong struct wmi_per_chain_rssi_stats {
4807b488c766SWen Gong 	u32 num_per_chain_rssi_stats;
4808b488c766SWen Gong } __packed;
4809b488c766SWen Gong 
4810d5c65159SKalle Valo struct wmi_pdev_ctl_failsafe_chk_event {
4811d5c65159SKalle Valo 	u32 pdev_id;
4812d5c65159SKalle Valo 	u32 ctl_failsafe_status;
4813d5c65159SKalle Valo } __packed;
4814d5c65159SKalle Valo 
4815d5c65159SKalle Valo struct wmi_pdev_csa_switch_ev {
4816d5c65159SKalle Valo 	u32 pdev_id;
4817d5c65159SKalle Valo 	u32 current_switch_count;
4818d5c65159SKalle Valo 	u32 num_vdevs;
4819d5c65159SKalle Valo } __packed;
4820d5c65159SKalle Valo 
4821d5c65159SKalle Valo struct wmi_pdev_radar_ev {
4822d5c65159SKalle Valo 	u32 pdev_id;
4823d5c65159SKalle Valo 	u32 detection_mode;
4824d5c65159SKalle Valo 	u32 chan_freq;
4825d5c65159SKalle Valo 	u32 chan_width;
4826d5c65159SKalle Valo 	u32 detector_id;
4827d5c65159SKalle Valo 	u32 segment_id;
4828d5c65159SKalle Valo 	u32 timestamp;
4829d5c65159SKalle Valo 	u32 is_chirp;
4830d5c65159SKalle Valo 	s32 freq_offset;
4831d5c65159SKalle Valo 	s32 sidx;
4832d5c65159SKalle Valo } __packed;
4833d5c65159SKalle Valo 
4834a41d1034SPradeep Kumar Chitrapu struct wmi_pdev_temperature_event {
48353fecca0eSJeff Johnson 	/* temperature value in Celsius degree */
4836a41d1034SPradeep Kumar Chitrapu 	s32 temp;
4837a41d1034SPradeep Kumar Chitrapu 	u32 pdev_id;
4838a41d1034SPradeep Kumar Chitrapu } __packed;
4839a41d1034SPradeep Kumar Chitrapu 
4840d5c65159SKalle Valo #define WMI_RX_STATUS_OK			0x00
4841d5c65159SKalle Valo #define WMI_RX_STATUS_ERR_CRC			0x01
4842d5c65159SKalle Valo #define WMI_RX_STATUS_ERR_DECRYPT		0x08
4843d5c65159SKalle Valo #define WMI_RX_STATUS_ERR_MIC			0x10
4844d5c65159SKalle Valo #define WMI_RX_STATUS_ERR_KEY_CACHE_MISS	0x20
4845d5c65159SKalle Valo 
4846d5c65159SKalle Valo #define WLAN_MGMT_TXRX_HOST_MAX_ANTENNA 4
4847d5c65159SKalle Valo 
4848d5c65159SKalle Valo struct mgmt_rx_event_params {
48495dcf42f8SPradeep Kumar Chitrapu 	u32 chan_freq;
4850d5c65159SKalle Valo 	u32 channel;
4851d5c65159SKalle Valo 	u32 snr;
4852d5c65159SKalle Valo 	u8 rssi_ctl[WLAN_MGMT_TXRX_HOST_MAX_ANTENNA];
4853d5c65159SKalle Valo 	u32 rate;
4854d5c65159SKalle Valo 	enum wmi_phy_mode phy_mode;
4855d5c65159SKalle Valo 	u32 buf_len;
4856d5c65159SKalle Valo 	int status;
4857d5c65159SKalle Valo 	u32 flags;
4858d5c65159SKalle Valo 	int rssi;
4859d5c65159SKalle Valo 	u32 tsf_delta;
4860d5c65159SKalle Valo 	u8 pdev_id;
4861d5c65159SKalle Valo };
4862d5c65159SKalle Valo 
4863d5c65159SKalle Valo #define ATH_MAX_ANTENNA 4
4864d5c65159SKalle Valo 
4865d5c65159SKalle Valo struct wmi_mgmt_rx_hdr {
4866d5c65159SKalle Valo 	u32 channel;
4867d5c65159SKalle Valo 	u32 snr;
4868d5c65159SKalle Valo 	u32 rate;
4869d5c65159SKalle Valo 	u32 phy_mode;
4870d5c65159SKalle Valo 	u32 buf_len;
4871d5c65159SKalle Valo 	u32 status;
4872d5c65159SKalle Valo 	u32 rssi_ctl[ATH_MAX_ANTENNA];
4873d5c65159SKalle Valo 	u32 flags;
4874d5c65159SKalle Valo 	int rssi;
4875d5c65159SKalle Valo 	u32 tsf_delta;
4876d5c65159SKalle Valo 	u32 rx_tsf_l32;
4877d5c65159SKalle Valo 	u32 rx_tsf_u32;
4878d5c65159SKalle Valo 	u32 pdev_id;
48795dcf42f8SPradeep Kumar Chitrapu 	u32 chan_freq;
4880d5c65159SKalle Valo } __packed;
4881d5c65159SKalle Valo 
4882d5c65159SKalle Valo #define MAX_ANTENNA_EIGHT 8
4883d5c65159SKalle Valo 
4884d5c65159SKalle Valo struct wmi_rssi_ctl_ext {
4885d5c65159SKalle Valo 	u32 tlv_header;
4886d5c65159SKalle Valo 	u32 rssi_ctl_ext[MAX_ANTENNA_EIGHT - ATH_MAX_ANTENNA];
4887d5c65159SKalle Valo };
4888d5c65159SKalle Valo 
4889d5c65159SKalle Valo struct wmi_mgmt_tx_compl_event {
4890d5c65159SKalle Valo 	u32 desc_id;
4891d5c65159SKalle Valo 	u32 status;
4892d5c65159SKalle Valo 	u32 pdev_id;
489301c6c9fcSAbinaya Kalaiselvan 	u32 ppdu_id;
489401c6c9fcSAbinaya Kalaiselvan 	u32 ack_rssi;
4895d5c65159SKalle Valo } __packed;
4896d5c65159SKalle Valo 
4897d5c65159SKalle Valo struct wmi_scan_event {
4898d5c65159SKalle Valo 	u32 event_type; /* %WMI_SCAN_EVENT_ */
4899d5c65159SKalle Valo 	u32 reason; /* %WMI_SCAN_REASON_ */
4900d5c65159SKalle Valo 	u32 channel_freq; /* only valid for WMI_SCAN_EVENT_FOREIGN_CHANNEL */
4901d5c65159SKalle Valo 	u32 scan_req_id;
4902d5c65159SKalle Valo 	u32 scan_id;
4903d5c65159SKalle Valo 	u32 vdev_id;
4904d5c65159SKalle Valo 	/* TSF Timestamp when the scan event (%WMI_SCAN_EVENT_) is completed
4905d5c65159SKalle Valo 	 * In case of AP it is TSF of the AP vdev
4906d5c65159SKalle Valo 	 * In case of STA connected state, this is the TSF of the AP
4907d5c65159SKalle Valo 	 * In case of STA not connected, it will be the free running HW timer
4908d5c65159SKalle Valo 	 */
4909d5c65159SKalle Valo 	u32 tsf_timestamp;
4910d5c65159SKalle Valo } __packed;
4911d5c65159SKalle Valo 
4912d5c65159SKalle Valo struct wmi_peer_sta_kickout_arg {
4913d5c65159SKalle Valo 	const u8 *mac_addr;
4914d5c65159SKalle Valo };
4915d5c65159SKalle Valo 
4916d5c65159SKalle Valo struct wmi_peer_sta_kickout_event {
4917d5c65159SKalle Valo 	struct wmi_mac_addr peer_macaddr;
4918d5c65159SKalle Valo } __packed;
4919d5c65159SKalle Valo 
4920d5c65159SKalle Valo enum wmi_roam_reason {
4921d5c65159SKalle Valo 	WMI_ROAM_REASON_BETTER_AP = 1,
4922d5c65159SKalle Valo 	WMI_ROAM_REASON_BEACON_MISS = 2,
4923d5c65159SKalle Valo 	WMI_ROAM_REASON_LOW_RSSI = 3,
4924d5c65159SKalle Valo 	WMI_ROAM_REASON_SUITABLE_AP_FOUND = 4,
4925d5c65159SKalle Valo 	WMI_ROAM_REASON_HO_FAILED = 5,
4926d5c65159SKalle Valo 
4927d5c65159SKalle Valo 	/* keep last */
4928d5c65159SKalle Valo 	WMI_ROAM_REASON_MAX,
4929d5c65159SKalle Valo };
4930d5c65159SKalle Valo 
4931d5c65159SKalle Valo struct wmi_roam_event {
4932d5c65159SKalle Valo 	u32 vdev_id;
4933d5c65159SKalle Valo 	u32 reason;
4934d5c65159SKalle Valo 	u32 rssi;
4935d5c65159SKalle Valo } __packed;
4936d5c65159SKalle Valo 
4937d5c65159SKalle Valo #define WMI_CHAN_INFO_START_RESP 0
4938d5c65159SKalle Valo #define WMI_CHAN_INFO_END_RESP 1
4939d5c65159SKalle Valo 
4940d5c65159SKalle Valo struct wmi_chan_info_event {
4941d5c65159SKalle Valo 	u32 err_code;
4942d5c65159SKalle Valo 	u32 freq;
4943d5c65159SKalle Valo 	u32 cmd_flags;
4944d5c65159SKalle Valo 	u32 noise_floor;
4945d5c65159SKalle Valo 	u32 rx_clear_count;
4946d5c65159SKalle Valo 	u32 cycle_count;
4947d5c65159SKalle Valo 	u32 chan_tx_pwr_range;
4948d5c65159SKalle Valo 	u32 chan_tx_pwr_tp;
4949d5c65159SKalle Valo 	u32 rx_frame_count;
4950d5c65159SKalle Valo 	u32 my_bss_rx_cycle_count;
4951d5c65159SKalle Valo 	u32 rx_11b_mode_data_duration;
4952d5c65159SKalle Valo 	u32 tx_frame_cnt;
4953d5c65159SKalle Valo 	u32 mac_clk_mhz;
4954d5c65159SKalle Valo 	u32 vdev_id;
4955d5c65159SKalle Valo } __packed;
4956d5c65159SKalle Valo 
4957d5c65159SKalle Valo struct ath11k_targ_cap {
4958d5c65159SKalle Valo 	u32 phy_capability;
4959d5c65159SKalle Valo 	u32 max_frag_entry;
4960d5c65159SKalle Valo 	u32 num_rf_chains;
4961d5c65159SKalle Valo 	u32 ht_cap_info;
4962d5c65159SKalle Valo 	u32 vht_cap_info;
4963d5c65159SKalle Valo 	u32 vht_supp_mcs;
4964d5c65159SKalle Valo 	u32 hw_min_tx_power;
4965d5c65159SKalle Valo 	u32 hw_max_tx_power;
4966d5c65159SKalle Valo 	u32 sys_cap_info;
4967d5c65159SKalle Valo 	u32 min_pkt_size_enable;
4968d5c65159SKalle Valo 	u32 max_bcn_ie_size;
4969d5c65159SKalle Valo 	u32 max_num_scan_channels;
4970d5c65159SKalle Valo 	u32 max_supported_macs;
4971d5c65159SKalle Valo 	u32 wmi_fw_sub_feat_caps;
4972d5c65159SKalle Valo 	u32 txrx_chainmask;
4973d5c65159SKalle Valo 	u32 default_dbs_hw_mode_index;
4974d5c65159SKalle Valo 	u32 num_msdu_desc;
4975d5c65159SKalle Valo };
4976d5c65159SKalle Valo 
4977d5c65159SKalle Valo enum wmi_vdev_type {
4978d5c65159SKalle Valo 	WMI_VDEV_TYPE_AP      = 1,
4979d5c65159SKalle Valo 	WMI_VDEV_TYPE_STA     = 2,
4980d5c65159SKalle Valo 	WMI_VDEV_TYPE_IBSS    = 3,
4981d5c65159SKalle Valo 	WMI_VDEV_TYPE_MONITOR = 4,
4982d5c65159SKalle Valo };
4983d5c65159SKalle Valo 
4984d5c65159SKalle Valo enum wmi_vdev_subtype {
4985d5c65159SKalle Valo 	WMI_VDEV_SUBTYPE_NONE,
4986d5c65159SKalle Valo 	WMI_VDEV_SUBTYPE_P2P_DEVICE,
4987d5c65159SKalle Valo 	WMI_VDEV_SUBTYPE_P2P_CLIENT,
4988d5c65159SKalle Valo 	WMI_VDEV_SUBTYPE_P2P_GO,
4989d5c65159SKalle Valo 	WMI_VDEV_SUBTYPE_PROXY_STA,
4990d5c65159SKalle Valo 	WMI_VDEV_SUBTYPE_MESH_NON_11S,
4991d5c65159SKalle Valo 	WMI_VDEV_SUBTYPE_MESH_11S,
4992d5c65159SKalle Valo };
4993d5c65159SKalle Valo 
4994d5c65159SKalle Valo enum wmi_sta_powersave_param {
4995d5c65159SKalle Valo 	WMI_STA_PS_PARAM_RX_WAKE_POLICY = 0,
4996d5c65159SKalle Valo 	WMI_STA_PS_PARAM_TX_WAKE_THRESHOLD = 1,
4997d5c65159SKalle Valo 	WMI_STA_PS_PARAM_PSPOLL_COUNT = 2,
4998d5c65159SKalle Valo 	WMI_STA_PS_PARAM_INACTIVITY_TIME = 3,
4999d5c65159SKalle Valo 	WMI_STA_PS_PARAM_UAPSD = 4,
5000d5c65159SKalle Valo };
5001d5c65159SKalle Valo 
5002d5c65159SKalle Valo #define WMI_UAPSD_AC_TYPE_DELI 0
5003d5c65159SKalle Valo #define WMI_UAPSD_AC_TYPE_TRIG 1
5004d5c65159SKalle Valo 
5005d5c65159SKalle Valo #define WMI_UAPSD_AC_BIT_MASK(ac, type) \
5006d5c65159SKalle Valo 	((type ==  WMI_UAPSD_AC_TYPE_DELI) ? \
5007d5c65159SKalle Valo 	 (1 << (ac << 1)) : (1 << ((ac << 1) + 1)))
5008d5c65159SKalle Valo 
5009d5c65159SKalle Valo enum wmi_sta_ps_param_uapsd {
5010d5c65159SKalle Valo 	WMI_STA_PS_UAPSD_AC0_DELIVERY_EN = (1 << 0),
5011d5c65159SKalle Valo 	WMI_STA_PS_UAPSD_AC0_TRIGGER_EN  = (1 << 1),
5012d5c65159SKalle Valo 	WMI_STA_PS_UAPSD_AC1_DELIVERY_EN = (1 << 2),
5013d5c65159SKalle Valo 	WMI_STA_PS_UAPSD_AC1_TRIGGER_EN  = (1 << 3),
5014d5c65159SKalle Valo 	WMI_STA_PS_UAPSD_AC2_DELIVERY_EN = (1 << 4),
5015d5c65159SKalle Valo 	WMI_STA_PS_UAPSD_AC2_TRIGGER_EN  = (1 << 5),
5016d5c65159SKalle Valo 	WMI_STA_PS_UAPSD_AC3_DELIVERY_EN = (1 << 6),
5017d5c65159SKalle Valo 	WMI_STA_PS_UAPSD_AC3_TRIGGER_EN  = (1 << 7),
5018d5c65159SKalle Valo };
5019d5c65159SKalle Valo 
5020d5c65159SKalle Valo #define WMI_STA_UAPSD_MAX_INTERVAL_MSEC UINT_MAX
5021d5c65159SKalle Valo 
5022d5c65159SKalle Valo struct wmi_sta_uapsd_auto_trig_param {
5023d5c65159SKalle Valo 	u32 wmm_ac;
5024d5c65159SKalle Valo 	u32 user_priority;
5025d5c65159SKalle Valo 	u32 service_interval;
5026d5c65159SKalle Valo 	u32 suspend_interval;
5027d5c65159SKalle Valo 	u32 delay_interval;
5028d5c65159SKalle Valo };
5029d5c65159SKalle Valo 
5030d5c65159SKalle Valo struct wmi_sta_uapsd_auto_trig_cmd_fixed_param {
5031d5c65159SKalle Valo 	u32 vdev_id;
5032d5c65159SKalle Valo 	struct wmi_mac_addr peer_macaddr;
5033d5c65159SKalle Valo 	u32 num_ac;
5034d5c65159SKalle Valo };
5035d5c65159SKalle Valo 
5036d5c65159SKalle Valo struct wmi_sta_uapsd_auto_trig_arg {
5037d5c65159SKalle Valo 	u32 wmm_ac;
5038d5c65159SKalle Valo 	u32 user_priority;
5039d5c65159SKalle Valo 	u32 service_interval;
5040d5c65159SKalle Valo 	u32 suspend_interval;
5041d5c65159SKalle Valo 	u32 delay_interval;
5042d5c65159SKalle Valo };
5043d5c65159SKalle Valo 
5044d5c65159SKalle Valo enum wmi_sta_ps_param_tx_wake_threshold {
5045d5c65159SKalle Valo 	WMI_STA_PS_TX_WAKE_THRESHOLD_NEVER = 0,
5046d5c65159SKalle Valo 	WMI_STA_PS_TX_WAKE_THRESHOLD_ALWAYS = 1,
5047d5c65159SKalle Valo 
5048d5c65159SKalle Valo 	/* Values greater than one indicate that many TX attempts per beacon
5049d5c65159SKalle Valo 	 * interval before the STA will wake up
5050d5c65159SKalle Valo 	 */
5051d5c65159SKalle Valo };
5052d5c65159SKalle Valo 
5053d5c65159SKalle Valo /* The maximum number of PS-Poll frames the FW will send in response to
5054d5c65159SKalle Valo  * traffic advertised in TIM before waking up (by sending a null frame with PS
5055d5c65159SKalle Valo  * = 0). Value 0 has a special meaning: there is no maximum count and the FW
5056d5c65159SKalle Valo  * will send as many PS-Poll as are necessary to retrieve buffered BU. This
5057d5c65159SKalle Valo  * parameter is used when the RX wake policy is
5058d5c65159SKalle Valo  * WMI_STA_PS_RX_WAKE_POLICY_POLL_UAPSD and ignored when the RX wake
5059d5c65159SKalle Valo  * policy is WMI_STA_PS_RX_WAKE_POLICY_WAKE.
5060d5c65159SKalle Valo  */
5061d5c65159SKalle Valo enum wmi_sta_ps_param_pspoll_count {
5062d5c65159SKalle Valo 	WMI_STA_PS_PSPOLL_COUNT_NO_MAX = 0,
50633fecca0eSJeff Johnson 	/* Values greater than 0 indicate the maximum number of PS-Poll frames
5064d5c65159SKalle Valo 	 * FW will send before waking up.
5065d5c65159SKalle Valo 	 */
5066d5c65159SKalle Valo };
5067d5c65159SKalle Valo 
5068d5c65159SKalle Valo /* U-APSD configuration of peer station from (re)assoc request and TSPECs */
5069d5c65159SKalle Valo enum wmi_ap_ps_param_uapsd {
5070d5c65159SKalle Valo 	WMI_AP_PS_UAPSD_AC0_DELIVERY_EN = (1 << 0),
5071d5c65159SKalle Valo 	WMI_AP_PS_UAPSD_AC0_TRIGGER_EN  = (1 << 1),
5072d5c65159SKalle Valo 	WMI_AP_PS_UAPSD_AC1_DELIVERY_EN = (1 << 2),
5073d5c65159SKalle Valo 	WMI_AP_PS_UAPSD_AC1_TRIGGER_EN  = (1 << 3),
5074d5c65159SKalle Valo 	WMI_AP_PS_UAPSD_AC2_DELIVERY_EN = (1 << 4),
5075d5c65159SKalle Valo 	WMI_AP_PS_UAPSD_AC2_TRIGGER_EN  = (1 << 5),
5076d5c65159SKalle Valo 	WMI_AP_PS_UAPSD_AC3_DELIVERY_EN = (1 << 6),
5077d5c65159SKalle Valo 	WMI_AP_PS_UAPSD_AC3_TRIGGER_EN  = (1 << 7),
5078d5c65159SKalle Valo };
5079d5c65159SKalle Valo 
5080d5c65159SKalle Valo /* U-APSD maximum service period of peer station */
5081d5c65159SKalle Valo enum wmi_ap_ps_peer_param_max_sp {
5082d5c65159SKalle Valo 	WMI_AP_PS_PEER_PARAM_MAX_SP_UNLIMITED = 0,
5083d5c65159SKalle Valo 	WMI_AP_PS_PEER_PARAM_MAX_SP_2 = 1,
5084d5c65159SKalle Valo 	WMI_AP_PS_PEER_PARAM_MAX_SP_4 = 2,
5085d5c65159SKalle Valo 	WMI_AP_PS_PEER_PARAM_MAX_SP_6 = 3,
5086d5c65159SKalle Valo 	MAX_WMI_AP_PS_PEER_PARAM_MAX_SP,
5087d5c65159SKalle Valo };
5088d5c65159SKalle Valo 
5089d5c65159SKalle Valo enum wmi_ap_ps_peer_param {
5090d5c65159SKalle Valo 	/** Set uapsd configuration for a given peer.
5091d5c65159SKalle Valo 	 *
5092d5c65159SKalle Valo 	 * This include the delivery and trigger enabled state for each AC.
5093d5c65159SKalle Valo 	 * The host MLME needs to set this based on AP capability and stations
5094d5c65159SKalle Valo 	 * request Set in the association request  received from the station.
5095d5c65159SKalle Valo 	 *
5096d5c65159SKalle Valo 	 * Lower 8 bits of the value specify the UAPSD configuration.
5097d5c65159SKalle Valo 	 *
5098d5c65159SKalle Valo 	 * (see enum wmi_ap_ps_param_uapsd)
5099d5c65159SKalle Valo 	 * The default value is 0.
5100d5c65159SKalle Valo 	 */
5101d5c65159SKalle Valo 	WMI_AP_PS_PEER_PARAM_UAPSD = 0,
5102d5c65159SKalle Valo 
5103d5c65159SKalle Valo 	/**
5104d5c65159SKalle Valo 	 * Set the service period for a UAPSD capable station
5105d5c65159SKalle Valo 	 *
5106d5c65159SKalle Valo 	 * The service period from wme ie in the (re)assoc request frame.
5107d5c65159SKalle Valo 	 *
5108d5c65159SKalle Valo 	 * (see enum wmi_ap_ps_peer_param_max_sp)
5109d5c65159SKalle Valo 	 */
5110d5c65159SKalle Valo 	WMI_AP_PS_PEER_PARAM_MAX_SP = 1,
5111d5c65159SKalle Valo 
5112d5c65159SKalle Valo 	/** Time in seconds for aging out buffered frames
5113d5c65159SKalle Valo 	 * for STA in power save
5114d5c65159SKalle Valo 	 */
5115d5c65159SKalle Valo 	WMI_AP_PS_PEER_PARAM_AGEOUT_TIME = 2,
5116d5c65159SKalle Valo 
5117d5c65159SKalle Valo 	/** Specify frame types that are considered SIFS
5118d5c65159SKalle Valo 	 * RESP trigger frame
5119d5c65159SKalle Valo 	 */
5120d5c65159SKalle Valo 	WMI_AP_PS_PEER_PARAM_SIFS_RESP_FRMTYPE = 3,
5121d5c65159SKalle Valo 
5122d5c65159SKalle Valo 	/** Specifies the trigger state of TID.
5123d5c65159SKalle Valo 	 * Valid only for UAPSD frame type
5124d5c65159SKalle Valo 	 */
5125d5c65159SKalle Valo 	WMI_AP_PS_PEER_PARAM_SIFS_RESP_UAPSD = 4,
5126d5c65159SKalle Valo 
5127d5c65159SKalle Valo 	/* Specifies the WNM sleep state of a STA */
5128d5c65159SKalle Valo 	WMI_AP_PS_PEER_PARAM_WNM_SLEEP = 5,
5129d5c65159SKalle Valo };
5130d5c65159SKalle Valo 
5131d5c65159SKalle Valo #define DISABLE_SIFS_RESPONSE_TRIGGER 0
5132d5c65159SKalle Valo 
5133d5c65159SKalle Valo #define WMI_MAX_KEY_INDEX   3
5134d5c65159SKalle Valo #define WMI_MAX_KEY_LEN     32
5135d5c65159SKalle Valo 
5136d5c65159SKalle Valo #define WMI_KEY_PAIRWISE 0x00
5137d5c65159SKalle Valo #define WMI_KEY_GROUP    0x01
5138d5c65159SKalle Valo 
5139d5c65159SKalle Valo #define WMI_CIPHER_NONE     0x0 /* clear key */
5140d5c65159SKalle Valo #define WMI_CIPHER_WEP      0x1
5141d5c65159SKalle Valo #define WMI_CIPHER_TKIP     0x2
5142d5c65159SKalle Valo #define WMI_CIPHER_AES_OCB  0x3
5143d5c65159SKalle Valo #define WMI_CIPHER_AES_CCM  0x4
5144d5c65159SKalle Valo #define WMI_CIPHER_WAPI     0x5
5145d5c65159SKalle Valo #define WMI_CIPHER_CKIP     0x6
5146d5c65159SKalle Valo #define WMI_CIPHER_AES_CMAC 0x7
5147d5c65159SKalle Valo #define WMI_CIPHER_ANY      0x8
5148d5c65159SKalle Valo #define WMI_CIPHER_AES_GCM  0x9
5149d5c65159SKalle Valo #define WMI_CIPHER_AES_GMAC 0xa
5150d5c65159SKalle Valo 
5151d5c65159SKalle Valo /* Value to disable fixed rate setting */
5152d5c65159SKalle Valo #define WMI_FIXED_RATE_NONE	(0xffff)
5153d5c65159SKalle Valo 
5154d5c65159SKalle Valo #define ATH11K_RC_VERSION_OFFSET	28
5155d5c65159SKalle Valo #define ATH11K_RC_PREAMBLE_OFFSET	8
5156d5c65159SKalle Valo #define ATH11K_RC_NSS_OFFSET		5
5157d5c65159SKalle Valo 
5158d5c65159SKalle Valo #define ATH11K_HW_RATE_CODE(rate, nss, preamble)	\
5159d5c65159SKalle Valo 	((1 << ATH11K_RC_VERSION_OFFSET) |		\
5160d5c65159SKalle Valo 	 ((nss) << ATH11K_RC_NSS_OFFSET) |		\
5161d5c65159SKalle Valo 	 ((preamble) << ATH11K_RC_PREAMBLE_OFFSET) |	\
5162d5c65159SKalle Valo 	 (rate))
5163d5c65159SKalle Valo 
5164d5c65159SKalle Valo /* Preamble types to be used with VDEV fixed rate configuration */
5165d5c65159SKalle Valo enum wmi_rate_preamble {
5166d5c65159SKalle Valo 	WMI_RATE_PREAMBLE_OFDM,
5167d5c65159SKalle Valo 	WMI_RATE_PREAMBLE_CCK,
5168d5c65159SKalle Valo 	WMI_RATE_PREAMBLE_HT,
5169d5c65159SKalle Valo 	WMI_RATE_PREAMBLE_VHT,
5170d5c65159SKalle Valo 	WMI_RATE_PREAMBLE_HE,
5171d5c65159SKalle Valo };
5172d5c65159SKalle Valo 
5173d5c65159SKalle Valo /**
5174d5c65159SKalle Valo  * enum wmi_rtscts_prot_mode - Enable/Disable RTS/CTS and CTS2Self Protection.
5175d5c65159SKalle Valo  * @WMI_RTS_CTS_DISABLED: RTS/CTS protection is disabled.
5176d5c65159SKalle Valo  * @WMI_USE_RTS_CTS: RTS/CTS Enabled.
5177d5c65159SKalle Valo  * @WMI_USE_CTS2SELF: CTS to self protection Enabled.
5178d5c65159SKalle Valo  */
5179d5c65159SKalle Valo enum wmi_rtscts_prot_mode {
5180d5c65159SKalle Valo 	WMI_RTS_CTS_DISABLED = 0,
5181d5c65159SKalle Valo 	WMI_USE_RTS_CTS = 1,
5182d5c65159SKalle Valo 	WMI_USE_CTS2SELF = 2,
5183d5c65159SKalle Valo };
5184d5c65159SKalle Valo 
5185d5c65159SKalle Valo /**
5186d5c65159SKalle Valo  * enum wmi_rtscts_profile - Selection of RTS CTS profile along with enabling
5187d5c65159SKalle Valo  *                           protection mode.
51883f505a30SJeff Johnson  * @WMI_RTSCTS_FOR_NO_RATESERIES: Neither of rate-series should use RTS-CTS
51893f505a30SJeff Johnson  * @WMI_RTSCTS_FOR_SECOND_RATESERIES: Only second rate-series will use RTS-CTS
51903f505a30SJeff Johnson  * @WMI_RTSCTS_ACROSS_SW_RETRIES: Only the second rate-series will use RTS-CTS,
5191d5c65159SKalle Valo  *                                but if there's a sw retry, both the rate
5192d5c65159SKalle Valo  *                                series will use RTS-CTS.
51933f505a30SJeff Johnson  * @WMI_RTSCTS_ERP: RTS/CTS used for ERP protection for every PPDU.
51943f505a30SJeff Johnson  * @WMI_RTSCTS_FOR_ALL_RATESERIES: Enable RTS-CTS for all rate series.
5195d5c65159SKalle Valo  */
5196d5c65159SKalle Valo enum wmi_rtscts_profile {
5197d5c65159SKalle Valo 	WMI_RTSCTS_FOR_NO_RATESERIES = 0,
5198d5c65159SKalle Valo 	WMI_RTSCTS_FOR_SECOND_RATESERIES = 1,
5199d5c65159SKalle Valo 	WMI_RTSCTS_ACROSS_SW_RETRIES = 2,
5200d5c65159SKalle Valo 	WMI_RTSCTS_ERP = 3,
5201d5c65159SKalle Valo 	WMI_RTSCTS_FOR_ALL_RATESERIES = 4,
5202d5c65159SKalle Valo };
5203d5c65159SKalle Valo 
5204d5c65159SKalle Valo struct ath11k_hal_reg_cap {
5205d5c65159SKalle Valo 	u32 eeprom_rd;
5206d5c65159SKalle Valo 	u32 eeprom_rd_ext;
5207d5c65159SKalle Valo 	u32 regcap1;
5208d5c65159SKalle Valo 	u32 regcap2;
5209d5c65159SKalle Valo 	u32 wireless_modes;
5210d5c65159SKalle Valo 	u32 low_2ghz_chan;
5211d5c65159SKalle Valo 	u32 high_2ghz_chan;
5212d5c65159SKalle Valo 	u32 low_5ghz_chan;
5213d5c65159SKalle Valo 	u32 high_5ghz_chan;
5214d5c65159SKalle Valo };
5215d5c65159SKalle Valo 
5216d5c65159SKalle Valo struct ath11k_mem_chunk {
5217d5c65159SKalle Valo 	void *vaddr;
5218d5c65159SKalle Valo 	dma_addr_t paddr;
5219d5c65159SKalle Valo 	u32 len;
5220d5c65159SKalle Valo 	u32 req_id;
5221d5c65159SKalle Valo };
5222d5c65159SKalle Valo 
5223d5c65159SKalle Valo #define WMI_SKB_HEADROOM sizeof(struct wmi_cmd_hdr)
5224d5c65159SKalle Valo 
5225d5c65159SKalle Valo enum wmi_sta_ps_param_rx_wake_policy {
5226d5c65159SKalle Valo 	WMI_STA_PS_RX_WAKE_POLICY_WAKE = 0,
5227d5c65159SKalle Valo 	WMI_STA_PS_RX_WAKE_POLICY_POLL_UAPSD = 1,
5228d5c65159SKalle Valo };
5229d5c65159SKalle Valo 
5230e7f33e0cSJohn Crispin /* Do not change existing values! Used by ath11k_frame_mode parameter
5231e7f33e0cSJohn Crispin  * module parameter.
5232e7f33e0cSJohn Crispin  */
5233d5c65159SKalle Valo enum ath11k_hw_txrx_mode {
5234d5c65159SKalle Valo 	ATH11K_HW_TXRX_RAW = 0,
5235d5c65159SKalle Valo 	ATH11K_HW_TXRX_NATIVE_WIFI = 1,
5236d5c65159SKalle Valo 	ATH11K_HW_TXRX_ETHERNET = 2,
5237d5c65159SKalle Valo };
5238d5c65159SKalle Valo 
5239d5c65159SKalle Valo struct wmi_wmm_params {
5240d5c65159SKalle Valo 	u32 tlv_header;
5241d5c65159SKalle Valo 	u32 cwmin;
5242d5c65159SKalle Valo 	u32 cwmax;
5243d5c65159SKalle Valo 	u32 aifs;
5244d5c65159SKalle Valo 	u32 txoplimit;
5245d5c65159SKalle Valo 	u32 acm;
5246d5c65159SKalle Valo 	u32 no_ack;
5247d5c65159SKalle Valo } __packed;
5248d5c65159SKalle Valo 
5249d5c65159SKalle Valo struct wmi_wmm_params_arg {
5250d5c65159SKalle Valo 	u8 acm;
5251d5c65159SKalle Valo 	u8 aifs;
5252f1d34a01SKarthikeyan Periyasamy 	u16 cwmin;
5253f1d34a01SKarthikeyan Periyasamy 	u16 cwmax;
5254d5c65159SKalle Valo 	u16 txop;
5255d5c65159SKalle Valo 	u8 no_ack;
5256d5c65159SKalle Valo };
5257d5c65159SKalle Valo 
5258d5c65159SKalle Valo struct wmi_vdev_set_wmm_params_cmd {
5259d5c65159SKalle Valo 	u32 tlv_header;
5260d5c65159SKalle Valo 	u32 vdev_id;
5261d5c65159SKalle Valo 	struct wmi_wmm_params wmm_params[4];
5262d5c65159SKalle Valo 	u32 wmm_param_type;
5263d5c65159SKalle Valo } __packed;
5264d5c65159SKalle Valo 
5265d5c65159SKalle Valo struct wmi_wmm_params_all_arg {
5266d5c65159SKalle Valo 	struct wmi_wmm_params_arg ac_be;
5267d5c65159SKalle Valo 	struct wmi_wmm_params_arg ac_bk;
5268d5c65159SKalle Valo 	struct wmi_wmm_params_arg ac_vi;
5269d5c65159SKalle Valo 	struct wmi_wmm_params_arg ac_vo;
5270d5c65159SKalle Valo };
5271d5c65159SKalle Valo 
52726d293d44SJohn Crispin #define ATH11K_TWT_DEF_STA_CONG_TIMER_MS		5000
52736d293d44SJohn Crispin #define ATH11K_TWT_DEF_DEFAULT_SLOT_SIZE		10
52746d293d44SJohn Crispin #define ATH11K_TWT_DEF_CONGESTION_THRESH_SETUP		50
52756d293d44SJohn Crispin #define ATH11K_TWT_DEF_CONGESTION_THRESH_TEARDOWN	20
52766d293d44SJohn Crispin #define ATH11K_TWT_DEF_CONGESTION_THRESH_CRITICAL	100
52776d293d44SJohn Crispin #define ATH11K_TWT_DEF_INTERFERENCE_THRESH_TEARDOWN	80
52786d293d44SJohn Crispin #define ATH11K_TWT_DEF_INTERFERENCE_THRESH_SETUP	50
52796d293d44SJohn Crispin #define ATH11K_TWT_DEF_MIN_NO_STA_SETUP			10
52806d293d44SJohn Crispin #define ATH11K_TWT_DEF_MIN_NO_STA_TEARDOWN		2
52816d293d44SJohn Crispin #define ATH11K_TWT_DEF_NO_OF_BCAST_MCAST_SLOTS		2
52826d293d44SJohn Crispin #define ATH11K_TWT_DEF_MIN_NO_TWT_SLOTS			2
52836d293d44SJohn Crispin #define ATH11K_TWT_DEF_MAX_NO_STA_TWT			500
52846d293d44SJohn Crispin #define ATH11K_TWT_DEF_MODE_CHECK_INTERVAL		10000
52856d293d44SJohn Crispin #define ATH11K_TWT_DEF_ADD_STA_SLOT_INTERVAL		1000
52866d293d44SJohn Crispin #define ATH11K_TWT_DEF_REMOVE_STA_SLOT_INTERVAL		5000
52876d293d44SJohn Crispin 
52889e2747c3SManikanta Pubbisetty struct wmi_twt_enable_params {
52899e2747c3SManikanta Pubbisetty 	u32 sta_cong_timer_ms;
52909e2747c3SManikanta Pubbisetty 	u32 mbss_support;
52919e2747c3SManikanta Pubbisetty 	u32 default_slot_size;
52929e2747c3SManikanta Pubbisetty 	u32 congestion_thresh_setup;
52939e2747c3SManikanta Pubbisetty 	u32 congestion_thresh_teardown;
52949e2747c3SManikanta Pubbisetty 	u32 congestion_thresh_critical;
52959e2747c3SManikanta Pubbisetty 	u32 interference_thresh_teardown;
52969e2747c3SManikanta Pubbisetty 	u32 interference_thresh_setup;
52979e2747c3SManikanta Pubbisetty 	u32 min_no_sta_setup;
52989e2747c3SManikanta Pubbisetty 	u32 min_no_sta_teardown;
52999e2747c3SManikanta Pubbisetty 	u32 no_of_bcast_mcast_slots;
53009e2747c3SManikanta Pubbisetty 	u32 min_no_twt_slots;
53019e2747c3SManikanta Pubbisetty 	u32 max_no_sta_twt;
53029e2747c3SManikanta Pubbisetty 	u32 mode_check_interval;
53039e2747c3SManikanta Pubbisetty 	u32 add_sta_slot_interval;
53049e2747c3SManikanta Pubbisetty 	u32 remove_sta_slot_interval;
53059e2747c3SManikanta Pubbisetty };
53069e2747c3SManikanta Pubbisetty 
53076d293d44SJohn Crispin struct wmi_twt_enable_params_cmd {
53086d293d44SJohn Crispin 	u32 tlv_header;
53096d293d44SJohn Crispin 	u32 pdev_id;
53106d293d44SJohn Crispin 	u32 sta_cong_timer_ms;
53116d293d44SJohn Crispin 	u32 mbss_support;
53126d293d44SJohn Crispin 	u32 default_slot_size;
53136d293d44SJohn Crispin 	u32 congestion_thresh_setup;
53146d293d44SJohn Crispin 	u32 congestion_thresh_teardown;
53156d293d44SJohn Crispin 	u32 congestion_thresh_critical;
53166d293d44SJohn Crispin 	u32 interference_thresh_teardown;
53176d293d44SJohn Crispin 	u32 interference_thresh_setup;
53186d293d44SJohn Crispin 	u32 min_no_sta_setup;
53196d293d44SJohn Crispin 	u32 min_no_sta_teardown;
53206d293d44SJohn Crispin 	u32 no_of_bcast_mcast_slots;
53216d293d44SJohn Crispin 	u32 min_no_twt_slots;
53226d293d44SJohn Crispin 	u32 max_no_sta_twt;
53236d293d44SJohn Crispin 	u32 mode_check_interval;
53246d293d44SJohn Crispin 	u32 add_sta_slot_interval;
53256d293d44SJohn Crispin 	u32 remove_sta_slot_interval;
532620c3c4fdSJohn Crispin } __packed;
53276d293d44SJohn Crispin 
53286d293d44SJohn Crispin struct wmi_twt_disable_params_cmd {
53296d293d44SJohn Crispin 	u32 tlv_header;
53306d293d44SJohn Crispin 	u32 pdev_id;
533120c3c4fdSJohn Crispin } __packed;
53326d293d44SJohn Crispin 
53333d00e8b5SJohn Crispin enum WMI_HOST_TWT_COMMAND {
53343d00e8b5SJohn Crispin 	WMI_HOST_TWT_COMMAND_REQUEST_TWT = 0,
53353d00e8b5SJohn Crispin 	WMI_HOST_TWT_COMMAND_SUGGEST_TWT,
53363d00e8b5SJohn Crispin 	WMI_HOST_TWT_COMMAND_DEMAND_TWT,
53373d00e8b5SJohn Crispin 	WMI_HOST_TWT_COMMAND_TWT_GROUPING,
53383d00e8b5SJohn Crispin 	WMI_HOST_TWT_COMMAND_ACCEPT_TWT,
53393d00e8b5SJohn Crispin 	WMI_HOST_TWT_COMMAND_ALTERNATE_TWT,
53403d00e8b5SJohn Crispin 	WMI_HOST_TWT_COMMAND_DICTATE_TWT,
53413d00e8b5SJohn Crispin 	WMI_HOST_TWT_COMMAND_REJECT_TWT,
53423d00e8b5SJohn Crispin };
53433d00e8b5SJohn Crispin 
53443d00e8b5SJohn Crispin #define WMI_TWT_ADD_DIALOG_FLAG_BCAST           BIT(8)
53453d00e8b5SJohn Crispin #define WMI_TWT_ADD_DIALOG_FLAG_TRIGGER         BIT(9)
53463d00e8b5SJohn Crispin #define WMI_TWT_ADD_DIALOG_FLAG_FLOW_TYPE       BIT(10)
53473d00e8b5SJohn Crispin #define WMI_TWT_ADD_DIALOG_FLAG_PROTECTION      BIT(11)
53483d00e8b5SJohn Crispin 
53493d00e8b5SJohn Crispin struct wmi_twt_add_dialog_params_cmd {
53503d00e8b5SJohn Crispin 	u32 tlv_header;
53513d00e8b5SJohn Crispin 	u32 vdev_id;
53523d00e8b5SJohn Crispin 	struct wmi_mac_addr peer_macaddr;
53533d00e8b5SJohn Crispin 	u32 dialog_id;
53543d00e8b5SJohn Crispin 	u32 wake_intvl_us;
53553d00e8b5SJohn Crispin 	u32 wake_intvl_mantis;
53563d00e8b5SJohn Crispin 	u32 wake_dura_us;
53573d00e8b5SJohn Crispin 	u32 sp_offset_us;
53583d00e8b5SJohn Crispin 	u32 flags;
53593d00e8b5SJohn Crispin } __packed;
53603d00e8b5SJohn Crispin 
53613d00e8b5SJohn Crispin struct wmi_twt_add_dialog_params {
53623d00e8b5SJohn Crispin 	u32 vdev_id;
53633d00e8b5SJohn Crispin 	u8 peer_macaddr[ETH_ALEN];
53643d00e8b5SJohn Crispin 	u32 dialog_id;
53653d00e8b5SJohn Crispin 	u32 wake_intvl_us;
53663d00e8b5SJohn Crispin 	u32 wake_intvl_mantis;
53673d00e8b5SJohn Crispin 	u32 wake_dura_us;
53683d00e8b5SJohn Crispin 	u32 sp_offset_us;
53693d00e8b5SJohn Crispin 	u8 twt_cmd;
53703d00e8b5SJohn Crispin 	u8 flag_bcast;
53713d00e8b5SJohn Crispin 	u8 flag_trigger;
53723d00e8b5SJohn Crispin 	u8 flag_flow_type;
53733d00e8b5SJohn Crispin 	u8 flag_protection;
53743d00e8b5SJohn Crispin } __packed;
53753d00e8b5SJohn Crispin 
53763d00e8b5SJohn Crispin enum  wmi_twt_add_dialog_status {
53773d00e8b5SJohn Crispin 	WMI_ADD_TWT_STATUS_OK,
53783d00e8b5SJohn Crispin 	WMI_ADD_TWT_STATUS_TWT_NOT_ENABLED,
53793d00e8b5SJohn Crispin 	WMI_ADD_TWT_STATUS_USED_DIALOG_ID,
53803d00e8b5SJohn Crispin 	WMI_ADD_TWT_STATUS_INVALID_PARAM,
53813d00e8b5SJohn Crispin 	WMI_ADD_TWT_STATUS_NOT_READY,
53823d00e8b5SJohn Crispin 	WMI_ADD_TWT_STATUS_NO_RESOURCE,
53833d00e8b5SJohn Crispin 	WMI_ADD_TWT_STATUS_NO_ACK,
53843d00e8b5SJohn Crispin 	WMI_ADD_TWT_STATUS_NO_RESPONSE,
53853d00e8b5SJohn Crispin 	WMI_ADD_TWT_STATUS_DENIED,
53863d00e8b5SJohn Crispin 	WMI_ADD_TWT_STATUS_UNKNOWN_ERROR,
53873d00e8b5SJohn Crispin };
53883d00e8b5SJohn Crispin 
53893d00e8b5SJohn Crispin struct wmi_twt_add_dialog_event {
53903d00e8b5SJohn Crispin 	u32 vdev_id;
53913d00e8b5SJohn Crispin 	struct wmi_mac_addr peer_macaddr;
53923d00e8b5SJohn Crispin 	u32 dialog_id;
53933d00e8b5SJohn Crispin 	u32 status;
53943d00e8b5SJohn Crispin } __packed;
53953d00e8b5SJohn Crispin 
53963d00e8b5SJohn Crispin struct wmi_twt_del_dialog_params {
53973d00e8b5SJohn Crispin 	u32 vdev_id;
53983d00e8b5SJohn Crispin 	u8 peer_macaddr[ETH_ALEN];
53993d00e8b5SJohn Crispin 	u32 dialog_id;
54003d00e8b5SJohn Crispin } __packed;
54013d00e8b5SJohn Crispin 
54023d00e8b5SJohn Crispin struct wmi_twt_del_dialog_params_cmd {
54033d00e8b5SJohn Crispin 	u32 tlv_header;
54043d00e8b5SJohn Crispin 	u32 vdev_id;
54053d00e8b5SJohn Crispin 	struct wmi_mac_addr peer_macaddr;
54063d00e8b5SJohn Crispin 	u32 dialog_id;
54073d00e8b5SJohn Crispin } __packed;
54083d00e8b5SJohn Crispin 
54093d00e8b5SJohn Crispin struct wmi_twt_pause_dialog_params {
54103d00e8b5SJohn Crispin 	u32 vdev_id;
54113d00e8b5SJohn Crispin 	u8 peer_macaddr[ETH_ALEN];
54123d00e8b5SJohn Crispin 	u32 dialog_id;
54133d00e8b5SJohn Crispin } __packed;
54143d00e8b5SJohn Crispin 
54153d00e8b5SJohn Crispin struct wmi_twt_pause_dialog_params_cmd {
54163d00e8b5SJohn Crispin 	u32 tlv_header;
54173d00e8b5SJohn Crispin 	u32 vdev_id;
54183d00e8b5SJohn Crispin 	struct wmi_mac_addr peer_macaddr;
54193d00e8b5SJohn Crispin 	u32 dialog_id;
54203d00e8b5SJohn Crispin } __packed;
54213d00e8b5SJohn Crispin 
54223d00e8b5SJohn Crispin struct wmi_twt_resume_dialog_params {
54233d00e8b5SJohn Crispin 	u32 vdev_id;
54243d00e8b5SJohn Crispin 	u8 peer_macaddr[ETH_ALEN];
54253d00e8b5SJohn Crispin 	u32 dialog_id;
54263d00e8b5SJohn Crispin 	u32 sp_offset_us;
54273d00e8b5SJohn Crispin 	u32 next_twt_size;
54283d00e8b5SJohn Crispin } __packed;
54293d00e8b5SJohn Crispin 
54303d00e8b5SJohn Crispin struct wmi_twt_resume_dialog_params_cmd {
54313d00e8b5SJohn Crispin 	u32 tlv_header;
54323d00e8b5SJohn Crispin 	u32 vdev_id;
54333d00e8b5SJohn Crispin 	struct wmi_mac_addr peer_macaddr;
54343d00e8b5SJohn Crispin 	u32 dialog_id;
54353d00e8b5SJohn Crispin 	u32 sp_offset_us;
54363d00e8b5SJohn Crispin 	u32 next_twt_size;
54373d00e8b5SJohn Crispin } __packed;
54383d00e8b5SJohn Crispin 
54393f8be640SJohn Crispin struct wmi_obss_spatial_reuse_params_cmd {
54403f8be640SJohn Crispin 	u32 tlv_header;
54413f8be640SJohn Crispin 	u32 pdev_id;
54423f8be640SJohn Crispin 	u32 enable;
54433f8be640SJohn Crispin 	s32 obss_min;
54443f8be640SJohn Crispin 	s32 obss_max;
54453f8be640SJohn Crispin 	u32 vdev_id;
544620c3c4fdSJohn Crispin } __packed;
54473f8be640SJohn Crispin 
5448b56b08aeSRajkumar Manoharan struct wmi_pdev_obss_pd_bitmap_cmd {
5449b56b08aeSRajkumar Manoharan 	u32 tlv_header;
5450b56b08aeSRajkumar Manoharan 	u32 pdev_id;
5451b56b08aeSRajkumar Manoharan 	u32 bitmap[2];
5452b56b08aeSRajkumar Manoharan } __packed;
5453b56b08aeSRajkumar Manoharan 
54545a032c8dSJohn Crispin #define ATH11K_BSS_COLOR_COLLISION_SCAN_PERIOD_MS		200
54555a032c8dSJohn Crispin #define ATH11K_OBSS_COLOR_COLLISION_DETECTION_DISABLE		0
54565a032c8dSJohn Crispin #define ATH11K_OBSS_COLOR_COLLISION_DETECTION			1
54575a032c8dSJohn Crispin 
54585a032c8dSJohn Crispin #define ATH11K_BSS_COLOR_COLLISION_DETECTION_STA_PERIOD_MS	10000
54595a032c8dSJohn Crispin #define ATH11K_BSS_COLOR_COLLISION_DETECTION_AP_PERIOD_MS	5000
54605a032c8dSJohn Crispin 
5461886433a9SJohn Crispin enum wmi_bss_color_collision {
5462886433a9SJohn Crispin 	WMI_BSS_COLOR_COLLISION_DISABLE = 0,
5463886433a9SJohn Crispin 	WMI_BSS_COLOR_COLLISION_DETECTION,
5464886433a9SJohn Crispin 	WMI_BSS_COLOR_FREE_SLOT_TIMER_EXPIRY,
5465886433a9SJohn Crispin 	WMI_BSS_COLOR_FREE_SLOT_AVAILABLE,
5466886433a9SJohn Crispin };
5467886433a9SJohn Crispin 
54685a032c8dSJohn Crispin struct wmi_obss_color_collision_cfg_params_cmd {
54695a032c8dSJohn Crispin 	u32 tlv_header;
54705a032c8dSJohn Crispin 	u32 vdev_id;
54715a032c8dSJohn Crispin 	u32 flags;
54725a032c8dSJohn Crispin 	u32 evt_type;
54735a032c8dSJohn Crispin 	u32 current_bss_color;
54745a032c8dSJohn Crispin 	u32 detection_period_ms;
54755a032c8dSJohn Crispin 	u32 scan_period_ms;
54765a032c8dSJohn Crispin 	u32 free_slot_expiry_time_ms;
54775a032c8dSJohn Crispin } __packed;
54785a032c8dSJohn Crispin 
54795a032c8dSJohn Crispin struct wmi_bss_color_change_enable_params_cmd {
54805a032c8dSJohn Crispin 	u32 tlv_header;
54815a032c8dSJohn Crispin 	u32 vdev_id;
54825a032c8dSJohn Crispin 	u32 enable;
54835a032c8dSJohn Crispin } __packed;
54845a032c8dSJohn Crispin 
5485886433a9SJohn Crispin struct wmi_obss_color_collision_event {
5486886433a9SJohn Crispin 	u32 vdev_id;
5487886433a9SJohn Crispin 	u32 evt_type;
5488886433a9SJohn Crispin 	u64 obss_color_bitmap;
5489886433a9SJohn Crispin } __packed;
5490886433a9SJohn Crispin 
549126c79927SSriram R #define ATH11K_IPV4_TH_SEED_SIZE 5
549226c79927SSriram R #define ATH11K_IPV6_TH_SEED_SIZE 11
549326c79927SSriram R 
549426c79927SSriram R struct ath11k_wmi_pdev_lro_config_cmd {
549526c79927SSriram R 	u32 tlv_header;
549626c79927SSriram R 	u32 lro_enable;
549726c79927SSriram R 	u32 res;
549826c79927SSriram R 	u32 th_4[ATH11K_IPV4_TH_SEED_SIZE];
549926c79927SSriram R 	u32 th_6[ATH11K_IPV6_TH_SEED_SIZE];
550026c79927SSriram R 	u32 pdev_id;
550126c79927SSriram R } __packed;
550226c79927SSriram R 
55039d11b7bfSKarthikeyan Periyasamy #define ATH11K_WMI_SPECTRAL_COUNT_DEFAULT                 0
55049d11b7bfSKarthikeyan Periyasamy #define ATH11K_WMI_SPECTRAL_PERIOD_DEFAULT              224
55059d11b7bfSKarthikeyan Periyasamy #define ATH11K_WMI_SPECTRAL_PRIORITY_DEFAULT              1
55069d11b7bfSKarthikeyan Periyasamy #define ATH11K_WMI_SPECTRAL_FFT_SIZE_DEFAULT              7
55079d11b7bfSKarthikeyan Periyasamy #define ATH11K_WMI_SPECTRAL_GC_ENA_DEFAULT                1
55089d11b7bfSKarthikeyan Periyasamy #define ATH11K_WMI_SPECTRAL_RESTART_ENA_DEFAULT           0
55099d11b7bfSKarthikeyan Periyasamy #define ATH11K_WMI_SPECTRAL_NOISE_FLOOR_REF_DEFAULT     -96
55109d11b7bfSKarthikeyan Periyasamy #define ATH11K_WMI_SPECTRAL_INIT_DELAY_DEFAULT           80
55119d11b7bfSKarthikeyan Periyasamy #define ATH11K_WMI_SPECTRAL_NB_TONE_THR_DEFAULT          12
55129d11b7bfSKarthikeyan Periyasamy #define ATH11K_WMI_SPECTRAL_STR_BIN_THR_DEFAULT           8
55139d11b7bfSKarthikeyan Periyasamy #define ATH11K_WMI_SPECTRAL_WB_RPT_MODE_DEFAULT           0
55149d11b7bfSKarthikeyan Periyasamy #define ATH11K_WMI_SPECTRAL_RSSI_RPT_MODE_DEFAULT         0
55159d11b7bfSKarthikeyan Periyasamy #define ATH11K_WMI_SPECTRAL_RSSI_THR_DEFAULT           0xf0
55169d11b7bfSKarthikeyan Periyasamy #define ATH11K_WMI_SPECTRAL_PWR_FORMAT_DEFAULT            0
55179d11b7bfSKarthikeyan Periyasamy #define ATH11K_WMI_SPECTRAL_RPT_MODE_DEFAULT              2
55189d11b7bfSKarthikeyan Periyasamy #define ATH11K_WMI_SPECTRAL_BIN_SCALE_DEFAULT             1
55199d11b7bfSKarthikeyan Periyasamy #define ATH11K_WMI_SPECTRAL_DBM_ADJ_DEFAULT               1
55209d11b7bfSKarthikeyan Periyasamy #define ATH11K_WMI_SPECTRAL_CHN_MASK_DEFAULT              1
55219d11b7bfSKarthikeyan Periyasamy 
55229d11b7bfSKarthikeyan Periyasamy struct ath11k_wmi_vdev_spectral_conf_param {
55239d11b7bfSKarthikeyan Periyasamy 	u32 vdev_id;
55249d11b7bfSKarthikeyan Periyasamy 	u32 scan_count;
55259d11b7bfSKarthikeyan Periyasamy 	u32 scan_period;
55269d11b7bfSKarthikeyan Periyasamy 	u32 scan_priority;
55279d11b7bfSKarthikeyan Periyasamy 	u32 scan_fft_size;
55289d11b7bfSKarthikeyan Periyasamy 	u32 scan_gc_ena;
55299d11b7bfSKarthikeyan Periyasamy 	u32 scan_restart_ena;
55309d11b7bfSKarthikeyan Periyasamy 	u32 scan_noise_floor_ref;
55319d11b7bfSKarthikeyan Periyasamy 	u32 scan_init_delay;
55329d11b7bfSKarthikeyan Periyasamy 	u32 scan_nb_tone_thr;
55339d11b7bfSKarthikeyan Periyasamy 	u32 scan_str_bin_thr;
55349d11b7bfSKarthikeyan Periyasamy 	u32 scan_wb_rpt_mode;
55359d11b7bfSKarthikeyan Periyasamy 	u32 scan_rssi_rpt_mode;
55369d11b7bfSKarthikeyan Periyasamy 	u32 scan_rssi_thr;
55379d11b7bfSKarthikeyan Periyasamy 	u32 scan_pwr_format;
55389d11b7bfSKarthikeyan Periyasamy 	u32 scan_rpt_mode;
55399d11b7bfSKarthikeyan Periyasamy 	u32 scan_bin_scale;
55409d11b7bfSKarthikeyan Periyasamy 	u32 scan_dbm_adj;
55419d11b7bfSKarthikeyan Periyasamy 	u32 scan_chn_mask;
55429d11b7bfSKarthikeyan Periyasamy } __packed;
55439d11b7bfSKarthikeyan Periyasamy 
55449d11b7bfSKarthikeyan Periyasamy struct ath11k_wmi_vdev_spectral_conf_cmd {
55459d11b7bfSKarthikeyan Periyasamy 	u32 tlv_header;
55469d11b7bfSKarthikeyan Periyasamy 	struct ath11k_wmi_vdev_spectral_conf_param param;
55479d11b7bfSKarthikeyan Periyasamy } __packed;
55489d11b7bfSKarthikeyan Periyasamy 
55499d11b7bfSKarthikeyan Periyasamy #define ATH11K_WMI_SPECTRAL_TRIGGER_CMD_TRIGGER  1
55509d11b7bfSKarthikeyan Periyasamy #define ATH11K_WMI_SPECTRAL_TRIGGER_CMD_CLEAR    2
55519d11b7bfSKarthikeyan Periyasamy #define ATH11K_WMI_SPECTRAL_ENABLE_CMD_ENABLE    1
55529d11b7bfSKarthikeyan Periyasamy #define ATH11K_WMI_SPECTRAL_ENABLE_CMD_DISABLE   2
55539d11b7bfSKarthikeyan Periyasamy 
55549d11b7bfSKarthikeyan Periyasamy struct ath11k_wmi_vdev_spectral_enable_cmd {
55559d11b7bfSKarthikeyan Periyasamy 	u32 tlv_header;
55569d11b7bfSKarthikeyan Periyasamy 	u32 vdev_id;
55579d11b7bfSKarthikeyan Periyasamy 	u32 trigger_cmd;
55589d11b7bfSKarthikeyan Periyasamy 	u32 enable_cmd;
55599d11b7bfSKarthikeyan Periyasamy } __packed;
55609d11b7bfSKarthikeyan Periyasamy 
5561bd647855SKarthikeyan Periyasamy struct ath11k_wmi_pdev_dma_ring_cfg_req_cmd {
5562bd647855SKarthikeyan Periyasamy 	u32 tlv_header;
5563bd647855SKarthikeyan Periyasamy 	u32 pdev_id;
5564bd647855SKarthikeyan Periyasamy 	u32 module_id;		/* see enum wmi_direct_buffer_module */
5565bd647855SKarthikeyan Periyasamy 	u32 base_paddr_lo;
5566bd647855SKarthikeyan Periyasamy 	u32 base_paddr_hi;
5567bd647855SKarthikeyan Periyasamy 	u32 head_idx_paddr_lo;
5568bd647855SKarthikeyan Periyasamy 	u32 head_idx_paddr_hi;
5569bd647855SKarthikeyan Periyasamy 	u32 tail_idx_paddr_lo;
5570bd647855SKarthikeyan Periyasamy 	u32 tail_idx_paddr_hi;
5571bd647855SKarthikeyan Periyasamy 	u32 num_elems;		/* Number of elems in the ring */
5572bd647855SKarthikeyan Periyasamy 	u32 buf_size;		/* size of allocated buffer in bytes */
5573bd647855SKarthikeyan Periyasamy 
5574bd647855SKarthikeyan Periyasamy 	/* Number of wmi_dma_buf_release_entry packed together */
5575bd647855SKarthikeyan Periyasamy 	u32 num_resp_per_event;
5576bd647855SKarthikeyan Periyasamy 
5577bd647855SKarthikeyan Periyasamy 	/* Target should timeout and send whatever resp
5578bd647855SKarthikeyan Periyasamy 	 * it has if this time expires, units in milliseconds
5579bd647855SKarthikeyan Periyasamy 	 */
5580bd647855SKarthikeyan Periyasamy 	u32 event_timeout_ms;
5581bd647855SKarthikeyan Periyasamy } __packed;
5582bd647855SKarthikeyan Periyasamy 
5583bd647855SKarthikeyan Periyasamy struct ath11k_wmi_dma_buf_release_fixed_param {
5584bd647855SKarthikeyan Periyasamy 	u32 pdev_id;
5585bd647855SKarthikeyan Periyasamy 	u32 module_id;
5586bd647855SKarthikeyan Periyasamy 	u32 num_buf_release_entry;
5587bd647855SKarthikeyan Periyasamy 	u32 num_meta_data_entry;
5588bd647855SKarthikeyan Periyasamy } __packed;
5589bd647855SKarthikeyan Periyasamy 
5590bd647855SKarthikeyan Periyasamy struct wmi_dma_buf_release_entry {
5591bd647855SKarthikeyan Periyasamy 	u32 tlv_header;
5592bd647855SKarthikeyan Periyasamy 	u32 paddr_lo;
5593bd647855SKarthikeyan Periyasamy 
5594bd647855SKarthikeyan Periyasamy 	/* Bits 11:0:   address of data
5595bd647855SKarthikeyan Periyasamy 	 * Bits 31:12:  host context data
5596bd647855SKarthikeyan Periyasamy 	 */
5597bd647855SKarthikeyan Periyasamy 	u32 paddr_hi;
5598bd647855SKarthikeyan Periyasamy } __packed;
5599bd647855SKarthikeyan Periyasamy 
5600bd647855SKarthikeyan Periyasamy #define WMI_SPECTRAL_META_INFO1_FREQ1		GENMASK(15, 0)
5601bd647855SKarthikeyan Periyasamy #define WMI_SPECTRAL_META_INFO1_FREQ2		GENMASK(31, 16)
5602bd647855SKarthikeyan Periyasamy 
5603bd647855SKarthikeyan Periyasamy #define WMI_SPECTRAL_META_INFO2_CHN_WIDTH	GENMASK(7, 0)
5604bd647855SKarthikeyan Periyasamy 
5605bd647855SKarthikeyan Periyasamy struct wmi_dma_buf_release_meta_data {
5606bd647855SKarthikeyan Periyasamy 	u32 tlv_header;
5607bd647855SKarthikeyan Periyasamy 	s32 noise_floor[WMI_MAX_CHAINS];
5608bd647855SKarthikeyan Periyasamy 	u32 reset_delay;
5609bd647855SKarthikeyan Periyasamy 	u32 freq1;
5610bd647855SKarthikeyan Periyasamy 	u32 freq2;
5611bd647855SKarthikeyan Periyasamy 	u32 ch_width;
5612bd647855SKarthikeyan Periyasamy } __packed;
5613bd647855SKarthikeyan Periyasamy 
5614047679e3SAloka Dixit enum wmi_fils_discovery_cmd_type {
5615047679e3SAloka Dixit 	WMI_FILS_DISCOVERY_CMD,
5616047679e3SAloka Dixit 	WMI_UNSOL_BCAST_PROBE_RESP,
5617047679e3SAloka Dixit };
5618047679e3SAloka Dixit 
5619047679e3SAloka Dixit struct wmi_fils_discovery_cmd {
5620047679e3SAloka Dixit 	u32 tlv_header;
5621047679e3SAloka Dixit 	u32 vdev_id;
5622047679e3SAloka Dixit 	u32 interval;
5623047679e3SAloka Dixit 	u32 config; /* enum wmi_fils_discovery_cmd_type */
5624047679e3SAloka Dixit } __packed;
5625047679e3SAloka Dixit 
5626047679e3SAloka Dixit struct wmi_fils_discovery_tmpl_cmd {
5627047679e3SAloka Dixit 	u32 tlv_header;
5628047679e3SAloka Dixit 	u32 vdev_id;
5629047679e3SAloka Dixit 	u32 buf_len;
5630047679e3SAloka Dixit } __packed;
5631047679e3SAloka Dixit 
5632047679e3SAloka Dixit struct wmi_probe_tmpl_cmd {
5633047679e3SAloka Dixit 	u32 tlv_header;
5634047679e3SAloka Dixit 	u32 vdev_id;
5635047679e3SAloka Dixit 	u32 buf_len;
5636047679e3SAloka Dixit } __packed;
5637047679e3SAloka Dixit 
5638d5c65159SKalle Valo struct target_resource_config {
5639d5c65159SKalle Valo 	u32 num_vdevs;
5640d5c65159SKalle Valo 	u32 num_peers;
5641d5c65159SKalle Valo 	u32 num_active_peers;
5642d5c65159SKalle Valo 	u32 num_offload_peers;
5643d5c65159SKalle Valo 	u32 num_offload_reorder_buffs;
5644d5c65159SKalle Valo 	u32 num_peer_keys;
5645d5c65159SKalle Valo 	u32 num_tids;
5646d5c65159SKalle Valo 	u32 ast_skid_limit;
5647d5c65159SKalle Valo 	u32 tx_chain_mask;
5648d5c65159SKalle Valo 	u32 rx_chain_mask;
5649d5c65159SKalle Valo 	u32 rx_timeout_pri[4];
5650d5c65159SKalle Valo 	u32 rx_decap_mode;
5651d5c65159SKalle Valo 	u32 scan_max_pending_req;
5652d5c65159SKalle Valo 	u32 bmiss_offload_max_vdev;
5653d5c65159SKalle Valo 	u32 roam_offload_max_vdev;
5654d5c65159SKalle Valo 	u32 roam_offload_max_ap_profiles;
5655d5c65159SKalle Valo 	u32 num_mcast_groups;
5656d5c65159SKalle Valo 	u32 num_mcast_table_elems;
5657d5c65159SKalle Valo 	u32 mcast2ucast_mode;
5658d5c65159SKalle Valo 	u32 tx_dbg_log_size;
5659d5c65159SKalle Valo 	u32 num_wds_entries;
5660d5c65159SKalle Valo 	u32 dma_burst_size;
5661d5c65159SKalle Valo 	u32 mac_aggr_delim;
5662d5c65159SKalle Valo 	u32 rx_skip_defrag_timeout_dup_detection_check;
5663d5c65159SKalle Valo 	u32 vow_config;
5664d5c65159SKalle Valo 	u32 gtk_offload_max_vdev;
5665d5c65159SKalle Valo 	u32 num_msdu_desc;
5666d5c65159SKalle Valo 	u32 max_frag_entries;
5667d5c65159SKalle Valo 	u32 max_peer_ext_stats;
5668d5c65159SKalle Valo 	u32 smart_ant_cap;
5669d5c65159SKalle Valo 	u32 bk_minfree;
5670d5c65159SKalle Valo 	u32 be_minfree;
5671d5c65159SKalle Valo 	u32 vi_minfree;
5672d5c65159SKalle Valo 	u32 vo_minfree;
5673d5c65159SKalle Valo 	u32 rx_batchmode;
5674d5c65159SKalle Valo 	u32 tt_support;
56757e9fb241SSeevalamuthu Mariappan 	u32 flag1;
5676d5c65159SKalle Valo 	u32 iphdr_pad_config;
5677d5c65159SKalle Valo 	u32 qwrap_config:16,
5678d5c65159SKalle Valo 	    alloc_frag_desc_for_data_pkt:16;
5679d5c65159SKalle Valo 	u32 num_tdls_vdevs;
5680d5c65159SKalle Valo 	u32 num_tdls_conn_table_entries;
5681d5c65159SKalle Valo 	u32 beacon_tx_offload_max_vdev;
5682d5c65159SKalle Valo 	u32 num_multicast_filter_entries;
5683d5c65159SKalle Valo 	u32 num_wow_filters;
5684d5c65159SKalle Valo 	u32 num_keep_alive_pattern;
5685d5c65159SKalle Valo 	u32 keep_alive_pattern_size;
5686d5c65159SKalle Valo 	u32 max_tdls_concurrent_sleep_sta;
5687d5c65159SKalle Valo 	u32 max_tdls_concurrent_buffer_sta;
5688d5c65159SKalle Valo 	u32 wmi_send_separate;
5689d5c65159SKalle Valo 	u32 num_ocb_vdevs;
5690d5c65159SKalle Valo 	u32 num_ocb_channels;
5691d5c65159SKalle Valo 	u32 num_ocb_schedules;
5692d5c65159SKalle Valo 	u32 num_ns_ext_tuples_cfg;
5693d5c65159SKalle Valo 	u32 bpf_instruction_size;
5694d5c65159SKalle Valo 	u32 max_bssid_rx_filters;
5695d5c65159SKalle Valo 	u32 use_pdev_id;
5696d5c65159SKalle Valo 	u32 peer_map_unmap_v2_support;
56976d293d44SJohn Crispin 	u32 sched_params;
56986d293d44SJohn Crispin 	u32 twt_ap_pdev_count;
56996d293d44SJohn Crispin 	u32 twt_ap_sta_count;
570091fa00faSAditya Kumar Singh 	u8 is_reg_cc_ext_event_supported;
5701a08dbb04SAloka Dixit 	u32 ema_max_vap_cnt;
5702a08dbb04SAloka Dixit 	u32 ema_max_profile_period;
5703d5c65159SKalle Valo };
5704d5c65159SKalle Valo 
5705f295ad91SSeevalamuthu Mariappan enum wmi_debug_log_param {
5706f295ad91SSeevalamuthu Mariappan 	WMI_DEBUG_LOG_PARAM_LOG_LEVEL = 0x1,
5707f295ad91SSeevalamuthu Mariappan 	WMI_DEBUG_LOG_PARAM_VDEV_ENABLE,
5708f295ad91SSeevalamuthu Mariappan 	WMI_DEBUG_LOG_PARAM_VDEV_DISABLE,
5709f295ad91SSeevalamuthu Mariappan 	WMI_DEBUG_LOG_PARAM_VDEV_ENABLE_BITMAP,
5710f295ad91SSeevalamuthu Mariappan 	WMI_DEBUG_LOG_PARAM_MOD_ENABLE_BITMAP,
5711f295ad91SSeevalamuthu Mariappan 	WMI_DEBUG_LOG_PARAM_WOW_MOD_ENABLE_BITMAP,
5712f295ad91SSeevalamuthu Mariappan };
5713f295ad91SSeevalamuthu Mariappan 
5714f295ad91SSeevalamuthu Mariappan struct wmi_debug_log_config_cmd_fixed_param {
5715f295ad91SSeevalamuthu Mariappan 	u32 tlv_header;
5716f295ad91SSeevalamuthu Mariappan 	u32 dbg_log_param;
5717f295ad91SSeevalamuthu Mariappan 	u32 value;
5718f295ad91SSeevalamuthu Mariappan } __packed;
5719f295ad91SSeevalamuthu Mariappan 
5720d5c65159SKalle Valo #define WMI_MAX_MEM_REQS 32
5721d5c65159SKalle Valo 
5722d5c65159SKalle Valo #define MAX_RADIOS 3
5723d5c65159SKalle Valo 
5724d5c65159SKalle Valo #define WMI_SERVICE_READY_TIMEOUT_HZ (5 * HZ)
5725d5c65159SKalle Valo #define WMI_SEND_TIMEOUT_HZ (3 * HZ)
5726d5c65159SKalle Valo 
5727710a95f9SVenkateswara Naralasetty enum ath11k_wmi_peer_ps_state {
5728710a95f9SVenkateswara Naralasetty 	WMI_PEER_PS_STATE_OFF,
5729710a95f9SVenkateswara Naralasetty 	WMI_PEER_PS_STATE_ON,
5730710a95f9SVenkateswara Naralasetty 	WMI_PEER_PS_STATE_DISABLED,
5731710a95f9SVenkateswara Naralasetty };
5732710a95f9SVenkateswara Naralasetty 
5733710a95f9SVenkateswara Naralasetty enum wmi_peer_ps_supported_bitmap {
5734710a95f9SVenkateswara Naralasetty 	/* Used to indicate that power save state change is valid */
5735710a95f9SVenkateswara Naralasetty 	WMI_PEER_PS_VALID = 0x1,
5736710a95f9SVenkateswara Naralasetty 	WMI_PEER_PS_STATE_TIMESTAMP = 0x2,
5737710a95f9SVenkateswara Naralasetty };
5738710a95f9SVenkateswara Naralasetty 
5739710a95f9SVenkateswara Naralasetty struct wmi_peer_sta_ps_state_chg_event {
5740710a95f9SVenkateswara Naralasetty 	struct wmi_mac_addr peer_macaddr;
5741710a95f9SVenkateswara Naralasetty 	u32 peer_ps_state;
5742710a95f9SVenkateswara Naralasetty 	u32 ps_supported_bitmap;
5743710a95f9SVenkateswara Naralasetty 	u32 peer_ps_valid;
5744710a95f9SVenkateswara Naralasetty 	u32 peer_ps_timestamp;
5745710a95f9SVenkateswara Naralasetty } __packed;
5746710a95f9SVenkateswara Naralasetty 
5747d5c65159SKalle Valo struct ath11k_wmi_base {
5748d5c65159SKalle Valo 	struct ath11k_base *ab;
5749d5c65159SKalle Valo 	struct ath11k_pdev_wmi wmi[MAX_RADIOS];
5750d5c65159SKalle Valo 	enum ath11k_htc_ep_id wmi_endpoint_id[MAX_RADIOS];
5751d5c65159SKalle Valo 	u32 max_msg_len[MAX_RADIOS];
5752d5c65159SKalle Valo 
5753d5c65159SKalle Valo 	struct completion service_ready;
5754d5c65159SKalle Valo 	struct completion unified_ready;
5755e2e23a79SWen Gong 	DECLARE_BITMAP(svc_map, WMI_MAX_EXT2_SERVICE);
5756d5c65159SKalle Valo 	wait_queue_head_t tx_credits_wq;
5757d5c65159SKalle Valo 	const struct wmi_peer_flags_map *peer_flags;
5758d5c65159SKalle Valo 	u32 num_mem_chunks;
5759d5c65159SKalle Valo 	u32 rx_decap_mode;
5760d5c65159SKalle Valo 	struct wmi_host_mem_chunk mem_chunks[WMI_MAX_MEM_REQS];
5761d5c65159SKalle Valo 
5762d5c65159SKalle Valo 	enum wmi_host_hw_mode_config_type preferred_hw_mode;
5763d5c65159SKalle Valo 	struct target_resource_config  wlan_resource_config;
5764d5c65159SKalle Valo 
5765d5c65159SKalle Valo 	struct ath11k_targ_cap *targ_cap;
5766d5c65159SKalle Valo };
5767d5c65159SKalle Valo 
5768c417b247SCarl Huang /* Definition of HW data filtering */
5769c417b247SCarl Huang enum hw_data_filter_type {
5770c417b247SCarl Huang 	WMI_HW_DATA_FILTER_DROP_NON_ARP_BC = BIT(0),
5771c417b247SCarl Huang 	WMI_HW_DATA_FILTER_DROP_NON_ICMPV6_MC = BIT(1),
5772c417b247SCarl Huang };
5773c417b247SCarl Huang 
5774c417b247SCarl Huang struct wmi_hw_data_filter_cmd {
5775c417b247SCarl Huang 	u32 tlv_header;
5776c417b247SCarl Huang 	u32 vdev_id;
5777c417b247SCarl Huang 	u32 enable;
5778c417b247SCarl Huang 	u32 hw_filter_bitmap;
5779c417b247SCarl Huang } __packed;
5780c417b247SCarl Huang 
578179802b13SCarl Huang /* WOW structures */
578279802b13SCarl Huang enum wmi_wow_wakeup_event {
578379802b13SCarl Huang 	WOW_BMISS_EVENT = 0,
578479802b13SCarl Huang 	WOW_BETTER_AP_EVENT,
578579802b13SCarl Huang 	WOW_DEAUTH_RECVD_EVENT,
578679802b13SCarl Huang 	WOW_MAGIC_PKT_RECVD_EVENT,
578779802b13SCarl Huang 	WOW_GTK_ERR_EVENT,
578879802b13SCarl Huang 	WOW_FOURWAY_HSHAKE_EVENT,
578979802b13SCarl Huang 	WOW_EAPOL_RECVD_EVENT,
579079802b13SCarl Huang 	WOW_NLO_DETECTED_EVENT,
579179802b13SCarl Huang 	WOW_DISASSOC_RECVD_EVENT,
579279802b13SCarl Huang 	WOW_PATTERN_MATCH_EVENT,
579379802b13SCarl Huang 	WOW_CSA_IE_EVENT,
579479802b13SCarl Huang 	WOW_PROBE_REQ_WPS_IE_EVENT,
579579802b13SCarl Huang 	WOW_AUTH_REQ_EVENT,
579679802b13SCarl Huang 	WOW_ASSOC_REQ_EVENT,
579779802b13SCarl Huang 	WOW_HTT_EVENT,
579879802b13SCarl Huang 	WOW_RA_MATCH_EVENT,
579979802b13SCarl Huang 	WOW_HOST_AUTO_SHUTDOWN_EVENT,
580079802b13SCarl Huang 	WOW_IOAC_MAGIC_EVENT,
580179802b13SCarl Huang 	WOW_IOAC_SHORT_EVENT,
580279802b13SCarl Huang 	WOW_IOAC_EXTEND_EVENT,
580379802b13SCarl Huang 	WOW_IOAC_TIMER_EVENT,
580479802b13SCarl Huang 	WOW_DFS_PHYERR_RADAR_EVENT,
580579802b13SCarl Huang 	WOW_BEACON_EVENT,
580679802b13SCarl Huang 	WOW_CLIENT_KICKOUT_EVENT,
580779802b13SCarl Huang 	WOW_EVENT_MAX,
580879802b13SCarl Huang };
580979802b13SCarl Huang 
581079802b13SCarl Huang enum wmi_wow_interface_cfg {
581179802b13SCarl Huang 	WOW_IFACE_PAUSE_ENABLED,
581279802b13SCarl Huang 	WOW_IFACE_PAUSE_DISABLED
581379802b13SCarl Huang };
581479802b13SCarl Huang 
581579802b13SCarl Huang #define C2S(x) case x: return #x
581679802b13SCarl Huang 
wow_wakeup_event(enum wmi_wow_wakeup_event ev)581779802b13SCarl Huang static inline const char *wow_wakeup_event(enum wmi_wow_wakeup_event ev)
581879802b13SCarl Huang {
581979802b13SCarl Huang 	switch (ev) {
582079802b13SCarl Huang 	C2S(WOW_BMISS_EVENT);
582179802b13SCarl Huang 	C2S(WOW_BETTER_AP_EVENT);
582279802b13SCarl Huang 	C2S(WOW_DEAUTH_RECVD_EVENT);
582379802b13SCarl Huang 	C2S(WOW_MAGIC_PKT_RECVD_EVENT);
582479802b13SCarl Huang 	C2S(WOW_GTK_ERR_EVENT);
582579802b13SCarl Huang 	C2S(WOW_FOURWAY_HSHAKE_EVENT);
582679802b13SCarl Huang 	C2S(WOW_EAPOL_RECVD_EVENT);
582779802b13SCarl Huang 	C2S(WOW_NLO_DETECTED_EVENT);
582879802b13SCarl Huang 	C2S(WOW_DISASSOC_RECVD_EVENT);
582979802b13SCarl Huang 	C2S(WOW_PATTERN_MATCH_EVENT);
583079802b13SCarl Huang 	C2S(WOW_CSA_IE_EVENT);
583179802b13SCarl Huang 	C2S(WOW_PROBE_REQ_WPS_IE_EVENT);
583279802b13SCarl Huang 	C2S(WOW_AUTH_REQ_EVENT);
583379802b13SCarl Huang 	C2S(WOW_ASSOC_REQ_EVENT);
583479802b13SCarl Huang 	C2S(WOW_HTT_EVENT);
583579802b13SCarl Huang 	C2S(WOW_RA_MATCH_EVENT);
583679802b13SCarl Huang 	C2S(WOW_HOST_AUTO_SHUTDOWN_EVENT);
583779802b13SCarl Huang 	C2S(WOW_IOAC_MAGIC_EVENT);
583879802b13SCarl Huang 	C2S(WOW_IOAC_SHORT_EVENT);
583979802b13SCarl Huang 	C2S(WOW_IOAC_EXTEND_EVENT);
584079802b13SCarl Huang 	C2S(WOW_IOAC_TIMER_EVENT);
584179802b13SCarl Huang 	C2S(WOW_DFS_PHYERR_RADAR_EVENT);
584279802b13SCarl Huang 	C2S(WOW_BEACON_EVENT);
584379802b13SCarl Huang 	C2S(WOW_CLIENT_KICKOUT_EVENT);
584479802b13SCarl Huang 	C2S(WOW_EVENT_MAX);
584579802b13SCarl Huang 	default:
584679802b13SCarl Huang 		return NULL;
584779802b13SCarl Huang 	}
584879802b13SCarl Huang }
584979802b13SCarl Huang 
585079802b13SCarl Huang enum wmi_wow_wake_reason {
585179802b13SCarl Huang 	WOW_REASON_UNSPECIFIED = -1,
585279802b13SCarl Huang 	WOW_REASON_NLOD = 0,
585379802b13SCarl Huang 	WOW_REASON_AP_ASSOC_LOST,
585479802b13SCarl Huang 	WOW_REASON_LOW_RSSI,
585579802b13SCarl Huang 	WOW_REASON_DEAUTH_RECVD,
585679802b13SCarl Huang 	WOW_REASON_DISASSOC_RECVD,
585779802b13SCarl Huang 	WOW_REASON_GTK_HS_ERR,
585879802b13SCarl Huang 	WOW_REASON_EAP_REQ,
585979802b13SCarl Huang 	WOW_REASON_FOURWAY_HS_RECV,
586079802b13SCarl Huang 	WOW_REASON_TIMER_INTR_RECV,
586179802b13SCarl Huang 	WOW_REASON_PATTERN_MATCH_FOUND,
586279802b13SCarl Huang 	WOW_REASON_RECV_MAGIC_PATTERN,
586379802b13SCarl Huang 	WOW_REASON_P2P_DISC,
586479802b13SCarl Huang 	WOW_REASON_WLAN_HB,
586579802b13SCarl Huang 	WOW_REASON_CSA_EVENT,
586679802b13SCarl Huang 	WOW_REASON_PROBE_REQ_WPS_IE_RECV,
586779802b13SCarl Huang 	WOW_REASON_AUTH_REQ_RECV,
586879802b13SCarl Huang 	WOW_REASON_ASSOC_REQ_RECV,
586979802b13SCarl Huang 	WOW_REASON_HTT_EVENT,
587079802b13SCarl Huang 	WOW_REASON_RA_MATCH,
587179802b13SCarl Huang 	WOW_REASON_HOST_AUTO_SHUTDOWN,
587279802b13SCarl Huang 	WOW_REASON_IOAC_MAGIC_EVENT,
587379802b13SCarl Huang 	WOW_REASON_IOAC_SHORT_EVENT,
587479802b13SCarl Huang 	WOW_REASON_IOAC_EXTEND_EVENT,
587579802b13SCarl Huang 	WOW_REASON_IOAC_TIMER_EVENT,
587679802b13SCarl Huang 	WOW_REASON_ROAM_HO,
587779802b13SCarl Huang 	WOW_REASON_DFS_PHYERR_RADADR_EVENT,
587879802b13SCarl Huang 	WOW_REASON_BEACON_RECV,
587979802b13SCarl Huang 	WOW_REASON_CLIENT_KICKOUT_EVENT,
588079802b13SCarl Huang 	WOW_REASON_PAGE_FAULT = 0x3a,
588179802b13SCarl Huang 	WOW_REASON_DEBUG_TEST = 0xFF,
588279802b13SCarl Huang };
588379802b13SCarl Huang 
wow_reason(enum wmi_wow_wake_reason reason)588479802b13SCarl Huang static inline const char *wow_reason(enum wmi_wow_wake_reason reason)
588579802b13SCarl Huang {
588679802b13SCarl Huang 	switch (reason) {
588779802b13SCarl Huang 	C2S(WOW_REASON_UNSPECIFIED);
588879802b13SCarl Huang 	C2S(WOW_REASON_NLOD);
588979802b13SCarl Huang 	C2S(WOW_REASON_AP_ASSOC_LOST);
589079802b13SCarl Huang 	C2S(WOW_REASON_LOW_RSSI);
589179802b13SCarl Huang 	C2S(WOW_REASON_DEAUTH_RECVD);
589279802b13SCarl Huang 	C2S(WOW_REASON_DISASSOC_RECVD);
589379802b13SCarl Huang 	C2S(WOW_REASON_GTK_HS_ERR);
589479802b13SCarl Huang 	C2S(WOW_REASON_EAP_REQ);
589579802b13SCarl Huang 	C2S(WOW_REASON_FOURWAY_HS_RECV);
589679802b13SCarl Huang 	C2S(WOW_REASON_TIMER_INTR_RECV);
589779802b13SCarl Huang 	C2S(WOW_REASON_PATTERN_MATCH_FOUND);
589879802b13SCarl Huang 	C2S(WOW_REASON_RECV_MAGIC_PATTERN);
589979802b13SCarl Huang 	C2S(WOW_REASON_P2P_DISC);
590079802b13SCarl Huang 	C2S(WOW_REASON_WLAN_HB);
590179802b13SCarl Huang 	C2S(WOW_REASON_CSA_EVENT);
590279802b13SCarl Huang 	C2S(WOW_REASON_PROBE_REQ_WPS_IE_RECV);
590379802b13SCarl Huang 	C2S(WOW_REASON_AUTH_REQ_RECV);
590479802b13SCarl Huang 	C2S(WOW_REASON_ASSOC_REQ_RECV);
590579802b13SCarl Huang 	C2S(WOW_REASON_HTT_EVENT);
590679802b13SCarl Huang 	C2S(WOW_REASON_RA_MATCH);
590779802b13SCarl Huang 	C2S(WOW_REASON_HOST_AUTO_SHUTDOWN);
590879802b13SCarl Huang 	C2S(WOW_REASON_IOAC_MAGIC_EVENT);
590979802b13SCarl Huang 	C2S(WOW_REASON_IOAC_SHORT_EVENT);
591079802b13SCarl Huang 	C2S(WOW_REASON_IOAC_EXTEND_EVENT);
591179802b13SCarl Huang 	C2S(WOW_REASON_IOAC_TIMER_EVENT);
591279802b13SCarl Huang 	C2S(WOW_REASON_ROAM_HO);
591379802b13SCarl Huang 	C2S(WOW_REASON_DFS_PHYERR_RADADR_EVENT);
591479802b13SCarl Huang 	C2S(WOW_REASON_BEACON_RECV);
591579802b13SCarl Huang 	C2S(WOW_REASON_CLIENT_KICKOUT_EVENT);
591679802b13SCarl Huang 	C2S(WOW_REASON_PAGE_FAULT);
591779802b13SCarl Huang 	C2S(WOW_REASON_DEBUG_TEST);
591879802b13SCarl Huang 	default:
591979802b13SCarl Huang 		return NULL;
592079802b13SCarl Huang 	}
592179802b13SCarl Huang }
592279802b13SCarl Huang 
592379802b13SCarl Huang #undef C2S
592479802b13SCarl Huang 
5925ba9177fcSCarl Huang struct wmi_wow_ev_arg {
5926ba9177fcSCarl Huang 	u32 vdev_id;
5927ba9177fcSCarl Huang 	u32 flag;
5928ba9177fcSCarl Huang 	enum wmi_wow_wake_reason wake_reason;
5929ba9177fcSCarl Huang 	u32 data_len;
5930ba9177fcSCarl Huang };
5931ba9177fcSCarl Huang 
5932ba9177fcSCarl Huang enum wmi_tlv_pattern_type {
5933ba9177fcSCarl Huang 	WOW_PATTERN_MIN = 0,
5934ba9177fcSCarl Huang 	WOW_BITMAP_PATTERN = WOW_PATTERN_MIN,
5935ba9177fcSCarl Huang 	WOW_IPV4_SYNC_PATTERN,
5936ba9177fcSCarl Huang 	WOW_IPV6_SYNC_PATTERN,
5937ba9177fcSCarl Huang 	WOW_WILD_CARD_PATTERN,
5938ba9177fcSCarl Huang 	WOW_TIMER_PATTERN,
5939ba9177fcSCarl Huang 	WOW_MAGIC_PATTERN,
5940ba9177fcSCarl Huang 	WOW_IPV6_RA_PATTERN,
5941ba9177fcSCarl Huang 	WOW_IOAC_PKT_PATTERN,
5942ba9177fcSCarl Huang 	WOW_IOAC_TMR_PATTERN,
5943ba9177fcSCarl Huang 	WOW_PATTERN_MAX
5944ba9177fcSCarl Huang };
5945ba9177fcSCarl Huang 
5946ba9177fcSCarl Huang #define WOW_DEFAULT_BITMAP_PATTERN_SIZE		148
5947ba9177fcSCarl Huang #define WOW_DEFAULT_BITMASK_SIZE		148
5948ba9177fcSCarl Huang 
5949ba9177fcSCarl Huang #define WOW_MIN_PATTERN_SIZE	1
5950ba9177fcSCarl Huang #define WOW_MAX_PATTERN_SIZE	148
5951ba9177fcSCarl Huang #define WOW_MAX_PKT_OFFSET	128
5952ba9177fcSCarl Huang #define WOW_HDR_LEN	(sizeof(struct ieee80211_hdr_3addr) + \
5953ba9177fcSCarl Huang 	sizeof(struct rfc1042_hdr))
5954ba9177fcSCarl Huang #define WOW_MAX_REDUCE	(WOW_HDR_LEN - sizeof(struct ethhdr) - \
5955ba9177fcSCarl Huang 	offsetof(struct ieee80211_hdr_3addr, addr1))
5956ba9177fcSCarl Huang 
5957ba9177fcSCarl Huang struct wmi_wow_add_del_event_cmd {
5958ba9177fcSCarl Huang 	u32 tlv_header;
5959ba9177fcSCarl Huang 	u32 vdev_id;
5960ba9177fcSCarl Huang 	u32 is_add;
5961ba9177fcSCarl Huang 	u32 event_bitmap;
5962ba9177fcSCarl Huang } __packed;
5963ba9177fcSCarl Huang 
596479802b13SCarl Huang struct wmi_wow_enable_cmd {
596579802b13SCarl Huang 	u32 tlv_header;
596679802b13SCarl Huang 	u32 enable;
596779802b13SCarl Huang 	u32 pause_iface_config;
596879802b13SCarl Huang 	u32 flags;
596979802b13SCarl Huang }  __packed;
597079802b13SCarl Huang 
597179802b13SCarl Huang struct wmi_wow_host_wakeup_ind {
597279802b13SCarl Huang 	u32 tlv_header;
597379802b13SCarl Huang 	u32 reserved;
597479802b13SCarl Huang } __packed;
597579802b13SCarl Huang 
5976ba9177fcSCarl Huang struct wmi_tlv_wow_event_info {
597779802b13SCarl Huang 	u32 vdev_id;
597879802b13SCarl Huang 	u32 flag;
5979ba9177fcSCarl Huang 	u32 wake_reason;
598079802b13SCarl Huang 	u32 data_len;
5981ba9177fcSCarl Huang } __packed;
5982ba9177fcSCarl Huang 
5983ba9177fcSCarl Huang struct wmi_wow_bitmap_pattern {
5984ba9177fcSCarl Huang 	u32 tlv_header;
5985ba9177fcSCarl Huang 	u8 patternbuf[WOW_DEFAULT_BITMAP_PATTERN_SIZE];
5986ba9177fcSCarl Huang 	u8 bitmaskbuf[WOW_DEFAULT_BITMASK_SIZE];
5987ba9177fcSCarl Huang 	u32 pattern_offset;
5988ba9177fcSCarl Huang 	u32 pattern_len;
5989ba9177fcSCarl Huang 	u32 bitmask_len;
5990ba9177fcSCarl Huang 	u32 pattern_id;
5991ba9177fcSCarl Huang } __packed;
5992ba9177fcSCarl Huang 
5993ba9177fcSCarl Huang struct wmi_wow_add_pattern_cmd {
5994ba9177fcSCarl Huang 	u32 tlv_header;
5995ba9177fcSCarl Huang 	u32 vdev_id;
5996ba9177fcSCarl Huang 	u32 pattern_id;
5997ba9177fcSCarl Huang 	u32 pattern_type;
5998ba9177fcSCarl Huang } __packed;
5999ba9177fcSCarl Huang 
6000ba9177fcSCarl Huang struct wmi_wow_del_pattern_cmd {
6001ba9177fcSCarl Huang 	u32 tlv_header;
6002ba9177fcSCarl Huang 	u32 vdev_id;
6003ba9177fcSCarl Huang 	u32 pattern_id;
6004ba9177fcSCarl Huang 	u32 pattern_type;
6005ba9177fcSCarl Huang } __packed;
600679802b13SCarl Huang 
6007fec4b898SCarl Huang #define WMI_PNO_MAX_SCHED_SCAN_PLANS      2
6008fec4b898SCarl Huang #define WMI_PNO_MAX_SCHED_SCAN_PLAN_INT   7200
6009fec4b898SCarl Huang #define WMI_PNO_MAX_SCHED_SCAN_PLAN_ITRNS 100
6010fec4b898SCarl Huang #define WMI_PNO_MAX_NETW_CHANNELS         26
6011fec4b898SCarl Huang #define WMI_PNO_MAX_NETW_CHANNELS_EX      60
6012fec4b898SCarl Huang #define WMI_PNO_MAX_SUPP_NETWORKS         WLAN_SCAN_PARAMS_MAX_SSID
6013fec4b898SCarl Huang #define WMI_PNO_MAX_IE_LENGTH             WLAN_SCAN_PARAMS_MAX_IE_LEN
6014fec4b898SCarl Huang 
6015fec4b898SCarl Huang /* size based of dot11 declaration without extra IEs as we will not carry those for PNO */
6016fec4b898SCarl Huang #define WMI_PNO_MAX_PB_REQ_SIZE    450
6017fec4b898SCarl Huang 
6018fec4b898SCarl Huang #define WMI_PNO_24G_DEFAULT_CH     1
6019fec4b898SCarl Huang #define WMI_PNO_5G_DEFAULT_CH      36
6020fec4b898SCarl Huang 
6021fec4b898SCarl Huang #define WMI_ACTIVE_MAX_CHANNEL_TIME 40
6022fec4b898SCarl Huang #define WMI_PASSIVE_MAX_CHANNEL_TIME   110
6023fec4b898SCarl Huang 
6024fec4b898SCarl Huang /* SSID broadcast type */
6025fec4b898SCarl Huang enum wmi_ssid_bcast_type {
6026fec4b898SCarl Huang 	BCAST_UNKNOWN      = 0,
6027fec4b898SCarl Huang 	BCAST_NORMAL       = 1,
6028fec4b898SCarl Huang 	BCAST_HIDDEN       = 2,
6029fec4b898SCarl Huang };
6030fec4b898SCarl Huang 
6031fec4b898SCarl Huang #define WMI_NLO_MAX_SSIDS    16
6032fec4b898SCarl Huang #define WMI_NLO_MAX_CHAN     48
6033fec4b898SCarl Huang 
6034fec4b898SCarl Huang #define WMI_NLO_CONFIG_STOP                             BIT(0)
6035fec4b898SCarl Huang #define WMI_NLO_CONFIG_START                            BIT(1)
6036fec4b898SCarl Huang #define WMI_NLO_CONFIG_RESET                            BIT(2)
6037fec4b898SCarl Huang #define WMI_NLO_CONFIG_SLOW_SCAN                        BIT(4)
6038fec4b898SCarl Huang #define WMI_NLO_CONFIG_FAST_SCAN                        BIT(5)
6039fec4b898SCarl Huang #define WMI_NLO_CONFIG_SSID_HIDE_EN                     BIT(6)
6040fec4b898SCarl Huang 
6041fec4b898SCarl Huang /* This bit is used to indicate if EPNO or supplicant PNO is enabled.
6042fec4b898SCarl Huang  * Only one of them can be enabled at a given time
6043fec4b898SCarl Huang  */
6044fec4b898SCarl Huang #define WMI_NLO_CONFIG_ENLO                             BIT(7)
6045fec4b898SCarl Huang #define WMI_NLO_CONFIG_SCAN_PASSIVE                     BIT(8)
6046fec4b898SCarl Huang #define WMI_NLO_CONFIG_ENLO_RESET                       BIT(9)
6047fec4b898SCarl Huang #define WMI_NLO_CONFIG_SPOOFED_MAC_IN_PROBE_REQ         BIT(10)
6048fec4b898SCarl Huang #define WMI_NLO_CONFIG_RANDOM_SEQ_NO_IN_PROBE_REQ       BIT(11)
6049fec4b898SCarl Huang #define WMI_NLO_CONFIG_ENABLE_IE_WHITELIST_IN_PROBE_REQ BIT(12)
6050fec4b898SCarl Huang #define WMI_NLO_CONFIG_ENABLE_CNLO_RSSI_CONFIG          BIT(13)
6051fec4b898SCarl Huang 
6052fec4b898SCarl Huang struct wmi_nlo_ssid_param {
6053fec4b898SCarl Huang 	u32 valid;
6054fec4b898SCarl Huang 	struct wmi_ssid ssid;
6055fec4b898SCarl Huang } __packed;
6056fec4b898SCarl Huang 
6057fec4b898SCarl Huang struct wmi_nlo_enc_param {
6058fec4b898SCarl Huang 	u32 valid;
6059fec4b898SCarl Huang 	u32 enc_type;
6060fec4b898SCarl Huang } __packed;
6061fec4b898SCarl Huang 
6062fec4b898SCarl Huang struct wmi_nlo_auth_param {
6063fec4b898SCarl Huang 	u32 valid;
6064fec4b898SCarl Huang 	u32 auth_type;
6065fec4b898SCarl Huang } __packed;
6066fec4b898SCarl Huang 
6067fec4b898SCarl Huang struct wmi_nlo_bcast_nw_param {
6068fec4b898SCarl Huang 	u32 valid;
6069fec4b898SCarl Huang 	u32 bcast_nw_type;
6070fec4b898SCarl Huang } __packed;
6071fec4b898SCarl Huang 
6072fec4b898SCarl Huang struct wmi_nlo_rssi_param {
6073fec4b898SCarl Huang 	u32 valid;
6074fec4b898SCarl Huang 	s32 rssi;
6075fec4b898SCarl Huang } __packed;
6076fec4b898SCarl Huang 
6077fec4b898SCarl Huang struct nlo_configured_parameters {
6078fec4b898SCarl Huang 	/* TLV tag and len;*/
6079fec4b898SCarl Huang 	u32 tlv_header;
6080fec4b898SCarl Huang 	struct wmi_nlo_ssid_param ssid;
6081fec4b898SCarl Huang 	struct wmi_nlo_enc_param enc_type;
6082fec4b898SCarl Huang 	struct wmi_nlo_auth_param auth_type;
6083fec4b898SCarl Huang 	struct wmi_nlo_rssi_param rssi_cond;
6084fec4b898SCarl Huang 
6085fec4b898SCarl Huang 	/* indicates if the SSID is hidden or not */
6086fec4b898SCarl Huang 	struct wmi_nlo_bcast_nw_param bcast_nw_type;
6087fec4b898SCarl Huang } __packed;
6088fec4b898SCarl Huang 
6089fec4b898SCarl Huang struct wmi_network_type {
6090fec4b898SCarl Huang 	struct wmi_ssid ssid;
6091fec4b898SCarl Huang 	u32 authentication;
6092fec4b898SCarl Huang 	u32 encryption;
6093fec4b898SCarl Huang 	u32 bcast_nw_type;
6094fec4b898SCarl Huang 	u8 channel_count;
6095fec4b898SCarl Huang 	u16 channels[WMI_PNO_MAX_NETW_CHANNELS_EX];
6096fec4b898SCarl Huang 	s32 rssi_threshold;
6097fec4b898SCarl Huang };
6098fec4b898SCarl Huang 
6099fec4b898SCarl Huang struct wmi_pno_scan_req {
6100fec4b898SCarl Huang 	u8 enable;
6101fec4b898SCarl Huang 	u8 vdev_id;
6102fec4b898SCarl Huang 	u8 uc_networks_count;
6103fec4b898SCarl Huang 	struct wmi_network_type a_networks[WMI_PNO_MAX_SUPP_NETWORKS];
6104fec4b898SCarl Huang 	u32 fast_scan_period;
6105fec4b898SCarl Huang 	u32 slow_scan_period;
6106fec4b898SCarl Huang 	u8 fast_scan_max_cycles;
6107fec4b898SCarl Huang 
6108fec4b898SCarl Huang 	bool do_passive_scan;
6109fec4b898SCarl Huang 
6110fec4b898SCarl Huang 	u32 delay_start_time;
6111fec4b898SCarl Huang 	u32 active_min_time;
6112fec4b898SCarl Huang 	u32 active_max_time;
6113fec4b898SCarl Huang 	u32 passive_min_time;
6114fec4b898SCarl Huang 	u32 passive_max_time;
6115fec4b898SCarl Huang 
6116fec4b898SCarl Huang 	/* mac address randomization attributes */
6117fec4b898SCarl Huang 	u32 enable_pno_scan_randomization;
6118fec4b898SCarl Huang 	u8 mac_addr[ETH_ALEN];
6119fec4b898SCarl Huang 	u8 mac_addr_mask[ETH_ALEN];
6120fec4b898SCarl Huang };
6121fec4b898SCarl Huang 
6122fec4b898SCarl Huang struct wmi_wow_nlo_config_cmd {
6123fec4b898SCarl Huang 	u32 tlv_header;
6124fec4b898SCarl Huang 	u32 flags;
6125fec4b898SCarl Huang 	u32 vdev_id;
6126fec4b898SCarl Huang 	u32 fast_scan_max_cycles;
6127fec4b898SCarl Huang 	u32 active_dwell_time;
6128fec4b898SCarl Huang 	u32 passive_dwell_time;
6129fec4b898SCarl Huang 	u32 probe_bundle_size;
6130fec4b898SCarl Huang 
6131fec4b898SCarl Huang 	/* ART = IRT */
6132fec4b898SCarl Huang 	u32 rest_time;
6133fec4b898SCarl Huang 
6134fec4b898SCarl Huang 	/* Max value that can be reached after SBM */
6135fec4b898SCarl Huang 	u32 max_rest_time;
6136fec4b898SCarl Huang 
6137fec4b898SCarl Huang 	/* SBM */
6138fec4b898SCarl Huang 	u32 scan_backoff_multiplier;
6139fec4b898SCarl Huang 
6140fec4b898SCarl Huang 	/* SCBM */
6141fec4b898SCarl Huang 	u32 fast_scan_period;
6142fec4b898SCarl Huang 
6143fec4b898SCarl Huang 	/* specific to windows */
6144fec4b898SCarl Huang 	u32 slow_scan_period;
6145fec4b898SCarl Huang 
6146fec4b898SCarl Huang 	u32 no_of_ssids;
6147fec4b898SCarl Huang 
6148fec4b898SCarl Huang 	u32 num_of_channels;
6149fec4b898SCarl Huang 
6150fec4b898SCarl Huang 	/* NLO scan start delay time in milliseconds */
6151fec4b898SCarl Huang 	u32 delay_start_time;
6152fec4b898SCarl Huang 
6153fec4b898SCarl Huang 	/* MAC Address to use in Probe Req as SA */
6154fec4b898SCarl Huang 	struct wmi_mac_addr mac_addr;
6155fec4b898SCarl Huang 
6156fec4b898SCarl Huang 	/* Mask on which MAC has to be randomized */
6157fec4b898SCarl Huang 	struct wmi_mac_addr mac_mask;
6158fec4b898SCarl Huang 
6159fec4b898SCarl Huang 	/* IE bitmap to use in Probe Req */
6160fec4b898SCarl Huang 	u32 ie_bitmap[8];
6161fec4b898SCarl Huang 
6162fec4b898SCarl Huang 	/* Number of vendor OUIs. In the TLV vendor_oui[] */
6163fec4b898SCarl Huang 	u32 num_vendor_oui;
6164fec4b898SCarl Huang 
6165fec4b898SCarl Huang 	/* Number of connected NLO band preferences */
6166fec4b898SCarl Huang 	u32 num_cnlo_band_pref;
6167fec4b898SCarl Huang 
6168fec4b898SCarl Huang 	/* The TLVs will follow.
6169fec4b898SCarl Huang 	 * nlo_configured_parameters nlo_list[];
6170fec4b898SCarl Huang 	 * u32 channel_list[num_of_channels];
6171fec4b898SCarl Huang 	 */
6172fec4b898SCarl Huang } __packed;
6173fec4b898SCarl Huang 
6174c3c36bfeSCarl Huang #define WMI_MAX_NS_OFFLOADS           2
6175c3c36bfeSCarl Huang #define WMI_MAX_ARP_OFFLOADS          2
6176c3c36bfeSCarl Huang 
6177c3c36bfeSCarl Huang #define WMI_ARPOL_FLAGS_VALID              BIT(0)
6178c3c36bfeSCarl Huang #define WMI_ARPOL_FLAGS_MAC_VALID          BIT(1)
6179c3c36bfeSCarl Huang #define WMI_ARPOL_FLAGS_REMOTE_IP_VALID    BIT(2)
6180c3c36bfeSCarl Huang 
6181c3c36bfeSCarl Huang struct wmi_arp_offload_tuple {
6182c3c36bfeSCarl Huang 	u32 tlv_header;
6183c3c36bfeSCarl Huang 	u32 flags;
6184c3c36bfeSCarl Huang 	u8 target_ipaddr[4];
6185c3c36bfeSCarl Huang 	u8 remote_ipaddr[4];
6186c3c36bfeSCarl Huang 	struct wmi_mac_addr target_mac;
6187c3c36bfeSCarl Huang } __packed;
6188c3c36bfeSCarl Huang 
6189c3c36bfeSCarl Huang #define WMI_NSOL_FLAGS_VALID               BIT(0)
6190c3c36bfeSCarl Huang #define WMI_NSOL_FLAGS_MAC_VALID           BIT(1)
6191c3c36bfeSCarl Huang #define WMI_NSOL_FLAGS_REMOTE_IP_VALID     BIT(2)
6192c3c36bfeSCarl Huang #define WMI_NSOL_FLAGS_IS_IPV6_ANYCAST     BIT(3)
6193c3c36bfeSCarl Huang 
6194c3c36bfeSCarl Huang #define WMI_NSOL_MAX_TARGET_IPS    2
6195c3c36bfeSCarl Huang 
6196c3c36bfeSCarl Huang struct wmi_ns_offload_tuple {
6197c3c36bfeSCarl Huang 	u32 tlv_header;
6198c3c36bfeSCarl Huang 	u32 flags;
6199c3c36bfeSCarl Huang 	u8 target_ipaddr[WMI_NSOL_MAX_TARGET_IPS][16];
6200c3c36bfeSCarl Huang 	u8 solicitation_ipaddr[16];
6201c3c36bfeSCarl Huang 	u8 remote_ipaddr[16];
6202c3c36bfeSCarl Huang 	struct wmi_mac_addr target_mac;
6203c3c36bfeSCarl Huang } __packed;
6204c3c36bfeSCarl Huang 
6205c3c36bfeSCarl Huang struct wmi_set_arp_ns_offload_cmd {
6206c3c36bfeSCarl Huang 	u32 tlv_header;
6207c3c36bfeSCarl Huang 	u32 flags;
6208c3c36bfeSCarl Huang 	u32 vdev_id;
6209c3c36bfeSCarl Huang 	u32 num_ns_ext_tuples;
6210c3c36bfeSCarl Huang 	/* The TLVs follow:
6211c3c36bfeSCarl Huang 	 * wmi_ns_offload_tuple  ns_tuples[WMI_MAX_NS_OFFLOADS];
6212c3c36bfeSCarl Huang 	 * wmi_arp_offload_tuple arp_tuples[WMI_MAX_ARP_OFFLOADS];
6213c3c36bfeSCarl Huang 	 * wmi_ns_offload_tuple  ns_ext_tuples[num_ns_ext_tuples];
6214c3c36bfeSCarl Huang 	 */
6215c3c36bfeSCarl Huang } __packed;
6216c3c36bfeSCarl Huang 
6217a16d9b50SCarl Huang #define GTK_OFFLOAD_OPCODE_MASK             0xFF000000
6218a16d9b50SCarl Huang #define GTK_OFFLOAD_ENABLE_OPCODE           0x01000000
6219a16d9b50SCarl Huang #define GTK_OFFLOAD_DISABLE_OPCODE          0x02000000
6220a16d9b50SCarl Huang #define GTK_OFFLOAD_REQUEST_STATUS_OPCODE   0x04000000
6221a16d9b50SCarl Huang 
6222a16d9b50SCarl Huang #define GTK_OFFLOAD_KEK_BYTES       16
6223a16d9b50SCarl Huang #define GTK_OFFLOAD_KCK_BYTES       16
6224a16d9b50SCarl Huang #define GTK_REPLAY_COUNTER_BYTES    8
6225a16d9b50SCarl Huang #define WMI_MAX_KEY_LEN             32
6226a16d9b50SCarl Huang #define IGTK_PN_SIZE                6
6227a16d9b50SCarl Huang 
6228a16d9b50SCarl Huang struct wmi_replayc_cnt {
6229a16d9b50SCarl Huang 	union {
6230a16d9b50SCarl Huang 		u8 counter[GTK_REPLAY_COUNTER_BYTES];
6231a16d9b50SCarl Huang 		struct {
6232a16d9b50SCarl Huang 			u32 word0;
6233a16d9b50SCarl Huang 			u32 word1;
6234a16d9b50SCarl Huang 		} __packed;
6235a16d9b50SCarl Huang 	} __packed;
6236a16d9b50SCarl Huang } __packed;
6237a16d9b50SCarl Huang 
6238a16d9b50SCarl Huang struct wmi_gtk_offload_status_event {
6239a16d9b50SCarl Huang 	u32 vdev_id;
6240a16d9b50SCarl Huang 	u32 flags;
6241a16d9b50SCarl Huang 	u32 refresh_cnt;
6242a16d9b50SCarl Huang 	struct wmi_replayc_cnt replay_ctr;
6243a16d9b50SCarl Huang 	u8 igtk_key_index;
6244a16d9b50SCarl Huang 	u8 igtk_key_length;
6245a16d9b50SCarl Huang 	u8 igtk_key_rsc[IGTK_PN_SIZE];
6246a16d9b50SCarl Huang 	u8 igtk_key[WMI_MAX_KEY_LEN];
6247a16d9b50SCarl Huang 	u8 gtk_key_index;
6248a16d9b50SCarl Huang 	u8 gtk_key_length;
6249a16d9b50SCarl Huang 	u8 gtk_key_rsc[GTK_REPLAY_COUNTER_BYTES];
6250a16d9b50SCarl Huang 	u8 gtk_key[WMI_MAX_KEY_LEN];
6251a16d9b50SCarl Huang } __packed;
6252a16d9b50SCarl Huang 
6253a16d9b50SCarl Huang struct wmi_gtk_rekey_offload_cmd {
6254a16d9b50SCarl Huang 	u32 tlv_header;
6255a16d9b50SCarl Huang 	u32 vdev_id;
6256a16d9b50SCarl Huang 	u32 flags;
6257a16d9b50SCarl Huang 	u8 kek[GTK_OFFLOAD_KEK_BYTES];
6258a16d9b50SCarl Huang 	u8 kck[GTK_OFFLOAD_KCK_BYTES];
6259a16d9b50SCarl Huang 	u8 replay_ctr[GTK_REPLAY_COUNTER_BYTES];
6260a16d9b50SCarl Huang } __packed;
6261a16d9b50SCarl Huang 
6262652f69edSBaochen Qiang #define BIOS_SAR_TABLE_LEN	(22)
6263652f69edSBaochen Qiang #define BIOS_SAR_RSVD1_LEN	(6)
6264652f69edSBaochen Qiang #define BIOS_SAR_RSVD2_LEN	(18)
6265652f69edSBaochen Qiang 
6266652f69edSBaochen Qiang struct wmi_pdev_set_sar_table_cmd {
6267652f69edSBaochen Qiang 	u32 tlv_header;
6268652f69edSBaochen Qiang 	u32 pdev_id;
6269652f69edSBaochen Qiang 	u32 sar_len;
6270652f69edSBaochen Qiang 	u32 rsvd_len;
6271652f69edSBaochen Qiang } __packed;
6272652f69edSBaochen Qiang 
6273652f69edSBaochen Qiang struct wmi_pdev_set_geo_table_cmd {
6274652f69edSBaochen Qiang 	u32 tlv_header;
6275652f69edSBaochen Qiang 	u32 pdev_id;
6276652f69edSBaochen Qiang 	u32 rsvd_len;
6277652f69edSBaochen Qiang } __packed;
6278652f69edSBaochen Qiang 
62790f84a156SBaochen Qiang struct wmi_sta_keepalive_cmd {
62800f84a156SBaochen Qiang 	u32 tlv_header;
62810f84a156SBaochen Qiang 	u32 vdev_id;
62820f84a156SBaochen Qiang 	u32 enabled;
62830f84a156SBaochen Qiang 
62840f84a156SBaochen Qiang 	/* WMI_STA_KEEPALIVE_METHOD_ */
62850f84a156SBaochen Qiang 	u32 method;
62860f84a156SBaochen Qiang 
62870f84a156SBaochen Qiang 	/* in seconds */
62880f84a156SBaochen Qiang 	u32 interval;
62890f84a156SBaochen Qiang 
62900f84a156SBaochen Qiang 	/* following this structure is the TLV for struct
62910f84a156SBaochen Qiang 	 * wmi_sta_keepalive_arp_resp
62920f84a156SBaochen Qiang 	 */
62930f84a156SBaochen Qiang } __packed;
62940f84a156SBaochen Qiang 
62950f84a156SBaochen Qiang struct wmi_sta_keepalive_arp_resp {
62960f84a156SBaochen Qiang 	u32 tlv_header;
62970f84a156SBaochen Qiang 	u32 src_ip4_addr;
62980f84a156SBaochen Qiang 	u32 dest_ip4_addr;
62990f84a156SBaochen Qiang 	struct wmi_mac_addr dest_mac_addr;
63000f84a156SBaochen Qiang } __packed;
63010f84a156SBaochen Qiang 
63020f84a156SBaochen Qiang struct wmi_sta_keepalive_arg {
63030f84a156SBaochen Qiang 	u32 vdev_id;
63040f84a156SBaochen Qiang 	u32 enabled;
63050f84a156SBaochen Qiang 	u32 method;
63060f84a156SBaochen Qiang 	u32 interval;
63070f84a156SBaochen Qiang 	u32 src_ip4_addr;
63080f84a156SBaochen Qiang 	u32 dest_ip4_addr;
63090f84a156SBaochen Qiang 	const u8 dest_mac_addr[ETH_ALEN];
63100f84a156SBaochen Qiang };
63110f84a156SBaochen Qiang 
63120f84a156SBaochen Qiang enum wmi_sta_keepalive_method {
63130f84a156SBaochen Qiang 	WMI_STA_KEEPALIVE_METHOD_NULL_FRAME = 1,
63140f84a156SBaochen Qiang 	WMI_STA_KEEPALIVE_METHOD_UNSOLICITED_ARP_RESPONSE = 2,
63150f84a156SBaochen Qiang 	WMI_STA_KEEPALIVE_METHOD_ETHERNET_LOOPBACK = 3,
63160f84a156SBaochen Qiang 	WMI_STA_KEEPALIVE_METHOD_GRATUITOUS_ARP_REQUEST = 4,
63170f84a156SBaochen Qiang 	WMI_STA_KEEPALIVE_METHOD_MGMT_VENDOR_ACTION = 5,
63180f84a156SBaochen Qiang };
63190f84a156SBaochen Qiang 
63200f84a156SBaochen Qiang #define WMI_STA_KEEPALIVE_INTERVAL_DEFAULT	30
63210f84a156SBaochen Qiang #define WMI_STA_KEEPALIVE_INTERVAL_DISABLE	0
63220f84a156SBaochen Qiang 
6323b43310e4SGovindaraj Saminathan const void **ath11k_wmi_tlv_parse_alloc(struct ath11k_base *ab, const void *ptr,
6324b43310e4SGovindaraj Saminathan 					size_t len, gfp_t gfp);
6325d5c65159SKalle Valo int ath11k_wmi_cmd_send(struct ath11k_pdev_wmi *wmi, struct sk_buff *skb,
6326d5c65159SKalle Valo 			u32 cmd_id);
6327d5c65159SKalle Valo struct sk_buff *ath11k_wmi_alloc_skb(struct ath11k_wmi_base *wmi_sc, u32 len);
6328d5c65159SKalle Valo int ath11k_wmi_mgmt_send(struct ath11k *ar, u32 vdev_id, u32 buf_id,
6329d5c65159SKalle Valo 			 struct sk_buff *frame);
6330d5c65159SKalle Valo int ath11k_wmi_bcn_tmpl(struct ath11k *ar, u32 vdev_id,
6331d5c65159SKalle Valo 			struct ieee80211_mutable_offsets *offs,
633287bd4011SAloka Dixit 			struct sk_buff *bcn, u32 ema_param);
6333d5c65159SKalle Valo int ath11k_wmi_vdev_down(struct ath11k *ar, u8 vdev_id);
6334d5c65159SKalle Valo int ath11k_wmi_vdev_up(struct ath11k *ar, u32 vdev_id, u32 aid,
6335c82dc33fSAloka Dixit 		       const u8 *bssid, u8 *tx_bssid, u32 nontx_profile_idx,
6336c82dc33fSAloka Dixit 		       u32 nontx_profile_cnt);
6337d5c65159SKalle Valo int ath11k_wmi_vdev_stop(struct ath11k *ar, u8 vdev_id);
6338d5c65159SKalle Valo int ath11k_wmi_vdev_start(struct ath11k *ar, struct wmi_vdev_start_req_arg *arg,
6339d5c65159SKalle Valo 			  bool restart);
6340d5c65159SKalle Valo int ath11k_wmi_set_peer_param(struct ath11k *ar, const u8 *peer_addr,
6341d5c65159SKalle Valo 			      u32 vdev_id, u32 param_id, u32 param_val);
6342d5c65159SKalle Valo int ath11k_wmi_pdev_set_param(struct ath11k *ar, u32 param_id,
6343d5c65159SKalle Valo 			      u32 param_value, u8 pdev_id);
6344af3d8964SKalle Valo int ath11k_wmi_pdev_set_ps_mode(struct ath11k *ar, int vdev_id,
6345af3d8964SKalle Valo 				enum wmi_sta_ps_mode psmode);
6346d5c65159SKalle Valo int ath11k_wmi_wait_for_unified_ready(struct ath11k_base *ab);
6347d5c65159SKalle Valo int ath11k_wmi_cmd_init(struct ath11k_base *ab);
6348d5c65159SKalle Valo int ath11k_wmi_wait_for_service_ready(struct ath11k_base *ab);
6349d5c65159SKalle Valo int ath11k_wmi_connect(struct ath11k_base *ab);
6350d5c65159SKalle Valo int ath11k_wmi_pdev_attach(struct ath11k_base *ab,
6351d5c65159SKalle Valo 			   u8 pdev_id);
6352d5c65159SKalle Valo int ath11k_wmi_attach(struct ath11k_base *ab);
6353d5c65159SKalle Valo void ath11k_wmi_detach(struct ath11k_base *ab);
6354d5c65159SKalle Valo int ath11k_wmi_vdev_create(struct ath11k *ar, u8 *macaddr,
6355d5c65159SKalle Valo 			   struct vdev_create_params *param);
6356d5c65159SKalle Valo int ath11k_wmi_peer_rx_reorder_queue_setup(struct ath11k *ar, int vdev_id,
6357d5c65159SKalle Valo 					   const u8 *addr, dma_addr_t paddr,
6358d5c65159SKalle Valo 					   u8 tid, u8 ba_window_size_valid,
6359d5c65159SKalle Valo 					   u32 ba_window_size);
6360d5c65159SKalle Valo int ath11k_wmi_send_peer_create_cmd(struct ath11k *ar,
6361d5c65159SKalle Valo 				    struct peer_create_params *param);
6362d5c65159SKalle Valo int ath11k_wmi_vdev_set_param_cmd(struct ath11k *ar, u32 vdev_id,
6363d5c65159SKalle Valo 				  u32 param_id, u32 param_value);
6364d5c65159SKalle Valo 
6365d5c65159SKalle Valo int ath11k_wmi_set_sta_ps_param(struct ath11k *ar, u32 vdev_id,
6366d5c65159SKalle Valo 				u32 param, u32 param_value);
6367d5c65159SKalle Valo int ath11k_wmi_force_fw_hang_cmd(struct ath11k *ar, u32 type, u32 delay_time_ms);
6368d5c65159SKalle Valo int ath11k_wmi_send_peer_delete_cmd(struct ath11k *ar,
6369d5c65159SKalle Valo 				    const u8 *peer_addr, u8 vdev_id);
6370d5c65159SKalle Valo int ath11k_wmi_vdev_delete(struct ath11k *ar, u8 vdev_id);
6371d5c65159SKalle Valo void ath11k_wmi_start_scan_init(struct ath11k *ar, struct scan_req_params *arg);
6372d5c65159SKalle Valo int ath11k_wmi_send_scan_start_cmd(struct ath11k *ar,
6373d5c65159SKalle Valo 				   struct scan_req_params *params);
6374d5c65159SKalle Valo int ath11k_wmi_send_scan_stop_cmd(struct ath11k *ar,
6375d5c65159SKalle Valo 				  struct scan_cancel_param *param);
6376d5c65159SKalle Valo int ath11k_wmi_send_wmm_update_cmd_tlv(struct ath11k *ar, u32 vdev_id,
6377d5c65159SKalle Valo 				       struct wmi_wmm_params_all_arg *param);
6378d5c65159SKalle Valo int ath11k_wmi_pdev_suspend(struct ath11k *ar, u32 suspend_opt,
6379d5c65159SKalle Valo 			    u32 pdev_id);
6380d5c65159SKalle Valo int ath11k_wmi_pdev_resume(struct ath11k *ar, u32 pdev_id);
6381d5c65159SKalle Valo 
6382d5c65159SKalle Valo int ath11k_wmi_send_peer_assoc_cmd(struct ath11k *ar,
6383d5c65159SKalle Valo 				   struct peer_assoc_params *param);
6384d5c65159SKalle Valo int ath11k_wmi_vdev_install_key(struct ath11k *ar,
6385d5c65159SKalle Valo 				struct wmi_vdev_install_key_arg *arg);
6386d5c65159SKalle Valo int ath11k_wmi_pdev_bss_chan_info_request(struct ath11k *ar,
6387d5c65159SKalle Valo 					  enum wmi_bss_chan_info_req_type type);
6388d5c65159SKalle Valo int ath11k_wmi_send_stats_request_cmd(struct ath11k *ar,
6389d5c65159SKalle Valo 				      struct stats_request_params *param);
6390a41d1034SPradeep Kumar Chitrapu int ath11k_wmi_send_pdev_temperature_cmd(struct ath11k *ar);
6391d5c65159SKalle Valo int ath11k_wmi_send_peer_flush_tids_cmd(struct ath11k *ar,
6392d5c65159SKalle Valo 					u8 peer_addr[ETH_ALEN],
6393d5c65159SKalle Valo 					struct peer_flush_params *param);
6394d5c65159SKalle Valo int ath11k_wmi_send_set_ap_ps_param_cmd(struct ath11k *ar, u8 *peer_addr,
6395d5c65159SKalle Valo 					struct ap_ps_params *param);
6396d5c65159SKalle Valo int ath11k_wmi_send_scan_chan_list_cmd(struct ath11k *ar,
6397d5c65159SKalle Valo 				       struct scan_chan_list_params *chan_list);
6398d5c65159SKalle Valo int ath11k_wmi_send_dfs_phyerr_offload_enable_cmd(struct ath11k *ar,
6399d5c65159SKalle Valo 						  u32 pdev_id);
64009556dfa2SMaharaja Kennadyrajan int ath11k_wmi_addba_clear_resp(struct ath11k *ar, u32 vdev_id, const u8 *mac);
64019556dfa2SMaharaja Kennadyrajan int ath11k_wmi_addba_send(struct ath11k *ar, u32 vdev_id, const u8 *mac,
64029556dfa2SMaharaja Kennadyrajan 			  u32 tid, u32 buf_size);
64039556dfa2SMaharaja Kennadyrajan int ath11k_wmi_addba_set_resp(struct ath11k *ar, u32 vdev_id, const u8 *mac,
64049556dfa2SMaharaja Kennadyrajan 			      u32 tid, u32 status);
64059556dfa2SMaharaja Kennadyrajan int ath11k_wmi_delba_send(struct ath11k *ar, u32 vdev_id, const u8 *mac,
64069556dfa2SMaharaja Kennadyrajan 			  u32 tid, u32 initiator, u32 reason);
6407d5c65159SKalle Valo int ath11k_wmi_send_bcn_offload_control_cmd(struct ath11k *ar,
6408d5c65159SKalle Valo 					    u32 vdev_id, u32 bcn_ctrl_op);
64090b05ddadSWen Gong int ath11k_wmi_send_set_current_country_cmd(struct ath11k *ar,
64100b05ddadSWen Gong 					    struct wmi_set_current_country_params *param);
6411d5c65159SKalle Valo int
6412d5c65159SKalle Valo ath11k_wmi_send_init_country_cmd(struct ath11k *ar,
6413d5c65159SKalle Valo 				 struct wmi_init_country_params init_cc_param);
64149dcf6808SWen Gong 
64159dcf6808SWen Gong int ath11k_wmi_send_11d_scan_start_cmd(struct ath11k *ar,
64169dcf6808SWen Gong 				       struct wmi_11d_scan_start_params *param);
64179dcf6808SWen Gong int ath11k_wmi_send_11d_scan_stop_cmd(struct ath11k *ar, u32 vdev_id);
64189dcf6808SWen Gong 
64192a63bbcaSPradeep Kumar Chitrapu int
64202a63bbcaSPradeep Kumar Chitrapu ath11k_wmi_send_thermal_mitigation_param_cmd(struct ath11k *ar,
64212a63bbcaSPradeep Kumar Chitrapu 					     struct thermal_mitigation_params *param);
6422d5c65159SKalle Valo int ath11k_wmi_pdev_pktlog_enable(struct ath11k *ar, u32 pktlog_filter);
6423d5c65159SKalle Valo int ath11k_wmi_pdev_pktlog_disable(struct ath11k *ar);
6424d5c65159SKalle Valo int ath11k_wmi_pdev_peer_pktlog_filter(struct ath11k *ar, u8 *addr, u8 enable);
6425d5c65159SKalle Valo int
6426d5c65159SKalle Valo ath11k_wmi_rx_reord_queue_remove(struct ath11k *ar,
6427d5c65159SKalle Valo 				 struct rx_reorder_queue_remove_params *param);
6428d5c65159SKalle Valo int ath11k_wmi_send_pdev_set_regdomain(struct ath11k *ar,
6429d5c65159SKalle Valo 				       struct pdev_set_regdomain_params *param);
6430d5c65159SKalle Valo int ath11k_wmi_pull_fw_stats(struct ath11k_base *ab, struct sk_buff *skb,
6431d5c65159SKalle Valo 			     struct ath11k_fw_stats *stats);
6432d5c65159SKalle Valo void ath11k_wmi_fw_stats_fill(struct ath11k *ar,
6433d5c65159SKalle Valo 			      struct ath11k_fw_stats *fw_stats, u32 stats_id,
6434d5c65159SKalle Valo 			      char *buf);
6435d5c65159SKalle Valo int ath11k_wmi_simulate_radar(struct ath11k *ar);
64369e2747c3SManikanta Pubbisetty void ath11k_wmi_fill_default_twt_params(struct wmi_twt_enable_params *twt_params);
64379e2747c3SManikanta Pubbisetty int ath11k_wmi_send_twt_enable_cmd(struct ath11k *ar, u32 pdev_id,
64389e2747c3SManikanta Pubbisetty 				   struct wmi_twt_enable_params *params);
64396d293d44SJohn Crispin int ath11k_wmi_send_twt_disable_cmd(struct ath11k *ar, u32 pdev_id);
64403d00e8b5SJohn Crispin int ath11k_wmi_send_twt_add_dialog_cmd(struct ath11k *ar,
64413d00e8b5SJohn Crispin 				       struct wmi_twt_add_dialog_params *params);
64423d00e8b5SJohn Crispin int ath11k_wmi_send_twt_del_dialog_cmd(struct ath11k *ar,
64433d00e8b5SJohn Crispin 				       struct wmi_twt_del_dialog_params *params);
64443d00e8b5SJohn Crispin int ath11k_wmi_send_twt_pause_dialog_cmd(struct ath11k *ar,
64453d00e8b5SJohn Crispin 					 struct wmi_twt_pause_dialog_params *params);
64463d00e8b5SJohn Crispin int ath11k_wmi_send_twt_resume_dialog_cmd(struct ath11k *ar,
64473d00e8b5SJohn Crispin 					  struct wmi_twt_resume_dialog_params *params);
64483f8be640SJohn Crispin int ath11k_wmi_send_obss_spr_cmd(struct ath11k *ar, u32 vdev_id,
64493f8be640SJohn Crispin 				 struct ieee80211_he_obss_pd *he_obss_pd);
6450b56b08aeSRajkumar Manoharan int ath11k_wmi_pdev_set_srg_bss_color_bitmap(struct ath11k *ar, u32 *bitmap);
6451b56b08aeSRajkumar Manoharan int ath11k_wmi_pdev_set_srg_patial_bssid_bitmap(struct ath11k *ar, u32 *bitmap);
6452b56b08aeSRajkumar Manoharan int ath11k_wmi_pdev_srg_obss_color_enable_bitmap(struct ath11k *ar,
6453b56b08aeSRajkumar Manoharan 						 u32 *bitmap);
6454b56b08aeSRajkumar Manoharan int ath11k_wmi_pdev_srg_obss_bssid_enable_bitmap(struct ath11k *ar,
6455b56b08aeSRajkumar Manoharan 						 u32 *bitmap);
6456b56b08aeSRajkumar Manoharan int ath11k_wmi_pdev_non_srg_obss_color_enable_bitmap(struct ath11k *ar,
6457b56b08aeSRajkumar Manoharan 						     u32 *bitmap);
6458b56b08aeSRajkumar Manoharan int ath11k_wmi_pdev_non_srg_obss_bssid_enable_bitmap(struct ath11k *ar,
6459b56b08aeSRajkumar Manoharan 						     u32 *bitmap);
64605a032c8dSJohn Crispin int ath11k_wmi_send_obss_color_collision_cfg_cmd(struct ath11k *ar, u32 vdev_id,
64615a032c8dSJohn Crispin 						 u8 bss_color, u32 period,
64625a032c8dSJohn Crispin 						 bool enable);
64635a032c8dSJohn Crispin int ath11k_wmi_send_bss_color_change_enable_cmd(struct ath11k *ar, u32 vdev_id,
64645a032c8dSJohn Crispin 						bool enable);
646526c79927SSriram R int ath11k_wmi_pdev_lro_cfg(struct ath11k *ar, int pdev_id);
6466bd647855SKarthikeyan Periyasamy int ath11k_wmi_pdev_dma_ring_cfg(struct ath11k *ar,
6467bd647855SKarthikeyan Periyasamy 				 struct ath11k_wmi_pdev_dma_ring_cfg_req_cmd *param);
64689d11b7bfSKarthikeyan Periyasamy int ath11k_wmi_vdev_spectral_enable(struct ath11k *ar, u32 vdev_id,
64699d11b7bfSKarthikeyan Periyasamy 				    u32 trigger, u32 enable);
64709d11b7bfSKarthikeyan Periyasamy int ath11k_wmi_vdev_spectral_conf(struct ath11k *ar,
64719d11b7bfSKarthikeyan Periyasamy 				  struct ath11k_wmi_vdev_spectral_conf_param *param);
6472047679e3SAloka Dixit int ath11k_wmi_fils_discovery_tmpl(struct ath11k *ar, u32 vdev_id,
6473047679e3SAloka Dixit 				   struct sk_buff *tmpl);
6474047679e3SAloka Dixit int ath11k_wmi_fils_discovery(struct ath11k *ar, u32 vdev_id, u32 interval,
6475047679e3SAloka Dixit 			      bool unsol_bcast_probe_resp_enabled);
6476047679e3SAloka Dixit int ath11k_wmi_probe_resp_tmpl(struct ath11k *ar, u32 vdev_id,
6477047679e3SAloka Dixit 			       struct sk_buff *tmpl);
647843ed15e1SCarl Huang int ath11k_wmi_set_hw_mode(struct ath11k_base *ab,
647943ed15e1SCarl Huang 			   enum wmi_host_hw_mode_config_type mode);
648079802b13SCarl Huang int ath11k_wmi_wow_host_wakeup_ind(struct ath11k *ar);
648179802b13SCarl Huang int ath11k_wmi_wow_enable(struct ath11k *ar);
64829cbd7fc9SCarl Huang int ath11k_wmi_scan_prob_req_oui(struct ath11k *ar,
64839cbd7fc9SCarl Huang 				 const u8 mac_addr[ETH_ALEN]);
6484f295ad91SSeevalamuthu Mariappan int ath11k_wmi_fw_dbglog_cfg(struct ath11k *ar, u32 *module_id_bitmap,
6485f295ad91SSeevalamuthu Mariappan 			     struct ath11k_fw_dbglog *dbglog);
6486fec4b898SCarl Huang int ath11k_wmi_wow_config_pno(struct ath11k *ar, u32 vdev_id,
6487fec4b898SCarl Huang 			      struct wmi_pno_scan_req  *pno_scan);
6488ba9177fcSCarl Huang int ath11k_wmi_wow_del_pattern(struct ath11k *ar, u32 vdev_id, u32 pattern_id);
6489ba9177fcSCarl Huang int ath11k_wmi_wow_add_pattern(struct ath11k *ar, u32 vdev_id, u32 pattern_id,
6490ba9177fcSCarl Huang 			       const u8 *pattern, const u8 *mask,
6491ba9177fcSCarl Huang 			       int pattern_len, int pattern_offset);
6492ba9177fcSCarl Huang int ath11k_wmi_wow_add_wakeup_event(struct ath11k *ar, u32 vdev_id,
6493ba9177fcSCarl Huang 				    enum wmi_wow_wakeup_event event,
6494ba9177fcSCarl Huang 				    u32 enable);
6495c417b247SCarl Huang int ath11k_wmi_hw_data_filter_cmd(struct ath11k *ar, u32 vdev_id,
6496c417b247SCarl Huang 				  u32 filter_bitmap, bool enable);
6497c3c36bfeSCarl Huang int ath11k_wmi_arp_ns_offload(struct ath11k *ar,
6498c3c36bfeSCarl Huang 			      struct ath11k_vif *arvif, bool enable);
6499a16d9b50SCarl Huang int ath11k_wmi_gtk_rekey_offload(struct ath11k *ar,
6500a16d9b50SCarl Huang 				 struct ath11k_vif *arvif, bool enable);
6501a16d9b50SCarl Huang int ath11k_wmi_gtk_rekey_getinfo(struct ath11k *ar,
6502a16d9b50SCarl Huang 				 struct ath11k_vif *arvif);
6503652f69edSBaochen Qiang int ath11k_wmi_pdev_set_bios_sar_table_param(struct ath11k *ar, const u8 *sar_val);
6504652f69edSBaochen Qiang int ath11k_wmi_pdev_set_bios_geo_table_param(struct ath11k *ar);
65050f84a156SBaochen Qiang int ath11k_wmi_sta_keepalive(struct ath11k *ar,
65060f84a156SBaochen Qiang 			     const struct wmi_sta_keepalive_arg *arg);
6507c3c36bfeSCarl Huang 
6508d5c65159SKalle Valo #endif
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