1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* 3 * Copyright (c) 2019-2020 The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/module.h> 7 #include <linux/msi.h> 8 #include <linux/pci.h> 9 10 #include "pci.h" 11 #include "core.h" 12 #include "hif.h" 13 #include "mhi.h" 14 #include "debug.h" 15 16 #define ATH11K_PCI_BAR_NUM 0 17 #define ATH11K_PCI_DMA_MASK 32 18 19 #define ATH11K_PCI_IRQ_CE0_OFFSET 3 20 21 #define WINDOW_ENABLE_BIT 0x40000000 22 #define WINDOW_REG_ADDRESS 0x310c 23 #define WINDOW_VALUE_MASK GENMASK(24, 19) 24 #define WINDOW_START 0x80000 25 #define WINDOW_RANGE_MASK GENMASK(18, 0) 26 27 #define TCSR_SOC_HW_VERSION 0x0224 28 #define TCSR_SOC_HW_VERSION_MAJOR_MASK GENMASK(16, 8) 29 #define TCSR_SOC_HW_VERSION_MINOR_MASK GENMASK(7, 0) 30 31 /* BAR0 + 4k is always accessible, and no 32 * need to force wakeup. 33 * 4K - 32 = 0xFE0 34 */ 35 #define ACCESS_ALWAYS_OFF 0xFE0 36 37 #define QCA6390_DEVICE_ID 0x1101 38 #define QCN9074_DEVICE_ID 0x1104 39 #define WCN6855_DEVICE_ID 0x1103 40 41 static const struct pci_device_id ath11k_pci_id_table[] = { 42 { PCI_VDEVICE(QCOM, QCA6390_DEVICE_ID) }, 43 { PCI_VDEVICE(QCOM, WCN6855_DEVICE_ID) }, 44 { PCI_VDEVICE(QCOM, QCN9074_DEVICE_ID) }, 45 {0} 46 }; 47 48 MODULE_DEVICE_TABLE(pci, ath11k_pci_id_table); 49 50 static const struct ath11k_bus_params ath11k_pci_bus_params = { 51 .mhi_support = true, 52 .m3_fw_support = true, 53 .fixed_bdf_addr = false, 54 .fixed_mem_region = false, 55 }; 56 57 static const struct ath11k_msi_config ath11k_msi_config[] = { 58 { 59 .total_vectors = 32, 60 .total_users = 4, 61 .users = (struct ath11k_msi_user[]) { 62 { .name = "MHI", .num_vectors = 3, .base_vector = 0 }, 63 { .name = "CE", .num_vectors = 10, .base_vector = 3 }, 64 { .name = "WAKE", .num_vectors = 1, .base_vector = 13 }, 65 { .name = "DP", .num_vectors = 18, .base_vector = 14 }, 66 }, 67 }, 68 { 69 .total_vectors = 16, 70 .total_users = 3, 71 .users = (struct ath11k_msi_user[]) { 72 { .name = "MHI", .num_vectors = 3, .base_vector = 0 }, 73 { .name = "CE", .num_vectors = 5, .base_vector = 3 }, 74 { .name = "DP", .num_vectors = 8, .base_vector = 8 }, 75 }, 76 }, 77 }; 78 79 static const char *irq_name[ATH11K_IRQ_NUM_MAX] = { 80 "bhi", 81 "mhi-er0", 82 "mhi-er1", 83 "ce0", 84 "ce1", 85 "ce2", 86 "ce3", 87 "ce4", 88 "ce5", 89 "ce6", 90 "ce7", 91 "ce8", 92 "ce9", 93 "ce10", 94 "ce11", 95 "host2wbm-desc-feed", 96 "host2reo-re-injection", 97 "host2reo-command", 98 "host2rxdma-monitor-ring3", 99 "host2rxdma-monitor-ring2", 100 "host2rxdma-monitor-ring1", 101 "reo2ost-exception", 102 "wbm2host-rx-release", 103 "reo2host-status", 104 "reo2host-destination-ring4", 105 "reo2host-destination-ring3", 106 "reo2host-destination-ring2", 107 "reo2host-destination-ring1", 108 "rxdma2host-monitor-destination-mac3", 109 "rxdma2host-monitor-destination-mac2", 110 "rxdma2host-monitor-destination-mac1", 111 "ppdu-end-interrupts-mac3", 112 "ppdu-end-interrupts-mac2", 113 "ppdu-end-interrupts-mac1", 114 "rxdma2host-monitor-status-ring-mac3", 115 "rxdma2host-monitor-status-ring-mac2", 116 "rxdma2host-monitor-status-ring-mac1", 117 "host2rxdma-host-buf-ring-mac3", 118 "host2rxdma-host-buf-ring-mac2", 119 "host2rxdma-host-buf-ring-mac1", 120 "rxdma2host-destination-ring-mac3", 121 "rxdma2host-destination-ring-mac2", 122 "rxdma2host-destination-ring-mac1", 123 "host2tcl-input-ring4", 124 "host2tcl-input-ring3", 125 "host2tcl-input-ring2", 126 "host2tcl-input-ring1", 127 "wbm2host-tx-completions-ring3", 128 "wbm2host-tx-completions-ring2", 129 "wbm2host-tx-completions-ring1", 130 "tcl2host-status-ring", 131 }; 132 133 static inline void ath11k_pci_select_window(struct ath11k_pci *ab_pci, u32 offset) 134 { 135 struct ath11k_base *ab = ab_pci->ab; 136 137 u32 window = FIELD_GET(WINDOW_VALUE_MASK, offset); 138 139 lockdep_assert_held(&ab_pci->window_lock); 140 141 if (window != ab_pci->register_window) { 142 iowrite32(WINDOW_ENABLE_BIT | window, 143 ab->mem + WINDOW_REG_ADDRESS); 144 ioread32(ab->mem + WINDOW_REG_ADDRESS); 145 ab_pci->register_window = window; 146 } 147 } 148 149 static inline void ath11k_pci_select_static_window(struct ath11k_pci *ab_pci) 150 { 151 u32 umac_window = FIELD_GET(WINDOW_VALUE_MASK, HAL_SEQ_WCSS_UMAC_OFFSET); 152 u32 ce_window = FIELD_GET(WINDOW_VALUE_MASK, HAL_CE_WFSS_CE_REG_BASE); 153 u32 window; 154 155 window = (umac_window << 12) | (ce_window << 6); 156 157 iowrite32(WINDOW_ENABLE_BIT | window, ab_pci->ab->mem + WINDOW_REG_ADDRESS); 158 } 159 160 static inline u32 ath11k_pci_get_window_start(struct ath11k_base *ab, 161 u32 offset) 162 { 163 u32 window_start; 164 165 /* If offset lies within DP register range, use 3rd window */ 166 if ((offset ^ HAL_SEQ_WCSS_UMAC_OFFSET) < WINDOW_RANGE_MASK) 167 window_start = 3 * WINDOW_START; 168 /* If offset lies within CE register range, use 2nd window */ 169 else if ((offset ^ HAL_CE_WFSS_CE_REG_BASE) < WINDOW_RANGE_MASK) 170 window_start = 2 * WINDOW_START; 171 else 172 window_start = WINDOW_START; 173 174 return window_start; 175 } 176 177 void ath11k_pci_write32(struct ath11k_base *ab, u32 offset, u32 value) 178 { 179 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab); 180 u32 window_start; 181 182 /* for offset beyond BAR + 4K - 32, may 183 * need to wakeup MHI to access. 184 */ 185 if (ab->hw_params.wakeup_mhi && 186 test_bit(ATH11K_PCI_FLAG_INIT_DONE, &ab_pci->flags) && 187 offset >= ACCESS_ALWAYS_OFF) 188 mhi_device_get_sync(ab_pci->mhi_ctrl->mhi_dev); 189 190 if (offset < WINDOW_START) { 191 iowrite32(value, ab->mem + offset); 192 } else { 193 if (ab->bus_params.static_window_map) 194 window_start = ath11k_pci_get_window_start(ab, offset); 195 else 196 window_start = WINDOW_START; 197 198 if (window_start == WINDOW_START) { 199 spin_lock_bh(&ab_pci->window_lock); 200 ath11k_pci_select_window(ab_pci, offset); 201 iowrite32(value, ab->mem + window_start + 202 (offset & WINDOW_RANGE_MASK)); 203 spin_unlock_bh(&ab_pci->window_lock); 204 } else { 205 iowrite32(value, ab->mem + window_start + 206 (offset & WINDOW_RANGE_MASK)); 207 } 208 } 209 210 if (ab->hw_params.wakeup_mhi && 211 test_bit(ATH11K_PCI_FLAG_INIT_DONE, &ab_pci->flags) && 212 offset >= ACCESS_ALWAYS_OFF) 213 mhi_device_put(ab_pci->mhi_ctrl->mhi_dev); 214 } 215 216 u32 ath11k_pci_read32(struct ath11k_base *ab, u32 offset) 217 { 218 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab); 219 u32 val, window_start; 220 221 /* for offset beyond BAR + 4K - 32, may 222 * need to wakeup MHI to access. 223 */ 224 if (ab->hw_params.wakeup_mhi && 225 test_bit(ATH11K_PCI_FLAG_INIT_DONE, &ab_pci->flags) && 226 offset >= ACCESS_ALWAYS_OFF) 227 mhi_device_get_sync(ab_pci->mhi_ctrl->mhi_dev); 228 229 if (offset < WINDOW_START) { 230 val = ioread32(ab->mem + offset); 231 } else { 232 if (ab->bus_params.static_window_map) 233 window_start = ath11k_pci_get_window_start(ab, offset); 234 else 235 window_start = WINDOW_START; 236 237 if (window_start == WINDOW_START) { 238 spin_lock_bh(&ab_pci->window_lock); 239 ath11k_pci_select_window(ab_pci, offset); 240 val = ioread32(ab->mem + window_start + 241 (offset & WINDOW_RANGE_MASK)); 242 spin_unlock_bh(&ab_pci->window_lock); 243 } else { 244 val = ioread32(ab->mem + window_start + 245 (offset & WINDOW_RANGE_MASK)); 246 } 247 } 248 249 if (ab->hw_params.wakeup_mhi && 250 test_bit(ATH11K_PCI_FLAG_INIT_DONE, &ab_pci->flags) && 251 offset >= ACCESS_ALWAYS_OFF) 252 mhi_device_put(ab_pci->mhi_ctrl->mhi_dev); 253 254 return val; 255 } 256 257 static void ath11k_pci_soc_global_reset(struct ath11k_base *ab) 258 { 259 u32 val, delay; 260 261 val = ath11k_pci_read32(ab, PCIE_SOC_GLOBAL_RESET); 262 263 val |= PCIE_SOC_GLOBAL_RESET_V; 264 265 ath11k_pci_write32(ab, PCIE_SOC_GLOBAL_RESET, val); 266 267 /* TODO: exact time to sleep is uncertain */ 268 delay = 10; 269 mdelay(delay); 270 271 /* Need to toggle V bit back otherwise stuck in reset status */ 272 val &= ~PCIE_SOC_GLOBAL_RESET_V; 273 274 ath11k_pci_write32(ab, PCIE_SOC_GLOBAL_RESET, val); 275 276 mdelay(delay); 277 278 val = ath11k_pci_read32(ab, PCIE_SOC_GLOBAL_RESET); 279 if (val == 0xffffffff) 280 ath11k_warn(ab, "link down error during global reset\n"); 281 } 282 283 static void ath11k_pci_clear_dbg_registers(struct ath11k_base *ab) 284 { 285 u32 val; 286 287 /* read cookie */ 288 val = ath11k_pci_read32(ab, PCIE_Q6_COOKIE_ADDR); 289 ath11k_dbg(ab, ATH11K_DBG_PCI, "cookie:0x%x\n", val); 290 291 val = ath11k_pci_read32(ab, WLAON_WARM_SW_ENTRY); 292 ath11k_dbg(ab, ATH11K_DBG_PCI, "WLAON_WARM_SW_ENTRY 0x%x\n", val); 293 294 /* TODO: exact time to sleep is uncertain */ 295 mdelay(10); 296 297 /* write 0 to WLAON_WARM_SW_ENTRY to prevent Q6 from 298 * continuing warm path and entering dead loop. 299 */ 300 ath11k_pci_write32(ab, WLAON_WARM_SW_ENTRY, 0); 301 mdelay(10); 302 303 val = ath11k_pci_read32(ab, WLAON_WARM_SW_ENTRY); 304 ath11k_dbg(ab, ATH11K_DBG_PCI, "WLAON_WARM_SW_ENTRY 0x%x\n", val); 305 306 /* A read clear register. clear the register to prevent 307 * Q6 from entering wrong code path. 308 */ 309 val = ath11k_pci_read32(ab, WLAON_SOC_RESET_CAUSE_REG); 310 ath11k_dbg(ab, ATH11K_DBG_PCI, "soc reset cause:%d\n", val); 311 } 312 313 static int ath11k_pci_set_link_reg(struct ath11k_base *ab, 314 u32 offset, u32 value, u32 mask) 315 { 316 u32 v; 317 int i; 318 319 v = ath11k_pci_read32(ab, offset); 320 if ((v & mask) == value) 321 return 0; 322 323 for (i = 0; i < 10; i++) { 324 ath11k_pci_write32(ab, offset, (v & ~mask) | value); 325 326 v = ath11k_pci_read32(ab, offset); 327 if ((v & mask) == value) 328 return 0; 329 330 mdelay(2); 331 } 332 333 ath11k_warn(ab, "failed to set pcie link register 0x%08x: 0x%08x != 0x%08x\n", 334 offset, v & mask, value); 335 336 return -ETIMEDOUT; 337 } 338 339 static int ath11k_pci_fix_l1ss(struct ath11k_base *ab) 340 { 341 int ret; 342 343 ret = ath11k_pci_set_link_reg(ab, 344 PCIE_QSERDES_COM_SYSCLK_EN_SEL_REG(ab), 345 PCIE_QSERDES_COM_SYSCLK_EN_SEL_VAL, 346 PCIE_QSERDES_COM_SYSCLK_EN_SEL_MSK); 347 if (ret) { 348 ath11k_warn(ab, "failed to set sysclk: %d\n", ret); 349 return ret; 350 } 351 352 ret = ath11k_pci_set_link_reg(ab, 353 PCIE_PCS_OSC_DTCT_CONFIG1_REG(ab), 354 PCIE_PCS_OSC_DTCT_CONFIG1_VAL, 355 PCIE_PCS_OSC_DTCT_CONFIG_MSK); 356 if (ret) { 357 ath11k_warn(ab, "failed to set dtct config1 error: %d\n", ret); 358 return ret; 359 } 360 361 ret = ath11k_pci_set_link_reg(ab, 362 PCIE_PCS_OSC_DTCT_CONFIG2_REG(ab), 363 PCIE_PCS_OSC_DTCT_CONFIG2_VAL, 364 PCIE_PCS_OSC_DTCT_CONFIG_MSK); 365 if (ret) { 366 ath11k_warn(ab, "failed to set dtct config2: %d\n", ret); 367 return ret; 368 } 369 370 ret = ath11k_pci_set_link_reg(ab, 371 PCIE_PCS_OSC_DTCT_CONFIG4_REG(ab), 372 PCIE_PCS_OSC_DTCT_CONFIG4_VAL, 373 PCIE_PCS_OSC_DTCT_CONFIG_MSK); 374 if (ret) { 375 ath11k_warn(ab, "failed to set dtct config4: %d\n", ret); 376 return ret; 377 } 378 379 return 0; 380 } 381 382 static void ath11k_pci_enable_ltssm(struct ath11k_base *ab) 383 { 384 u32 val; 385 int i; 386 387 val = ath11k_pci_read32(ab, PCIE_PCIE_PARF_LTSSM); 388 389 /* PCIE link seems very unstable after the Hot Reset*/ 390 for (i = 0; val != PARM_LTSSM_VALUE && i < 5; i++) { 391 if (val == 0xffffffff) 392 mdelay(5); 393 394 ath11k_pci_write32(ab, PCIE_PCIE_PARF_LTSSM, PARM_LTSSM_VALUE); 395 val = ath11k_pci_read32(ab, PCIE_PCIE_PARF_LTSSM); 396 } 397 398 ath11k_dbg(ab, ATH11K_DBG_PCI, "pci ltssm 0x%x\n", val); 399 400 val = ath11k_pci_read32(ab, GCC_GCC_PCIE_HOT_RST); 401 val |= GCC_GCC_PCIE_HOT_RST_VAL; 402 ath11k_pci_write32(ab, GCC_GCC_PCIE_HOT_RST, val); 403 val = ath11k_pci_read32(ab, GCC_GCC_PCIE_HOT_RST); 404 405 ath11k_dbg(ab, ATH11K_DBG_PCI, "pci pcie_hot_rst 0x%x\n", val); 406 407 mdelay(5); 408 } 409 410 static void ath11k_pci_clear_all_intrs(struct ath11k_base *ab) 411 { 412 /* This is a WAR for PCIE Hotreset. 413 * When target receive Hotreset, but will set the interrupt. 414 * So when download SBL again, SBL will open Interrupt and 415 * receive it, and crash immediately. 416 */ 417 ath11k_pci_write32(ab, PCIE_PCIE_INT_ALL_CLEAR, PCIE_INT_CLEAR_ALL); 418 } 419 420 static void ath11k_pci_set_wlaon_pwr_ctrl(struct ath11k_base *ab) 421 { 422 u32 val; 423 424 val = ath11k_pci_read32(ab, WLAON_QFPROM_PWR_CTRL_REG); 425 val &= ~QFPROM_PWR_CTRL_VDD4BLOW_MASK; 426 ath11k_pci_write32(ab, WLAON_QFPROM_PWR_CTRL_REG, val); 427 } 428 429 static void ath11k_pci_force_wake(struct ath11k_base *ab) 430 { 431 ath11k_pci_write32(ab, PCIE_SOC_WAKE_PCIE_LOCAL_REG, 1); 432 mdelay(5); 433 } 434 435 static void ath11k_pci_sw_reset(struct ath11k_base *ab, bool power_on) 436 { 437 mdelay(100); 438 439 if (power_on) { 440 ath11k_pci_enable_ltssm(ab); 441 ath11k_pci_clear_all_intrs(ab); 442 ath11k_pci_set_wlaon_pwr_ctrl(ab); 443 if (ab->hw_params.fix_l1ss) 444 ath11k_pci_fix_l1ss(ab); 445 } 446 447 ath11k_mhi_clear_vector(ab); 448 ath11k_pci_clear_dbg_registers(ab); 449 ath11k_pci_soc_global_reset(ab); 450 ath11k_mhi_set_mhictrl_reset(ab); 451 } 452 453 int ath11k_pci_get_msi_irq(struct device *dev, unsigned int vector) 454 { 455 struct pci_dev *pci_dev = to_pci_dev(dev); 456 457 return pci_irq_vector(pci_dev, vector); 458 } 459 460 static void ath11k_pci_get_msi_address(struct ath11k_base *ab, u32 *msi_addr_lo, 461 u32 *msi_addr_hi) 462 { 463 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab); 464 struct pci_dev *pci_dev = to_pci_dev(ab->dev); 465 466 pci_read_config_dword(pci_dev, pci_dev->msi_cap + PCI_MSI_ADDRESS_LO, 467 msi_addr_lo); 468 469 if (test_bit(ATH11K_PCI_FLAG_IS_MSI_64, &ab_pci->flags)) { 470 pci_read_config_dword(pci_dev, pci_dev->msi_cap + PCI_MSI_ADDRESS_HI, 471 msi_addr_hi); 472 } else { 473 *msi_addr_hi = 0; 474 } 475 } 476 477 int ath11k_pci_get_user_msi_assignment(struct ath11k_pci *ab_pci, char *user_name, 478 int *num_vectors, u32 *user_base_data, 479 u32 *base_vector) 480 { 481 struct ath11k_base *ab = ab_pci->ab; 482 const struct ath11k_msi_config *msi_config = ab_pci->msi_config; 483 int idx; 484 485 for (idx = 0; idx < msi_config->total_users; idx++) { 486 if (strcmp(user_name, msi_config->users[idx].name) == 0) { 487 *num_vectors = msi_config->users[idx].num_vectors; 488 *user_base_data = msi_config->users[idx].base_vector 489 + ab_pci->msi_ep_base_data; 490 *base_vector = msi_config->users[idx].base_vector; 491 492 ath11k_dbg(ab, ATH11K_DBG_PCI, "Assign MSI to user: %s, num_vectors: %d, user_base_data: %u, base_vector: %u\n", 493 user_name, *num_vectors, *user_base_data, 494 *base_vector); 495 496 return 0; 497 } 498 } 499 500 ath11k_err(ab, "Failed to find MSI assignment for %s!\n", user_name); 501 502 return -EINVAL; 503 } 504 505 static void ath11k_pci_get_ce_msi_idx(struct ath11k_base *ab, u32 ce_id, 506 u32 *msi_idx) 507 { 508 u32 i, msi_data_idx; 509 510 for (i = 0, msi_data_idx = 0; i < ab->hw_params.ce_count; i++) { 511 if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR) 512 continue; 513 514 if (ce_id == i) 515 break; 516 517 msi_data_idx++; 518 } 519 *msi_idx = msi_data_idx; 520 } 521 522 static int ath11k_get_user_msi_assignment(struct ath11k_base *ab, char *user_name, 523 int *num_vectors, u32 *user_base_data, 524 u32 *base_vector) 525 { 526 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab); 527 528 return ath11k_pci_get_user_msi_assignment(ab_pci, user_name, 529 num_vectors, user_base_data, 530 base_vector); 531 } 532 533 static void ath11k_pci_free_ext_irq(struct ath11k_base *ab) 534 { 535 int i, j; 536 537 for (i = 0; i < ATH11K_EXT_IRQ_GRP_NUM_MAX; i++) { 538 struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i]; 539 540 for (j = 0; j < irq_grp->num_irq; j++) 541 free_irq(ab->irq_num[irq_grp->irqs[j]], irq_grp); 542 543 netif_napi_del(&irq_grp->napi); 544 } 545 } 546 547 static void ath11k_pci_free_irq(struct ath11k_base *ab) 548 { 549 int i, irq_idx; 550 551 for (i = 0; i < ab->hw_params.ce_count; i++) { 552 if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR) 553 continue; 554 irq_idx = ATH11K_PCI_IRQ_CE0_OFFSET + i; 555 free_irq(ab->irq_num[irq_idx], &ab->ce.ce_pipe[i]); 556 } 557 558 ath11k_pci_free_ext_irq(ab); 559 } 560 561 static void ath11k_pci_ce_irq_enable(struct ath11k_base *ab, u16 ce_id) 562 { 563 u32 irq_idx; 564 565 irq_idx = ATH11K_PCI_IRQ_CE0_OFFSET + ce_id; 566 enable_irq(ab->irq_num[irq_idx]); 567 } 568 569 static void ath11k_pci_ce_irq_disable(struct ath11k_base *ab, u16 ce_id) 570 { 571 u32 irq_idx; 572 573 irq_idx = ATH11K_PCI_IRQ_CE0_OFFSET + ce_id; 574 disable_irq_nosync(ab->irq_num[irq_idx]); 575 } 576 577 static void ath11k_pci_ce_irqs_disable(struct ath11k_base *ab) 578 { 579 int i; 580 581 for (i = 0; i < ab->hw_params.ce_count; i++) { 582 if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR) 583 continue; 584 ath11k_pci_ce_irq_disable(ab, i); 585 } 586 } 587 588 static void ath11k_pci_sync_ce_irqs(struct ath11k_base *ab) 589 { 590 int i; 591 int irq_idx; 592 593 for (i = 0; i < ab->hw_params.ce_count; i++) { 594 if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR) 595 continue; 596 597 irq_idx = ATH11K_PCI_IRQ_CE0_OFFSET + i; 598 synchronize_irq(ab->irq_num[irq_idx]); 599 } 600 } 601 602 static void ath11k_pci_ce_tasklet(struct tasklet_struct *t) 603 { 604 struct ath11k_ce_pipe *ce_pipe = from_tasklet(ce_pipe, t, intr_tq); 605 606 ath11k_ce_per_engine_service(ce_pipe->ab, ce_pipe->pipe_num); 607 608 ath11k_pci_ce_irq_enable(ce_pipe->ab, ce_pipe->pipe_num); 609 } 610 611 static irqreturn_t ath11k_pci_ce_interrupt_handler(int irq, void *arg) 612 { 613 struct ath11k_ce_pipe *ce_pipe = arg; 614 615 /* last interrupt received for this CE */ 616 ce_pipe->timestamp = jiffies; 617 618 ath11k_pci_ce_irq_disable(ce_pipe->ab, ce_pipe->pipe_num); 619 tasklet_schedule(&ce_pipe->intr_tq); 620 621 return IRQ_HANDLED; 622 } 623 624 static void ath11k_pci_ext_grp_disable(struct ath11k_ext_irq_grp *irq_grp) 625 { 626 int i; 627 628 for (i = 0; i < irq_grp->num_irq; i++) 629 disable_irq_nosync(irq_grp->ab->irq_num[irq_grp->irqs[i]]); 630 } 631 632 static void __ath11k_pci_ext_irq_disable(struct ath11k_base *sc) 633 { 634 int i; 635 636 for (i = 0; i < ATH11K_EXT_IRQ_GRP_NUM_MAX; i++) { 637 struct ath11k_ext_irq_grp *irq_grp = &sc->ext_irq_grp[i]; 638 639 ath11k_pci_ext_grp_disable(irq_grp); 640 641 napi_synchronize(&irq_grp->napi); 642 napi_disable(&irq_grp->napi); 643 } 644 } 645 646 static void ath11k_pci_ext_grp_enable(struct ath11k_ext_irq_grp *irq_grp) 647 { 648 int i; 649 650 for (i = 0; i < irq_grp->num_irq; i++) 651 enable_irq(irq_grp->ab->irq_num[irq_grp->irqs[i]]); 652 } 653 654 static void ath11k_pci_ext_irq_enable(struct ath11k_base *ab) 655 { 656 int i; 657 658 for (i = 0; i < ATH11K_EXT_IRQ_GRP_NUM_MAX; i++) { 659 struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i]; 660 661 napi_enable(&irq_grp->napi); 662 ath11k_pci_ext_grp_enable(irq_grp); 663 } 664 } 665 666 static void ath11k_pci_sync_ext_irqs(struct ath11k_base *ab) 667 { 668 int i, j, irq_idx; 669 670 for (i = 0; i < ATH11K_EXT_IRQ_GRP_NUM_MAX; i++) { 671 struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i]; 672 673 for (j = 0; j < irq_grp->num_irq; j++) { 674 irq_idx = irq_grp->irqs[j]; 675 synchronize_irq(ab->irq_num[irq_idx]); 676 } 677 } 678 } 679 680 static void ath11k_pci_ext_irq_disable(struct ath11k_base *ab) 681 { 682 __ath11k_pci_ext_irq_disable(ab); 683 ath11k_pci_sync_ext_irqs(ab); 684 } 685 686 static int ath11k_pci_ext_grp_napi_poll(struct napi_struct *napi, int budget) 687 { 688 struct ath11k_ext_irq_grp *irq_grp = container_of(napi, 689 struct ath11k_ext_irq_grp, 690 napi); 691 struct ath11k_base *ab = irq_grp->ab; 692 int work_done; 693 694 work_done = ath11k_dp_service_srng(ab, irq_grp, budget); 695 if (work_done < budget) { 696 napi_complete_done(napi, work_done); 697 ath11k_pci_ext_grp_enable(irq_grp); 698 } 699 700 if (work_done > budget) 701 work_done = budget; 702 703 return work_done; 704 } 705 706 static irqreturn_t ath11k_pci_ext_interrupt_handler(int irq, void *arg) 707 { 708 struct ath11k_ext_irq_grp *irq_grp = arg; 709 710 ath11k_dbg(irq_grp->ab, ATH11K_DBG_PCI, "ext irq:%d\n", irq); 711 712 /* last interrupt received for this group */ 713 irq_grp->timestamp = jiffies; 714 715 ath11k_pci_ext_grp_disable(irq_grp); 716 717 napi_schedule(&irq_grp->napi); 718 719 return IRQ_HANDLED; 720 } 721 722 static int ath11k_pci_ext_irq_config(struct ath11k_base *ab) 723 { 724 int i, j, ret, num_vectors = 0; 725 u32 user_base_data = 0, base_vector = 0, base_idx; 726 727 base_idx = ATH11K_PCI_IRQ_CE0_OFFSET + CE_COUNT_MAX; 728 ret = ath11k_pci_get_user_msi_assignment(ath11k_pci_priv(ab), "DP", 729 &num_vectors, 730 &user_base_data, 731 &base_vector); 732 if (ret < 0) 733 return ret; 734 735 for (i = 0; i < ATH11K_EXT_IRQ_GRP_NUM_MAX; i++) { 736 struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i]; 737 u32 num_irq = 0; 738 739 irq_grp->ab = ab; 740 irq_grp->grp_id = i; 741 init_dummy_netdev(&irq_grp->napi_ndev); 742 netif_napi_add(&irq_grp->napi_ndev, &irq_grp->napi, 743 ath11k_pci_ext_grp_napi_poll, NAPI_POLL_WEIGHT); 744 745 if (ab->hw_params.ring_mask->tx[i] || 746 ab->hw_params.ring_mask->rx[i] || 747 ab->hw_params.ring_mask->rx_err[i] || 748 ab->hw_params.ring_mask->rx_wbm_rel[i] || 749 ab->hw_params.ring_mask->reo_status[i] || 750 ab->hw_params.ring_mask->rxdma2host[i] || 751 ab->hw_params.ring_mask->host2rxdma[i] || 752 ab->hw_params.ring_mask->rx_mon_status[i]) { 753 num_irq = 1; 754 } 755 756 irq_grp->num_irq = num_irq; 757 irq_grp->irqs[0] = base_idx + i; 758 759 for (j = 0; j < irq_grp->num_irq; j++) { 760 int irq_idx = irq_grp->irqs[j]; 761 int vector = (i % num_vectors) + base_vector; 762 int irq = ath11k_pci_get_msi_irq(ab->dev, vector); 763 764 ab->irq_num[irq_idx] = irq; 765 766 ath11k_dbg(ab, ATH11K_DBG_PCI, 767 "irq:%d group:%d\n", irq, i); 768 769 irq_set_status_flags(irq, IRQ_DISABLE_UNLAZY); 770 ret = request_irq(irq, ath11k_pci_ext_interrupt_handler, 771 IRQF_SHARED, 772 "DP_EXT_IRQ", irq_grp); 773 if (ret) { 774 ath11k_err(ab, "failed request irq %d: %d\n", 775 vector, ret); 776 return ret; 777 } 778 779 disable_irq_nosync(ab->irq_num[irq_idx]); 780 } 781 } 782 783 return 0; 784 } 785 786 static int ath11k_pci_config_irq(struct ath11k_base *ab) 787 { 788 struct ath11k_ce_pipe *ce_pipe; 789 u32 msi_data_start; 790 u32 msi_data_count, msi_data_idx; 791 u32 msi_irq_start; 792 unsigned int msi_data; 793 int irq, i, ret, irq_idx; 794 795 ret = ath11k_pci_get_user_msi_assignment(ath11k_pci_priv(ab), 796 "CE", &msi_data_count, 797 &msi_data_start, &msi_irq_start); 798 if (ret) 799 return ret; 800 801 /* Configure CE irqs */ 802 for (i = 0, msi_data_idx = 0; i < ab->hw_params.ce_count; i++) { 803 if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR) 804 continue; 805 806 msi_data = (msi_data_idx % msi_data_count) + msi_irq_start; 807 irq = ath11k_pci_get_msi_irq(ab->dev, msi_data); 808 ce_pipe = &ab->ce.ce_pipe[i]; 809 810 irq_idx = ATH11K_PCI_IRQ_CE0_OFFSET + i; 811 812 tasklet_setup(&ce_pipe->intr_tq, ath11k_pci_ce_tasklet); 813 814 ret = request_irq(irq, ath11k_pci_ce_interrupt_handler, 815 IRQF_SHARED, irq_name[irq_idx], 816 ce_pipe); 817 if (ret) { 818 ath11k_err(ab, "failed to request irq %d: %d\n", 819 irq_idx, ret); 820 return ret; 821 } 822 823 ab->irq_num[irq_idx] = irq; 824 msi_data_idx++; 825 826 ath11k_pci_ce_irq_disable(ab, i); 827 } 828 829 ret = ath11k_pci_ext_irq_config(ab); 830 if (ret) 831 return ret; 832 833 return 0; 834 } 835 836 static void ath11k_pci_init_qmi_ce_config(struct ath11k_base *ab) 837 { 838 struct ath11k_qmi_ce_cfg *cfg = &ab->qmi.ce_cfg; 839 840 cfg->tgt_ce = ab->hw_params.target_ce_config; 841 cfg->tgt_ce_len = ab->hw_params.target_ce_count; 842 843 cfg->svc_to_ce_map = ab->hw_params.svc_to_ce_map; 844 cfg->svc_to_ce_map_len = ab->hw_params.svc_to_ce_map_len; 845 ab->qmi.service_ins_id = ab->hw_params.qmi_service_ins_id; 846 847 ath11k_ce_get_shadow_config(ab, &cfg->shadow_reg_v2, 848 &cfg->shadow_reg_v2_len); 849 } 850 851 static void ath11k_pci_ce_irqs_enable(struct ath11k_base *ab) 852 { 853 int i; 854 855 for (i = 0; i < ab->hw_params.ce_count; i++) { 856 if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR) 857 continue; 858 ath11k_pci_ce_irq_enable(ab, i); 859 } 860 } 861 862 static void ath11k_pci_msi_config(struct ath11k_pci *ab_pci, bool enable) 863 { 864 struct pci_dev *dev = ab_pci->pdev; 865 u16 control; 866 867 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); 868 869 if (enable) 870 control |= PCI_MSI_FLAGS_ENABLE; 871 else 872 control &= ~PCI_MSI_FLAGS_ENABLE; 873 874 pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control); 875 } 876 877 static void ath11k_pci_msi_enable(struct ath11k_pci *ab_pci) 878 { 879 ath11k_pci_msi_config(ab_pci, true); 880 } 881 882 static void ath11k_pci_msi_disable(struct ath11k_pci *ab_pci) 883 { 884 ath11k_pci_msi_config(ab_pci, false); 885 } 886 887 static int ath11k_pci_alloc_msi(struct ath11k_pci *ab_pci) 888 { 889 struct ath11k_base *ab = ab_pci->ab; 890 const struct ath11k_msi_config *msi_config = ab_pci->msi_config; 891 struct msi_desc *msi_desc; 892 int num_vectors; 893 int ret; 894 895 num_vectors = pci_alloc_irq_vectors(ab_pci->pdev, 896 msi_config->total_vectors, 897 msi_config->total_vectors, 898 PCI_IRQ_MSI); 899 if (num_vectors != msi_config->total_vectors) { 900 ath11k_err(ab, "failed to get %d MSI vectors, only %d available", 901 msi_config->total_vectors, num_vectors); 902 903 if (num_vectors >= 0) 904 return -EINVAL; 905 else 906 return num_vectors; 907 } 908 ath11k_pci_msi_disable(ab_pci); 909 910 msi_desc = irq_get_msi_desc(ab_pci->pdev->irq); 911 if (!msi_desc) { 912 ath11k_err(ab, "msi_desc is NULL!\n"); 913 ret = -EINVAL; 914 goto free_msi_vector; 915 } 916 917 ab_pci->msi_ep_base_data = msi_desc->msg.data; 918 if (msi_desc->msi_attrib.is_64) 919 set_bit(ATH11K_PCI_FLAG_IS_MSI_64, &ab_pci->flags); 920 921 ath11k_dbg(ab, ATH11K_DBG_PCI, "msi base data is %d\n", ab_pci->msi_ep_base_data); 922 923 return 0; 924 925 free_msi_vector: 926 pci_free_irq_vectors(ab_pci->pdev); 927 928 return ret; 929 } 930 931 static void ath11k_pci_free_msi(struct ath11k_pci *ab_pci) 932 { 933 pci_free_irq_vectors(ab_pci->pdev); 934 } 935 936 static int ath11k_pci_config_msi_data(struct ath11k_pci *ab_pci) 937 { 938 struct msi_desc *msi_desc; 939 940 msi_desc = irq_get_msi_desc(ab_pci->pdev->irq); 941 if (!msi_desc) { 942 ath11k_err(ab_pci->ab, "msi_desc is NULL!\n"); 943 pci_free_irq_vectors(ab_pci->pdev); 944 return -EINVAL; 945 } 946 947 ab_pci->msi_ep_base_data = msi_desc->msg.data; 948 949 ath11k_dbg(ab_pci->ab, ATH11K_DBG_PCI, "pci after request_irq msi_ep_base_data %d\n", 950 ab_pci->msi_ep_base_data); 951 952 return 0; 953 } 954 955 static int ath11k_pci_claim(struct ath11k_pci *ab_pci, struct pci_dev *pdev) 956 { 957 struct ath11k_base *ab = ab_pci->ab; 958 u16 device_id; 959 int ret = 0; 960 961 pci_read_config_word(pdev, PCI_DEVICE_ID, &device_id); 962 if (device_id != ab_pci->dev_id) { 963 ath11k_err(ab, "pci device id mismatch: 0x%x 0x%x\n", 964 device_id, ab_pci->dev_id); 965 ret = -EIO; 966 goto out; 967 } 968 969 ret = pci_assign_resource(pdev, ATH11K_PCI_BAR_NUM); 970 if (ret) { 971 ath11k_err(ab, "failed to assign pci resource: %d\n", ret); 972 goto out; 973 } 974 975 ret = pci_enable_device(pdev); 976 if (ret) { 977 ath11k_err(ab, "failed to enable pci device: %d\n", ret); 978 goto out; 979 } 980 981 ret = pci_request_region(pdev, ATH11K_PCI_BAR_NUM, "ath11k_pci"); 982 if (ret) { 983 ath11k_err(ab, "failed to request pci region: %d\n", ret); 984 goto disable_device; 985 } 986 987 ret = dma_set_mask_and_coherent(&pdev->dev, 988 DMA_BIT_MASK(ATH11K_PCI_DMA_MASK)); 989 if (ret) { 990 ath11k_err(ab, "failed to set pci dma mask to %d: %d\n", 991 ATH11K_PCI_DMA_MASK, ret); 992 goto release_region; 993 } 994 995 pci_set_master(pdev); 996 997 ab->mem_len = pci_resource_len(pdev, ATH11K_PCI_BAR_NUM); 998 ab->mem = pci_iomap(pdev, ATH11K_PCI_BAR_NUM, 0); 999 if (!ab->mem) { 1000 ath11k_err(ab, "failed to map pci bar %d\n", ATH11K_PCI_BAR_NUM); 1001 ret = -EIO; 1002 goto clear_master; 1003 } 1004 1005 ath11k_dbg(ab, ATH11K_DBG_BOOT, "boot pci_mem 0x%pK\n", ab->mem); 1006 return 0; 1007 1008 clear_master: 1009 pci_clear_master(pdev); 1010 release_region: 1011 pci_release_region(pdev, ATH11K_PCI_BAR_NUM); 1012 disable_device: 1013 pci_disable_device(pdev); 1014 out: 1015 return ret; 1016 } 1017 1018 static void ath11k_pci_free_region(struct ath11k_pci *ab_pci) 1019 { 1020 struct ath11k_base *ab = ab_pci->ab; 1021 struct pci_dev *pci_dev = ab_pci->pdev; 1022 1023 pci_iounmap(pci_dev, ab->mem); 1024 ab->mem = NULL; 1025 pci_clear_master(pci_dev); 1026 pci_release_region(pci_dev, ATH11K_PCI_BAR_NUM); 1027 if (pci_is_enabled(pci_dev)) 1028 pci_disable_device(pci_dev); 1029 } 1030 1031 static void ath11k_pci_aspm_disable(struct ath11k_pci *ab_pci) 1032 { 1033 struct ath11k_base *ab = ab_pci->ab; 1034 1035 pcie_capability_read_word(ab_pci->pdev, PCI_EXP_LNKCTL, 1036 &ab_pci->link_ctl); 1037 1038 ath11k_dbg(ab, ATH11K_DBG_PCI, "pci link_ctl 0x%04x L0s %d L1 %d\n", 1039 ab_pci->link_ctl, 1040 u16_get_bits(ab_pci->link_ctl, PCI_EXP_LNKCTL_ASPM_L0S), 1041 u16_get_bits(ab_pci->link_ctl, PCI_EXP_LNKCTL_ASPM_L1)); 1042 1043 /* disable L0s and L1 */ 1044 pcie_capability_write_word(ab_pci->pdev, PCI_EXP_LNKCTL, 1045 ab_pci->link_ctl & ~PCI_EXP_LNKCTL_ASPMC); 1046 1047 set_bit(ATH11K_PCI_ASPM_RESTORE, &ab_pci->flags); 1048 } 1049 1050 static void ath11k_pci_aspm_restore(struct ath11k_pci *ab_pci) 1051 { 1052 if (test_and_clear_bit(ATH11K_PCI_ASPM_RESTORE, &ab_pci->flags)) 1053 pcie_capability_write_word(ab_pci->pdev, PCI_EXP_LNKCTL, 1054 ab_pci->link_ctl); 1055 } 1056 1057 static int ath11k_pci_power_up(struct ath11k_base *ab) 1058 { 1059 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab); 1060 int ret; 1061 1062 ab_pci->register_window = 0; 1063 clear_bit(ATH11K_PCI_FLAG_INIT_DONE, &ab_pci->flags); 1064 ath11k_pci_sw_reset(ab_pci->ab, true); 1065 1066 /* Disable ASPM during firmware download due to problems switching 1067 * to AMSS state. 1068 */ 1069 ath11k_pci_aspm_disable(ab_pci); 1070 1071 ath11k_pci_msi_enable(ab_pci); 1072 1073 ret = ath11k_mhi_start(ab_pci); 1074 if (ret) { 1075 ath11k_err(ab, "failed to start mhi: %d\n", ret); 1076 return ret; 1077 } 1078 1079 if (ab->bus_params.static_window_map) 1080 ath11k_pci_select_static_window(ab_pci); 1081 1082 return 0; 1083 } 1084 1085 static void ath11k_pci_power_down(struct ath11k_base *ab) 1086 { 1087 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab); 1088 1089 /* restore aspm in case firmware bootup fails */ 1090 ath11k_pci_aspm_restore(ab_pci); 1091 1092 ath11k_pci_force_wake(ab_pci->ab); 1093 1094 ath11k_pci_msi_disable(ab_pci); 1095 1096 ath11k_mhi_stop(ab_pci); 1097 clear_bit(ATH11K_PCI_FLAG_INIT_DONE, &ab_pci->flags); 1098 ath11k_pci_sw_reset(ab_pci->ab, false); 1099 } 1100 1101 static int ath11k_pci_hif_suspend(struct ath11k_base *ab) 1102 { 1103 struct ath11k_pci *ar_pci = ath11k_pci_priv(ab); 1104 1105 ath11k_mhi_suspend(ar_pci); 1106 1107 return 0; 1108 } 1109 1110 static int ath11k_pci_hif_resume(struct ath11k_base *ab) 1111 { 1112 struct ath11k_pci *ar_pci = ath11k_pci_priv(ab); 1113 1114 ath11k_mhi_resume(ar_pci); 1115 1116 return 0; 1117 } 1118 1119 static void ath11k_pci_kill_tasklets(struct ath11k_base *ab) 1120 { 1121 int i; 1122 1123 for (i = 0; i < ab->hw_params.ce_count; i++) { 1124 struct ath11k_ce_pipe *ce_pipe = &ab->ce.ce_pipe[i]; 1125 1126 if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR) 1127 continue; 1128 1129 tasklet_kill(&ce_pipe->intr_tq); 1130 } 1131 } 1132 1133 static void ath11k_pci_ce_irq_disable_sync(struct ath11k_base *ab) 1134 { 1135 ath11k_pci_ce_irqs_disable(ab); 1136 ath11k_pci_sync_ce_irqs(ab); 1137 ath11k_pci_kill_tasklets(ab); 1138 } 1139 1140 static void ath11k_pci_stop(struct ath11k_base *ab) 1141 { 1142 ath11k_pci_ce_irq_disable_sync(ab); 1143 ath11k_ce_cleanup_pipes(ab); 1144 } 1145 1146 static int ath11k_pci_start(struct ath11k_base *ab) 1147 { 1148 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab); 1149 1150 set_bit(ATH11K_PCI_FLAG_INIT_DONE, &ab_pci->flags); 1151 1152 ath11k_pci_aspm_restore(ab_pci); 1153 1154 ath11k_pci_ce_irqs_enable(ab); 1155 ath11k_ce_rx_post_buf(ab); 1156 1157 return 0; 1158 } 1159 1160 static void ath11k_pci_hif_ce_irq_enable(struct ath11k_base *ab) 1161 { 1162 ath11k_pci_ce_irqs_enable(ab); 1163 } 1164 1165 static void ath11k_pci_hif_ce_irq_disable(struct ath11k_base *ab) 1166 { 1167 ath11k_pci_ce_irq_disable_sync(ab); 1168 } 1169 1170 static int ath11k_pci_map_service_to_pipe(struct ath11k_base *ab, u16 service_id, 1171 u8 *ul_pipe, u8 *dl_pipe) 1172 { 1173 const struct service_to_pipe *entry; 1174 bool ul_set = false, dl_set = false; 1175 int i; 1176 1177 for (i = 0; i < ab->hw_params.svc_to_ce_map_len; i++) { 1178 entry = &ab->hw_params.svc_to_ce_map[i]; 1179 1180 if (__le32_to_cpu(entry->service_id) != service_id) 1181 continue; 1182 1183 switch (__le32_to_cpu(entry->pipedir)) { 1184 case PIPEDIR_NONE: 1185 break; 1186 case PIPEDIR_IN: 1187 WARN_ON(dl_set); 1188 *dl_pipe = __le32_to_cpu(entry->pipenum); 1189 dl_set = true; 1190 break; 1191 case PIPEDIR_OUT: 1192 WARN_ON(ul_set); 1193 *ul_pipe = __le32_to_cpu(entry->pipenum); 1194 ul_set = true; 1195 break; 1196 case PIPEDIR_INOUT: 1197 WARN_ON(dl_set); 1198 WARN_ON(ul_set); 1199 *dl_pipe = __le32_to_cpu(entry->pipenum); 1200 *ul_pipe = __le32_to_cpu(entry->pipenum); 1201 dl_set = true; 1202 ul_set = true; 1203 break; 1204 } 1205 } 1206 1207 if (WARN_ON(!ul_set || !dl_set)) 1208 return -ENOENT; 1209 1210 return 0; 1211 } 1212 1213 static const struct ath11k_hif_ops ath11k_pci_hif_ops = { 1214 .start = ath11k_pci_start, 1215 .stop = ath11k_pci_stop, 1216 .read32 = ath11k_pci_read32, 1217 .write32 = ath11k_pci_write32, 1218 .power_down = ath11k_pci_power_down, 1219 .power_up = ath11k_pci_power_up, 1220 .suspend = ath11k_pci_hif_suspend, 1221 .resume = ath11k_pci_hif_resume, 1222 .irq_enable = ath11k_pci_ext_irq_enable, 1223 .irq_disable = ath11k_pci_ext_irq_disable, 1224 .get_msi_address = ath11k_pci_get_msi_address, 1225 .get_user_msi_vector = ath11k_get_user_msi_assignment, 1226 .map_service_to_pipe = ath11k_pci_map_service_to_pipe, 1227 .ce_irq_enable = ath11k_pci_hif_ce_irq_enable, 1228 .ce_irq_disable = ath11k_pci_hif_ce_irq_disable, 1229 .get_ce_msi_idx = ath11k_pci_get_ce_msi_idx, 1230 }; 1231 1232 static void ath11k_pci_read_hw_version(struct ath11k_base *ab, u32 *major, u32 *minor) 1233 { 1234 u32 soc_hw_version; 1235 1236 soc_hw_version = ath11k_pci_read32(ab, TCSR_SOC_HW_VERSION); 1237 *major = FIELD_GET(TCSR_SOC_HW_VERSION_MAJOR_MASK, 1238 soc_hw_version); 1239 *minor = FIELD_GET(TCSR_SOC_HW_VERSION_MINOR_MASK, 1240 soc_hw_version); 1241 1242 ath11k_dbg(ab, ATH11K_DBG_PCI, "pci tcsr_soc_hw_version major %d minor %d\n", 1243 *major, *minor); 1244 } 1245 1246 static int ath11k_pci_probe(struct pci_dev *pdev, 1247 const struct pci_device_id *pci_dev) 1248 { 1249 struct ath11k_base *ab; 1250 struct ath11k_pci *ab_pci; 1251 u32 soc_hw_version_major, soc_hw_version_minor; 1252 int ret; 1253 1254 ab = ath11k_core_alloc(&pdev->dev, sizeof(*ab_pci), ATH11K_BUS_PCI, 1255 &ath11k_pci_bus_params); 1256 if (!ab) { 1257 dev_err(&pdev->dev, "failed to allocate ath11k base\n"); 1258 return -ENOMEM; 1259 } 1260 1261 ab->dev = &pdev->dev; 1262 pci_set_drvdata(pdev, ab); 1263 ab_pci = ath11k_pci_priv(ab); 1264 ab_pci->dev_id = pci_dev->device; 1265 ab_pci->ab = ab; 1266 ab_pci->pdev = pdev; 1267 ab->hif.ops = &ath11k_pci_hif_ops; 1268 pci_set_drvdata(pdev, ab); 1269 spin_lock_init(&ab_pci->window_lock); 1270 1271 ret = ath11k_pci_claim(ab_pci, pdev); 1272 if (ret) { 1273 ath11k_err(ab, "failed to claim device: %d\n", ret); 1274 goto err_free_core; 1275 } 1276 1277 ath11k_dbg(ab, ATH11K_DBG_BOOT, "pci probe %04x:%04x %04x:%04x\n", 1278 pdev->vendor, pdev->device, 1279 pdev->subsystem_vendor, pdev->subsystem_device); 1280 1281 ab->id.vendor = pdev->vendor; 1282 ab->id.device = pdev->device; 1283 ab->id.subsystem_vendor = pdev->subsystem_vendor; 1284 ab->id.subsystem_device = pdev->subsystem_device; 1285 1286 switch (pci_dev->device) { 1287 case QCA6390_DEVICE_ID: 1288 ath11k_pci_read_hw_version(ab, &soc_hw_version_major, 1289 &soc_hw_version_minor); 1290 switch (soc_hw_version_major) { 1291 case 2: 1292 ab->hw_rev = ATH11K_HW_QCA6390_HW20; 1293 break; 1294 default: 1295 dev_err(&pdev->dev, "Unsupported QCA6390 SOC hardware version: %d %d\n", 1296 soc_hw_version_major, soc_hw_version_minor); 1297 ret = -EOPNOTSUPP; 1298 goto err_pci_free_region; 1299 } 1300 ab_pci->msi_config = &ath11k_msi_config[0]; 1301 break; 1302 case QCN9074_DEVICE_ID: 1303 ab_pci->msi_config = &ath11k_msi_config[1]; 1304 ab->bus_params.static_window_map = true; 1305 ab->hw_rev = ATH11K_HW_QCN9074_HW10; 1306 break; 1307 case WCN6855_DEVICE_ID: 1308 ab->id.bdf_search = ATH11K_BDF_SEARCH_BUS_AND_BOARD; 1309 ath11k_pci_read_hw_version(ab, &soc_hw_version_major, 1310 &soc_hw_version_minor); 1311 switch (soc_hw_version_major) { 1312 case 2: 1313 ab->hw_rev = ATH11K_HW_WCN6855_HW20; 1314 break; 1315 default: 1316 dev_err(&pdev->dev, "Unsupported WCN6855 SOC hardware version: %d %d\n", 1317 soc_hw_version_major, soc_hw_version_minor); 1318 ret = -EOPNOTSUPP; 1319 goto err_pci_free_region; 1320 } 1321 ab_pci->msi_config = &ath11k_msi_config[0]; 1322 break; 1323 default: 1324 dev_err(&pdev->dev, "Unknown PCI device found: 0x%x\n", 1325 pci_dev->device); 1326 ret = -EOPNOTSUPP; 1327 goto err_pci_free_region; 1328 } 1329 1330 ret = ath11k_pci_alloc_msi(ab_pci); 1331 if (ret) { 1332 ath11k_err(ab, "failed to enable msi: %d\n", ret); 1333 goto err_pci_free_region; 1334 } 1335 1336 ret = ath11k_core_pre_init(ab); 1337 if (ret) 1338 goto err_pci_disable_msi; 1339 1340 ret = ath11k_mhi_register(ab_pci); 1341 if (ret) { 1342 ath11k_err(ab, "failed to register mhi: %d\n", ret); 1343 goto err_pci_disable_msi; 1344 } 1345 1346 ret = ath11k_hal_srng_init(ab); 1347 if (ret) 1348 goto err_mhi_unregister; 1349 1350 ret = ath11k_ce_alloc_pipes(ab); 1351 if (ret) { 1352 ath11k_err(ab, "failed to allocate ce pipes: %d\n", ret); 1353 goto err_hal_srng_deinit; 1354 } 1355 1356 ath11k_pci_init_qmi_ce_config(ab); 1357 1358 ret = ath11k_pci_config_irq(ab); 1359 if (ret) { 1360 ath11k_err(ab, "failed to config irq: %d\n", ret); 1361 goto err_ce_free; 1362 } 1363 1364 /* kernel may allocate a dummy vector before request_irq and 1365 * then allocate a real vector when request_irq is called. 1366 * So get msi_data here again to avoid spurious interrupt 1367 * as msi_data will configured to srngs. 1368 */ 1369 ret = ath11k_pci_config_msi_data(ab_pci); 1370 if (ret) { 1371 ath11k_err(ab, "failed to config msi_data: %d\n", ret); 1372 goto err_free_irq; 1373 } 1374 1375 ret = ath11k_core_init(ab); 1376 if (ret) { 1377 ath11k_err(ab, "failed to init core: %d\n", ret); 1378 goto err_free_irq; 1379 } 1380 return 0; 1381 1382 err_free_irq: 1383 ath11k_pci_free_irq(ab); 1384 1385 err_ce_free: 1386 ath11k_ce_free_pipes(ab); 1387 1388 err_hal_srng_deinit: 1389 ath11k_hal_srng_deinit(ab); 1390 1391 err_mhi_unregister: 1392 ath11k_mhi_unregister(ab_pci); 1393 1394 err_pci_disable_msi: 1395 ath11k_pci_free_msi(ab_pci); 1396 1397 err_pci_free_region: 1398 ath11k_pci_free_region(ab_pci); 1399 1400 err_free_core: 1401 ath11k_core_free(ab); 1402 1403 return ret; 1404 } 1405 1406 static void ath11k_pci_remove(struct pci_dev *pdev) 1407 { 1408 struct ath11k_base *ab = pci_get_drvdata(pdev); 1409 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab); 1410 1411 if (test_bit(ATH11K_FLAG_QMI_FAIL, &ab->dev_flags)) { 1412 ath11k_pci_power_down(ab); 1413 ath11k_debugfs_soc_destroy(ab); 1414 ath11k_qmi_deinit_service(ab); 1415 goto qmi_fail; 1416 } 1417 1418 set_bit(ATH11K_FLAG_UNREGISTERING, &ab->dev_flags); 1419 1420 ath11k_core_deinit(ab); 1421 1422 qmi_fail: 1423 ath11k_mhi_unregister(ab_pci); 1424 1425 ath11k_pci_free_irq(ab); 1426 ath11k_pci_free_msi(ab_pci); 1427 ath11k_pci_free_region(ab_pci); 1428 1429 ath11k_hal_srng_deinit(ab); 1430 ath11k_ce_free_pipes(ab); 1431 ath11k_core_free(ab); 1432 } 1433 1434 static void ath11k_pci_shutdown(struct pci_dev *pdev) 1435 { 1436 struct ath11k_base *ab = pci_get_drvdata(pdev); 1437 1438 ath11k_pci_power_down(ab); 1439 } 1440 1441 static __maybe_unused int ath11k_pci_pm_suspend(struct device *dev) 1442 { 1443 struct ath11k_base *ab = dev_get_drvdata(dev); 1444 int ret; 1445 1446 ret = ath11k_core_suspend(ab); 1447 if (ret) 1448 ath11k_warn(ab, "failed to suspend core: %d\n", ret); 1449 1450 return ret; 1451 } 1452 1453 static __maybe_unused int ath11k_pci_pm_resume(struct device *dev) 1454 { 1455 struct ath11k_base *ab = dev_get_drvdata(dev); 1456 int ret; 1457 1458 ret = ath11k_core_resume(ab); 1459 if (ret) 1460 ath11k_warn(ab, "failed to resume core: %d\n", ret); 1461 1462 return ret; 1463 } 1464 1465 static SIMPLE_DEV_PM_OPS(ath11k_pci_pm_ops, 1466 ath11k_pci_pm_suspend, 1467 ath11k_pci_pm_resume); 1468 1469 static struct pci_driver ath11k_pci_driver = { 1470 .name = "ath11k_pci", 1471 .id_table = ath11k_pci_id_table, 1472 .probe = ath11k_pci_probe, 1473 .remove = ath11k_pci_remove, 1474 .shutdown = ath11k_pci_shutdown, 1475 #ifdef CONFIG_PM 1476 .driver.pm = &ath11k_pci_pm_ops, 1477 #endif 1478 }; 1479 1480 static int ath11k_pci_init(void) 1481 { 1482 int ret; 1483 1484 ret = pci_register_driver(&ath11k_pci_driver); 1485 if (ret) 1486 pr_err("failed to register ath11k pci driver: %d\n", 1487 ret); 1488 1489 return ret; 1490 } 1491 module_init(ath11k_pci_init); 1492 1493 static void ath11k_pci_exit(void) 1494 { 1495 pci_unregister_driver(&ath11k_pci_driver); 1496 } 1497 1498 module_exit(ath11k_pci_exit); 1499 1500 MODULE_DESCRIPTION("Driver support for Qualcomm Technologies 802.11ax WLAN PCIe devices"); 1501 MODULE_LICENSE("Dual BSD/GPL"); 1502 1503 /* QCA639x 2.0 firmware files */ 1504 MODULE_FIRMWARE(ATH11K_FW_DIR "/QCA6390/hw2.0/" ATH11K_BOARD_API2_FILE); 1505 MODULE_FIRMWARE(ATH11K_FW_DIR "/QCA6390/hw2.0/" ATH11K_AMSS_FILE); 1506 MODULE_FIRMWARE(ATH11K_FW_DIR "/QCA6390/hw2.0/" ATH11K_M3_FILE); 1507