1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * wanXL serial card driver for Linux 4 * host part 5 * 6 * Copyright (C) 2003 Krzysztof Halasa <khc@pm.waw.pl> 7 * 8 * Status: 9 * - Only DTE (external clock) support with NRZ and NRZI encodings 10 * - wanXL100 will require minor driver modifications, no access to hw 11 */ 12 13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 14 15 #include <linux/module.h> 16 #include <linux/kernel.h> 17 #include <linux/slab.h> 18 #include <linux/sched.h> 19 #include <linux/types.h> 20 #include <linux/fcntl.h> 21 #include <linux/string.h> 22 #include <linux/errno.h> 23 #include <linux/init.h> 24 #include <linux/interrupt.h> 25 #include <linux/ioport.h> 26 #include <linux/netdevice.h> 27 #include <linux/hdlc.h> 28 #include <linux/pci.h> 29 #include <linux/dma-mapping.h> 30 #include <linux/delay.h> 31 #include <asm/io.h> 32 33 #include "wanxl.h" 34 35 static const char *version = "wanXL serial card driver version: 0.48"; 36 37 #define PLX_CTL_RESET 0x40000000 /* adapter reset */ 38 39 #undef DEBUG_PKT 40 #undef DEBUG_PCI 41 42 /* MAILBOX #1 - PUTS COMMANDS */ 43 #define MBX1_CMD_ABORTJ 0x85000000 /* Abort and Jump */ 44 #ifdef __LITTLE_ENDIAN 45 #define MBX1_CMD_BSWAP 0x8C000001 /* little-endian Byte Swap Mode */ 46 #else 47 #define MBX1_CMD_BSWAP 0x8C000000 /* big-endian Byte Swap Mode */ 48 #endif 49 50 /* MAILBOX #2 - DRAM SIZE */ 51 #define MBX2_MEMSZ_MASK 0xFFFF0000 /* PUTS Memory Size Register mask */ 52 53 struct port { 54 struct net_device *dev; 55 struct card *card; 56 spinlock_t lock; /* for wanxl_xmit */ 57 int node; /* physical port #0 - 3 */ 58 unsigned int clock_type; 59 int tx_in, tx_out; 60 struct sk_buff *tx_skbs[TX_BUFFERS]; 61 }; 62 63 struct card_status { 64 desc_t rx_descs[RX_QUEUE_LENGTH]; 65 port_status_t port_status[4]; 66 }; 67 68 struct card { 69 int n_ports; /* 1, 2 or 4 ports */ 70 u8 irq; 71 72 u8 __iomem *plx; /* PLX PCI9060 virtual base address */ 73 struct pci_dev *pdev; /* for pci_name(pdev) */ 74 int rx_in; 75 struct sk_buff *rx_skbs[RX_QUEUE_LENGTH]; 76 struct card_status *status; /* shared between host and card */ 77 dma_addr_t status_address; 78 struct port ports[]; /* 1 - 4 port structures follow */ 79 }; 80 81 static inline struct port *dev_to_port(struct net_device *dev) 82 { 83 return (struct port *)dev_to_hdlc(dev)->priv; 84 } 85 86 static inline port_status_t *get_status(struct port *port) 87 { 88 return &port->card->status->port_status[port->node]; 89 } 90 91 #ifdef DEBUG_PCI 92 static inline dma_addr_t pci_map_single_debug(struct pci_dev *pdev, void *ptr, 93 size_t size, int direction) 94 { 95 dma_addr_t addr = dma_map_single(&pdev->dev, ptr, size, direction); 96 97 if (addr + size > 0x100000000LL) 98 pr_crit("%s: pci_map_single() returned memory at 0x%llx!\n", 99 pci_name(pdev), (unsigned long long)addr); 100 return addr; 101 } 102 103 #undef pci_map_single 104 #define pci_map_single pci_map_single_debug 105 #endif 106 107 /* Cable and/or personality module change interrupt service */ 108 static inline void wanxl_cable_intr(struct port *port) 109 { 110 u32 value = get_status(port)->cable; 111 int valid = 1; 112 const char *cable, *pm, *dte = "", *dsr = "", *dcd = ""; 113 114 switch (value & 0x7) { 115 case STATUS_CABLE_V35: 116 cable = "V.35"; 117 break; 118 case STATUS_CABLE_X21: 119 cable = "X.21"; 120 break; 121 case STATUS_CABLE_V24: 122 cable = "V.24"; 123 break; 124 case STATUS_CABLE_EIA530: 125 cable = "EIA530"; 126 break; 127 case STATUS_CABLE_NONE: 128 cable = "no"; 129 break; 130 default: 131 cable = "invalid"; 132 } 133 134 switch ((value >> STATUS_CABLE_PM_SHIFT) & 0x7) { 135 case STATUS_CABLE_V35: 136 pm = "V.35"; 137 break; 138 case STATUS_CABLE_X21: 139 pm = "X.21"; 140 break; 141 case STATUS_CABLE_V24: 142 pm = "V.24"; 143 break; 144 case STATUS_CABLE_EIA530: 145 pm = "EIA530"; 146 break; 147 case STATUS_CABLE_NONE: 148 pm = "no personality"; 149 valid = 0; 150 break; 151 default: 152 pm = "invalid personality"; 153 valid = 0; 154 } 155 156 if (valid) { 157 if ((value & 7) == ((value >> STATUS_CABLE_PM_SHIFT) & 7)) { 158 dsr = (value & STATUS_CABLE_DSR) ? ", DSR ON" : 159 ", DSR off"; 160 dcd = (value & STATUS_CABLE_DCD) ? ", carrier ON" : 161 ", carrier off"; 162 } 163 dte = (value & STATUS_CABLE_DCE) ? " DCE" : " DTE"; 164 } 165 netdev_info(port->dev, "%s%s module, %s cable%s%s\n", 166 pm, dte, cable, dsr, dcd); 167 168 if (value & STATUS_CABLE_DCD) 169 netif_carrier_on(port->dev); 170 else 171 netif_carrier_off(port->dev); 172 } 173 174 /* Transmit complete interrupt service */ 175 static inline void wanxl_tx_intr(struct port *port) 176 { 177 struct net_device *dev = port->dev; 178 179 while (1) { 180 desc_t *desc = &get_status(port)->tx_descs[port->tx_in]; 181 struct sk_buff *skb = port->tx_skbs[port->tx_in]; 182 183 switch (desc->stat) { 184 case PACKET_FULL: 185 case PACKET_EMPTY: 186 netif_wake_queue(dev); 187 return; 188 189 case PACKET_UNDERRUN: 190 dev->stats.tx_errors++; 191 dev->stats.tx_fifo_errors++; 192 break; 193 194 default: 195 dev->stats.tx_packets++; 196 dev->stats.tx_bytes += skb->len; 197 } 198 desc->stat = PACKET_EMPTY; /* Free descriptor */ 199 dma_unmap_single(&port->card->pdev->dev, desc->address, 200 skb->len, DMA_TO_DEVICE); 201 dev_consume_skb_irq(skb); 202 port->tx_in = (port->tx_in + 1) % TX_BUFFERS; 203 } 204 } 205 206 /* Receive complete interrupt service */ 207 static inline void wanxl_rx_intr(struct card *card) 208 { 209 desc_t *desc; 210 211 while (desc = &card->status->rx_descs[card->rx_in], 212 desc->stat != PACKET_EMPTY) { 213 if ((desc->stat & PACKET_PORT_MASK) > card->n_ports) 214 pr_crit("%s: received packet for nonexistent port\n", 215 pci_name(card->pdev)); 216 else { 217 struct sk_buff *skb = card->rx_skbs[card->rx_in]; 218 struct port *port = &card->ports[desc->stat & 219 PACKET_PORT_MASK]; 220 struct net_device *dev = port->dev; 221 222 if (!skb) 223 dev->stats.rx_dropped++; 224 else { 225 dma_unmap_single(&card->pdev->dev, 226 desc->address, BUFFER_LENGTH, 227 DMA_FROM_DEVICE); 228 skb_put(skb, desc->length); 229 230 #ifdef DEBUG_PKT 231 printk(KERN_DEBUG "%s RX(%i):", dev->name, 232 skb->len); 233 debug_frame(skb); 234 #endif 235 dev->stats.rx_packets++; 236 dev->stats.rx_bytes += skb->len; 237 skb->protocol = hdlc_type_trans(skb, dev); 238 netif_rx(skb); 239 skb = NULL; 240 } 241 242 if (!skb) { 243 skb = dev_alloc_skb(BUFFER_LENGTH); 244 desc->address = skb ? 245 dma_map_single(&card->pdev->dev, 246 skb->data, 247 BUFFER_LENGTH, 248 DMA_FROM_DEVICE) : 0; 249 card->rx_skbs[card->rx_in] = skb; 250 } 251 } 252 desc->stat = PACKET_EMPTY; /* Free descriptor */ 253 card->rx_in = (card->rx_in + 1) % RX_QUEUE_LENGTH; 254 } 255 } 256 257 static irqreturn_t wanxl_intr(int irq, void *dev_id) 258 { 259 struct card *card = dev_id; 260 int i; 261 u32 stat; 262 int handled = 0; 263 264 while ((stat = readl(card->plx + PLX_DOORBELL_FROM_CARD)) != 0) { 265 handled = 1; 266 writel(stat, card->plx + PLX_DOORBELL_FROM_CARD); 267 268 for (i = 0; i < card->n_ports; i++) { 269 if (stat & (1 << (DOORBELL_FROM_CARD_TX_0 + i))) 270 wanxl_tx_intr(&card->ports[i]); 271 if (stat & (1 << (DOORBELL_FROM_CARD_CABLE_0 + i))) 272 wanxl_cable_intr(&card->ports[i]); 273 } 274 if (stat & (1 << DOORBELL_FROM_CARD_RX)) 275 wanxl_rx_intr(card); 276 } 277 278 return IRQ_RETVAL(handled); 279 } 280 281 static netdev_tx_t wanxl_xmit(struct sk_buff *skb, struct net_device *dev) 282 { 283 struct port *port = dev_to_port(dev); 284 desc_t *desc; 285 286 spin_lock(&port->lock); 287 288 desc = &get_status(port)->tx_descs[port->tx_out]; 289 if (desc->stat != PACKET_EMPTY) { 290 /* should never happen - previous xmit should stop queue */ 291 #ifdef DEBUG_PKT 292 printk(KERN_DEBUG "%s: transmitter buffer full\n", dev->name); 293 #endif 294 netif_stop_queue(dev); 295 spin_unlock(&port->lock); 296 return NETDEV_TX_BUSY; /* request packet to be queued */ 297 } 298 299 #ifdef DEBUG_PKT 300 printk(KERN_DEBUG "%s TX(%i):", dev->name, skb->len); 301 debug_frame(skb); 302 #endif 303 304 port->tx_skbs[port->tx_out] = skb; 305 desc->address = dma_map_single(&port->card->pdev->dev, skb->data, 306 skb->len, DMA_TO_DEVICE); 307 desc->length = skb->len; 308 desc->stat = PACKET_FULL; 309 writel(1 << (DOORBELL_TO_CARD_TX_0 + port->node), 310 port->card->plx + PLX_DOORBELL_TO_CARD); 311 312 port->tx_out = (port->tx_out + 1) % TX_BUFFERS; 313 314 if (get_status(port)->tx_descs[port->tx_out].stat != PACKET_EMPTY) { 315 netif_stop_queue(dev); 316 #ifdef DEBUG_PKT 317 printk(KERN_DEBUG "%s: transmitter buffer full\n", dev->name); 318 #endif 319 } 320 321 spin_unlock(&port->lock); 322 return NETDEV_TX_OK; 323 } 324 325 static int wanxl_attach(struct net_device *dev, unsigned short encoding, 326 unsigned short parity) 327 { 328 struct port *port = dev_to_port(dev); 329 330 if (encoding != ENCODING_NRZ && 331 encoding != ENCODING_NRZI) 332 return -EINVAL; 333 334 if (parity != PARITY_NONE && 335 parity != PARITY_CRC32_PR1_CCITT && 336 parity != PARITY_CRC16_PR1_CCITT && 337 parity != PARITY_CRC32_PR0_CCITT && 338 parity != PARITY_CRC16_PR0_CCITT) 339 return -EINVAL; 340 341 get_status(port)->encoding = encoding; 342 get_status(port)->parity = parity; 343 return 0; 344 } 345 346 static int wanxl_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 347 { 348 const size_t size = sizeof(sync_serial_settings); 349 sync_serial_settings line; 350 struct port *port = dev_to_port(dev); 351 352 if (cmd != SIOCWANDEV) 353 return hdlc_ioctl(dev, ifr, cmd); 354 355 switch (ifr->ifr_settings.type) { 356 case IF_GET_IFACE: 357 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL; 358 if (ifr->ifr_settings.size < size) { 359 ifr->ifr_settings.size = size; /* data size wanted */ 360 return -ENOBUFS; 361 } 362 memset(&line, 0, sizeof(line)); 363 line.clock_type = get_status(port)->clocking; 364 line.clock_rate = 0; 365 line.loopback = 0; 366 367 if (copy_to_user(ifr->ifr_settings.ifs_ifsu.sync, &line, size)) 368 return -EFAULT; 369 return 0; 370 371 case IF_IFACE_SYNC_SERIAL: 372 if (!capable(CAP_NET_ADMIN)) 373 return -EPERM; 374 if (dev->flags & IFF_UP) 375 return -EBUSY; 376 377 if (copy_from_user(&line, ifr->ifr_settings.ifs_ifsu.sync, 378 size)) 379 return -EFAULT; 380 381 if (line.clock_type != CLOCK_EXT && 382 line.clock_type != CLOCK_TXFROMRX) 383 return -EINVAL; /* No such clock setting */ 384 385 if (line.loopback != 0) 386 return -EINVAL; 387 388 get_status(port)->clocking = line.clock_type; 389 return 0; 390 391 default: 392 return hdlc_ioctl(dev, ifr, cmd); 393 } 394 } 395 396 static int wanxl_open(struct net_device *dev) 397 { 398 struct port *port = dev_to_port(dev); 399 u8 __iomem *dbr = port->card->plx + PLX_DOORBELL_TO_CARD; 400 unsigned long timeout; 401 int i; 402 403 if (get_status(port)->open) { 404 netdev_err(dev, "port already open\n"); 405 return -EIO; 406 } 407 if ((i = hdlc_open(dev)) != 0) 408 return i; 409 410 port->tx_in = port->tx_out = 0; 411 for (i = 0; i < TX_BUFFERS; i++) 412 get_status(port)->tx_descs[i].stat = PACKET_EMPTY; 413 /* signal the card */ 414 writel(1 << (DOORBELL_TO_CARD_OPEN_0 + port->node), dbr); 415 416 timeout = jiffies + HZ; 417 do { 418 if (get_status(port)->open) { 419 netif_start_queue(dev); 420 return 0; 421 } 422 } while (time_after(timeout, jiffies)); 423 424 netdev_err(dev, "unable to open port\n"); 425 /* ask the card to close the port, should it be still alive */ 426 writel(1 << (DOORBELL_TO_CARD_CLOSE_0 + port->node), dbr); 427 return -EFAULT; 428 } 429 430 static int wanxl_close(struct net_device *dev) 431 { 432 struct port *port = dev_to_port(dev); 433 unsigned long timeout; 434 int i; 435 436 hdlc_close(dev); 437 /* signal the card */ 438 writel(1 << (DOORBELL_TO_CARD_CLOSE_0 + port->node), 439 port->card->plx + PLX_DOORBELL_TO_CARD); 440 441 timeout = jiffies + HZ; 442 do { 443 if (!get_status(port)->open) 444 break; 445 } while (time_after(timeout, jiffies)); 446 447 if (get_status(port)->open) 448 netdev_err(dev, "unable to close port\n"); 449 450 netif_stop_queue(dev); 451 452 for (i = 0; i < TX_BUFFERS; i++) { 453 desc_t *desc = &get_status(port)->tx_descs[i]; 454 455 if (desc->stat != PACKET_EMPTY) { 456 desc->stat = PACKET_EMPTY; 457 dma_unmap_single(&port->card->pdev->dev, 458 desc->address, port->tx_skbs[i]->len, 459 DMA_TO_DEVICE); 460 dev_kfree_skb(port->tx_skbs[i]); 461 } 462 } 463 return 0; 464 } 465 466 static struct net_device_stats *wanxl_get_stats(struct net_device *dev) 467 { 468 struct port *port = dev_to_port(dev); 469 470 dev->stats.rx_over_errors = get_status(port)->rx_overruns; 471 dev->stats.rx_frame_errors = get_status(port)->rx_frame_errors; 472 dev->stats.rx_errors = dev->stats.rx_over_errors + 473 dev->stats.rx_frame_errors; 474 return &dev->stats; 475 } 476 477 static int wanxl_puts_command(struct card *card, u32 cmd) 478 { 479 unsigned long timeout = jiffies + 5 * HZ; 480 481 writel(cmd, card->plx + PLX_MAILBOX_1); 482 do { 483 if (readl(card->plx + PLX_MAILBOX_1) == 0) 484 return 0; 485 486 schedule(); 487 } while (time_after(timeout, jiffies)); 488 489 return -1; 490 } 491 492 static void wanxl_reset(struct card *card) 493 { 494 u32 old_value = readl(card->plx + PLX_CONTROL) & ~PLX_CTL_RESET; 495 496 writel(0x80, card->plx + PLX_MAILBOX_0); 497 writel(old_value | PLX_CTL_RESET, card->plx + PLX_CONTROL); 498 readl(card->plx + PLX_CONTROL); /* wait for posted write */ 499 udelay(1); 500 writel(old_value, card->plx + PLX_CONTROL); 501 readl(card->plx + PLX_CONTROL); /* wait for posted write */ 502 } 503 504 static void wanxl_pci_remove_one(struct pci_dev *pdev) 505 { 506 struct card *card = pci_get_drvdata(pdev); 507 int i; 508 509 for (i = 0; i < card->n_ports; i++) { 510 unregister_hdlc_device(card->ports[i].dev); 511 free_netdev(card->ports[i].dev); 512 } 513 514 /* unregister and free all host resources */ 515 if (card->irq) 516 free_irq(card->irq, card); 517 518 wanxl_reset(card); 519 520 for (i = 0; i < RX_QUEUE_LENGTH; i++) 521 if (card->rx_skbs[i]) { 522 dma_unmap_single(&card->pdev->dev, 523 card->status->rx_descs[i].address, 524 BUFFER_LENGTH, DMA_FROM_DEVICE); 525 dev_kfree_skb(card->rx_skbs[i]); 526 } 527 528 if (card->plx) 529 iounmap(card->plx); 530 531 if (card->status) 532 dma_free_coherent(&pdev->dev, sizeof(struct card_status), 533 card->status, card->status_address); 534 535 pci_release_regions(pdev); 536 pci_disable_device(pdev); 537 kfree(card); 538 } 539 540 #include "wanxlfw.inc" 541 542 static const struct net_device_ops wanxl_ops = { 543 .ndo_open = wanxl_open, 544 .ndo_stop = wanxl_close, 545 .ndo_start_xmit = hdlc_start_xmit, 546 .ndo_do_ioctl = wanxl_ioctl, 547 .ndo_get_stats = wanxl_get_stats, 548 }; 549 550 static int wanxl_pci_init_one(struct pci_dev *pdev, 551 const struct pci_device_id *ent) 552 { 553 struct card *card; 554 u32 ramsize, stat; 555 unsigned long timeout; 556 u32 plx_phy; /* PLX PCI base address */ 557 u32 mem_phy; /* memory PCI base addr */ 558 u8 __iomem *mem; /* memory virtual base addr */ 559 int i, ports; 560 561 #ifndef MODULE 562 pr_info_once("%s\n", version); 563 #endif 564 565 i = pci_enable_device(pdev); 566 if (i) 567 return i; 568 569 /* QUICC can only access first 256 MB of host RAM directly, 570 but PLX9060 DMA does 32-bits for actual packet data transfers */ 571 572 /* FIXME when PCI/DMA subsystems are fixed. 573 We set both dma_mask and consistent_dma_mask to 28 bits 574 and pray pci_alloc_consistent() will use this info. It should 575 work on most platforms */ 576 if (dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(28)) || 577 dma_set_mask(&pdev->dev, DMA_BIT_MASK(28))) { 578 pr_err("No usable DMA configuration\n"); 579 pci_disable_device(pdev); 580 return -EIO; 581 } 582 583 i = pci_request_regions(pdev, "wanXL"); 584 if (i) { 585 pci_disable_device(pdev); 586 return i; 587 } 588 589 switch (pdev->device) { 590 case PCI_DEVICE_ID_SBE_WANXL100: 591 ports = 1; 592 break; 593 case PCI_DEVICE_ID_SBE_WANXL200: 594 ports = 2; 595 break; 596 default: 597 ports = 4; 598 } 599 600 card = kzalloc(struct_size(card, ports, ports), GFP_KERNEL); 601 if (card == NULL) { 602 pci_release_regions(pdev); 603 pci_disable_device(pdev); 604 return -ENOBUFS; 605 } 606 607 pci_set_drvdata(pdev, card); 608 card->pdev = pdev; 609 610 card->status = dma_alloc_coherent(&pdev->dev, 611 sizeof(struct card_status), 612 &card->status_address, GFP_KERNEL); 613 if (card->status == NULL) { 614 wanxl_pci_remove_one(pdev); 615 return -ENOBUFS; 616 } 617 618 #ifdef DEBUG_PCI 619 printk(KERN_DEBUG "wanXL %s: pci_alloc_consistent() returned memory" 620 " at 0x%LX\n", pci_name(pdev), 621 (unsigned long long)card->status_address); 622 #endif 623 624 /* FIXME when PCI/DMA subsystems are fixed. 625 We set both dma_mask and consistent_dma_mask back to 32 bits 626 to indicate the card can do 32-bit DMA addressing */ 627 if (dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)) || 628 dma_set_mask(&pdev->dev, DMA_BIT_MASK(32))) { 629 pr_err("No usable DMA configuration\n"); 630 wanxl_pci_remove_one(pdev); 631 return -EIO; 632 } 633 634 /* set up PLX mapping */ 635 plx_phy = pci_resource_start(pdev, 0); 636 637 card->plx = ioremap(plx_phy, 0x70); 638 if (!card->plx) { 639 pr_err("ioremap() failed\n"); 640 wanxl_pci_remove_one(pdev); 641 return -EFAULT; 642 } 643 644 #if RESET_WHILE_LOADING 645 wanxl_reset(card); 646 #endif 647 648 timeout = jiffies + 20 * HZ; 649 while ((stat = readl(card->plx + PLX_MAILBOX_0)) != 0) { 650 if (time_before(timeout, jiffies)) { 651 pr_warn("%s: timeout waiting for PUTS to complete\n", 652 pci_name(pdev)); 653 wanxl_pci_remove_one(pdev); 654 return -ENODEV; 655 } 656 657 switch (stat & 0xC0) { 658 case 0x00: /* hmm - PUTS completed with non-zero code? */ 659 case 0x80: /* PUTS still testing the hardware */ 660 break; 661 662 default: 663 pr_warn("%s: PUTS test 0x%X failed\n", 664 pci_name(pdev), stat & 0x30); 665 wanxl_pci_remove_one(pdev); 666 return -ENODEV; 667 } 668 669 schedule(); 670 } 671 672 /* get on-board memory size (PUTS detects no more than 4 MB) */ 673 ramsize = readl(card->plx + PLX_MAILBOX_2) & MBX2_MEMSZ_MASK; 674 675 /* set up on-board RAM mapping */ 676 mem_phy = pci_resource_start(pdev, 2); 677 678 /* sanity check the board's reported memory size */ 679 if (ramsize < BUFFERS_ADDR + 680 (TX_BUFFERS + RX_BUFFERS) * BUFFER_LENGTH * ports) { 681 pr_warn("%s: no enough on-board RAM (%u bytes detected, %u bytes required)\n", 682 pci_name(pdev), ramsize, 683 BUFFERS_ADDR + 684 (TX_BUFFERS + RX_BUFFERS) * BUFFER_LENGTH * ports); 685 wanxl_pci_remove_one(pdev); 686 return -ENODEV; 687 } 688 689 if (wanxl_puts_command(card, MBX1_CMD_BSWAP)) { 690 pr_warn("%s: unable to Set Byte Swap Mode\n", pci_name(pdev)); 691 wanxl_pci_remove_one(pdev); 692 return -ENODEV; 693 } 694 695 for (i = 0; i < RX_QUEUE_LENGTH; i++) { 696 struct sk_buff *skb = dev_alloc_skb(BUFFER_LENGTH); 697 698 card->rx_skbs[i] = skb; 699 if (skb) 700 card->status->rx_descs[i].address = 701 dma_map_single(&card->pdev->dev, skb->data, 702 BUFFER_LENGTH, DMA_FROM_DEVICE); 703 } 704 705 mem = ioremap(mem_phy, PDM_OFFSET + sizeof(firmware)); 706 if (!mem) { 707 pr_err("ioremap() failed\n"); 708 wanxl_pci_remove_one(pdev); 709 return -EFAULT; 710 } 711 712 for (i = 0; i < sizeof(firmware); i += 4) 713 writel(ntohl(*(__be32 *)(firmware + i)), mem + PDM_OFFSET + i); 714 715 for (i = 0; i < ports; i++) 716 writel(card->status_address + 717 (void *)&card->status->port_status[i] - 718 (void *)card->status, mem + PDM_OFFSET + 4 + i * 4); 719 writel(card->status_address, mem + PDM_OFFSET + 20); 720 writel(PDM_OFFSET, mem); 721 iounmap(mem); 722 723 writel(0, card->plx + PLX_MAILBOX_5); 724 725 if (wanxl_puts_command(card, MBX1_CMD_ABORTJ)) { 726 pr_warn("%s: unable to Abort and Jump\n", pci_name(pdev)); 727 wanxl_pci_remove_one(pdev); 728 return -ENODEV; 729 } 730 731 timeout = jiffies + 5 * HZ; 732 do { 733 if ((stat = readl(card->plx + PLX_MAILBOX_5)) != 0) 734 break; 735 schedule(); 736 } while (time_after(timeout, jiffies)); 737 738 if (!stat) { 739 pr_warn("%s: timeout while initializing card firmware\n", 740 pci_name(pdev)); 741 wanxl_pci_remove_one(pdev); 742 return -ENODEV; 743 } 744 745 #if DETECT_RAM 746 ramsize = stat; 747 #endif 748 749 pr_info("%s: at 0x%X, %u KB of RAM at 0x%X, irq %u\n", 750 pci_name(pdev), plx_phy, ramsize / 1024, mem_phy, pdev->irq); 751 752 /* Allocate IRQ */ 753 if (request_irq(pdev->irq, wanxl_intr, IRQF_SHARED, "wanXL", card)) { 754 pr_warn("%s: could not allocate IRQ%i\n", 755 pci_name(pdev), pdev->irq); 756 wanxl_pci_remove_one(pdev); 757 return -EBUSY; 758 } 759 card->irq = pdev->irq; 760 761 for (i = 0; i < ports; i++) { 762 hdlc_device *hdlc; 763 struct port *port = &card->ports[i]; 764 struct net_device *dev = alloc_hdlcdev(port); 765 766 if (!dev) { 767 pr_err("%s: unable to allocate memory\n", 768 pci_name(pdev)); 769 wanxl_pci_remove_one(pdev); 770 return -ENOMEM; 771 } 772 773 port->dev = dev; 774 hdlc = dev_to_hdlc(dev); 775 spin_lock_init(&port->lock); 776 dev->tx_queue_len = 50; 777 dev->netdev_ops = &wanxl_ops; 778 hdlc->attach = wanxl_attach; 779 hdlc->xmit = wanxl_xmit; 780 port->card = card; 781 port->node = i; 782 get_status(port)->clocking = CLOCK_EXT; 783 if (register_hdlc_device(dev)) { 784 pr_err("%s: unable to register hdlc device\n", 785 pci_name(pdev)); 786 free_netdev(dev); 787 wanxl_pci_remove_one(pdev); 788 return -ENOBUFS; 789 } 790 card->n_ports++; 791 } 792 793 pr_info("%s: port", pci_name(pdev)); 794 for (i = 0; i < ports; i++) 795 pr_cont("%s #%i: %s", 796 i ? "," : "", i, card->ports[i].dev->name); 797 pr_cont("\n"); 798 799 for (i = 0; i < ports; i++) 800 wanxl_cable_intr(&card->ports[i]); /* get carrier status etc.*/ 801 802 return 0; 803 } 804 805 static const struct pci_device_id wanxl_pci_tbl[] = { 806 { PCI_VENDOR_ID_SBE, PCI_DEVICE_ID_SBE_WANXL100, PCI_ANY_ID, 807 PCI_ANY_ID, 0, 0, 0 }, 808 { PCI_VENDOR_ID_SBE, PCI_DEVICE_ID_SBE_WANXL200, PCI_ANY_ID, 809 PCI_ANY_ID, 0, 0, 0 }, 810 { PCI_VENDOR_ID_SBE, PCI_DEVICE_ID_SBE_WANXL400, PCI_ANY_ID, 811 PCI_ANY_ID, 0, 0, 0 }, 812 { 0, } 813 }; 814 815 static struct pci_driver wanxl_pci_driver = { 816 .name = "wanXL", 817 .id_table = wanxl_pci_tbl, 818 .probe = wanxl_pci_init_one, 819 .remove = wanxl_pci_remove_one, 820 }; 821 822 static int __init wanxl_init_module(void) 823 { 824 #ifdef MODULE 825 pr_info("%s\n", version); 826 #endif 827 return pci_register_driver(&wanxl_pci_driver); 828 } 829 830 static void __exit wanxl_cleanup_module(void) 831 { 832 pci_unregister_driver(&wanxl_pci_driver); 833 } 834 835 MODULE_AUTHOR("Krzysztof Halasa <khc@pm.waw.pl>"); 836 MODULE_DESCRIPTION("SBE Inc. wanXL serial port driver"); 837 MODULE_LICENSE("GPL v2"); 838 MODULE_DEVICE_TABLE(pci, wanxl_pci_tbl); 839 840 module_init(wanxl_init_module); 841 module_exit(wanxl_cleanup_module); 842