12874c5fdSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later 2c37d4a00SZhao Qiang /* 3c37d4a00SZhao Qiang * drivers/net/wan/slic_ds26522.c 4c37d4a00SZhao Qiang * 5c37d4a00SZhao Qiang * Copyright (C) 2016 Freescale Semiconductor, Inc. 6c37d4a00SZhao Qiang * 7c37d4a00SZhao Qiang * Author:Zhao Qiang<qiang.zhao@nxp.com> 8c37d4a00SZhao Qiang */ 9c37d4a00SZhao Qiang 10c37d4a00SZhao Qiang #include <linux/bitrev.h> 11c37d4a00SZhao Qiang #include <linux/module.h> 12c37d4a00SZhao Qiang #include <linux/device.h> 13c37d4a00SZhao Qiang #include <linux/kernel.h> 14c37d4a00SZhao Qiang #include <linux/sched.h> 15c37d4a00SZhao Qiang #include <linux/kthread.h> 16c37d4a00SZhao Qiang #include <linux/spi/spi.h> 17c37d4a00SZhao Qiang #include <linux/wait.h> 18c37d4a00SZhao Qiang #include <linux/param.h> 19c37d4a00SZhao Qiang #include <linux/delay.h> 20c37d4a00SZhao Qiang #include <linux/of.h> 21c37d4a00SZhao Qiang #include <linux/of_address.h> 22c37d4a00SZhao Qiang #include <linux/io.h> 23c37d4a00SZhao Qiang #include "slic_ds26522.h" 24c37d4a00SZhao Qiang 25c37d4a00SZhao Qiang #define SLIC_TRANS_LEN 1 26c37d4a00SZhao Qiang #define SLIC_TWO_LEN 2 27c37d4a00SZhao Qiang #define SLIC_THREE_LEN 3 28c37d4a00SZhao Qiang 29c37d4a00SZhao Qiang static struct spi_device *g_spi; 30c37d4a00SZhao Qiang 31c37d4a00SZhao Qiang MODULE_LICENSE("GPL"); 32c37d4a00SZhao Qiang MODULE_AUTHOR("Zhao Qiang<B45475@freescale.com>"); 33c37d4a00SZhao Qiang 34c37d4a00SZhao Qiang /* the read/write format of address is 35c37d4a00SZhao Qiang * w/r|A13|A12|A11|A10|A9|A8|A7|A6|A5|A4|A3|A2|A1|A0|x 36c37d4a00SZhao Qiang */ 37c37d4a00SZhao Qiang static void slic_write(struct spi_device *spi, u16 addr, 38c37d4a00SZhao Qiang u8 data) 39c37d4a00SZhao Qiang { 40c37d4a00SZhao Qiang u8 temp[3]; 41c37d4a00SZhao Qiang 42c37d4a00SZhao Qiang addr = bitrev16(addr) >> 1; 43c37d4a00SZhao Qiang data = bitrev8(data); 44c37d4a00SZhao Qiang temp[0] = (u8)((addr >> 8) & 0x7f); 45c37d4a00SZhao Qiang temp[1] = (u8)(addr & 0xfe); 46c37d4a00SZhao Qiang temp[2] = data; 47c37d4a00SZhao Qiang 48c37d4a00SZhao Qiang /* write spi addr and value */ 49c37d4a00SZhao Qiang spi_write(spi, &temp[0], SLIC_THREE_LEN); 50c37d4a00SZhao Qiang } 51c37d4a00SZhao Qiang 52c37d4a00SZhao Qiang static u8 slic_read(struct spi_device *spi, u16 addr) 53c37d4a00SZhao Qiang { 54c37d4a00SZhao Qiang u8 temp[2]; 55c37d4a00SZhao Qiang u8 data; 56c37d4a00SZhao Qiang 57c37d4a00SZhao Qiang addr = bitrev16(addr) >> 1; 58c37d4a00SZhao Qiang temp[0] = (u8)(((addr >> 8) & 0x7f) | 0x80); 59c37d4a00SZhao Qiang temp[1] = (u8)(addr & 0xfe); 60c37d4a00SZhao Qiang 61c37d4a00SZhao Qiang spi_write_then_read(spi, &temp[0], SLIC_TWO_LEN, &data, 62c37d4a00SZhao Qiang SLIC_TRANS_LEN); 63c37d4a00SZhao Qiang 64c37d4a00SZhao Qiang data = bitrev8(data); 65c37d4a00SZhao Qiang return data; 66c37d4a00SZhao Qiang } 67c37d4a00SZhao Qiang 68c37d4a00SZhao Qiang static bool get_slic_product_code(struct spi_device *spi) 69c37d4a00SZhao Qiang { 70c37d4a00SZhao Qiang u8 device_id; 71c37d4a00SZhao Qiang 72c37d4a00SZhao Qiang device_id = slic_read(spi, DS26522_IDR_ADDR); 73c37d4a00SZhao Qiang if ((device_id & 0xf8) == 0x68) 74c37d4a00SZhao Qiang return true; 75c37d4a00SZhao Qiang else 76c37d4a00SZhao Qiang return false; 77c37d4a00SZhao Qiang } 78c37d4a00SZhao Qiang 79c37d4a00SZhao Qiang static void ds26522_e1_spec_config(struct spi_device *spi) 80c37d4a00SZhao Qiang { 81c37d4a00SZhao Qiang /* Receive E1 Mode, Framer Disabled */ 82c37d4a00SZhao Qiang slic_write(spi, DS26522_RMMR_ADDR, DS26522_RMMR_E1); 83c37d4a00SZhao Qiang 84c37d4a00SZhao Qiang /* Transmit E1 Mode, Framer Disable */ 85c37d4a00SZhao Qiang slic_write(spi, DS26522_TMMR_ADDR, DS26522_TMMR_E1); 86c37d4a00SZhao Qiang 87c37d4a00SZhao Qiang /* Receive E1 Mode Framer Enable */ 88c37d4a00SZhao Qiang slic_write(spi, DS26522_RMMR_ADDR, 89c37d4a00SZhao Qiang slic_read(spi, DS26522_RMMR_ADDR) | DS26522_RMMR_FRM_EN); 90c37d4a00SZhao Qiang 91c37d4a00SZhao Qiang /* Transmit E1 Mode Framer Enable */ 92c37d4a00SZhao Qiang slic_write(spi, DS26522_TMMR_ADDR, 93c37d4a00SZhao Qiang slic_read(spi, DS26522_TMMR_ADDR) | DS26522_TMMR_FRM_EN); 94c37d4a00SZhao Qiang 95c37d4a00SZhao Qiang /* RCR1, receive E1 B8zs & ESF */ 96c37d4a00SZhao Qiang slic_write(spi, DS26522_RCR1_ADDR, 97c37d4a00SZhao Qiang DS26522_RCR1_E1_HDB3 | DS26522_RCR1_E1_CCS); 98c37d4a00SZhao Qiang 99c37d4a00SZhao Qiang /* RSYSCLK=2.048MHz, RSYNC-Output */ 100c37d4a00SZhao Qiang slic_write(spi, DS26522_RIOCR_ADDR, 101c37d4a00SZhao Qiang DS26522_RIOCR_2048KHZ | DS26522_RIOCR_RSIO_OUT); 102c37d4a00SZhao Qiang 103c37d4a00SZhao Qiang /* TCR1 Transmit E1 b8zs */ 104c37d4a00SZhao Qiang slic_write(spi, DS26522_TCR1_ADDR, DS26522_TCR1_TB8ZS); 105c37d4a00SZhao Qiang 106c37d4a00SZhao Qiang /* TSYSCLK=2.048MHz, TSYNC-Output */ 107c37d4a00SZhao Qiang slic_write(spi, DS26522_TIOCR_ADDR, 108c37d4a00SZhao Qiang DS26522_TIOCR_2048KHZ | DS26522_TIOCR_TSIO_OUT); 109c37d4a00SZhao Qiang 110c37d4a00SZhao Qiang /* Set E1TAF */ 111c37d4a00SZhao Qiang slic_write(spi, DS26522_E1TAF_ADDR, DS26522_E1TAF_DEFAULT); 112c37d4a00SZhao Qiang 113c37d4a00SZhao Qiang /* Set E1TNAF register */ 114c37d4a00SZhao Qiang slic_write(spi, DS26522_E1TNAF_ADDR, DS26522_E1TNAF_DEFAULT); 115c37d4a00SZhao Qiang 116c37d4a00SZhao Qiang /* Receive E1 Mode Framer Enable & init Done */ 117c37d4a00SZhao Qiang slic_write(spi, DS26522_RMMR_ADDR, slic_read(spi, DS26522_RMMR_ADDR) | 118c37d4a00SZhao Qiang DS26522_RMMR_INIT_DONE); 119c37d4a00SZhao Qiang 120c37d4a00SZhao Qiang /* Transmit E1 Mode Framer Enable & init Done */ 121c37d4a00SZhao Qiang slic_write(spi, DS26522_TMMR_ADDR, slic_read(spi, DS26522_TMMR_ADDR) | 122c37d4a00SZhao Qiang DS26522_TMMR_INIT_DONE); 123c37d4a00SZhao Qiang 124c37d4a00SZhao Qiang /* Configure LIU E1 mode */ 125c37d4a00SZhao Qiang slic_write(spi, DS26522_LTRCR_ADDR, DS26522_LTRCR_E1); 126c37d4a00SZhao Qiang 127c37d4a00SZhao Qiang /* E1 Mode default 75 ohm w/Transmit Impedance Matlinking */ 128c37d4a00SZhao Qiang slic_write(spi, DS26522_LTITSR_ADDR, 129c37d4a00SZhao Qiang DS26522_LTITSR_TLIS_75OHM | DS26522_LTITSR_LBOS_75OHM); 130c37d4a00SZhao Qiang 131c37d4a00SZhao Qiang /* E1 Mode default 75 ohm Long Haul w/Receive Impedance Matlinking */ 132c37d4a00SZhao Qiang slic_write(spi, DS26522_LRISMR_ADDR, 133c37d4a00SZhao Qiang DS26522_LRISMR_75OHM | DS26522_LRISMR_MAX); 134c37d4a00SZhao Qiang 135c37d4a00SZhao Qiang /* Enable Transmit output */ 136c37d4a00SZhao Qiang slic_write(spi, DS26522_LMCR_ADDR, DS26522_LMCR_TE); 137c37d4a00SZhao Qiang } 138c37d4a00SZhao Qiang 139c37d4a00SZhao Qiang static int slic_ds26522_init_configure(struct spi_device *spi) 140c37d4a00SZhao Qiang { 141c37d4a00SZhao Qiang u16 addr; 142c37d4a00SZhao Qiang 143c37d4a00SZhao Qiang /* set clock */ 144c37d4a00SZhao Qiang slic_write(spi, DS26522_GTCCR_ADDR, DS26522_GTCCR_BPREFSEL_REFCLKIN | 145c37d4a00SZhao Qiang DS26522_GTCCR_BFREQSEL_2048KHZ | 146c37d4a00SZhao Qiang DS26522_GTCCR_FREQSEL_2048KHZ); 147c37d4a00SZhao Qiang slic_write(spi, DS26522_GTCR2_ADDR, DS26522_GTCR2_TSSYNCOUT); 148c37d4a00SZhao Qiang slic_write(spi, DS26522_GFCR_ADDR, DS26522_GFCR_BPCLK_2048KHZ); 149c37d4a00SZhao Qiang 150c37d4a00SZhao Qiang /* set gtcr */ 151c37d4a00SZhao Qiang slic_write(spi, DS26522_GTCR1_ADDR, DS26522_GTCR1); 152c37d4a00SZhao Qiang 153c37d4a00SZhao Qiang /* Global LIU Software Reset Register */ 154c37d4a00SZhao Qiang slic_write(spi, DS26522_GLSRR_ADDR, DS26522_GLSRR_RESET); 155c37d4a00SZhao Qiang 156c37d4a00SZhao Qiang /* Global Framer and BERT Software Reset Register */ 157c37d4a00SZhao Qiang slic_write(spi, DS26522_GFSRR_ADDR, DS26522_GFSRR_RESET); 158c37d4a00SZhao Qiang 159c37d4a00SZhao Qiang usleep_range(100, 120); 160c37d4a00SZhao Qiang 161c37d4a00SZhao Qiang slic_write(spi, DS26522_GLSRR_ADDR, DS26522_GLSRR_NORMAL); 162c37d4a00SZhao Qiang slic_write(spi, DS26522_GFSRR_ADDR, DS26522_GFSRR_NORMAL); 163c37d4a00SZhao Qiang 164c37d4a00SZhao Qiang /* Perform RX/TX SRESET,Reset receiver */ 165c37d4a00SZhao Qiang slic_write(spi, DS26522_RMMR_ADDR, DS26522_RMMR_SFTRST); 166c37d4a00SZhao Qiang 167c37d4a00SZhao Qiang /* Reset tranceiver */ 168c37d4a00SZhao Qiang slic_write(spi, DS26522_TMMR_ADDR, DS26522_TMMR_SFTRST); 169c37d4a00SZhao Qiang 170c37d4a00SZhao Qiang usleep_range(100, 120); 171c37d4a00SZhao Qiang 172c37d4a00SZhao Qiang /* Zero all Framer Registers */ 173c37d4a00SZhao Qiang for (addr = DS26522_RF_ADDR_START; addr <= DS26522_RF_ADDR_END; 174c37d4a00SZhao Qiang addr++) 175c37d4a00SZhao Qiang slic_write(spi, addr, 0); 176c37d4a00SZhao Qiang 177c37d4a00SZhao Qiang for (addr = DS26522_TF_ADDR_START; addr <= DS26522_TF_ADDR_END; 178c37d4a00SZhao Qiang addr++) 179c37d4a00SZhao Qiang slic_write(spi, addr, 0); 180c37d4a00SZhao Qiang 181c37d4a00SZhao Qiang for (addr = DS26522_LIU_ADDR_START; addr <= DS26522_LIU_ADDR_END; 182c37d4a00SZhao Qiang addr++) 183c37d4a00SZhao Qiang slic_write(spi, addr, 0); 184c37d4a00SZhao Qiang 185c37d4a00SZhao Qiang for (addr = DS26522_BERT_ADDR_START; addr <= DS26522_BERT_ADDR_END; 186c37d4a00SZhao Qiang addr++) 187c37d4a00SZhao Qiang slic_write(spi, addr, 0); 188c37d4a00SZhao Qiang 189c37d4a00SZhao Qiang /* setup ds26522 for E1 specification */ 190c37d4a00SZhao Qiang ds26522_e1_spec_config(spi); 191c37d4a00SZhao Qiang 192c37d4a00SZhao Qiang slic_write(spi, DS26522_GTCR1_ADDR, 0x00); 193c37d4a00SZhao Qiang 194c37d4a00SZhao Qiang return 0; 195c37d4a00SZhao Qiang } 196c37d4a00SZhao Qiang 197*a0386bbaSUwe Kleine-König static void slic_ds26522_remove(struct spi_device *spi) 198c37d4a00SZhao Qiang { 199c37d4a00SZhao Qiang pr_info("DS26522 module uninstalled\n"); 200c37d4a00SZhao Qiang } 201c37d4a00SZhao Qiang 202c37d4a00SZhao Qiang static int slic_ds26522_probe(struct spi_device *spi) 203c37d4a00SZhao Qiang { 204c37d4a00SZhao Qiang int ret = 0; 205c37d4a00SZhao Qiang 206c37d4a00SZhao Qiang g_spi = spi; 207c37d4a00SZhao Qiang spi->bits_per_word = 8; 208c37d4a00SZhao Qiang 209c37d4a00SZhao Qiang if (!get_slic_product_code(spi)) 210c37d4a00SZhao Qiang return ret; 211c37d4a00SZhao Qiang 212c37d4a00SZhao Qiang ret = slic_ds26522_init_configure(spi); 213c37d4a00SZhao Qiang if (ret == 0) 21460133867SColin Ian King pr_info("DS26522 cs%d configured\n", spi->chip_select); 215c37d4a00SZhao Qiang 216c37d4a00SZhao Qiang return ret; 217c37d4a00SZhao Qiang } 218c37d4a00SZhao Qiang 219558c5eb5SJavier Martinez Canillas static const struct spi_device_id slic_ds26522_id[] = { 220558c5eb5SJavier Martinez Canillas { .name = "ds26522" }, 221558c5eb5SJavier Martinez Canillas { /* sentinel */ }, 222558c5eb5SJavier Martinez Canillas }; 223558c5eb5SJavier Martinez Canillas MODULE_DEVICE_TABLE(spi, slic_ds26522_id); 224558c5eb5SJavier Martinez Canillas 225c37d4a00SZhao Qiang static const struct of_device_id slic_ds26522_match[] = { 226c37d4a00SZhao Qiang { 227c37d4a00SZhao Qiang .compatible = "maxim,ds26522", 228c37d4a00SZhao Qiang }, 229c37d4a00SZhao Qiang {}, 230c37d4a00SZhao Qiang }; 231485c9d43SJavier Martinez Canillas MODULE_DEVICE_TABLE(of, slic_ds26522_match); 232c37d4a00SZhao Qiang 233c37d4a00SZhao Qiang static struct spi_driver slic_ds26522_driver = { 234c37d4a00SZhao Qiang .driver = { 235c37d4a00SZhao Qiang .name = "ds26522", 236c37d4a00SZhao Qiang .bus = &spi_bus_type, 237c37d4a00SZhao Qiang .of_match_table = slic_ds26522_match, 238c37d4a00SZhao Qiang }, 239c37d4a00SZhao Qiang .probe = slic_ds26522_probe, 240c37d4a00SZhao Qiang .remove = slic_ds26522_remove, 241558c5eb5SJavier Martinez Canillas .id_table = slic_ds26522_id, 242c37d4a00SZhao Qiang }; 243c37d4a00SZhao Qiang 244c3afa995SWei Yongjun module_spi_driver(slic_ds26522_driver); 245