12874c5fdSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */ 2c19b6d24SZhao Qiang /* Freescale QUICC Engine HDLC Device Driver 3c19b6d24SZhao Qiang * 4c19b6d24SZhao Qiang * Copyright 2014 Freescale Semiconductor Inc. 5c19b6d24SZhao Qiang */ 6c19b6d24SZhao Qiang 7c5739767SAndreas Ziegler #ifndef _UCC_HDLC_H_ 8c5739767SAndreas Ziegler #define _UCC_HDLC_H_ 9c19b6d24SZhao Qiang 10c19b6d24SZhao Qiang #include <linux/kernel.h> 11c19b6d24SZhao Qiang #include <linux/list.h> 12c19b6d24SZhao Qiang 13c19b6d24SZhao Qiang #include <soc/fsl/qe/immap_qe.h> 14c19b6d24SZhao Qiang #include <soc/fsl/qe/qe.h> 15c19b6d24SZhao Qiang 16c19b6d24SZhao Qiang #include <soc/fsl/qe/ucc.h> 17c19b6d24SZhao Qiang #include <soc/fsl/qe/ucc_fast.h> 18c19b6d24SZhao Qiang 19c19b6d24SZhao Qiang /* UCC HDLC event register */ 20c19b6d24SZhao Qiang #define UCCE_HDLC_RX_EVENTS \ 21c19b6d24SZhao Qiang (UCC_HDLC_UCCE_RXF | UCC_HDLC_UCCE_RXB | UCC_HDLC_UCCE_BSY) 22c19b6d24SZhao Qiang #define UCCE_HDLC_TX_EVENTS (UCC_HDLC_UCCE_TXB | UCC_HDLC_UCCE_TXE) 23c19b6d24SZhao Qiang 24c19b6d24SZhao Qiang struct ucc_hdlc_param { 25c19b6d24SZhao Qiang __be16 riptr; 26c19b6d24SZhao Qiang __be16 tiptr; 27c19b6d24SZhao Qiang __be16 res0; 28c19b6d24SZhao Qiang __be16 mrblr; 29c19b6d24SZhao Qiang __be32 rstate; 30c19b6d24SZhao Qiang __be32 rbase; 31c19b6d24SZhao Qiang __be16 rbdstat; 32c19b6d24SZhao Qiang __be16 rbdlen; 33c19b6d24SZhao Qiang __be32 rdptr; 34c19b6d24SZhao Qiang __be32 tstate; 35c19b6d24SZhao Qiang __be32 tbase; 36c19b6d24SZhao Qiang __be16 tbdstat; 37c19b6d24SZhao Qiang __be16 tbdlen; 38c19b6d24SZhao Qiang __be32 tdptr; 39c19b6d24SZhao Qiang __be32 rbptr; 40c19b6d24SZhao Qiang __be32 tbptr; 41c19b6d24SZhao Qiang __be32 rcrc; 42c19b6d24SZhao Qiang __be32 res1; 43c19b6d24SZhao Qiang __be32 tcrc; 44c19b6d24SZhao Qiang __be32 res2; 45c19b6d24SZhao Qiang __be32 res3; 46c19b6d24SZhao Qiang __be32 c_mask; 47c19b6d24SZhao Qiang __be32 c_pres; 48c19b6d24SZhao Qiang __be16 disfc; 49c19b6d24SZhao Qiang __be16 crcec; 50c19b6d24SZhao Qiang __be16 abtsc; 51c19b6d24SZhao Qiang __be16 nmarc; 52c19b6d24SZhao Qiang __be32 max_cnt; 53c19b6d24SZhao Qiang __be16 mflr; 54c19b6d24SZhao Qiang __be16 rfthr; 55c19b6d24SZhao Qiang __be16 rfcnt; 56c19b6d24SZhao Qiang __be16 hmask; 57c19b6d24SZhao Qiang __be16 haddr1; 58c19b6d24SZhao Qiang __be16 haddr2; 59c19b6d24SZhao Qiang __be16 haddr3; 60c19b6d24SZhao Qiang __be16 haddr4; 61c19b6d24SZhao Qiang __be16 ts_tmp; 62c19b6d24SZhao Qiang __be16 tmp_mb; 63c19b6d24SZhao Qiang }; 64c19b6d24SZhao Qiang 65c19b6d24SZhao Qiang struct ucc_hdlc_private { 66c19b6d24SZhao Qiang struct ucc_tdm *utdm; 67c19b6d24SZhao Qiang struct ucc_tdm_info *ut_info; 68c19b6d24SZhao Qiang struct ucc_fast_private *uccf; 69c19b6d24SZhao Qiang struct device *dev; 70c19b6d24SZhao Qiang struct net_device *ndev; 71c19b6d24SZhao Qiang struct napi_struct napi; 72c19b6d24SZhao Qiang struct ucc_fast __iomem *uf_regs; /* UCC Fast registers */ 73c19b6d24SZhao Qiang struct ucc_hdlc_param __iomem *ucc_pram; 74c19b6d24SZhao Qiang u16 tsa; 75c19b6d24SZhao Qiang bool hdlc_busy; 76c19b6d24SZhao Qiang bool loopback; 77067bb938SHolger Brunck bool hdlc_bus; 78c19b6d24SZhao Qiang 79c19b6d24SZhao Qiang u8 *tx_buffer; 80c19b6d24SZhao Qiang u8 *rx_buffer; 81c19b6d24SZhao Qiang dma_addr_t dma_tx_addr; 82c19b6d24SZhao Qiang dma_addr_t dma_rx_addr; 83c19b6d24SZhao Qiang 84c19b6d24SZhao Qiang struct qe_bd *tx_bd_base; 85c19b6d24SZhao Qiang struct qe_bd *rx_bd_base; 86c19b6d24SZhao Qiang dma_addr_t dma_tx_bd; 87c19b6d24SZhao Qiang dma_addr_t dma_rx_bd; 88c19b6d24SZhao Qiang struct qe_bd *curtx_bd; 89c19b6d24SZhao Qiang struct qe_bd *currx_bd; 90c19b6d24SZhao Qiang struct qe_bd *dirty_tx; 91c19b6d24SZhao Qiang u16 currx_bdnum; 92c19b6d24SZhao Qiang 93c19b6d24SZhao Qiang struct sk_buff **tx_skbuff; 94c19b6d24SZhao Qiang struct sk_buff **rx_skbuff; 95c19b6d24SZhao Qiang u16 skb_curtx; 96c19b6d24SZhao Qiang u16 skb_currx; 97c19b6d24SZhao Qiang unsigned short skb_dirtytx; 98c19b6d24SZhao Qiang 99c19b6d24SZhao Qiang unsigned short tx_ring_size; 100c19b6d24SZhao Qiang unsigned short rx_ring_size; 101*be2e9415SRasmus Villemoes s32 ucc_pram_offset; 102c19b6d24SZhao Qiang 103c19b6d24SZhao Qiang unsigned short encoding; 104c19b6d24SZhao Qiang unsigned short parity; 105045f77baSDavid Gounaris unsigned short hmask; 106c19b6d24SZhao Qiang u32 clocking; 107c19b6d24SZhao Qiang spinlock_t lock; /* lock for Tx BD and Tx buffer */ 108c19b6d24SZhao Qiang #ifdef CONFIG_PM 109c19b6d24SZhao Qiang struct ucc_hdlc_param *ucc_pram_bak; 110c19b6d24SZhao Qiang u32 gumr; 111c19b6d24SZhao Qiang u8 guemr; 112c19b6d24SZhao Qiang u32 cmxsi1cr_l, cmxsi1cr_h; 113c19b6d24SZhao Qiang u32 cmxsi1syr; 114c19b6d24SZhao Qiang u32 cmxucr[4]; 115c19b6d24SZhao Qiang #endif 116c19b6d24SZhao Qiang }; 117c19b6d24SZhao Qiang 118c19b6d24SZhao Qiang #define TX_BD_RING_LEN 0x10 119c19b6d24SZhao Qiang #define RX_BD_RING_LEN 0x20 120c19b6d24SZhao Qiang #define RX_CLEAN_MAX 0x10 121c19b6d24SZhao Qiang #define NUM_OF_BUF 4 122c19b6d24SZhao Qiang #define MAX_RX_BUF_LENGTH (48 * 0x20) 123c19b6d24SZhao Qiang #define MAX_FRAME_LENGTH (MAX_RX_BUF_LENGTH + 8) 124c19b6d24SZhao Qiang #define ALIGNMENT_OF_UCC_HDLC_PRAM 64 125c19b6d24SZhao Qiang #define SI_BANK_SIZE 128 126c19b6d24SZhao Qiang #define MAX_HDLC_NUM 4 127c19b6d24SZhao Qiang #define HDLC_HEAD_LEN 2 128c19b6d24SZhao Qiang #define HDLC_CRC_SIZE 2 129c19b6d24SZhao Qiang #define TX_RING_MOD_MASK(size) (size - 1) 130c19b6d24SZhao Qiang #define RX_RING_MOD_MASK(size) (size - 1) 131c19b6d24SZhao Qiang 132c19b6d24SZhao Qiang #define HDLC_HEAD_MASK 0x0000 133c19b6d24SZhao Qiang #define DEFAULT_HDLC_HEAD 0xff44 134c19b6d24SZhao Qiang #define DEFAULT_ADDR_MASK 0x00ff 135c19b6d24SZhao Qiang #define DEFAULT_HDLC_ADDR 0x00ff 136c19b6d24SZhao Qiang 137c19b6d24SZhao Qiang #define BMR_GBL 0x20000000 138c19b6d24SZhao Qiang #define BMR_BIG_ENDIAN 0x10000000 139c19b6d24SZhao Qiang #define CRC_16BIT_MASK 0x0000F0B8 140c19b6d24SZhao Qiang #define CRC_16BIT_PRES 0x0000FFFF 141c19b6d24SZhao Qiang #define DEFAULT_RFTHR 1 142c19b6d24SZhao Qiang 143c19b6d24SZhao Qiang #define DEFAULT_PPP_HEAD 0xff03 144c19b6d24SZhao Qiang 145c19b6d24SZhao Qiang #endif 146