1 /*************************************************************************** 2 * 3 * Copyright (C) 2007-2008 SMSC 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License 7 * as published by the Free Software Foundation; either version 2 8 * of the License, or (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 18 * 19 *****************************************************************************/ 20 21 #ifndef _SMSC95XX_H 22 #define _SMSC95XX_H 23 24 /* Tx command words */ 25 #define TX_CMD_A_DATA_OFFSET_ (0x001F0000) 26 #define TX_CMD_A_FIRST_SEG_ (0x00002000) 27 #define TX_CMD_A_LAST_SEG_ (0x00001000) 28 #define TX_CMD_A_BUF_SIZE_ (0x000007FF) 29 30 #define TX_CMD_B_CSUM_ENABLE (0x00004000) 31 #define TX_CMD_B_ADD_CRC_DISABLE_ (0x00002000) 32 #define TX_CMD_B_DISABLE_PADDING_ (0x00001000) 33 #define TX_CMD_B_PKT_BYTE_LENGTH_ (0x000007FF) 34 35 /* Rx status word */ 36 #define RX_STS_FF_ (0x40000000) /* Filter Fail */ 37 #define RX_STS_FL_ (0x3FFF0000) /* Frame Length */ 38 #define RX_STS_ES_ (0x00008000) /* Error Summary */ 39 #define RX_STS_BF_ (0x00002000) /* Broadcast Frame */ 40 #define RX_STS_LE_ (0x00001000) /* Length Error */ 41 #define RX_STS_RF_ (0x00000800) /* Runt Frame */ 42 #define RX_STS_MF_ (0x00000400) /* Multicast Frame */ 43 #define RX_STS_TL_ (0x00000080) /* Frame too long */ 44 #define RX_STS_CS_ (0x00000040) /* Collision Seen */ 45 #define RX_STS_FT_ (0x00000020) /* Frame Type */ 46 #define RX_STS_RW_ (0x00000010) /* Receive Watchdog */ 47 #define RX_STS_ME_ (0x00000008) /* Mii Error */ 48 #define RX_STS_DB_ (0x00000004) /* Dribbling */ 49 #define RX_STS_CRC_ (0x00000002) /* CRC Error */ 50 51 /* SCSRs */ 52 #define ID_REV (0x00) 53 #define ID_REV_CHIP_ID_MASK_ (0xFFFF0000) 54 #define ID_REV_CHIP_REV_MASK_ (0x0000FFFF) 55 #define ID_REV_CHIP_ID_9500_ (0x9500) 56 57 #define INT_STS (0x08) 58 #define INT_STS_TX_STOP_ (0x00020000) 59 #define INT_STS_RX_STOP_ (0x00010000) 60 #define INT_STS_PHY_INT_ (0x00008000) 61 #define INT_STS_TXE_ (0x00004000) 62 #define INT_STS_TDFU_ (0x00002000) 63 #define INT_STS_TDFO_ (0x00001000) 64 #define INT_STS_RXDF_ (0x00000800) 65 #define INT_STS_GPIOS_ (0x000007FF) 66 #define INT_STS_CLEAR_ALL_ (0xFFFFFFFF) 67 68 #define RX_CFG (0x0C) 69 #define RX_FIFO_FLUSH_ (0x00000001) 70 71 #define TX_CFG (0x10) 72 #define TX_CFG_ON_ (0x00000004) 73 #define TX_CFG_STOP_ (0x00000002) 74 #define TX_CFG_FIFO_FLUSH_ (0x00000001) 75 76 #define HW_CFG (0x14) 77 #define HW_CFG_BIR_ (0x00001000) 78 #define HW_CFG_LEDB_ (0x00000800) 79 #define HW_CFG_RXDOFF_ (0x00000600) 80 #define HW_CFG_DRP_ (0x00000040) 81 #define HW_CFG_MEF_ (0x00000020) 82 #define HW_CFG_LRST_ (0x00000008) 83 #define HW_CFG_PSEL_ (0x00000004) 84 #define HW_CFG_BCE_ (0x00000002) 85 #define HW_CFG_SRST_ (0x00000001) 86 87 #define RX_FIFO_INF (0x18) 88 89 #define PM_CTRL (0x20) 90 #define PM_CTL_RES_CLR_WKP_STS (0x00000200) 91 #define PM_CTL_DEV_RDY_ (0x00000080) 92 #define PM_CTL_SUS_MODE_ (0x00000060) 93 #define PM_CTL_SUS_MODE_0 (0x00000000) 94 #define PM_CTL_SUS_MODE_1 (0x00000020) 95 #define PM_CTL_SUS_MODE_2 (0x00000040) 96 #define PM_CTL_SUS_MODE_3 (0x00000060) 97 #define PM_CTL_PHY_RST_ (0x00000010) 98 #define PM_CTL_WOL_EN_ (0x00000008) 99 #define PM_CTL_ED_EN_ (0x00000004) 100 #define PM_CTL_WUPS_ (0x00000003) 101 #define PM_CTL_WUPS_NO_ (0x00000000) 102 #define PM_CTL_WUPS_ED_ (0x00000001) 103 #define PM_CTL_WUPS_WOL_ (0x00000002) 104 #define PM_CTL_WUPS_MULTI_ (0x00000003) 105 106 #define LED_GPIO_CFG (0x24) 107 #define LED_GPIO_CFG_SPD_LED (0x01000000) 108 #define LED_GPIO_CFG_LNK_LED (0x00100000) 109 #define LED_GPIO_CFG_FDX_LED (0x00010000) 110 111 #define GPIO_CFG (0x28) 112 113 #define AFC_CFG (0x2C) 114 115 /* Hi watermark = 15.5Kb (~10 mtu pkts) */ 116 /* low watermark = 3k (~2 mtu pkts) */ 117 /* backpressure duration = ~ 350us */ 118 /* Apply FC on any frame. */ 119 #define AFC_CFG_DEFAULT (0x00F830A1) 120 121 #define E2P_CMD (0x30) 122 #define E2P_CMD_BUSY_ (0x80000000) 123 #define E2P_CMD_MASK_ (0x70000000) 124 #define E2P_CMD_READ_ (0x00000000) 125 #define E2P_CMD_EWDS_ (0x10000000) 126 #define E2P_CMD_EWEN_ (0x20000000) 127 #define E2P_CMD_WRITE_ (0x30000000) 128 #define E2P_CMD_WRAL_ (0x40000000) 129 #define E2P_CMD_ERASE_ (0x50000000) 130 #define E2P_CMD_ERAL_ (0x60000000) 131 #define E2P_CMD_RELOAD_ (0x70000000) 132 #define E2P_CMD_TIMEOUT_ (0x00000400) 133 #define E2P_CMD_LOADED_ (0x00000200) 134 #define E2P_CMD_ADDR_ (0x000001FF) 135 136 #define MAX_EEPROM_SIZE (512) 137 138 #define E2P_DATA (0x34) 139 #define E2P_DATA_MASK_ (0x000000FF) 140 141 #define BURST_CAP (0x38) 142 143 #define GPIO_WAKE (0x64) 144 145 #define INT_EP_CTL (0x68) 146 #define INT_EP_CTL_INTEP_ (0x80000000) 147 #define INT_EP_CTL_MACRTO_ (0x00080000) 148 #define INT_EP_CTL_TX_STOP_ (0x00020000) 149 #define INT_EP_CTL_RX_STOP_ (0x00010000) 150 #define INT_EP_CTL_PHY_INT_ (0x00008000) 151 #define INT_EP_CTL_TXE_ (0x00004000) 152 #define INT_EP_CTL_TDFU_ (0x00002000) 153 #define INT_EP_CTL_TDFO_ (0x00001000) 154 #define INT_EP_CTL_RXDF_ (0x00000800) 155 #define INT_EP_CTL_GPIOS_ (0x000007FF) 156 157 #define BULK_IN_DLY (0x6C) 158 159 /* MAC CSRs */ 160 #define MAC_CR (0x100) 161 #define MAC_CR_RXALL_ (0x80000000) 162 #define MAC_CR_RCVOWN_ (0x00800000) 163 #define MAC_CR_LOOPBK_ (0x00200000) 164 #define MAC_CR_FDPX_ (0x00100000) 165 #define MAC_CR_MCPAS_ (0x00080000) 166 #define MAC_CR_PRMS_ (0x00040000) 167 #define MAC_CR_INVFILT_ (0x00020000) 168 #define MAC_CR_PASSBAD_ (0x00010000) 169 #define MAC_CR_HFILT_ (0x00008000) 170 #define MAC_CR_HPFILT_ (0x00002000) 171 #define MAC_CR_LCOLL_ (0x00001000) 172 #define MAC_CR_BCAST_ (0x00000800) 173 #define MAC_CR_DISRTY_ (0x00000400) 174 #define MAC_CR_PADSTR_ (0x00000100) 175 #define MAC_CR_BOLMT_MASK (0x000000C0) 176 #define MAC_CR_DFCHK_ (0x00000020) 177 #define MAC_CR_TXEN_ (0x00000008) 178 #define MAC_CR_RXEN_ (0x00000004) 179 180 #define ADDRH (0x104) 181 182 #define ADDRL (0x108) 183 184 #define HASHH (0x10C) 185 186 #define HASHL (0x110) 187 188 #define MII_ADDR (0x114) 189 #define MII_WRITE_ (0x02) 190 #define MII_BUSY_ (0x01) 191 #define MII_READ_ (0x00) /* ~of MII Write bit */ 192 193 #define MII_DATA (0x118) 194 195 #define FLOW (0x11C) 196 #define FLOW_FCPT_ (0xFFFF0000) 197 #define FLOW_FCPASS_ (0x00000004) 198 #define FLOW_FCEN_ (0x00000002) 199 #define FLOW_FCBSY_ (0x00000001) 200 201 #define VLAN1 (0x120) 202 203 #define VLAN2 (0x124) 204 205 #define WUFF (0x128) 206 207 #define WUCSR (0x12C) 208 #define WUCSR_GUE_ (0x00000200) 209 #define WUCSR_WUFR_ (0x00000040) 210 #define WUCSR_MPR_ (0x00000020) 211 #define WUCSR_WAKE_EN_ (0x00000004) 212 #define WUCSR_MPEN_ (0x00000002) 213 214 #define COE_CR (0x130) 215 #define Tx_COE_EN_ (0x00010000) 216 #define Rx_COE_MODE_ (0x00000002) 217 #define Rx_COE_EN_ (0x00000001) 218 219 /* Vendor-specific PHY Definitions */ 220 221 /* Mode Control/Status Register */ 222 #define PHY_MODE_CTRL_STS (17) 223 #define MODE_CTRL_STS_EDPWRDOWN_ ((u16)0x2000) 224 #define MODE_CTRL_STS_ENERGYON_ ((u16)0x0002) 225 226 #define SPECIAL_CTRL_STS (27) 227 #define SPECIAL_CTRL_STS_OVRRD_AMDIX_ ((u16)0x8000) 228 #define SPECIAL_CTRL_STS_AMDIX_ENABLE_ ((u16)0x4000) 229 #define SPECIAL_CTRL_STS_AMDIX_STATE_ ((u16)0x2000) 230 231 #define PHY_INT_SRC (29) 232 #define PHY_INT_SRC_ENERGY_ON_ ((u16)0x0080) 233 #define PHY_INT_SRC_ANEG_COMP_ ((u16)0x0040) 234 #define PHY_INT_SRC_REMOTE_FAULT_ ((u16)0x0020) 235 #define PHY_INT_SRC_LINK_DOWN_ ((u16)0x0010) 236 237 #define PHY_INT_MASK (30) 238 #define PHY_INT_MASK_ENERGY_ON_ ((u16)0x0080) 239 #define PHY_INT_MASK_ANEG_COMP_ ((u16)0x0040) 240 #define PHY_INT_MASK_REMOTE_FAULT_ ((u16)0x0020) 241 #define PHY_INT_MASK_LINK_DOWN_ ((u16)0x0010) 242 #define PHY_INT_MASK_DEFAULT_ (PHY_INT_MASK_ANEG_COMP_ | \ 243 PHY_INT_MASK_LINK_DOWN_) 244 245 #define PHY_SPECIAL (31) 246 #define PHY_SPECIAL_SPD_ ((u16)0x001C) 247 #define PHY_SPECIAL_SPD_10HALF_ ((u16)0x0004) 248 #define PHY_SPECIAL_SPD_10FULL_ ((u16)0x0014) 249 #define PHY_SPECIAL_SPD_100HALF_ ((u16)0x0008) 250 #define PHY_SPECIAL_SPD_100FULL_ ((u16)0x0018) 251 252 /* USB Vendor Requests */ 253 #define USB_VENDOR_REQUEST_WRITE_REGISTER 0xA0 254 #define USB_VENDOR_REQUEST_READ_REGISTER 0xA1 255 #define USB_VENDOR_REQUEST_GET_STATS 0xA2 256 257 /* Interrupt Endpoint status word bitfields */ 258 #define INT_ENP_TX_STOP_ ((u32)BIT(17)) 259 #define INT_ENP_RX_STOP_ ((u32)BIT(16)) 260 #define INT_ENP_PHY_INT_ ((u32)BIT(15)) 261 #define INT_ENP_TXE_ ((u32)BIT(14)) 262 #define INT_ENP_TDFU_ ((u32)BIT(13)) 263 #define INT_ENP_TDFO_ ((u32)BIT(12)) 264 #define INT_ENP_RXDF_ ((u32)BIT(11)) 265 266 #endif /* _SMSC95XX_H */ 267