1a2443fd1SAndrew Lunn // SPDX-License-Identifier: GPL-2.0+ 24621bf12SDavid S. Miller /* 34621bf12SDavid S. Miller * drivers/net/phy/national.c 44621bf12SDavid S. Miller * 54621bf12SDavid S. Miller * Driver for National Semiconductor PHYs 64621bf12SDavid S. Miller * 74621bf12SDavid S. Miller * Author: Stuart Menefy <stuart.menefy@st.com> 84621bf12SDavid S. Miller * Maintainer: Giuseppe Cavallaro <peppe.cavallaro@st.com> 94621bf12SDavid S. Miller * 104621bf12SDavid S. Miller * Copyright (c) 2008 STMicroelectronics Limited 114621bf12SDavid S. Miller */ 124621bf12SDavid S. Miller 138d242488SJoe Perches #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 148d242488SJoe Perches 154621bf12SDavid S. Miller #include <linux/kernel.h> 164621bf12SDavid S. Miller #include <linux/module.h> 174621bf12SDavid S. Miller #include <linux/mii.h> 184621bf12SDavid S. Miller #include <linux/ethtool.h> 194621bf12SDavid S. Miller #include <linux/phy.h> 204621bf12SDavid S. Miller #include <linux/netdevice.h> 214621bf12SDavid S. Miller 228d242488SJoe Perches #define DEBUG 238d242488SJoe Perches 244621bf12SDavid S. Miller /* DP83865 phy identifier values */ 254621bf12SDavid S. Miller #define DP83865_PHY_ID 0x20005c7a 264621bf12SDavid S. Miller 276e6f400fSGiuseppe CAVALLARO #define DP83865_INT_STATUS 0x14 286e6f400fSGiuseppe CAVALLARO #define DP83865_INT_MASK 0x15 296e6f400fSGiuseppe CAVALLARO #define DP83865_INT_CLEAR 0x17 304621bf12SDavid S. Miller 314621bf12SDavid S. Miller #define DP83865_INT_REMOTE_FAULT 0x0008 324621bf12SDavid S. Miller #define DP83865_INT_ANE_COMPLETED 0x0010 334621bf12SDavid S. Miller #define DP83865_INT_LINK_CHANGE 0xe000 344621bf12SDavid S. Miller #define DP83865_INT_MASK_DEFAULT (DP83865_INT_REMOTE_FAULT | \ 354621bf12SDavid S. Miller DP83865_INT_ANE_COMPLETED | \ 364621bf12SDavid S. Miller DP83865_INT_LINK_CHANGE) 374621bf12SDavid S. Miller 384621bf12SDavid S. Miller /* Advanced proprietary configuration */ 394621bf12SDavid S. Miller #define NS_EXP_MEM_CTL 0x16 404621bf12SDavid S. Miller #define NS_EXP_MEM_DATA 0x1d 414621bf12SDavid S. Miller #define NS_EXP_MEM_ADD 0x1e 424621bf12SDavid S. Miller 434621bf12SDavid S. Miller #define LED_CTRL_REG 0x13 444621bf12SDavid S. Miller #define AN_FALLBACK_AN 0x0001 454621bf12SDavid S. Miller #define AN_FALLBACK_CRC 0x0002 464621bf12SDavid S. Miller #define AN_FALLBACK_IE 0x0004 474621bf12SDavid S. Miller #define ALL_FALLBACK_ON (AN_FALLBACK_AN | AN_FALLBACK_CRC | AN_FALLBACK_IE) 484621bf12SDavid S. Miller 494621bf12SDavid S. Miller enum hdx_loopback { 504621bf12SDavid S. Miller hdx_loopback_on = 0, 514621bf12SDavid S. Miller hdx_loopback_off = 1, 524621bf12SDavid S. Miller }; 534621bf12SDavid S. Miller 544621bf12SDavid S. Miller static u8 ns_exp_read(struct phy_device *phydev, u16 reg) 554621bf12SDavid S. Miller { 564621bf12SDavid S. Miller phy_write(phydev, NS_EXP_MEM_ADD, reg); 574621bf12SDavid S. Miller return phy_read(phydev, NS_EXP_MEM_DATA); 584621bf12SDavid S. Miller } 594621bf12SDavid S. Miller 604621bf12SDavid S. Miller static void ns_exp_write(struct phy_device *phydev, u16 reg, u8 data) 614621bf12SDavid S. Miller { 624621bf12SDavid S. Miller phy_write(phydev, NS_EXP_MEM_ADD, reg); 634621bf12SDavid S. Miller phy_write(phydev, NS_EXP_MEM_DATA, data); 644621bf12SDavid S. Miller } 654621bf12SDavid S. Miller 664621bf12SDavid S. Miller static int ns_config_intr(struct phy_device *phydev) 674621bf12SDavid S. Miller { 684621bf12SDavid S. Miller int err; 694621bf12SDavid S. Miller 704621bf12SDavid S. Miller if (phydev->interrupts == PHY_INTERRUPT_ENABLED) 716e6f400fSGiuseppe CAVALLARO err = phy_write(phydev, DP83865_INT_MASK, 724621bf12SDavid S. Miller DP83865_INT_MASK_DEFAULT); 734621bf12SDavid S. Miller else 746e6f400fSGiuseppe CAVALLARO err = phy_write(phydev, DP83865_INT_MASK, 0); 754621bf12SDavid S. Miller 764621bf12SDavid S. Miller return err; 774621bf12SDavid S. Miller } 784621bf12SDavid S. Miller 794621bf12SDavid S. Miller static int ns_ack_interrupt(struct phy_device *phydev) 804621bf12SDavid S. Miller { 816e6f400fSGiuseppe CAVALLARO int ret = phy_read(phydev, DP83865_INT_STATUS); 824621bf12SDavid S. Miller if (ret < 0) 834621bf12SDavid S. Miller return ret; 844621bf12SDavid S. Miller 856e6f400fSGiuseppe CAVALLARO /* Clear the interrupt status bit by writing a “1” 866e6f400fSGiuseppe CAVALLARO * to the corresponding bit in INT_CLEAR (2:0 are reserved) */ 876e6f400fSGiuseppe CAVALLARO ret = phy_write(phydev, DP83865_INT_CLEAR, ret & ~0x7); 886e6f400fSGiuseppe CAVALLARO 896e6f400fSGiuseppe CAVALLARO return ret; 904621bf12SDavid S. Miller } 914621bf12SDavid S. Miller 92*6571b455SIoana Ciornei static irqreturn_t ns_handle_interrupt(struct phy_device *phydev) 93*6571b455SIoana Ciornei { 94*6571b455SIoana Ciornei int irq_status; 95*6571b455SIoana Ciornei 96*6571b455SIoana Ciornei irq_status = phy_read(phydev, DP83865_INT_STATUS); 97*6571b455SIoana Ciornei if (irq_status < 0) { 98*6571b455SIoana Ciornei phy_error(phydev); 99*6571b455SIoana Ciornei return IRQ_NONE; 100*6571b455SIoana Ciornei } 101*6571b455SIoana Ciornei 102*6571b455SIoana Ciornei if (!(irq_status & DP83865_INT_MASK_DEFAULT)) 103*6571b455SIoana Ciornei return IRQ_NONE; 104*6571b455SIoana Ciornei 105*6571b455SIoana Ciornei /* clear the interrupt */ 106*6571b455SIoana Ciornei phy_write(phydev, DP83865_INT_CLEAR, irq_status & ~0x7); 107*6571b455SIoana Ciornei 108*6571b455SIoana Ciornei phy_trigger_machine(phydev); 109*6571b455SIoana Ciornei 110*6571b455SIoana Ciornei return IRQ_HANDLED; 111*6571b455SIoana Ciornei } 112*6571b455SIoana Ciornei 1134621bf12SDavid S. Miller static void ns_giga_speed_fallback(struct phy_device *phydev, int mode) 1144621bf12SDavid S. Miller { 1154621bf12SDavid S. Miller int bmcr = phy_read(phydev, MII_BMCR); 1164621bf12SDavid S. Miller 1174621bf12SDavid S. Miller phy_write(phydev, MII_BMCR, (bmcr | BMCR_PDOWN)); 1184621bf12SDavid S. Miller 1194621bf12SDavid S. Miller /* Enable 8 bit expended memory read/write (no auto increment) */ 1204621bf12SDavid S. Miller phy_write(phydev, NS_EXP_MEM_CTL, 0); 1214621bf12SDavid S. Miller phy_write(phydev, NS_EXP_MEM_ADD, 0x1C0); 1224621bf12SDavid S. Miller phy_write(phydev, NS_EXP_MEM_DATA, 0x0008); 1234621bf12SDavid S. Miller phy_write(phydev, MII_BMCR, (bmcr & ~BMCR_PDOWN)); 1244621bf12SDavid S. Miller phy_write(phydev, LED_CTRL_REG, mode); 1254621bf12SDavid S. Miller } 1264621bf12SDavid S. Miller 1274621bf12SDavid S. Miller static void ns_10_base_t_hdx_loopack(struct phy_device *phydev, int disable) 1284621bf12SDavid S. Miller { 129e47488b2SPeter Mamonov u16 lb_dis = BIT(1); 130e47488b2SPeter Mamonov 1314621bf12SDavid S. Miller if (disable) 132e47488b2SPeter Mamonov ns_exp_write(phydev, 0x1c0, 133e47488b2SPeter Mamonov ns_exp_read(phydev, 0x1c0) | lb_dis); 1344621bf12SDavid S. Miller else 1354621bf12SDavid S. Miller ns_exp_write(phydev, 0x1c0, 136e47488b2SPeter Mamonov ns_exp_read(phydev, 0x1c0) & ~lb_dis); 1374621bf12SDavid S. Miller 1388d242488SJoe Perches pr_debug("10BASE-T HDX loopback %s\n", 139e47488b2SPeter Mamonov (ns_exp_read(phydev, 0x1c0) & lb_dis) ? "off" : "on"); 1404621bf12SDavid S. Miller } 1414621bf12SDavid S. Miller 1424621bf12SDavid S. Miller static int ns_config_init(struct phy_device *phydev) 1434621bf12SDavid S. Miller { 1444621bf12SDavid S. Miller ns_giga_speed_fallback(phydev, ALL_FALLBACK_ON); 1454621bf12SDavid S. Miller /* In the latest MAC or switches design, the 10 Mbps loopback 1464621bf12SDavid S. Miller is desired to be turned off. */ 1474621bf12SDavid S. Miller ns_10_base_t_hdx_loopack(phydev, hdx_loopback_off); 1484621bf12SDavid S. Miller return ns_ack_interrupt(phydev); 1494621bf12SDavid S. Miller } 1504621bf12SDavid S. Miller 151116dffa0SJohan Hovold static struct phy_driver dp83865_driver[] = { { 1524621bf12SDavid S. Miller .phy_id = DP83865_PHY_ID, 1534621bf12SDavid S. Miller .phy_id_mask = 0xfffffff0, 1544621bf12SDavid S. Miller .name = "NatSemi DP83865", 155dcdecdcfSHeiner Kallweit /* PHY_GBIT_FEATURES */ 1564621bf12SDavid S. Miller .config_init = ns_config_init, 1574621bf12SDavid S. Miller .ack_interrupt = ns_ack_interrupt, 1584621bf12SDavid S. Miller .config_intr = ns_config_intr, 159*6571b455SIoana Ciornei .handle_interrupt = ns_handle_interrupt, 160116dffa0SJohan Hovold } }; 1614621bf12SDavid S. Miller 162116dffa0SJohan Hovold module_phy_driver(dp83865_driver); 1634621bf12SDavid S. Miller 1644621bf12SDavid S. Miller MODULE_DESCRIPTION("NatSemi PHY driver"); 1654621bf12SDavid S. Miller MODULE_AUTHOR("Stuart Menefy"); 1664621bf12SDavid S. Miller MODULE_LICENSE("GPL"); 1674621bf12SDavid S. Miller 168cf93c945SUwe Kleine-König static struct mdio_device_id __maybe_unused ns_tbl[] = { 1694e4f10f6SDavid Woodhouse { DP83865_PHY_ID, 0xfffffff0 }, 1704e4f10f6SDavid Woodhouse { } 1714e4f10f6SDavid Woodhouse }; 1724e4f10f6SDavid Woodhouse 1734e4f10f6SDavid Woodhouse MODULE_DEVICE_TABLE(mdio, ns_tbl); 174