1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* 3 * Driver for Microsemi VSC85xx PHYs 4 * 5 * Author: Nagaraju Lakkaraju 6 * License: Dual MIT/GPL 7 * Copyright (c) 2016 Microsemi Corporation 8 */ 9 10 #include <linux/phy.h> 11 #include <dt-bindings/net/mscc-phy-vsc8531.h> 12 13 #include <crypto/aes.h> 14 15 #include <net/macsec.h> 16 17 #include "mscc.h" 18 #include "mscc_mac.h" 19 #include "mscc_macsec.h" 20 #include "mscc_fc_buffer.h" 21 22 static u32 vsc8584_macsec_phy_read(struct phy_device *phydev, 23 enum macsec_bank bank, u32 reg) 24 { 25 u32 val, val_l = 0, val_h = 0; 26 unsigned long deadline; 27 int rc; 28 29 rc = phy_select_page(phydev, MSCC_PHY_PAGE_MACSEC); 30 if (rc < 0) 31 goto failed; 32 33 __phy_write(phydev, MSCC_EXT_PAGE_MACSEC_20, 34 MSCC_PHY_MACSEC_20_TARGET(bank >> 2)); 35 36 if (bank >> 2 == 0x1) 37 /* non-MACsec access */ 38 bank &= 0x3; 39 else 40 bank = 0; 41 42 __phy_write(phydev, MSCC_EXT_PAGE_MACSEC_19, 43 MSCC_PHY_MACSEC_19_CMD | MSCC_PHY_MACSEC_19_READ | 44 MSCC_PHY_MACSEC_19_REG_ADDR(reg) | 45 MSCC_PHY_MACSEC_19_TARGET(bank)); 46 47 deadline = jiffies + msecs_to_jiffies(PROC_CMD_NCOMPLETED_TIMEOUT_MS); 48 do { 49 val = __phy_read(phydev, MSCC_EXT_PAGE_MACSEC_19); 50 } while (time_before(jiffies, deadline) && !(val & MSCC_PHY_MACSEC_19_CMD)); 51 52 val_l = __phy_read(phydev, MSCC_EXT_PAGE_MACSEC_17); 53 val_h = __phy_read(phydev, MSCC_EXT_PAGE_MACSEC_18); 54 55 failed: 56 phy_restore_page(phydev, rc, rc); 57 58 return (val_h << 16) | val_l; 59 } 60 61 static void vsc8584_macsec_phy_write(struct phy_device *phydev, 62 enum macsec_bank bank, u32 reg, u32 val) 63 { 64 unsigned long deadline; 65 int rc; 66 67 rc = phy_select_page(phydev, MSCC_PHY_PAGE_MACSEC); 68 if (rc < 0) 69 goto failed; 70 71 __phy_write(phydev, MSCC_EXT_PAGE_MACSEC_20, 72 MSCC_PHY_MACSEC_20_TARGET(bank >> 2)); 73 74 if ((bank >> 2 == 0x1) || (bank >> 2 == 0x3)) 75 bank &= 0x3; 76 else 77 /* MACsec access */ 78 bank = 0; 79 80 __phy_write(phydev, MSCC_EXT_PAGE_MACSEC_17, (u16)val); 81 __phy_write(phydev, MSCC_EXT_PAGE_MACSEC_18, (u16)(val >> 16)); 82 83 __phy_write(phydev, MSCC_EXT_PAGE_MACSEC_19, 84 MSCC_PHY_MACSEC_19_CMD | MSCC_PHY_MACSEC_19_REG_ADDR(reg) | 85 MSCC_PHY_MACSEC_19_TARGET(bank)); 86 87 deadline = jiffies + msecs_to_jiffies(PROC_CMD_NCOMPLETED_TIMEOUT_MS); 88 do { 89 val = __phy_read(phydev, MSCC_EXT_PAGE_MACSEC_19); 90 } while (time_before(jiffies, deadline) && !(val & MSCC_PHY_MACSEC_19_CMD)); 91 92 failed: 93 phy_restore_page(phydev, rc, rc); 94 } 95 96 static void vsc8584_macsec_classification(struct phy_device *phydev, 97 enum macsec_bank bank) 98 { 99 /* enable VLAN tag parsing */ 100 vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_CP_TAG, 101 MSCC_MS_SAM_CP_TAG_PARSE_STAG | 102 MSCC_MS_SAM_CP_TAG_PARSE_QTAG | 103 MSCC_MS_SAM_CP_TAG_PARSE_QINQ); 104 } 105 106 static void vsc8584_macsec_flow_default_action(struct phy_device *phydev, 107 enum macsec_bank bank, 108 bool block) 109 { 110 u32 port = (bank == MACSEC_INGR) ? 111 MSCC_MS_PORT_UNCONTROLLED : MSCC_MS_PORT_COMMON; 112 u32 action = MSCC_MS_FLOW_BYPASS; 113 114 if (block) 115 action = MSCC_MS_FLOW_DROP; 116 117 vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_NM_FLOW_NCP, 118 /* MACsec untagged */ 119 MSCC_MS_SAM_NM_FLOW_NCP_UNTAGGED_FLOW_TYPE(action) | 120 MSCC_MS_SAM_NM_FLOW_NCP_UNTAGGED_DROP_ACTION(MSCC_MS_ACTION_DROP) | 121 MSCC_MS_SAM_NM_FLOW_NCP_UNTAGGED_DEST_PORT(port) | 122 /* MACsec tagged */ 123 MSCC_MS_SAM_NM_FLOW_NCP_TAGGED_FLOW_TYPE(action) | 124 MSCC_MS_SAM_NM_FLOW_NCP_TAGGED_DROP_ACTION(MSCC_MS_ACTION_DROP) | 125 MSCC_MS_SAM_NM_FLOW_NCP_TAGGED_DEST_PORT(port) | 126 /* Bad tag */ 127 MSCC_MS_SAM_NM_FLOW_NCP_BADTAG_FLOW_TYPE(action) | 128 MSCC_MS_SAM_NM_FLOW_NCP_BADTAG_DROP_ACTION(MSCC_MS_ACTION_DROP) | 129 MSCC_MS_SAM_NM_FLOW_NCP_BADTAG_DEST_PORT(port) | 130 /* Kay tag */ 131 MSCC_MS_SAM_NM_FLOW_NCP_KAY_FLOW_TYPE(action) | 132 MSCC_MS_SAM_NM_FLOW_NCP_KAY_DROP_ACTION(MSCC_MS_ACTION_DROP) | 133 MSCC_MS_SAM_NM_FLOW_NCP_KAY_DEST_PORT(port)); 134 vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_NM_FLOW_CP, 135 /* MACsec untagged */ 136 MSCC_MS_SAM_NM_FLOW_NCP_UNTAGGED_FLOW_TYPE(action) | 137 MSCC_MS_SAM_NM_FLOW_CP_UNTAGGED_DROP_ACTION(MSCC_MS_ACTION_DROP) | 138 MSCC_MS_SAM_NM_FLOW_CP_UNTAGGED_DEST_PORT(port) | 139 /* MACsec tagged */ 140 MSCC_MS_SAM_NM_FLOW_NCP_TAGGED_FLOW_TYPE(action) | 141 MSCC_MS_SAM_NM_FLOW_CP_TAGGED_DROP_ACTION(MSCC_MS_ACTION_DROP) | 142 MSCC_MS_SAM_NM_FLOW_CP_TAGGED_DEST_PORT(port) | 143 /* Bad tag */ 144 MSCC_MS_SAM_NM_FLOW_NCP_BADTAG_FLOW_TYPE(action) | 145 MSCC_MS_SAM_NM_FLOW_CP_BADTAG_DROP_ACTION(MSCC_MS_ACTION_DROP) | 146 MSCC_MS_SAM_NM_FLOW_CP_BADTAG_DEST_PORT(port) | 147 /* Kay tag */ 148 MSCC_MS_SAM_NM_FLOW_NCP_KAY_FLOW_TYPE(action) | 149 MSCC_MS_SAM_NM_FLOW_CP_KAY_DROP_ACTION(MSCC_MS_ACTION_DROP) | 150 MSCC_MS_SAM_NM_FLOW_CP_KAY_DEST_PORT(port)); 151 } 152 153 static void vsc8584_macsec_integrity_checks(struct phy_device *phydev, 154 enum macsec_bank bank) 155 { 156 u32 val; 157 158 if (bank != MACSEC_INGR) 159 return; 160 161 /* Set default rules to pass unmatched frames */ 162 val = vsc8584_macsec_phy_read(phydev, bank, 163 MSCC_MS_PARAMS2_IG_CC_CONTROL); 164 val |= MSCC_MS_PARAMS2_IG_CC_CONTROL_NON_MATCH_CTRL_ACT | 165 MSCC_MS_PARAMS2_IG_CC_CONTROL_NON_MATCH_ACT; 166 vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_PARAMS2_IG_CC_CONTROL, 167 val); 168 169 vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_PARAMS2_IG_CP_TAG, 170 MSCC_MS_PARAMS2_IG_CP_TAG_PARSE_STAG | 171 MSCC_MS_PARAMS2_IG_CP_TAG_PARSE_QTAG | 172 MSCC_MS_PARAMS2_IG_CP_TAG_PARSE_QINQ); 173 } 174 175 static void vsc8584_macsec_block_init(struct phy_device *phydev, 176 enum macsec_bank bank) 177 { 178 u32 val; 179 int i; 180 181 vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_ENA_CFG, 182 MSCC_MS_ENA_CFG_SW_RST | 183 MSCC_MS_ENA_CFG_MACSEC_BYPASS_ENA); 184 185 /* Set the MACsec block out of s/w reset and enable clocks */ 186 vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_ENA_CFG, 187 MSCC_MS_ENA_CFG_CLK_ENA); 188 189 vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_STATUS_CONTEXT_CTRL, 190 bank == MACSEC_INGR ? 0xe5880214 : 0xe5880218); 191 vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_MISC_CONTROL, 192 MSCC_MS_MISC_CONTROL_MC_LATENCY_FIX(bank == MACSEC_INGR ? 57 : 40) | 193 MSCC_MS_MISC_CONTROL_XFORM_REC_SIZE(bank == MACSEC_INGR ? 1 : 2)); 194 195 /* Clear the counters */ 196 val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MS_COUNT_CONTROL); 197 val |= MSCC_MS_COUNT_CONTROL_AUTO_CNTR_RESET; 198 vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_COUNT_CONTROL, val); 199 200 /* Enable octet increment mode */ 201 vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_PP_CTRL, 202 MSCC_MS_PP_CTRL_MACSEC_OCTET_INCR_MODE); 203 204 vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_BLOCK_CTX_UPDATE, 0x3); 205 206 val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MS_COUNT_CONTROL); 207 val |= MSCC_MS_COUNT_CONTROL_RESET_ALL; 208 vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_COUNT_CONTROL, val); 209 210 /* Set the MTU */ 211 vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_NON_VLAN_MTU_CHECK, 212 MSCC_MS_NON_VLAN_MTU_CHECK_NV_MTU_COMPARE(32761) | 213 MSCC_MS_NON_VLAN_MTU_CHECK_NV_MTU_COMP_DROP); 214 215 for (i = 0; i < 8; i++) 216 vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_VLAN_MTU_CHECK(i), 217 MSCC_MS_VLAN_MTU_CHECK_MTU_COMPARE(32761) | 218 MSCC_MS_VLAN_MTU_CHECK_MTU_COMP_DROP); 219 220 if (bank == MACSEC_EGR) { 221 val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MS_INTR_CTRL_STATUS); 222 val &= ~MSCC_MS_INTR_CTRL_STATUS_INTR_ENABLE_M; 223 vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_INTR_CTRL_STATUS, val); 224 225 vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_FC_CFG, 226 MSCC_MS_FC_CFG_FCBUF_ENA | 227 MSCC_MS_FC_CFG_LOW_THRESH(0x1) | 228 MSCC_MS_FC_CFG_HIGH_THRESH(0x4) | 229 MSCC_MS_FC_CFG_LOW_BYTES_VAL(0x4) | 230 MSCC_MS_FC_CFG_HIGH_BYTES_VAL(0x6)); 231 } 232 233 vsc8584_macsec_classification(phydev, bank); 234 vsc8584_macsec_flow_default_action(phydev, bank, false); 235 vsc8584_macsec_integrity_checks(phydev, bank); 236 237 /* Enable the MACsec block */ 238 vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_ENA_CFG, 239 MSCC_MS_ENA_CFG_CLK_ENA | 240 MSCC_MS_ENA_CFG_MACSEC_ENA | 241 MSCC_MS_ENA_CFG_MACSEC_SPEED_MODE(0x5)); 242 } 243 244 static void vsc8584_macsec_mac_init(struct phy_device *phydev, 245 enum macsec_bank bank) 246 { 247 u32 val; 248 int i; 249 250 /* Clear host & line stats */ 251 for (i = 0; i < 36; i++) 252 vsc8584_macsec_phy_write(phydev, bank, 0x1c + i, 0); 253 254 val = vsc8584_macsec_phy_read(phydev, bank, 255 MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL); 256 val &= ~MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL_PAUSE_MODE_M; 257 val |= MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL_PAUSE_MODE(2) | 258 MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL_PAUSE_VALUE(0xffff); 259 vsc8584_macsec_phy_write(phydev, bank, 260 MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL, val); 261 262 val = vsc8584_macsec_phy_read(phydev, bank, 263 MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL_2); 264 val |= 0xffff; 265 vsc8584_macsec_phy_write(phydev, bank, 266 MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL_2, val); 267 268 val = vsc8584_macsec_phy_read(phydev, bank, 269 MSCC_MAC_PAUSE_CFG_RX_FRAME_CTRL); 270 if (bank == HOST_MAC) 271 val |= MSCC_MAC_PAUSE_CFG_RX_FRAME_CTRL_PAUSE_TIMER_ENA | 272 MSCC_MAC_PAUSE_CFG_RX_FRAME_CTRL_PAUSE_FRAME_DROP_ENA; 273 else 274 val |= MSCC_MAC_PAUSE_CFG_RX_FRAME_CTRL_PAUSE_REACT_ENA | 275 MSCC_MAC_PAUSE_CFG_RX_FRAME_CTRL_PAUSE_FRAME_DROP_ENA | 276 MSCC_MAC_PAUSE_CFG_RX_FRAME_CTRL_PAUSE_MODE | 277 MSCC_MAC_PAUSE_CFG_RX_FRAME_CTRL_EARLY_PAUSE_DETECT_ENA; 278 vsc8584_macsec_phy_write(phydev, bank, 279 MSCC_MAC_PAUSE_CFG_RX_FRAME_CTRL, val); 280 281 vsc8584_macsec_phy_write(phydev, bank, MSCC_MAC_CFG_PKTINF_CFG, 282 MSCC_MAC_CFG_PKTINF_CFG_STRIP_FCS_ENA | 283 MSCC_MAC_CFG_PKTINF_CFG_INSERT_FCS_ENA | 284 MSCC_MAC_CFG_PKTINF_CFG_LPI_RELAY_ENA | 285 MSCC_MAC_CFG_PKTINF_CFG_STRIP_PREAMBLE_ENA | 286 MSCC_MAC_CFG_PKTINF_CFG_INSERT_PREAMBLE_ENA | 287 (bank == HOST_MAC ? 288 MSCC_MAC_CFG_PKTINF_CFG_ENABLE_TX_PADDING : 0)); 289 290 val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MAC_CFG_MODE_CFG); 291 val &= ~MSCC_MAC_CFG_MODE_CFG_DISABLE_DIC; 292 vsc8584_macsec_phy_write(phydev, bank, MSCC_MAC_CFG_MODE_CFG, val); 293 294 val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MAC_CFG_MAXLEN_CFG); 295 val &= ~MSCC_MAC_CFG_MAXLEN_CFG_MAX_LEN_M; 296 val |= MSCC_MAC_CFG_MAXLEN_CFG_MAX_LEN(10240); 297 vsc8584_macsec_phy_write(phydev, bank, MSCC_MAC_CFG_MAXLEN_CFG, val); 298 299 vsc8584_macsec_phy_write(phydev, bank, MSCC_MAC_CFG_ADV_CHK_CFG, 300 MSCC_MAC_CFG_ADV_CHK_CFG_SFD_CHK_ENA | 301 MSCC_MAC_CFG_ADV_CHK_CFG_PRM_CHK_ENA | 302 MSCC_MAC_CFG_ADV_CHK_CFG_OOR_ERR_ENA | 303 MSCC_MAC_CFG_ADV_CHK_CFG_INR_ERR_ENA); 304 305 val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MAC_CFG_LFS_CFG); 306 val &= ~MSCC_MAC_CFG_LFS_CFG_LFS_MODE_ENA; 307 vsc8584_macsec_phy_write(phydev, bank, MSCC_MAC_CFG_LFS_CFG, val); 308 309 vsc8584_macsec_phy_write(phydev, bank, MSCC_MAC_CFG_ENA_CFG, 310 MSCC_MAC_CFG_ENA_CFG_RX_CLK_ENA | 311 MSCC_MAC_CFG_ENA_CFG_TX_CLK_ENA | 312 MSCC_MAC_CFG_ENA_CFG_RX_ENA | 313 MSCC_MAC_CFG_ENA_CFG_TX_ENA); 314 } 315 316 /* Must be called with mdio_lock taken */ 317 static int __vsc8584_macsec_init(struct phy_device *phydev) 318 { 319 struct vsc8531_private *priv = phydev->priv; 320 enum macsec_bank proc_bank; 321 u32 val; 322 323 vsc8584_macsec_block_init(phydev, MACSEC_INGR); 324 vsc8584_macsec_block_init(phydev, MACSEC_EGR); 325 vsc8584_macsec_mac_init(phydev, HOST_MAC); 326 vsc8584_macsec_mac_init(phydev, LINE_MAC); 327 328 vsc8584_macsec_phy_write(phydev, FC_BUFFER, 329 MSCC_FCBUF_FC_READ_THRESH_CFG, 330 MSCC_FCBUF_FC_READ_THRESH_CFG_TX_THRESH(4) | 331 MSCC_FCBUF_FC_READ_THRESH_CFG_RX_THRESH(5)); 332 333 val = vsc8584_macsec_phy_read(phydev, FC_BUFFER, MSCC_FCBUF_MODE_CFG); 334 val |= MSCC_FCBUF_MODE_CFG_PAUSE_GEN_ENA | 335 MSCC_FCBUF_MODE_CFG_RX_PPM_RATE_ADAPT_ENA | 336 MSCC_FCBUF_MODE_CFG_TX_PPM_RATE_ADAPT_ENA; 337 vsc8584_macsec_phy_write(phydev, FC_BUFFER, MSCC_FCBUF_MODE_CFG, val); 338 339 vsc8584_macsec_phy_write(phydev, FC_BUFFER, MSCC_FCBUF_PPM_RATE_ADAPT_THRESH_CFG, 340 MSCC_FCBUF_PPM_RATE_ADAPT_THRESH_CFG_TX_THRESH(8) | 341 MSCC_FCBUF_PPM_RATE_ADAPT_THRESH_CFG_TX_OFFSET(9)); 342 343 val = vsc8584_macsec_phy_read(phydev, FC_BUFFER, 344 MSCC_FCBUF_TX_DATA_QUEUE_CFG); 345 val &= ~(MSCC_FCBUF_TX_DATA_QUEUE_CFG_START_M | 346 MSCC_FCBUF_TX_DATA_QUEUE_CFG_END_M); 347 val |= MSCC_FCBUF_TX_DATA_QUEUE_CFG_START(0) | 348 MSCC_FCBUF_TX_DATA_QUEUE_CFG_END(5119); 349 vsc8584_macsec_phy_write(phydev, FC_BUFFER, 350 MSCC_FCBUF_TX_DATA_QUEUE_CFG, val); 351 352 val = vsc8584_macsec_phy_read(phydev, FC_BUFFER, MSCC_FCBUF_ENA_CFG); 353 val |= MSCC_FCBUF_ENA_CFG_TX_ENA | MSCC_FCBUF_ENA_CFG_RX_ENA; 354 vsc8584_macsec_phy_write(phydev, FC_BUFFER, MSCC_FCBUF_ENA_CFG, val); 355 356 proc_bank = (priv->addr < 2) ? PROC_0 : PROC_2; 357 358 val = vsc8584_macsec_phy_read(phydev, proc_bank, 359 MSCC_PROC_IP_1588_TOP_CFG_STAT_MODE_CTL); 360 val &= ~MSCC_PROC_IP_1588_TOP_CFG_STAT_MODE_CTL_PROTOCOL_MODE_M; 361 val |= MSCC_PROC_IP_1588_TOP_CFG_STAT_MODE_CTL_PROTOCOL_MODE(4); 362 vsc8584_macsec_phy_write(phydev, proc_bank, 363 MSCC_PROC_IP_1588_TOP_CFG_STAT_MODE_CTL, val); 364 365 return 0; 366 } 367 368 static void vsc8584_macsec_flow(struct phy_device *phydev, 369 struct macsec_flow *flow) 370 { 371 struct vsc8531_private *priv = phydev->priv; 372 enum macsec_bank bank = flow->bank; 373 u32 val, match = 0, mask = 0, action = 0, idx = flow->index; 374 375 if (flow->match.tagged) 376 match |= MSCC_MS_SAM_MISC_MATCH_TAGGED; 377 if (flow->match.untagged) 378 match |= MSCC_MS_SAM_MISC_MATCH_UNTAGGED; 379 380 if (bank == MACSEC_INGR && flow->assoc_num >= 0) { 381 match |= MSCC_MS_SAM_MISC_MATCH_AN(flow->assoc_num); 382 mask |= MSCC_MS_SAM_MASK_AN_MASK(0x3); 383 } 384 385 if (bank == MACSEC_INGR && flow->match.sci && flow->rx_sa->sc->sci) { 386 match |= MSCC_MS_SAM_MISC_MATCH_TCI(BIT(3)); 387 mask |= MSCC_MS_SAM_MASK_TCI_MASK(BIT(3)) | 388 MSCC_MS_SAM_MASK_SCI_MASK; 389 390 vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_MATCH_SCI_LO(idx), 391 lower_32_bits(flow->rx_sa->sc->sci)); 392 vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_MATCH_SCI_HI(idx), 393 upper_32_bits(flow->rx_sa->sc->sci)); 394 } 395 396 if (flow->match.etype) { 397 mask |= MSCC_MS_SAM_MASK_MAC_ETYPE_MASK; 398 399 vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_MAC_SA_MATCH_HI(idx), 400 MSCC_MS_SAM_MAC_SA_MATCH_HI_ETYPE(htons(flow->etype))); 401 } 402 403 match |= MSCC_MS_SAM_MISC_MATCH_PRIORITY(flow->priority); 404 405 vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_MISC_MATCH(idx), match); 406 vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_MASK(idx), mask); 407 408 /* Action for matching packets */ 409 if (flow->action.drop) 410 action = MSCC_MS_FLOW_DROP; 411 else if (flow->action.bypass || flow->port == MSCC_MS_PORT_UNCONTROLLED) 412 action = MSCC_MS_FLOW_BYPASS; 413 else 414 action = (bank == MACSEC_INGR) ? 415 MSCC_MS_FLOW_INGRESS : MSCC_MS_FLOW_EGRESS; 416 417 val = MSCC_MS_SAM_FLOW_CTRL_FLOW_TYPE(action) | 418 MSCC_MS_SAM_FLOW_CTRL_DROP_ACTION(MSCC_MS_ACTION_DROP) | 419 MSCC_MS_SAM_FLOW_CTRL_DEST_PORT(flow->port); 420 421 if (action == MSCC_MS_FLOW_BYPASS) 422 goto write_ctrl; 423 424 if (bank == MACSEC_INGR) { 425 if (priv->secy->replay_protect) 426 val |= MSCC_MS_SAM_FLOW_CTRL_REPLAY_PROTECT; 427 if (priv->secy->validate_frames == MACSEC_VALIDATE_STRICT) 428 val |= MSCC_MS_SAM_FLOW_CTRL_VALIDATE_FRAMES(MSCC_MS_VALIDATE_STRICT); 429 else if (priv->secy->validate_frames == MACSEC_VALIDATE_CHECK) 430 val |= MSCC_MS_SAM_FLOW_CTRL_VALIDATE_FRAMES(MSCC_MS_VALIDATE_CHECK); 431 } else if (bank == MACSEC_EGR) { 432 if (priv->secy->protect_frames) 433 val |= MSCC_MS_SAM_FLOW_CTRL_PROTECT_FRAME; 434 if (priv->secy->tx_sc.encrypt) 435 val |= MSCC_MS_SAM_FLOW_CTRL_CONF_PROTECT; 436 if (priv->secy->tx_sc.send_sci) 437 val |= MSCC_MS_SAM_FLOW_CTRL_INCLUDE_SCI; 438 } 439 440 write_ctrl: 441 vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_FLOW_CTRL(idx), val); 442 } 443 444 static struct macsec_flow *vsc8584_macsec_find_flow(struct macsec_context *ctx, 445 enum macsec_bank bank) 446 { 447 struct vsc8531_private *priv = ctx->phydev->priv; 448 struct macsec_flow *pos, *tmp; 449 450 list_for_each_entry_safe(pos, tmp, &priv->macsec_flows, list) 451 if (pos->assoc_num == ctx->sa.assoc_num && pos->bank == bank) 452 return pos; 453 454 return ERR_PTR(-ENOENT); 455 } 456 457 static void vsc8584_macsec_flow_enable(struct phy_device *phydev, 458 struct macsec_flow *flow) 459 { 460 enum macsec_bank bank = flow->bank; 461 u32 val, idx = flow->index; 462 463 if ((flow->bank == MACSEC_INGR && flow->rx_sa && !flow->rx_sa->active) || 464 (flow->bank == MACSEC_EGR && flow->tx_sa && !flow->tx_sa->active)) 465 return; 466 467 /* Enable */ 468 vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_ENTRY_SET1, BIT(idx)); 469 470 /* Set in-use */ 471 val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MS_SAM_FLOW_CTRL(idx)); 472 val |= MSCC_MS_SAM_FLOW_CTRL_SA_IN_USE; 473 vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_FLOW_CTRL(idx), val); 474 } 475 476 static void vsc8584_macsec_flow_disable(struct phy_device *phydev, 477 struct macsec_flow *flow) 478 { 479 enum macsec_bank bank = flow->bank; 480 u32 val, idx = flow->index; 481 482 /* Disable */ 483 vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_ENTRY_CLEAR1, BIT(idx)); 484 485 /* Clear in-use */ 486 val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MS_SAM_FLOW_CTRL(idx)); 487 val &= ~MSCC_MS_SAM_FLOW_CTRL_SA_IN_USE; 488 vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_FLOW_CTRL(idx), val); 489 } 490 491 static u32 vsc8584_macsec_flow_context_id(struct macsec_flow *flow) 492 { 493 if (flow->bank == MACSEC_INGR) 494 return flow->index + MSCC_MS_MAX_FLOWS; 495 496 return flow->index; 497 } 498 499 /* Derive the AES key to get a key for the hash autentication */ 500 static int vsc8584_macsec_derive_key(const u8 key[MACSEC_KEYID_LEN], 501 u16 key_len, u8 hkey[16]) 502 { 503 const u8 input[AES_BLOCK_SIZE] = {0}; 504 struct crypto_aes_ctx ctx; 505 int ret; 506 507 ret = aes_expandkey(&ctx, key, key_len); 508 if (ret) 509 return ret; 510 511 aes_encrypt(&ctx, hkey, input); 512 memzero_explicit(&ctx, sizeof(ctx)); 513 return 0; 514 } 515 516 static int vsc8584_macsec_transformation(struct phy_device *phydev, 517 struct macsec_flow *flow) 518 { 519 struct vsc8531_private *priv = phydev->priv; 520 enum macsec_bank bank = flow->bank; 521 int i, ret, index = flow->index; 522 u32 rec = 0, control = 0; 523 u8 hkey[16]; 524 sci_t sci; 525 526 ret = vsc8584_macsec_derive_key(flow->key, priv->secy->key_len, hkey); 527 if (ret) 528 return ret; 529 530 switch (priv->secy->key_len) { 531 case 16: 532 control |= CONTROL_CRYPTO_ALG(CTRYPTO_ALG_AES_CTR_128); 533 break; 534 case 32: 535 control |= CONTROL_CRYPTO_ALG(CTRYPTO_ALG_AES_CTR_256); 536 break; 537 default: 538 return -EINVAL; 539 } 540 541 control |= (bank == MACSEC_EGR) ? 542 (CONTROL_TYPE_EGRESS | CONTROL_AN(priv->secy->tx_sc.encoding_sa)) : 543 (CONTROL_TYPE_INGRESS | CONTROL_SEQ_MASK); 544 545 control |= CONTROL_UPDATE_SEQ | CONTROL_ENCRYPT_AUTH | CONTROL_KEY_IN_CTX | 546 CONTROL_IV0 | CONTROL_IV1 | CONTROL_IV_IN_SEQ | 547 CONTROL_DIGEST_TYPE(0x2) | CONTROL_SEQ_TYPE(0x1) | 548 CONTROL_AUTH_ALG(AUTH_ALG_AES_GHAS) | CONTROL_CONTEXT_ID; 549 550 /* Set the control word */ 551 vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_XFORM_REC(index, rec++), 552 control); 553 554 /* Set the context ID. Must be unique. */ 555 vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_XFORM_REC(index, rec++), 556 vsc8584_macsec_flow_context_id(flow)); 557 558 /* Set the encryption/decryption key */ 559 for (i = 0; i < priv->secy->key_len / sizeof(u32); i++) 560 vsc8584_macsec_phy_write(phydev, bank, 561 MSCC_MS_XFORM_REC(index, rec++), 562 ((u32 *)flow->key)[i]); 563 564 /* Set the authentication key */ 565 for (i = 0; i < 4; i++) 566 vsc8584_macsec_phy_write(phydev, bank, 567 MSCC_MS_XFORM_REC(index, rec++), 568 ((u32 *)hkey)[i]); 569 570 /* Initial sequence number */ 571 vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_XFORM_REC(index, rec++), 572 bank == MACSEC_INGR ? 573 flow->rx_sa->next_pn : flow->tx_sa->next_pn); 574 575 if (bank == MACSEC_INGR) 576 /* Set the mask (replay window size) */ 577 vsc8584_macsec_phy_write(phydev, bank, 578 MSCC_MS_XFORM_REC(index, rec++), 579 priv->secy->replay_window); 580 581 /* Set the input vectors */ 582 sci = bank == MACSEC_INGR ? flow->rx_sa->sc->sci : priv->secy->sci; 583 vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_XFORM_REC(index, rec++), 584 lower_32_bits(sci)); 585 vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_XFORM_REC(index, rec++), 586 upper_32_bits(sci)); 587 588 while (rec < 20) 589 vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_XFORM_REC(index, rec++), 590 0); 591 592 flow->has_transformation = true; 593 return 0; 594 } 595 596 static struct macsec_flow *vsc8584_macsec_alloc_flow(struct vsc8531_private *priv, 597 enum macsec_bank bank) 598 { 599 unsigned long *bitmap = bank == MACSEC_INGR ? 600 &priv->ingr_flows : &priv->egr_flows; 601 struct macsec_flow *flow; 602 int index; 603 604 index = find_first_zero_bit(bitmap, MSCC_MS_MAX_FLOWS); 605 606 if (index == MSCC_MS_MAX_FLOWS) 607 return ERR_PTR(-ENOMEM); 608 609 flow = kzalloc(sizeof(*flow), GFP_KERNEL); 610 if (!flow) 611 return ERR_PTR(-ENOMEM); 612 613 set_bit(index, bitmap); 614 flow->index = index; 615 flow->bank = bank; 616 flow->priority = 8; 617 flow->assoc_num = -1; 618 619 list_add_tail(&flow->list, &priv->macsec_flows); 620 return flow; 621 } 622 623 static void vsc8584_macsec_free_flow(struct vsc8531_private *priv, 624 struct macsec_flow *flow) 625 { 626 unsigned long *bitmap = flow->bank == MACSEC_INGR ? 627 &priv->ingr_flows : &priv->egr_flows; 628 629 list_del(&flow->list); 630 clear_bit(flow->index, bitmap); 631 kfree(flow); 632 } 633 634 static int vsc8584_macsec_add_flow(struct phy_device *phydev, 635 struct macsec_flow *flow, bool update) 636 { 637 int ret; 638 639 flow->port = MSCC_MS_PORT_CONTROLLED; 640 vsc8584_macsec_flow(phydev, flow); 641 642 if (update) 643 return 0; 644 645 ret = vsc8584_macsec_transformation(phydev, flow); 646 if (ret) { 647 vsc8584_macsec_free_flow(phydev->priv, flow); 648 return ret; 649 } 650 651 return 0; 652 } 653 654 static int vsc8584_macsec_default_flows(struct phy_device *phydev) 655 { 656 struct macsec_flow *flow; 657 658 /* Add a rule to let the MKA traffic go through, ingress */ 659 flow = vsc8584_macsec_alloc_flow(phydev->priv, MACSEC_INGR); 660 if (IS_ERR(flow)) 661 return PTR_ERR(flow); 662 663 flow->priority = 15; 664 flow->port = MSCC_MS_PORT_UNCONTROLLED; 665 flow->match.tagged = 1; 666 flow->match.untagged = 1; 667 flow->match.etype = 1; 668 flow->etype = ETH_P_PAE; 669 flow->action.bypass = 1; 670 671 vsc8584_macsec_flow(phydev, flow); 672 vsc8584_macsec_flow_enable(phydev, flow); 673 674 /* Add a rule to let the MKA traffic go through, egress */ 675 flow = vsc8584_macsec_alloc_flow(phydev->priv, MACSEC_EGR); 676 if (IS_ERR(flow)) 677 return PTR_ERR(flow); 678 679 flow->priority = 15; 680 flow->port = MSCC_MS_PORT_COMMON; 681 flow->match.untagged = 1; 682 flow->match.etype = 1; 683 flow->etype = ETH_P_PAE; 684 flow->action.bypass = 1; 685 686 vsc8584_macsec_flow(phydev, flow); 687 vsc8584_macsec_flow_enable(phydev, flow); 688 689 return 0; 690 } 691 692 static void vsc8584_macsec_del_flow(struct phy_device *phydev, 693 struct macsec_flow *flow) 694 { 695 vsc8584_macsec_flow_disable(phydev, flow); 696 vsc8584_macsec_free_flow(phydev->priv, flow); 697 } 698 699 static int __vsc8584_macsec_add_rxsa(struct macsec_context *ctx, 700 struct macsec_flow *flow, bool update) 701 { 702 struct phy_device *phydev = ctx->phydev; 703 struct vsc8531_private *priv = phydev->priv; 704 705 if (!flow) { 706 flow = vsc8584_macsec_alloc_flow(priv, MACSEC_INGR); 707 if (IS_ERR(flow)) 708 return PTR_ERR(flow); 709 710 memcpy(flow->key, ctx->sa.key, priv->secy->key_len); 711 } 712 713 flow->assoc_num = ctx->sa.assoc_num; 714 flow->rx_sa = ctx->sa.rx_sa; 715 716 /* Always match tagged packets on ingress */ 717 flow->match.tagged = 1; 718 flow->match.sci = 1; 719 720 if (priv->secy->validate_frames != MACSEC_VALIDATE_DISABLED) 721 flow->match.untagged = 1; 722 723 return vsc8584_macsec_add_flow(phydev, flow, update); 724 } 725 726 static int __vsc8584_macsec_add_txsa(struct macsec_context *ctx, 727 struct macsec_flow *flow, bool update) 728 { 729 struct phy_device *phydev = ctx->phydev; 730 struct vsc8531_private *priv = phydev->priv; 731 732 if (!flow) { 733 flow = vsc8584_macsec_alloc_flow(priv, MACSEC_EGR); 734 if (IS_ERR(flow)) 735 return PTR_ERR(flow); 736 737 memcpy(flow->key, ctx->sa.key, priv->secy->key_len); 738 } 739 740 flow->assoc_num = ctx->sa.assoc_num; 741 flow->tx_sa = ctx->sa.tx_sa; 742 743 /* Always match untagged packets on egress */ 744 flow->match.untagged = 1; 745 746 return vsc8584_macsec_add_flow(phydev, flow, update); 747 } 748 749 static int vsc8584_macsec_dev_open(struct macsec_context *ctx) 750 { 751 struct vsc8531_private *priv = ctx->phydev->priv; 752 struct macsec_flow *flow, *tmp; 753 754 /* No operation to perform before the commit step */ 755 if (ctx->prepare) 756 return 0; 757 758 list_for_each_entry_safe(flow, tmp, &priv->macsec_flows, list) 759 vsc8584_macsec_flow_enable(ctx->phydev, flow); 760 761 return 0; 762 } 763 764 static int vsc8584_macsec_dev_stop(struct macsec_context *ctx) 765 { 766 struct vsc8531_private *priv = ctx->phydev->priv; 767 struct macsec_flow *flow, *tmp; 768 769 /* No operation to perform before the commit step */ 770 if (ctx->prepare) 771 return 0; 772 773 list_for_each_entry_safe(flow, tmp, &priv->macsec_flows, list) 774 vsc8584_macsec_flow_disable(ctx->phydev, flow); 775 776 return 0; 777 } 778 779 static int vsc8584_macsec_add_secy(struct macsec_context *ctx) 780 { 781 struct vsc8531_private *priv = ctx->phydev->priv; 782 struct macsec_secy *secy = ctx->secy; 783 784 if (ctx->prepare) { 785 if (priv->secy) 786 return -EEXIST; 787 788 return 0; 789 } 790 791 priv->secy = secy; 792 793 vsc8584_macsec_flow_default_action(ctx->phydev, MACSEC_EGR, 794 secy->validate_frames != MACSEC_VALIDATE_DISABLED); 795 vsc8584_macsec_flow_default_action(ctx->phydev, MACSEC_INGR, 796 secy->validate_frames != MACSEC_VALIDATE_DISABLED); 797 798 return vsc8584_macsec_default_flows(ctx->phydev); 799 } 800 801 static int vsc8584_macsec_del_secy(struct macsec_context *ctx) 802 { 803 struct vsc8531_private *priv = ctx->phydev->priv; 804 struct macsec_flow *flow, *tmp; 805 806 /* No operation to perform before the commit step */ 807 if (ctx->prepare) 808 return 0; 809 810 list_for_each_entry_safe(flow, tmp, &priv->macsec_flows, list) 811 vsc8584_macsec_del_flow(ctx->phydev, flow); 812 813 vsc8584_macsec_flow_default_action(ctx->phydev, MACSEC_EGR, false); 814 vsc8584_macsec_flow_default_action(ctx->phydev, MACSEC_INGR, false); 815 816 priv->secy = NULL; 817 return 0; 818 } 819 820 static int vsc8584_macsec_upd_secy(struct macsec_context *ctx) 821 { 822 /* No operation to perform before the commit step */ 823 if (ctx->prepare) 824 return 0; 825 826 vsc8584_macsec_del_secy(ctx); 827 return vsc8584_macsec_add_secy(ctx); 828 } 829 830 static int vsc8584_macsec_add_rxsc(struct macsec_context *ctx) 831 { 832 /* Nothing to do */ 833 return 0; 834 } 835 836 static int vsc8584_macsec_upd_rxsc(struct macsec_context *ctx) 837 { 838 return -EOPNOTSUPP; 839 } 840 841 static int vsc8584_macsec_del_rxsc(struct macsec_context *ctx) 842 { 843 struct vsc8531_private *priv = ctx->phydev->priv; 844 struct macsec_flow *flow, *tmp; 845 846 /* No operation to perform before the commit step */ 847 if (ctx->prepare) 848 return 0; 849 850 list_for_each_entry_safe(flow, tmp, &priv->macsec_flows, list) { 851 if (flow->bank == MACSEC_INGR && flow->rx_sa && 852 flow->rx_sa->sc->sci == ctx->rx_sc->sci) 853 vsc8584_macsec_del_flow(ctx->phydev, flow); 854 } 855 856 return 0; 857 } 858 859 static int vsc8584_macsec_add_rxsa(struct macsec_context *ctx) 860 { 861 struct macsec_flow *flow = NULL; 862 863 if (ctx->prepare) 864 return __vsc8584_macsec_add_rxsa(ctx, flow, false); 865 866 flow = vsc8584_macsec_find_flow(ctx, MACSEC_INGR); 867 if (IS_ERR(flow)) 868 return PTR_ERR(flow); 869 870 vsc8584_macsec_flow_enable(ctx->phydev, flow); 871 return 0; 872 } 873 874 static int vsc8584_macsec_upd_rxsa(struct macsec_context *ctx) 875 { 876 struct macsec_flow *flow; 877 878 flow = vsc8584_macsec_find_flow(ctx, MACSEC_INGR); 879 if (IS_ERR(flow)) 880 return PTR_ERR(flow); 881 882 if (ctx->prepare) { 883 /* Make sure the flow is disabled before updating it */ 884 vsc8584_macsec_flow_disable(ctx->phydev, flow); 885 886 return __vsc8584_macsec_add_rxsa(ctx, flow, true); 887 } 888 889 vsc8584_macsec_flow_enable(ctx->phydev, flow); 890 return 0; 891 } 892 893 static int vsc8584_macsec_del_rxsa(struct macsec_context *ctx) 894 { 895 struct macsec_flow *flow; 896 897 flow = vsc8584_macsec_find_flow(ctx, MACSEC_INGR); 898 899 if (IS_ERR(flow)) 900 return PTR_ERR(flow); 901 if (ctx->prepare) 902 return 0; 903 904 vsc8584_macsec_del_flow(ctx->phydev, flow); 905 return 0; 906 } 907 908 static int vsc8584_macsec_add_txsa(struct macsec_context *ctx) 909 { 910 struct macsec_flow *flow = NULL; 911 912 if (ctx->prepare) 913 return __vsc8584_macsec_add_txsa(ctx, flow, false); 914 915 flow = vsc8584_macsec_find_flow(ctx, MACSEC_EGR); 916 if (IS_ERR(flow)) 917 return PTR_ERR(flow); 918 919 vsc8584_macsec_flow_enable(ctx->phydev, flow); 920 return 0; 921 } 922 923 static int vsc8584_macsec_upd_txsa(struct macsec_context *ctx) 924 { 925 struct macsec_flow *flow; 926 927 flow = vsc8584_macsec_find_flow(ctx, MACSEC_EGR); 928 if (IS_ERR(flow)) 929 return PTR_ERR(flow); 930 931 if (ctx->prepare) { 932 /* Make sure the flow is disabled before updating it */ 933 vsc8584_macsec_flow_disable(ctx->phydev, flow); 934 935 return __vsc8584_macsec_add_txsa(ctx, flow, true); 936 } 937 938 vsc8584_macsec_flow_enable(ctx->phydev, flow); 939 return 0; 940 } 941 942 static int vsc8584_macsec_del_txsa(struct macsec_context *ctx) 943 { 944 struct macsec_flow *flow; 945 946 flow = vsc8584_macsec_find_flow(ctx, MACSEC_EGR); 947 948 if (IS_ERR(flow)) 949 return PTR_ERR(flow); 950 if (ctx->prepare) 951 return 0; 952 953 vsc8584_macsec_del_flow(ctx->phydev, flow); 954 return 0; 955 } 956 957 static struct macsec_ops vsc8584_macsec_ops = { 958 .mdo_dev_open = vsc8584_macsec_dev_open, 959 .mdo_dev_stop = vsc8584_macsec_dev_stop, 960 .mdo_add_secy = vsc8584_macsec_add_secy, 961 .mdo_upd_secy = vsc8584_macsec_upd_secy, 962 .mdo_del_secy = vsc8584_macsec_del_secy, 963 .mdo_add_rxsc = vsc8584_macsec_add_rxsc, 964 .mdo_upd_rxsc = vsc8584_macsec_upd_rxsc, 965 .mdo_del_rxsc = vsc8584_macsec_del_rxsc, 966 .mdo_add_rxsa = vsc8584_macsec_add_rxsa, 967 .mdo_upd_rxsa = vsc8584_macsec_upd_rxsa, 968 .mdo_del_rxsa = vsc8584_macsec_del_rxsa, 969 .mdo_add_txsa = vsc8584_macsec_add_txsa, 970 .mdo_upd_txsa = vsc8584_macsec_upd_txsa, 971 .mdo_del_txsa = vsc8584_macsec_del_txsa, 972 }; 973 974 int vsc8584_macsec_init(struct phy_device *phydev) 975 { 976 struct vsc8531_private *vsc8531 = phydev->priv; 977 978 switch (phydev->phy_id & phydev->drv->phy_id_mask) { 979 case PHY_ID_VSC856X: 980 case PHY_ID_VSC8575: 981 case PHY_ID_VSC8582: 982 case PHY_ID_VSC8584: 983 INIT_LIST_HEAD(&vsc8531->macsec_flows); 984 vsc8531->secy = NULL; 985 986 phydev->macsec_ops = &vsc8584_macsec_ops; 987 988 return __vsc8584_macsec_init(phydev); 989 } 990 991 return 0; 992 } 993 994 void vsc8584_handle_macsec_interrupt(struct phy_device *phydev) 995 { 996 struct vsc8531_private *priv = phydev->priv; 997 struct macsec_flow *flow, *tmp; 998 u32 cause, rec; 999 1000 /* Check MACsec PN rollover */ 1001 cause = vsc8584_macsec_phy_read(phydev, MACSEC_EGR, 1002 MSCC_MS_INTR_CTRL_STATUS); 1003 cause &= MSCC_MS_INTR_CTRL_STATUS_INTR_CLR_STATUS_M; 1004 if (!(cause & MACSEC_INTR_CTRL_STATUS_ROLLOVER)) 1005 return; 1006 1007 rec = 6 + priv->secy->key_len / sizeof(u32); 1008 list_for_each_entry_safe(flow, tmp, &priv->macsec_flows, list) { 1009 u32 val; 1010 1011 if (flow->bank != MACSEC_EGR || !flow->has_transformation) 1012 continue; 1013 1014 val = vsc8584_macsec_phy_read(phydev, MACSEC_EGR, 1015 MSCC_MS_XFORM_REC(flow->index, rec)); 1016 if (val == 0xffffffff) { 1017 vsc8584_macsec_flow_disable(phydev, flow); 1018 macsec_pn_wrapped(priv->secy, flow->tx_sa); 1019 return; 1020 } 1021 } 1022 } 1023 1024 void vsc8584_config_macsec_intr(struct phy_device *phydev) 1025 { 1026 phy_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_2); 1027 phy_write(phydev, MSCC_PHY_EXTENDED_INT, MSCC_PHY_EXTENDED_INT_MS_EGR); 1028 phy_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); 1029 1030 vsc8584_macsec_phy_write(phydev, MACSEC_EGR, MSCC_MS_AIC_CTRL, 0xf); 1031 vsc8584_macsec_phy_write(phydev, MACSEC_EGR, MSCC_MS_INTR_CTRL_STATUS, 1032 MSCC_MS_INTR_CTRL_STATUS_INTR_ENABLE(MACSEC_INTR_CTRL_STATUS_ROLLOVER)); 1033 } 1034