xref: /openbmc/linux/drivers/net/phy/micrel.c (revision bced870152161435cc59a53e77f3699f8e8f22ca)
1d0507009SDavid J. Choi /*
2d0507009SDavid J. Choi  * drivers/net/phy/micrel.c
3d0507009SDavid J. Choi  *
4d0507009SDavid J. Choi  * Driver for Micrel PHYs
5d0507009SDavid J. Choi  *
6d0507009SDavid J. Choi  * Author: David J. Choi
7d0507009SDavid J. Choi  *
87ab59dc1SDavid J. Choi  * Copyright (c) 2010-2013 Micrel, Inc.
9ee0dc2fbSJohan Hovold  * Copyright (c) 2014 Johan Hovold <johan@kernel.org>
10d0507009SDavid J. Choi  *
11d0507009SDavid J. Choi  * This program is free software; you can redistribute  it and/or modify it
12d0507009SDavid J. Choi  * under  the terms of  the GNU General  Public License as published by the
13d0507009SDavid J. Choi  * Free Software Foundation;  either version 2 of the  License, or (at your
14d0507009SDavid J. Choi  * option) any later version.
15d0507009SDavid J. Choi  *
167ab59dc1SDavid J. Choi  * Support : Micrel Phys:
177ab59dc1SDavid J. Choi  *		Giga phys: ksz9021, ksz9031
187ab59dc1SDavid J. Choi  *		100/10 Phys : ksz8001, ksz8721, ksz8737, ksz8041
197ab59dc1SDavid J. Choi  *			   ksz8021, ksz8031, ksz8051,
207ab59dc1SDavid J. Choi  *			   ksz8081, ksz8091,
217ab59dc1SDavid J. Choi  *			   ksz8061,
227ab59dc1SDavid J. Choi  *		Switch : ksz8873, ksz886x
23d0507009SDavid J. Choi  */
24d0507009SDavid J. Choi 
25d0507009SDavid J. Choi #include <linux/kernel.h>
26d0507009SDavid J. Choi #include <linux/module.h>
27d0507009SDavid J. Choi #include <linux/phy.h>
28d606ef3fSBaruch Siach #include <linux/micrel_phy.h>
29954c3967SSean Cross #include <linux/of.h>
301fadee0cSSascha Hauer #include <linux/clk.h>
31d0507009SDavid J. Choi 
32212ea99aSMarek Vasut /* Operation Mode Strap Override */
33212ea99aSMarek Vasut #define MII_KSZPHY_OMSO				0x16
3400aee095SJohan Hovold #define KSZPHY_OMSO_B_CAST_OFF			BIT(9)
352b0ba96cSSylvain Rochet #define KSZPHY_OMSO_NAND_TREE_ON		BIT(5)
3600aee095SJohan Hovold #define KSZPHY_OMSO_RMII_OVERRIDE		BIT(1)
3700aee095SJohan Hovold #define KSZPHY_OMSO_MII_OVERRIDE		BIT(0)
38212ea99aSMarek Vasut 
3951f932c4SChoi, David /* general Interrupt control/status reg in vendor specific block. */
4051f932c4SChoi, David #define MII_KSZPHY_INTCS			0x1B
4100aee095SJohan Hovold #define	KSZPHY_INTCS_JABBER			BIT(15)
4200aee095SJohan Hovold #define	KSZPHY_INTCS_RECEIVE_ERR		BIT(14)
4300aee095SJohan Hovold #define	KSZPHY_INTCS_PAGE_RECEIVE		BIT(13)
4400aee095SJohan Hovold #define	KSZPHY_INTCS_PARELLEL			BIT(12)
4500aee095SJohan Hovold #define	KSZPHY_INTCS_LINK_PARTNER_ACK		BIT(11)
4600aee095SJohan Hovold #define	KSZPHY_INTCS_LINK_DOWN			BIT(10)
4700aee095SJohan Hovold #define	KSZPHY_INTCS_REMOTE_FAULT		BIT(9)
4800aee095SJohan Hovold #define	KSZPHY_INTCS_LINK_UP			BIT(8)
4951f932c4SChoi, David #define	KSZPHY_INTCS_ALL			(KSZPHY_INTCS_LINK_UP |\
5051f932c4SChoi, David 						KSZPHY_INTCS_LINK_DOWN)
5151f932c4SChoi, David 
525a16778eSJohan Hovold /* PHY Control 1 */
535a16778eSJohan Hovold #define	MII_KSZPHY_CTRL_1			0x1e
545a16778eSJohan Hovold 
555a16778eSJohan Hovold /* PHY Control 2 / PHY Control (if no PHY Control 1) */
565a16778eSJohan Hovold #define	MII_KSZPHY_CTRL_2			0x1f
575a16778eSJohan Hovold #define	MII_KSZPHY_CTRL				MII_KSZPHY_CTRL_2
5851f932c4SChoi, David /* bitmap of PHY register to set interrupt mode */
5900aee095SJohan Hovold #define KSZPHY_CTRL_INT_ACTIVE_HIGH		BIT(9)
6063f44b2bSJohan Hovold #define KSZPHY_RMII_REF_CLK_SEL			BIT(7)
6151f932c4SChoi, David 
62954c3967SSean Cross /* Write/read to/from extended registers */
63954c3967SSean Cross #define MII_KSZPHY_EXTREG                       0x0b
64954c3967SSean Cross #define KSZPHY_EXTREG_WRITE                     0x8000
65954c3967SSean Cross 
66954c3967SSean Cross #define MII_KSZPHY_EXTREG_WRITE                 0x0c
67954c3967SSean Cross #define MII_KSZPHY_EXTREG_READ                  0x0d
68954c3967SSean Cross 
69954c3967SSean Cross /* Extended registers */
70954c3967SSean Cross #define MII_KSZPHY_CLK_CONTROL_PAD_SKEW         0x104
71954c3967SSean Cross #define MII_KSZPHY_RX_DATA_PAD_SKEW             0x105
72954c3967SSean Cross #define MII_KSZPHY_TX_DATA_PAD_SKEW             0x106
73954c3967SSean Cross 
74954c3967SSean Cross #define PS_TO_REG				200
75954c3967SSean Cross 
76e6a423a8SJohan Hovold struct kszphy_type {
77e6a423a8SJohan Hovold 	u32 led_mode_reg;
78c6f9575cSJohan Hovold 	u16 interrupt_level_mask;
790f95903eSJohan Hovold 	bool has_broadcast_disable;
802b0ba96cSSylvain Rochet 	bool has_nand_tree_disable;
8163f44b2bSJohan Hovold 	bool has_rmii_ref_clk_sel;
82e6a423a8SJohan Hovold };
83e6a423a8SJohan Hovold 
84e6a423a8SJohan Hovold struct kszphy_priv {
85e6a423a8SJohan Hovold 	const struct kszphy_type *type;
86e7a792e9SJohan Hovold 	int led_mode;
8763f44b2bSJohan Hovold 	bool rmii_ref_clk_sel;
8863f44b2bSJohan Hovold 	bool rmii_ref_clk_sel_val;
89e6a423a8SJohan Hovold };
90e6a423a8SJohan Hovold 
91e6a423a8SJohan Hovold static const struct kszphy_type ksz8021_type = {
92e6a423a8SJohan Hovold 	.led_mode_reg		= MII_KSZPHY_CTRL_2,
93d0e1df9cSJohan Hovold 	.has_broadcast_disable	= true,
942b0ba96cSSylvain Rochet 	.has_nand_tree_disable	= true,
9563f44b2bSJohan Hovold 	.has_rmii_ref_clk_sel	= true,
96e6a423a8SJohan Hovold };
97e6a423a8SJohan Hovold 
98e6a423a8SJohan Hovold static const struct kszphy_type ksz8041_type = {
99e6a423a8SJohan Hovold 	.led_mode_reg		= MII_KSZPHY_CTRL_1,
100e6a423a8SJohan Hovold };
101e6a423a8SJohan Hovold 
102e6a423a8SJohan Hovold static const struct kszphy_type ksz8051_type = {
103e6a423a8SJohan Hovold 	.led_mode_reg		= MII_KSZPHY_CTRL_2,
1042b0ba96cSSylvain Rochet 	.has_nand_tree_disable	= true,
105e6a423a8SJohan Hovold };
106e6a423a8SJohan Hovold 
107e6a423a8SJohan Hovold static const struct kszphy_type ksz8081_type = {
108e6a423a8SJohan Hovold 	.led_mode_reg		= MII_KSZPHY_CTRL_2,
1090f95903eSJohan Hovold 	.has_broadcast_disable	= true,
1102b0ba96cSSylvain Rochet 	.has_nand_tree_disable	= true,
11186dc1342SJohan Hovold 	.has_rmii_ref_clk_sel	= true,
112e6a423a8SJohan Hovold };
113e6a423a8SJohan Hovold 
114c6f9575cSJohan Hovold static const struct kszphy_type ks8737_type = {
115c6f9575cSJohan Hovold 	.interrupt_level_mask	= BIT(14),
116c6f9575cSJohan Hovold };
117c6f9575cSJohan Hovold 
118c6f9575cSJohan Hovold static const struct kszphy_type ksz9021_type = {
119c6f9575cSJohan Hovold 	.interrupt_level_mask	= BIT(14),
120c6f9575cSJohan Hovold };
121c6f9575cSJohan Hovold 
122954c3967SSean Cross static int kszphy_extended_write(struct phy_device *phydev,
123954c3967SSean Cross 				u32 regnum, u16 val)
124954c3967SSean Cross {
125954c3967SSean Cross 	phy_write(phydev, MII_KSZPHY_EXTREG, KSZPHY_EXTREG_WRITE | regnum);
126954c3967SSean Cross 	return phy_write(phydev, MII_KSZPHY_EXTREG_WRITE, val);
127954c3967SSean Cross }
128954c3967SSean Cross 
129954c3967SSean Cross static int kszphy_extended_read(struct phy_device *phydev,
130954c3967SSean Cross 				u32 regnum)
131954c3967SSean Cross {
132954c3967SSean Cross 	phy_write(phydev, MII_KSZPHY_EXTREG, regnum);
133954c3967SSean Cross 	return phy_read(phydev, MII_KSZPHY_EXTREG_READ);
134954c3967SSean Cross }
135954c3967SSean Cross 
13651f932c4SChoi, David static int kszphy_ack_interrupt(struct phy_device *phydev)
13751f932c4SChoi, David {
13851f932c4SChoi, David 	/* bit[7..0] int status, which is a read and clear register. */
13951f932c4SChoi, David 	int rc;
14051f932c4SChoi, David 
14151f932c4SChoi, David 	rc = phy_read(phydev, MII_KSZPHY_INTCS);
14251f932c4SChoi, David 
14351f932c4SChoi, David 	return (rc < 0) ? rc : 0;
14451f932c4SChoi, David }
14551f932c4SChoi, David 
14651f932c4SChoi, David static int kszphy_config_intr(struct phy_device *phydev)
14751f932c4SChoi, David {
148c6f9575cSJohan Hovold 	const struct kszphy_type *type = phydev->drv->driver_data;
149c6f9575cSJohan Hovold 	int temp;
150c6f9575cSJohan Hovold 	u16 mask;
151c6f9575cSJohan Hovold 
152c6f9575cSJohan Hovold 	if (type && type->interrupt_level_mask)
153c6f9575cSJohan Hovold 		mask = type->interrupt_level_mask;
154c6f9575cSJohan Hovold 	else
155c6f9575cSJohan Hovold 		mask = KSZPHY_CTRL_INT_ACTIVE_HIGH;
15651f932c4SChoi, David 
15751f932c4SChoi, David 	/* set the interrupt pin active low */
15851f932c4SChoi, David 	temp = phy_read(phydev, MII_KSZPHY_CTRL);
1595bb8fc0dSJohan Hovold 	if (temp < 0)
1605bb8fc0dSJohan Hovold 		return temp;
161c6f9575cSJohan Hovold 	temp &= ~mask;
16251f932c4SChoi, David 	phy_write(phydev, MII_KSZPHY_CTRL, temp);
16351f932c4SChoi, David 
164c6f9575cSJohan Hovold 	/* enable / disable interrupts */
165c6f9575cSJohan Hovold 	if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
166c6f9575cSJohan Hovold 		temp = KSZPHY_INTCS_ALL;
167c6f9575cSJohan Hovold 	else
168c6f9575cSJohan Hovold 		temp = 0;
16951f932c4SChoi, David 
170c6f9575cSJohan Hovold 	return phy_write(phydev, MII_KSZPHY_INTCS, temp);
17151f932c4SChoi, David }
172d0507009SDavid J. Choi 
17363f44b2bSJohan Hovold static int kszphy_rmii_clk_sel(struct phy_device *phydev, bool val)
17463f44b2bSJohan Hovold {
17563f44b2bSJohan Hovold 	int ctrl;
17663f44b2bSJohan Hovold 
17763f44b2bSJohan Hovold 	ctrl = phy_read(phydev, MII_KSZPHY_CTRL);
17863f44b2bSJohan Hovold 	if (ctrl < 0)
17963f44b2bSJohan Hovold 		return ctrl;
18063f44b2bSJohan Hovold 
18163f44b2bSJohan Hovold 	if (val)
18263f44b2bSJohan Hovold 		ctrl |= KSZPHY_RMII_REF_CLK_SEL;
18363f44b2bSJohan Hovold 	else
18463f44b2bSJohan Hovold 		ctrl &= ~KSZPHY_RMII_REF_CLK_SEL;
18563f44b2bSJohan Hovold 
18663f44b2bSJohan Hovold 	return phy_write(phydev, MII_KSZPHY_CTRL, ctrl);
18763f44b2bSJohan Hovold }
18863f44b2bSJohan Hovold 
189e7a792e9SJohan Hovold static int kszphy_setup_led(struct phy_device *phydev, u32 reg, int val)
19020d8435aSBen Dooks {
1915a16778eSJohan Hovold 	int rc, temp, shift;
1928620546cSJohan Hovold 
1935a16778eSJohan Hovold 	switch (reg) {
1945a16778eSJohan Hovold 	case MII_KSZPHY_CTRL_1:
1955a16778eSJohan Hovold 		shift = 14;
1965a16778eSJohan Hovold 		break;
1975a16778eSJohan Hovold 	case MII_KSZPHY_CTRL_2:
1985a16778eSJohan Hovold 		shift = 4;
1995a16778eSJohan Hovold 		break;
2005a16778eSJohan Hovold 	default:
2015a16778eSJohan Hovold 		return -EINVAL;
2025a16778eSJohan Hovold 	}
2035a16778eSJohan Hovold 
20420d8435aSBen Dooks 	temp = phy_read(phydev, reg);
205b7035860SJohan Hovold 	if (temp < 0) {
206b7035860SJohan Hovold 		rc = temp;
207b7035860SJohan Hovold 		goto out;
208b7035860SJohan Hovold 	}
20920d8435aSBen Dooks 
21028bdc499SSergei Shtylyov 	temp &= ~(3 << shift);
21120d8435aSBen Dooks 	temp |= val << shift;
21220d8435aSBen Dooks 	rc = phy_write(phydev, reg, temp);
213b7035860SJohan Hovold out:
214b7035860SJohan Hovold 	if (rc < 0)
215b7035860SJohan Hovold 		dev_err(&phydev->dev, "failed to set led mode\n");
21620d8435aSBen Dooks 
217b7035860SJohan Hovold 	return rc;
21820d8435aSBen Dooks }
21920d8435aSBen Dooks 
220bde15129SJohan Hovold /* Disable PHY address 0 as the broadcast address, so that it can be used as a
221bde15129SJohan Hovold  * unique (non-broadcast) address on a shared bus.
222bde15129SJohan Hovold  */
223bde15129SJohan Hovold static int kszphy_broadcast_disable(struct phy_device *phydev)
224bde15129SJohan Hovold {
225bde15129SJohan Hovold 	int ret;
226bde15129SJohan Hovold 
227bde15129SJohan Hovold 	ret = phy_read(phydev, MII_KSZPHY_OMSO);
228bde15129SJohan Hovold 	if (ret < 0)
229bde15129SJohan Hovold 		goto out;
230bde15129SJohan Hovold 
231bde15129SJohan Hovold 	ret = phy_write(phydev, MII_KSZPHY_OMSO, ret | KSZPHY_OMSO_B_CAST_OFF);
232bde15129SJohan Hovold out:
233bde15129SJohan Hovold 	if (ret)
234bde15129SJohan Hovold 		dev_err(&phydev->dev, "failed to disable broadcast address\n");
235bde15129SJohan Hovold 
236bde15129SJohan Hovold 	return ret;
237bde15129SJohan Hovold }
238bde15129SJohan Hovold 
2392b0ba96cSSylvain Rochet static int kszphy_nand_tree_disable(struct phy_device *phydev)
2402b0ba96cSSylvain Rochet {
2412b0ba96cSSylvain Rochet 	int ret;
2422b0ba96cSSylvain Rochet 
2432b0ba96cSSylvain Rochet 	ret = phy_read(phydev, MII_KSZPHY_OMSO);
2442b0ba96cSSylvain Rochet 	if (ret < 0)
2452b0ba96cSSylvain Rochet 		goto out;
2462b0ba96cSSylvain Rochet 
2472b0ba96cSSylvain Rochet 	if (!(ret & KSZPHY_OMSO_NAND_TREE_ON))
2482b0ba96cSSylvain Rochet 		return 0;
2492b0ba96cSSylvain Rochet 
2502b0ba96cSSylvain Rochet 	ret = phy_write(phydev, MII_KSZPHY_OMSO,
2512b0ba96cSSylvain Rochet 			ret & ~KSZPHY_OMSO_NAND_TREE_ON);
2522b0ba96cSSylvain Rochet out:
2532b0ba96cSSylvain Rochet 	if (ret)
2542b0ba96cSSylvain Rochet 		dev_err(&phydev->dev, "failed to disable NAND tree mode\n");
2552b0ba96cSSylvain Rochet 
2562b0ba96cSSylvain Rochet 	return ret;
2572b0ba96cSSylvain Rochet }
2582b0ba96cSSylvain Rochet 
259d0507009SDavid J. Choi static int kszphy_config_init(struct phy_device *phydev)
260d0507009SDavid J. Choi {
261e6a423a8SJohan Hovold 	struct kszphy_priv *priv = phydev->priv;
262e6a423a8SJohan Hovold 	const struct kszphy_type *type;
26363f44b2bSJohan Hovold 	int ret;
264d0507009SDavid J. Choi 
265e6a423a8SJohan Hovold 	if (!priv)
266e6a423a8SJohan Hovold 		return 0;
267e6a423a8SJohan Hovold 
268e6a423a8SJohan Hovold 	type = priv->type;
269e6a423a8SJohan Hovold 
2700f95903eSJohan Hovold 	if (type->has_broadcast_disable)
2710f95903eSJohan Hovold 		kszphy_broadcast_disable(phydev);
2720f95903eSJohan Hovold 
2732b0ba96cSSylvain Rochet 	if (type->has_nand_tree_disable)
2742b0ba96cSSylvain Rochet 		kszphy_nand_tree_disable(phydev);
2752b0ba96cSSylvain Rochet 
27663f44b2bSJohan Hovold 	if (priv->rmii_ref_clk_sel) {
27763f44b2bSJohan Hovold 		ret = kszphy_rmii_clk_sel(phydev, priv->rmii_ref_clk_sel_val);
27863f44b2bSJohan Hovold 		if (ret) {
27963f44b2bSJohan Hovold 			dev_err(&phydev->dev, "failed to set rmii reference clock\n");
28063f44b2bSJohan Hovold 			return ret;
28163f44b2bSJohan Hovold 		}
28263f44b2bSJohan Hovold 	}
28363f44b2bSJohan Hovold 
284e7a792e9SJohan Hovold 	if (priv->led_mode >= 0)
285e7a792e9SJohan Hovold 		kszphy_setup_led(phydev, type->led_mode_reg, priv->led_mode);
286e6a423a8SJohan Hovold 
287e6a423a8SJohan Hovold 	return 0;
28820d8435aSBen Dooks }
28920d8435aSBen Dooks 
290954c3967SSean Cross static int ksz9021_load_values_from_of(struct phy_device *phydev,
291954c3967SSean Cross 				       struct device_node *of_node, u16 reg,
292954c3967SSean Cross 				       char *field1, char *field2,
293954c3967SSean Cross 				       char *field3, char *field4)
294954c3967SSean Cross {
295954c3967SSean Cross 	int val1 = -1;
296954c3967SSean Cross 	int val2 = -2;
297954c3967SSean Cross 	int val3 = -3;
298954c3967SSean Cross 	int val4 = -4;
299954c3967SSean Cross 	int newval;
300954c3967SSean Cross 	int matches = 0;
301954c3967SSean Cross 
302954c3967SSean Cross 	if (!of_property_read_u32(of_node, field1, &val1))
303954c3967SSean Cross 		matches++;
304954c3967SSean Cross 
305954c3967SSean Cross 	if (!of_property_read_u32(of_node, field2, &val2))
306954c3967SSean Cross 		matches++;
307954c3967SSean Cross 
308954c3967SSean Cross 	if (!of_property_read_u32(of_node, field3, &val3))
309954c3967SSean Cross 		matches++;
310954c3967SSean Cross 
311954c3967SSean Cross 	if (!of_property_read_u32(of_node, field4, &val4))
312954c3967SSean Cross 		matches++;
313954c3967SSean Cross 
314954c3967SSean Cross 	if (!matches)
315954c3967SSean Cross 		return 0;
316954c3967SSean Cross 
317954c3967SSean Cross 	if (matches < 4)
318954c3967SSean Cross 		newval = kszphy_extended_read(phydev, reg);
319954c3967SSean Cross 	else
320954c3967SSean Cross 		newval = 0;
321954c3967SSean Cross 
322954c3967SSean Cross 	if (val1 != -1)
323954c3967SSean Cross 		newval = ((newval & 0xfff0) | ((val1 / PS_TO_REG) & 0xf) << 0);
324954c3967SSean Cross 
3256a119745SHubert Chaumette 	if (val2 != -2)
326954c3967SSean Cross 		newval = ((newval & 0xff0f) | ((val2 / PS_TO_REG) & 0xf) << 4);
327954c3967SSean Cross 
3286a119745SHubert Chaumette 	if (val3 != -3)
329954c3967SSean Cross 		newval = ((newval & 0xf0ff) | ((val3 / PS_TO_REG) & 0xf) << 8);
330954c3967SSean Cross 
3316a119745SHubert Chaumette 	if (val4 != -4)
332954c3967SSean Cross 		newval = ((newval & 0x0fff) | ((val4 / PS_TO_REG) & 0xf) << 12);
333954c3967SSean Cross 
334954c3967SSean Cross 	return kszphy_extended_write(phydev, reg, newval);
335954c3967SSean Cross }
336954c3967SSean Cross 
337954c3967SSean Cross static int ksz9021_config_init(struct phy_device *phydev)
338954c3967SSean Cross {
339954c3967SSean Cross 	struct device *dev = &phydev->dev;
340954c3967SSean Cross 	struct device_node *of_node = dev->of_node;
341954c3967SSean Cross 
342954c3967SSean Cross 	if (!of_node && dev->parent->of_node)
343954c3967SSean Cross 		of_node = dev->parent->of_node;
344954c3967SSean Cross 
345954c3967SSean Cross 	if (of_node) {
346954c3967SSean Cross 		ksz9021_load_values_from_of(phydev, of_node,
347954c3967SSean Cross 				    MII_KSZPHY_CLK_CONTROL_PAD_SKEW,
348954c3967SSean Cross 				    "txen-skew-ps", "txc-skew-ps",
349954c3967SSean Cross 				    "rxdv-skew-ps", "rxc-skew-ps");
350954c3967SSean Cross 		ksz9021_load_values_from_of(phydev, of_node,
351954c3967SSean Cross 				    MII_KSZPHY_RX_DATA_PAD_SKEW,
352954c3967SSean Cross 				    "rxd0-skew-ps", "rxd1-skew-ps",
353954c3967SSean Cross 				    "rxd2-skew-ps", "rxd3-skew-ps");
354954c3967SSean Cross 		ksz9021_load_values_from_of(phydev, of_node,
355954c3967SSean Cross 				    MII_KSZPHY_TX_DATA_PAD_SKEW,
356954c3967SSean Cross 				    "txd0-skew-ps", "txd1-skew-ps",
357954c3967SSean Cross 				    "txd2-skew-ps", "txd3-skew-ps");
358954c3967SSean Cross 	}
359954c3967SSean Cross 	return 0;
360954c3967SSean Cross }
361954c3967SSean Cross 
3626e4b8273SHubert Chaumette #define MII_KSZ9031RN_MMD_CTRL_REG	0x0d
3636e4b8273SHubert Chaumette #define MII_KSZ9031RN_MMD_REGDATA_REG	0x0e
3646e4b8273SHubert Chaumette #define OP_DATA				1
3656e4b8273SHubert Chaumette #define KSZ9031_PS_TO_REG		60
3666e4b8273SHubert Chaumette 
3676e4b8273SHubert Chaumette /* Extended registers */
3686e4b8273SHubert Chaumette #define MII_KSZ9031RN_CONTROL_PAD_SKEW	4
3696e4b8273SHubert Chaumette #define MII_KSZ9031RN_RX_DATA_PAD_SKEW	5
3706e4b8273SHubert Chaumette #define MII_KSZ9031RN_TX_DATA_PAD_SKEW	6
3716e4b8273SHubert Chaumette #define MII_KSZ9031RN_CLK_PAD_SKEW	8
3726e4b8273SHubert Chaumette 
3736e4b8273SHubert Chaumette static int ksz9031_extended_write(struct phy_device *phydev,
3746e4b8273SHubert Chaumette 				  u8 mode, u32 dev_addr, u32 regnum, u16 val)
3756e4b8273SHubert Chaumette {
3766e4b8273SHubert Chaumette 	phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, dev_addr);
3776e4b8273SHubert Chaumette 	phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, regnum);
3786e4b8273SHubert Chaumette 	phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, (mode << 14) | dev_addr);
3796e4b8273SHubert Chaumette 	return phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, val);
3806e4b8273SHubert Chaumette }
3816e4b8273SHubert Chaumette 
3826e4b8273SHubert Chaumette static int ksz9031_extended_read(struct phy_device *phydev,
3836e4b8273SHubert Chaumette 				 u8 mode, u32 dev_addr, u32 regnum)
3846e4b8273SHubert Chaumette {
3856e4b8273SHubert Chaumette 	phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, dev_addr);
3866e4b8273SHubert Chaumette 	phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, regnum);
3876e4b8273SHubert Chaumette 	phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, (mode << 14) | dev_addr);
3886e4b8273SHubert Chaumette 	return phy_read(phydev, MII_KSZ9031RN_MMD_REGDATA_REG);
3896e4b8273SHubert Chaumette }
3906e4b8273SHubert Chaumette 
3916e4b8273SHubert Chaumette static int ksz9031_of_load_skew_values(struct phy_device *phydev,
3926e4b8273SHubert Chaumette 				       struct device_node *of_node,
3936e4b8273SHubert Chaumette 				       u16 reg, size_t field_sz,
3946e4b8273SHubert Chaumette 				       char *field[], u8 numfields)
3956e4b8273SHubert Chaumette {
3966e4b8273SHubert Chaumette 	int val[4] = {-1, -2, -3, -4};
3976e4b8273SHubert Chaumette 	int matches = 0;
3986e4b8273SHubert Chaumette 	u16 mask;
3996e4b8273SHubert Chaumette 	u16 maxval;
4006e4b8273SHubert Chaumette 	u16 newval;
4016e4b8273SHubert Chaumette 	int i;
4026e4b8273SHubert Chaumette 
4036e4b8273SHubert Chaumette 	for (i = 0; i < numfields; i++)
4046e4b8273SHubert Chaumette 		if (!of_property_read_u32(of_node, field[i], val + i))
4056e4b8273SHubert Chaumette 			matches++;
4066e4b8273SHubert Chaumette 
4076e4b8273SHubert Chaumette 	if (!matches)
4086e4b8273SHubert Chaumette 		return 0;
4096e4b8273SHubert Chaumette 
4106e4b8273SHubert Chaumette 	if (matches < numfields)
4116e4b8273SHubert Chaumette 		newval = ksz9031_extended_read(phydev, OP_DATA, 2, reg);
4126e4b8273SHubert Chaumette 	else
4136e4b8273SHubert Chaumette 		newval = 0;
4146e4b8273SHubert Chaumette 
4156e4b8273SHubert Chaumette 	maxval = (field_sz == 4) ? 0xf : 0x1f;
4166e4b8273SHubert Chaumette 	for (i = 0; i < numfields; i++)
4176e4b8273SHubert Chaumette 		if (val[i] != -(i + 1)) {
4186e4b8273SHubert Chaumette 			mask = 0xffff;
4196e4b8273SHubert Chaumette 			mask ^= maxval << (field_sz * i);
4206e4b8273SHubert Chaumette 			newval = (newval & mask) |
4216e4b8273SHubert Chaumette 				(((val[i] / KSZ9031_PS_TO_REG) & maxval)
4226e4b8273SHubert Chaumette 					<< (field_sz * i));
4236e4b8273SHubert Chaumette 		}
4246e4b8273SHubert Chaumette 
4256e4b8273SHubert Chaumette 	return ksz9031_extended_write(phydev, OP_DATA, 2, reg, newval);
4266e4b8273SHubert Chaumette }
4276e4b8273SHubert Chaumette 
4286e4b8273SHubert Chaumette static int ksz9031_config_init(struct phy_device *phydev)
4296e4b8273SHubert Chaumette {
4306e4b8273SHubert Chaumette 	struct device *dev = &phydev->dev;
4316e4b8273SHubert Chaumette 	struct device_node *of_node = dev->of_node;
4326e4b8273SHubert Chaumette 	char *clk_skews[2] = {"rxc-skew-ps", "txc-skew-ps"};
4336e4b8273SHubert Chaumette 	char *rx_data_skews[4] = {
4346e4b8273SHubert Chaumette 		"rxd0-skew-ps", "rxd1-skew-ps",
4356e4b8273SHubert Chaumette 		"rxd2-skew-ps", "rxd3-skew-ps"
4366e4b8273SHubert Chaumette 	};
4376e4b8273SHubert Chaumette 	char *tx_data_skews[4] = {
4386e4b8273SHubert Chaumette 		"txd0-skew-ps", "txd1-skew-ps",
4396e4b8273SHubert Chaumette 		"txd2-skew-ps", "txd3-skew-ps"
4406e4b8273SHubert Chaumette 	};
4416e4b8273SHubert Chaumette 	char *control_skews[2] = {"txen-skew-ps", "rxdv-skew-ps"};
4426e4b8273SHubert Chaumette 
4436e4b8273SHubert Chaumette 	if (!of_node && dev->parent->of_node)
4446e4b8273SHubert Chaumette 		of_node = dev->parent->of_node;
4456e4b8273SHubert Chaumette 
4466e4b8273SHubert Chaumette 	if (of_node) {
4476e4b8273SHubert Chaumette 		ksz9031_of_load_skew_values(phydev, of_node,
4486e4b8273SHubert Chaumette 				MII_KSZ9031RN_CLK_PAD_SKEW, 5,
4496e4b8273SHubert Chaumette 				clk_skews, 2);
4506e4b8273SHubert Chaumette 
4516e4b8273SHubert Chaumette 		ksz9031_of_load_skew_values(phydev, of_node,
4526e4b8273SHubert Chaumette 				MII_KSZ9031RN_CONTROL_PAD_SKEW, 4,
4536e4b8273SHubert Chaumette 				control_skews, 2);
4546e4b8273SHubert Chaumette 
4556e4b8273SHubert Chaumette 		ksz9031_of_load_skew_values(phydev, of_node,
4566e4b8273SHubert Chaumette 				MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4,
4576e4b8273SHubert Chaumette 				rx_data_skews, 4);
4586e4b8273SHubert Chaumette 
4596e4b8273SHubert Chaumette 		ksz9031_of_load_skew_values(phydev, of_node,
4606e4b8273SHubert Chaumette 				MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4,
4616e4b8273SHubert Chaumette 				tx_data_skews, 4);
4626e4b8273SHubert Chaumette 	}
4636e4b8273SHubert Chaumette 	return 0;
4646e4b8273SHubert Chaumette }
4656e4b8273SHubert Chaumette 
46693272e07SJean-Christophe PLAGNIOL-VILLARD #define KSZ8873MLL_GLOBAL_CONTROL_4	0x06
46700aee095SJohan Hovold #define KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX	BIT(6)
46800aee095SJohan Hovold #define KSZ8873MLL_GLOBAL_CONTROL_4_SPEED	BIT(4)
46932d73b14SJingoo Han static int ksz8873mll_read_status(struct phy_device *phydev)
47093272e07SJean-Christophe PLAGNIOL-VILLARD {
47193272e07SJean-Christophe PLAGNIOL-VILLARD 	int regval;
47293272e07SJean-Christophe PLAGNIOL-VILLARD 
47393272e07SJean-Christophe PLAGNIOL-VILLARD 	/* dummy read */
47493272e07SJean-Christophe PLAGNIOL-VILLARD 	regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
47593272e07SJean-Christophe PLAGNIOL-VILLARD 
47693272e07SJean-Christophe PLAGNIOL-VILLARD 	regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
47793272e07SJean-Christophe PLAGNIOL-VILLARD 
47893272e07SJean-Christophe PLAGNIOL-VILLARD 	if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX)
47993272e07SJean-Christophe PLAGNIOL-VILLARD 		phydev->duplex = DUPLEX_HALF;
48093272e07SJean-Christophe PLAGNIOL-VILLARD 	else
48193272e07SJean-Christophe PLAGNIOL-VILLARD 		phydev->duplex = DUPLEX_FULL;
48293272e07SJean-Christophe PLAGNIOL-VILLARD 
48393272e07SJean-Christophe PLAGNIOL-VILLARD 	if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_SPEED)
48493272e07SJean-Christophe PLAGNIOL-VILLARD 		phydev->speed = SPEED_10;
48593272e07SJean-Christophe PLAGNIOL-VILLARD 	else
48693272e07SJean-Christophe PLAGNIOL-VILLARD 		phydev->speed = SPEED_100;
48793272e07SJean-Christophe PLAGNIOL-VILLARD 
48893272e07SJean-Christophe PLAGNIOL-VILLARD 	phydev->link = 1;
48993272e07SJean-Christophe PLAGNIOL-VILLARD 	phydev->pause = phydev->asym_pause = 0;
49093272e07SJean-Christophe PLAGNIOL-VILLARD 
49193272e07SJean-Christophe PLAGNIOL-VILLARD 	return 0;
49293272e07SJean-Christophe PLAGNIOL-VILLARD }
49393272e07SJean-Christophe PLAGNIOL-VILLARD 
49493272e07SJean-Christophe PLAGNIOL-VILLARD static int ksz8873mll_config_aneg(struct phy_device *phydev)
49593272e07SJean-Christophe PLAGNIOL-VILLARD {
49693272e07SJean-Christophe PLAGNIOL-VILLARD 	return 0;
49793272e07SJean-Christophe PLAGNIOL-VILLARD }
49893272e07SJean-Christophe PLAGNIOL-VILLARD 
49919936942SVince Bridgers /* This routine returns -1 as an indication to the caller that the
50019936942SVince Bridgers  * Micrel ksz9021 10/100/1000 PHY does not support standard IEEE
50119936942SVince Bridgers  * MMD extended PHY registers.
50219936942SVince Bridgers  */
50319936942SVince Bridgers static int
50419936942SVince Bridgers ksz9021_rd_mmd_phyreg(struct phy_device *phydev, int ptrad, int devnum,
50519936942SVince Bridgers 		      int regnum)
50619936942SVince Bridgers {
50719936942SVince Bridgers 	return -1;
50819936942SVince Bridgers }
50919936942SVince Bridgers 
51019936942SVince Bridgers /* This routine does nothing since the Micrel ksz9021 does not support
51119936942SVince Bridgers  * standard IEEE MMD extended PHY registers.
51219936942SVince Bridgers  */
51319936942SVince Bridgers static void
51419936942SVince Bridgers ksz9021_wr_mmd_phyreg(struct phy_device *phydev, int ptrad, int devnum,
51519936942SVince Bridgers 		      int regnum, u32 val)
51619936942SVince Bridgers {
51719936942SVince Bridgers }
51819936942SVince Bridgers 
519e6a423a8SJohan Hovold static int kszphy_probe(struct phy_device *phydev)
520e6a423a8SJohan Hovold {
521e6a423a8SJohan Hovold 	const struct kszphy_type *type = phydev->drv->driver_data;
522e7a792e9SJohan Hovold 	struct device_node *np = phydev->dev.of_node;
523e6a423a8SJohan Hovold 	struct kszphy_priv *priv;
52463f44b2bSJohan Hovold 	struct clk *clk;
525e7a792e9SJohan Hovold 	int ret;
526e6a423a8SJohan Hovold 
527e6a423a8SJohan Hovold 	priv = devm_kzalloc(&phydev->dev, sizeof(*priv), GFP_KERNEL);
528e6a423a8SJohan Hovold 	if (!priv)
529e6a423a8SJohan Hovold 		return -ENOMEM;
530e6a423a8SJohan Hovold 
531e6a423a8SJohan Hovold 	phydev->priv = priv;
532e6a423a8SJohan Hovold 
533e6a423a8SJohan Hovold 	priv->type = type;
534e6a423a8SJohan Hovold 
535e7a792e9SJohan Hovold 	if (type->led_mode_reg) {
536e7a792e9SJohan Hovold 		ret = of_property_read_u32(np, "micrel,led-mode",
537e7a792e9SJohan Hovold 				&priv->led_mode);
538e7a792e9SJohan Hovold 		if (ret)
539e7a792e9SJohan Hovold 			priv->led_mode = -1;
540e7a792e9SJohan Hovold 
541e7a792e9SJohan Hovold 		if (priv->led_mode > 3) {
542e7a792e9SJohan Hovold 			dev_err(&phydev->dev, "invalid led mode: 0x%02x\n",
543e7a792e9SJohan Hovold 					priv->led_mode);
544e7a792e9SJohan Hovold 			priv->led_mode = -1;
545e7a792e9SJohan Hovold 		}
546e7a792e9SJohan Hovold 	} else {
547e7a792e9SJohan Hovold 		priv->led_mode = -1;
548e7a792e9SJohan Hovold 	}
549e7a792e9SJohan Hovold 
5501fadee0cSSascha Hauer 	clk = devm_clk_get(&phydev->dev, "rmii-ref");
551*bced8701SNiklas Cassel 	/* NOTE: clk may be NULL if building without CONFIG_HAVE_CLK */
552*bced8701SNiklas Cassel 	if (!IS_ERR_OR_NULL(clk)) {
5531fadee0cSSascha Hauer 		unsigned long rate = clk_get_rate(clk);
55486dc1342SJohan Hovold 		bool rmii_ref_clk_sel_25_mhz;
5551fadee0cSSascha Hauer 
55663f44b2bSJohan Hovold 		priv->rmii_ref_clk_sel = type->has_rmii_ref_clk_sel;
55786dc1342SJohan Hovold 		rmii_ref_clk_sel_25_mhz = of_property_read_bool(np,
55886dc1342SJohan Hovold 				"micrel,rmii-reference-clock-select-25-mhz");
55963f44b2bSJohan Hovold 
5601fadee0cSSascha Hauer 		if (rate > 24500000 && rate < 25500000) {
56186dc1342SJohan Hovold 			priv->rmii_ref_clk_sel_val = rmii_ref_clk_sel_25_mhz;
5621fadee0cSSascha Hauer 		} else if (rate > 49500000 && rate < 50500000) {
56386dc1342SJohan Hovold 			priv->rmii_ref_clk_sel_val = !rmii_ref_clk_sel_25_mhz;
5641fadee0cSSascha Hauer 		} else {
5651fadee0cSSascha Hauer 			dev_err(&phydev->dev, "Clock rate out of range: %ld\n", rate);
5661fadee0cSSascha Hauer 			return -EINVAL;
5671fadee0cSSascha Hauer 		}
5681fadee0cSSascha Hauer 	}
5691fadee0cSSascha Hauer 
57063f44b2bSJohan Hovold 	/* Support legacy board-file configuration */
57163f44b2bSJohan Hovold 	if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK) {
57263f44b2bSJohan Hovold 		priv->rmii_ref_clk_sel = true;
57363f44b2bSJohan Hovold 		priv->rmii_ref_clk_sel_val = true;
57463f44b2bSJohan Hovold 	}
57563f44b2bSJohan Hovold 
57663f44b2bSJohan Hovold 	return 0;
5771fadee0cSSascha Hauer }
5781fadee0cSSascha Hauer 
579d5bf9071SChristian Hohnstaedt static struct phy_driver ksphy_driver[] = {
580d5bf9071SChristian Hohnstaedt {
58151f932c4SChoi, David 	.phy_id		= PHY_ID_KS8737,
582d0507009SDavid J. Choi 	.phy_id_mask	= 0x00fffff0,
58351f932c4SChoi, David 	.name		= "Micrel KS8737",
58451f932c4SChoi, David 	.features	= (PHY_BASIC_FEATURES | SUPPORTED_Pause),
58551f932c4SChoi, David 	.flags		= PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
586c6f9575cSJohan Hovold 	.driver_data	= &ks8737_type,
587d0507009SDavid J. Choi 	.config_init	= kszphy_config_init,
588d0507009SDavid J. Choi 	.config_aneg	= genphy_config_aneg,
589d0507009SDavid J. Choi 	.read_status	= genphy_read_status,
59051f932c4SChoi, David 	.ack_interrupt	= kszphy_ack_interrupt,
591c6f9575cSJohan Hovold 	.config_intr	= kszphy_config_intr,
5921a5465f5SPatrice Vilchez 	.suspend	= genphy_suspend,
5931a5465f5SPatrice Vilchez 	.resume		= genphy_resume,
594d0507009SDavid J. Choi 	.driver		= { .owner = THIS_MODULE,},
595d5bf9071SChristian Hohnstaedt }, {
596212ea99aSMarek Vasut 	.phy_id		= PHY_ID_KSZ8021,
597212ea99aSMarek Vasut 	.phy_id_mask	= 0x00ffffff,
5987ab59dc1SDavid J. Choi 	.name		= "Micrel KSZ8021 or KSZ8031",
599212ea99aSMarek Vasut 	.features	= (PHY_BASIC_FEATURES | SUPPORTED_Pause |
600212ea99aSMarek Vasut 			   SUPPORTED_Asym_Pause),
601212ea99aSMarek Vasut 	.flags		= PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
602e6a423a8SJohan Hovold 	.driver_data	= &ksz8021_type,
60363f44b2bSJohan Hovold 	.probe		= kszphy_probe,
604d0e1df9cSJohan Hovold 	.config_init	= kszphy_config_init,
605212ea99aSMarek Vasut 	.config_aneg	= genphy_config_aneg,
606212ea99aSMarek Vasut 	.read_status	= genphy_read_status,
607212ea99aSMarek Vasut 	.ack_interrupt	= kszphy_ack_interrupt,
608212ea99aSMarek Vasut 	.config_intr	= kszphy_config_intr,
6091a5465f5SPatrice Vilchez 	.suspend	= genphy_suspend,
6101a5465f5SPatrice Vilchez 	.resume		= genphy_resume,
611212ea99aSMarek Vasut 	.driver		= { .owner = THIS_MODULE,},
612212ea99aSMarek Vasut }, {
613b818d1a7SHector Palacios 	.phy_id		= PHY_ID_KSZ8031,
614b818d1a7SHector Palacios 	.phy_id_mask	= 0x00ffffff,
615b818d1a7SHector Palacios 	.name		= "Micrel KSZ8031",
616b818d1a7SHector Palacios 	.features	= (PHY_BASIC_FEATURES | SUPPORTED_Pause |
617b818d1a7SHector Palacios 			   SUPPORTED_Asym_Pause),
618b818d1a7SHector Palacios 	.flags		= PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
619e6a423a8SJohan Hovold 	.driver_data	= &ksz8021_type,
62063f44b2bSJohan Hovold 	.probe		= kszphy_probe,
621d0e1df9cSJohan Hovold 	.config_init	= kszphy_config_init,
622b818d1a7SHector Palacios 	.config_aneg	= genphy_config_aneg,
623b818d1a7SHector Palacios 	.read_status	= genphy_read_status,
624b818d1a7SHector Palacios 	.ack_interrupt	= kszphy_ack_interrupt,
625b818d1a7SHector Palacios 	.config_intr	= kszphy_config_intr,
6261a5465f5SPatrice Vilchez 	.suspend	= genphy_suspend,
6271a5465f5SPatrice Vilchez 	.resume		= genphy_resume,
628b818d1a7SHector Palacios 	.driver		= { .owner = THIS_MODULE,},
629b818d1a7SHector Palacios }, {
630510d573fSMarek Vasut 	.phy_id		= PHY_ID_KSZ8041,
631d0507009SDavid J. Choi 	.phy_id_mask	= 0x00fffff0,
632510d573fSMarek Vasut 	.name		= "Micrel KSZ8041",
63351f932c4SChoi, David 	.features	= (PHY_BASIC_FEATURES | SUPPORTED_Pause
63451f932c4SChoi, David 				| SUPPORTED_Asym_Pause),
63551f932c4SChoi, David 	.flags		= PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
636e6a423a8SJohan Hovold 	.driver_data	= &ksz8041_type,
637e6a423a8SJohan Hovold 	.probe		= kszphy_probe,
638e6a423a8SJohan Hovold 	.config_init	= kszphy_config_init,
639d0507009SDavid J. Choi 	.config_aneg	= genphy_config_aneg,
640d0507009SDavid J. Choi 	.read_status	= genphy_read_status,
64151f932c4SChoi, David 	.ack_interrupt	= kszphy_ack_interrupt,
64251f932c4SChoi, David 	.config_intr	= kszphy_config_intr,
6431a5465f5SPatrice Vilchez 	.suspend	= genphy_suspend,
6441a5465f5SPatrice Vilchez 	.resume		= genphy_resume,
64551f932c4SChoi, David 	.driver		= { .owner = THIS_MODULE,},
646d5bf9071SChristian Hohnstaedt }, {
6474bd7b512SSergei Shtylyov 	.phy_id		= PHY_ID_KSZ8041RNLI,
6484bd7b512SSergei Shtylyov 	.phy_id_mask	= 0x00fffff0,
6494bd7b512SSergei Shtylyov 	.name		= "Micrel KSZ8041RNLI",
6504bd7b512SSergei Shtylyov 	.features	= PHY_BASIC_FEATURES |
6514bd7b512SSergei Shtylyov 			  SUPPORTED_Pause | SUPPORTED_Asym_Pause,
6524bd7b512SSergei Shtylyov 	.flags		= PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
653e6a423a8SJohan Hovold 	.driver_data	= &ksz8041_type,
654e6a423a8SJohan Hovold 	.probe		= kszphy_probe,
655e6a423a8SJohan Hovold 	.config_init	= kszphy_config_init,
6564bd7b512SSergei Shtylyov 	.config_aneg	= genphy_config_aneg,
6574bd7b512SSergei Shtylyov 	.read_status	= genphy_read_status,
6584bd7b512SSergei Shtylyov 	.ack_interrupt	= kszphy_ack_interrupt,
6594bd7b512SSergei Shtylyov 	.config_intr	= kszphy_config_intr,
6604bd7b512SSergei Shtylyov 	.suspend	= genphy_suspend,
6614bd7b512SSergei Shtylyov 	.resume		= genphy_resume,
6624bd7b512SSergei Shtylyov 	.driver		= { .owner = THIS_MODULE,},
6634bd7b512SSergei Shtylyov }, {
664510d573fSMarek Vasut 	.phy_id		= PHY_ID_KSZ8051,
66551f932c4SChoi, David 	.phy_id_mask	= 0x00fffff0,
666510d573fSMarek Vasut 	.name		= "Micrel KSZ8051",
66751f932c4SChoi, David 	.features	= (PHY_BASIC_FEATURES | SUPPORTED_Pause
66851f932c4SChoi, David 				| SUPPORTED_Asym_Pause),
66951f932c4SChoi, David 	.flags		= PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
670e6a423a8SJohan Hovold 	.driver_data	= &ksz8051_type,
671e6a423a8SJohan Hovold 	.probe		= kszphy_probe,
67263f44b2bSJohan Hovold 	.config_init	= kszphy_config_init,
67351f932c4SChoi, David 	.config_aneg	= genphy_config_aneg,
67451f932c4SChoi, David 	.read_status	= genphy_read_status,
67551f932c4SChoi, David 	.ack_interrupt	= kszphy_ack_interrupt,
67651f932c4SChoi, David 	.config_intr	= kszphy_config_intr,
6771a5465f5SPatrice Vilchez 	.suspend	= genphy_suspend,
6781a5465f5SPatrice Vilchez 	.resume		= genphy_resume,
67951f932c4SChoi, David 	.driver		= { .owner = THIS_MODULE,},
680d5bf9071SChristian Hohnstaedt }, {
681510d573fSMarek Vasut 	.phy_id		= PHY_ID_KSZ8001,
682510d573fSMarek Vasut 	.name		= "Micrel KSZ8001 or KS8721",
68348d7d0adSJason Wang 	.phy_id_mask	= 0x00ffffff,
68451f932c4SChoi, David 	.features	= (PHY_BASIC_FEATURES | SUPPORTED_Pause),
68551f932c4SChoi, David 	.flags		= PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
686e6a423a8SJohan Hovold 	.driver_data	= &ksz8041_type,
687e6a423a8SJohan Hovold 	.probe		= kszphy_probe,
688e6a423a8SJohan Hovold 	.config_init	= kszphy_config_init,
68951f932c4SChoi, David 	.config_aneg	= genphy_config_aneg,
69051f932c4SChoi, David 	.read_status	= genphy_read_status,
69151f932c4SChoi, David 	.ack_interrupt	= kszphy_ack_interrupt,
69251f932c4SChoi, David 	.config_intr	= kszphy_config_intr,
6931a5465f5SPatrice Vilchez 	.suspend	= genphy_suspend,
6941a5465f5SPatrice Vilchez 	.resume		= genphy_resume,
695d0507009SDavid J. Choi 	.driver		= { .owner = THIS_MODULE,},
696d5bf9071SChristian Hohnstaedt }, {
6977ab59dc1SDavid J. Choi 	.phy_id		= PHY_ID_KSZ8081,
6987ab59dc1SDavid J. Choi 	.name		= "Micrel KSZ8081 or KSZ8091",
6997ab59dc1SDavid J. Choi 	.phy_id_mask	= 0x00fffff0,
7007ab59dc1SDavid J. Choi 	.features	= (PHY_BASIC_FEATURES | SUPPORTED_Pause),
7017ab59dc1SDavid J. Choi 	.flags		= PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
702e6a423a8SJohan Hovold 	.driver_data	= &ksz8081_type,
703e6a423a8SJohan Hovold 	.probe		= kszphy_probe,
7040f95903eSJohan Hovold 	.config_init	= kszphy_config_init,
7057ab59dc1SDavid J. Choi 	.config_aneg	= genphy_config_aneg,
7067ab59dc1SDavid J. Choi 	.read_status	= genphy_read_status,
7077ab59dc1SDavid J. Choi 	.ack_interrupt	= kszphy_ack_interrupt,
7087ab59dc1SDavid J. Choi 	.config_intr	= kszphy_config_intr,
7091a5465f5SPatrice Vilchez 	.suspend	= genphy_suspend,
7101a5465f5SPatrice Vilchez 	.resume		= genphy_resume,
7117ab59dc1SDavid J. Choi 	.driver		= { .owner = THIS_MODULE,},
7127ab59dc1SDavid J. Choi }, {
7137ab59dc1SDavid J. Choi 	.phy_id		= PHY_ID_KSZ8061,
7147ab59dc1SDavid J. Choi 	.name		= "Micrel KSZ8061",
7157ab59dc1SDavid J. Choi 	.phy_id_mask	= 0x00fffff0,
7167ab59dc1SDavid J. Choi 	.features	= (PHY_BASIC_FEATURES | SUPPORTED_Pause),
7177ab59dc1SDavid J. Choi 	.flags		= PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
7187ab59dc1SDavid J. Choi 	.config_init	= kszphy_config_init,
7197ab59dc1SDavid J. Choi 	.config_aneg	= genphy_config_aneg,
7207ab59dc1SDavid J. Choi 	.read_status	= genphy_read_status,
7217ab59dc1SDavid J. Choi 	.ack_interrupt	= kszphy_ack_interrupt,
7227ab59dc1SDavid J. Choi 	.config_intr	= kszphy_config_intr,
7231a5465f5SPatrice Vilchez 	.suspend	= genphy_suspend,
7241a5465f5SPatrice Vilchez 	.resume		= genphy_resume,
7257ab59dc1SDavid J. Choi 	.driver		= { .owner = THIS_MODULE,},
7267ab59dc1SDavid J. Choi }, {
727d0507009SDavid J. Choi 	.phy_id		= PHY_ID_KSZ9021,
72848d7d0adSJason Wang 	.phy_id_mask	= 0x000ffffe,
729d0507009SDavid J. Choi 	.name		= "Micrel KSZ9021 Gigabit PHY",
73032fcafbcSVlastimil Kosar 	.features	= (PHY_GBIT_FEATURES | SUPPORTED_Pause),
73151f932c4SChoi, David 	.flags		= PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
732c6f9575cSJohan Hovold 	.driver_data	= &ksz9021_type,
733954c3967SSean Cross 	.config_init	= ksz9021_config_init,
734d0507009SDavid J. Choi 	.config_aneg	= genphy_config_aneg,
735d0507009SDavid J. Choi 	.read_status	= genphy_read_status,
73651f932c4SChoi, David 	.ack_interrupt	= kszphy_ack_interrupt,
737c6f9575cSJohan Hovold 	.config_intr	= kszphy_config_intr,
7381a5465f5SPatrice Vilchez 	.suspend	= genphy_suspend,
7391a5465f5SPatrice Vilchez 	.resume		= genphy_resume,
74019936942SVince Bridgers 	.read_mmd_indirect = ksz9021_rd_mmd_phyreg,
74119936942SVince Bridgers 	.write_mmd_indirect = ksz9021_wr_mmd_phyreg,
742d0507009SDavid J. Choi 	.driver		= { .owner = THIS_MODULE, },
74393272e07SJean-Christophe PLAGNIOL-VILLARD }, {
7447ab59dc1SDavid J. Choi 	.phy_id		= PHY_ID_KSZ9031,
7457ab59dc1SDavid J. Choi 	.phy_id_mask	= 0x00fffff0,
7467ab59dc1SDavid J. Choi 	.name		= "Micrel KSZ9031 Gigabit PHY",
74795e8b103SMike Looijmans 	.features	= (PHY_GBIT_FEATURES | SUPPORTED_Pause),
7487ab59dc1SDavid J. Choi 	.flags		= PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
749c6f9575cSJohan Hovold 	.driver_data	= &ksz9021_type,
7506e4b8273SHubert Chaumette 	.config_init	= ksz9031_config_init,
7517ab59dc1SDavid J. Choi 	.config_aneg	= genphy_config_aneg,
7527ab59dc1SDavid J. Choi 	.read_status	= genphy_read_status,
7537ab59dc1SDavid J. Choi 	.ack_interrupt	= kszphy_ack_interrupt,
754c6f9575cSJohan Hovold 	.config_intr	= kszphy_config_intr,
7551a5465f5SPatrice Vilchez 	.suspend	= genphy_suspend,
7561a5465f5SPatrice Vilchez 	.resume		= genphy_resume,
7577ab59dc1SDavid J. Choi 	.driver		= { .owner = THIS_MODULE, },
7587ab59dc1SDavid J. Choi }, {
75993272e07SJean-Christophe PLAGNIOL-VILLARD 	.phy_id		= PHY_ID_KSZ8873MLL,
76093272e07SJean-Christophe PLAGNIOL-VILLARD 	.phy_id_mask	= 0x00fffff0,
76193272e07SJean-Christophe PLAGNIOL-VILLARD 	.name		= "Micrel KSZ8873MLL Switch",
76293272e07SJean-Christophe PLAGNIOL-VILLARD 	.features	= (SUPPORTED_Pause | SUPPORTED_Asym_Pause),
76393272e07SJean-Christophe PLAGNIOL-VILLARD 	.flags		= PHY_HAS_MAGICANEG,
76493272e07SJean-Christophe PLAGNIOL-VILLARD 	.config_init	= kszphy_config_init,
76593272e07SJean-Christophe PLAGNIOL-VILLARD 	.config_aneg	= ksz8873mll_config_aneg,
76693272e07SJean-Christophe PLAGNIOL-VILLARD 	.read_status	= ksz8873mll_read_status,
7671a5465f5SPatrice Vilchez 	.suspend	= genphy_suspend,
7681a5465f5SPatrice Vilchez 	.resume		= genphy_resume,
76993272e07SJean-Christophe PLAGNIOL-VILLARD 	.driver		= { .owner = THIS_MODULE, },
7707ab59dc1SDavid J. Choi }, {
7717ab59dc1SDavid J. Choi 	.phy_id		= PHY_ID_KSZ886X,
7727ab59dc1SDavid J. Choi 	.phy_id_mask	= 0x00fffff0,
7737ab59dc1SDavid J. Choi 	.name		= "Micrel KSZ886X Switch",
7747ab59dc1SDavid J. Choi 	.features	= (PHY_BASIC_FEATURES | SUPPORTED_Pause),
7757ab59dc1SDavid J. Choi 	.flags		= PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
7767ab59dc1SDavid J. Choi 	.config_init	= kszphy_config_init,
7777ab59dc1SDavid J. Choi 	.config_aneg	= genphy_config_aneg,
7787ab59dc1SDavid J. Choi 	.read_status	= genphy_read_status,
7791a5465f5SPatrice Vilchez 	.suspend	= genphy_suspend,
7801a5465f5SPatrice Vilchez 	.resume		= genphy_resume,
7817ab59dc1SDavid J. Choi 	.driver		= { .owner = THIS_MODULE, },
782d5bf9071SChristian Hohnstaedt } };
783d0507009SDavid J. Choi 
78450fd7150SJohan Hovold module_phy_driver(ksphy_driver);
785d0507009SDavid J. Choi 
786d0507009SDavid J. Choi MODULE_DESCRIPTION("Micrel PHY driver");
787d0507009SDavid J. Choi MODULE_AUTHOR("David J. Choi");
788d0507009SDavid J. Choi MODULE_LICENSE("GPL");
78952a60ed2SDavid S. Miller 
790cf93c945SUwe Kleine-König static struct mdio_device_id __maybe_unused micrel_tbl[] = {
79148d7d0adSJason Wang 	{ PHY_ID_KSZ9021, 0x000ffffe },
7927ab59dc1SDavid J. Choi 	{ PHY_ID_KSZ9031, 0x00fffff0 },
793510d573fSMarek Vasut 	{ PHY_ID_KSZ8001, 0x00ffffff },
79451f932c4SChoi, David 	{ PHY_ID_KS8737, 0x00fffff0 },
795212ea99aSMarek Vasut 	{ PHY_ID_KSZ8021, 0x00ffffff },
796b818d1a7SHector Palacios 	{ PHY_ID_KSZ8031, 0x00ffffff },
797510d573fSMarek Vasut 	{ PHY_ID_KSZ8041, 0x00fffff0 },
798510d573fSMarek Vasut 	{ PHY_ID_KSZ8051, 0x00fffff0 },
7997ab59dc1SDavid J. Choi 	{ PHY_ID_KSZ8061, 0x00fffff0 },
8007ab59dc1SDavid J. Choi 	{ PHY_ID_KSZ8081, 0x00fffff0 },
80193272e07SJean-Christophe PLAGNIOL-VILLARD 	{ PHY_ID_KSZ8873MLL, 0x00fffff0 },
8027ab59dc1SDavid J. Choi 	{ PHY_ID_KSZ886X, 0x00fffff0 },
80352a60ed2SDavid S. Miller 	{ }
80452a60ed2SDavid S. Miller };
80552a60ed2SDavid S. Miller 
80652a60ed2SDavid S. Miller MODULE_DEVICE_TABLE(mdio, micrel_tbl);
807