10cefeebaSMichael Barkowski /* 20cefeebaSMichael Barkowski * Driver for ICPlus PHYs 30cefeebaSMichael Barkowski * 40cefeebaSMichael Barkowski * Copyright (c) 2007 Freescale Semiconductor, Inc. 50cefeebaSMichael Barkowski * 60cefeebaSMichael Barkowski * This program is free software; you can redistribute it and/or modify it 70cefeebaSMichael Barkowski * under the terms of the GNU General Public License as published by the 80cefeebaSMichael Barkowski * Free Software Foundation; either version 2 of the License, or (at your 90cefeebaSMichael Barkowski * option) any later version. 100cefeebaSMichael Barkowski * 110cefeebaSMichael Barkowski */ 120cefeebaSMichael Barkowski #include <linux/kernel.h> 130cefeebaSMichael Barkowski #include <linux/string.h> 140cefeebaSMichael Barkowski #include <linux/errno.h> 150cefeebaSMichael Barkowski #include <linux/unistd.h> 160cefeebaSMichael Barkowski #include <linux/interrupt.h> 170cefeebaSMichael Barkowski #include <linux/init.h> 180cefeebaSMichael Barkowski #include <linux/delay.h> 190cefeebaSMichael Barkowski #include <linux/netdevice.h> 200cefeebaSMichael Barkowski #include <linux/etherdevice.h> 210cefeebaSMichael Barkowski #include <linux/skbuff.h> 220cefeebaSMichael Barkowski #include <linux/spinlock.h> 230cefeebaSMichael Barkowski #include <linux/mm.h> 240cefeebaSMichael Barkowski #include <linux/module.h> 250cefeebaSMichael Barkowski #include <linux/mii.h> 260cefeebaSMichael Barkowski #include <linux/ethtool.h> 270cefeebaSMichael Barkowski #include <linux/phy.h> 280cefeebaSMichael Barkowski 290cefeebaSMichael Barkowski #include <asm/io.h> 300cefeebaSMichael Barkowski #include <asm/irq.h> 310cefeebaSMichael Barkowski #include <asm/uaccess.h> 320cefeebaSMichael Barkowski 33e3e09f26SGiuseppe CAVALLARO MODULE_DESCRIPTION("ICPlus IP175C/IP101A/IP101G/IC1001 PHY drivers"); 340cefeebaSMichael Barkowski MODULE_AUTHOR("Michael Barkowski"); 350cefeebaSMichael Barkowski MODULE_LICENSE("GPL"); 360cefeebaSMichael Barkowski 37e3e09f26SGiuseppe CAVALLARO /* IP101A/G - IP1001 */ 389c9b1f24SGiuseppe CAVALLARO #define IP10XX_SPEC_CTRL_STATUS 16 /* Spec. Control Register */ 399c9b1f24SGiuseppe CAVALLARO #define IP1001_SPEC_CTRL_STATUS_2 20 /* IP1001 Spec. Control Reg 2 */ 409c9b1f24SGiuseppe CAVALLARO #define IP1001_PHASE_SEL_MASK 3 /* IP1001 RX/TXPHASE_SEL */ 419c9b1f24SGiuseppe CAVALLARO #define IP1001_APS_ON 11 /* IP1001 APS Mode bit */ 42e3e09f26SGiuseppe CAVALLARO #define IP101A_G_APS_ON 2 /* IP101A/G APS Mode bit */ 43996f7393SGiuseppe CAVALLARO #define IP101A_G_IRQ_CONF_STATUS 0x11 /* Conf Info IRQ & Status Reg */ 449ec0db71SGiuseppe CAVALLARO #define IP101A_G_IRQ_PIN_USED (1<<15) /* INTR pin used */ 459ec0db71SGiuseppe CAVALLARO #define IP101A_G_IRQ_DEFAULT IP101A_G_IRQ_PIN_USED 469c9b1f24SGiuseppe CAVALLARO 470cefeebaSMichael Barkowski static int ip175c_config_init(struct phy_device *phydev) 480cefeebaSMichael Barkowski { 490cefeebaSMichael Barkowski int err, i; 500cefeebaSMichael Barkowski static int full_reset_performed = 0; 510cefeebaSMichael Barkowski 520cefeebaSMichael Barkowski if (full_reset_performed == 0) { 530cefeebaSMichael Barkowski 540cefeebaSMichael Barkowski /* master reset */ 5576231e02SDavid Daney err = mdiobus_write(phydev->bus, 30, 0, 0x175c); 560cefeebaSMichael Barkowski if (err < 0) 570cefeebaSMichael Barkowski return err; 580cefeebaSMichael Barkowski 590cefeebaSMichael Barkowski /* ensure no bus delays overlap reset period */ 6076231e02SDavid Daney err = mdiobus_read(phydev->bus, 30, 0); 610cefeebaSMichael Barkowski 620cefeebaSMichael Barkowski /* data sheet specifies reset period is 2 msec */ 630cefeebaSMichael Barkowski mdelay(2); 640cefeebaSMichael Barkowski 650cefeebaSMichael Barkowski /* enable IP175C mode */ 6676231e02SDavid Daney err = mdiobus_write(phydev->bus, 29, 31, 0x175c); 670cefeebaSMichael Barkowski if (err < 0) 680cefeebaSMichael Barkowski return err; 690cefeebaSMichael Barkowski 700cefeebaSMichael Barkowski /* Set MII0 speed and duplex (in PHY mode) */ 7176231e02SDavid Daney err = mdiobus_write(phydev->bus, 29, 22, 0x420); 720cefeebaSMichael Barkowski if (err < 0) 730cefeebaSMichael Barkowski return err; 740cefeebaSMichael Barkowski 750cefeebaSMichael Barkowski /* reset switch ports */ 760cefeebaSMichael Barkowski for (i = 0; i < 5; i++) { 7776231e02SDavid Daney err = mdiobus_write(phydev->bus, i, 780cefeebaSMichael Barkowski MII_BMCR, BMCR_RESET); 790cefeebaSMichael Barkowski if (err < 0) 800cefeebaSMichael Barkowski return err; 810cefeebaSMichael Barkowski } 820cefeebaSMichael Barkowski 830cefeebaSMichael Barkowski for (i = 0; i < 5; i++) 8476231e02SDavid Daney err = mdiobus_read(phydev->bus, i, MII_BMCR); 850cefeebaSMichael Barkowski 860cefeebaSMichael Barkowski mdelay(2); 870cefeebaSMichael Barkowski 880cefeebaSMichael Barkowski full_reset_performed = 1; 890cefeebaSMichael Barkowski } 900cefeebaSMichael Barkowski 910cefeebaSMichael Barkowski if (phydev->addr != 4) { 920cefeebaSMichael Barkowski phydev->state = PHY_RUNNING; 930cefeebaSMichael Barkowski phydev->speed = SPEED_100; 940cefeebaSMichael Barkowski phydev->duplex = DUPLEX_FULL; 950cefeebaSMichael Barkowski phydev->link = 1; 960cefeebaSMichael Barkowski netif_carrier_on(phydev->attached_dev); 970cefeebaSMichael Barkowski } 980cefeebaSMichael Barkowski 990cefeebaSMichael Barkowski return 0; 1000cefeebaSMichael Barkowski } 1010cefeebaSMichael Barkowski 1029c9b1f24SGiuseppe CAVALLARO static int ip1xx_reset(struct phy_device *phydev) 103377ecca9SGiuseppe CAVALLARO { 104b8e3995aSDavid McKay int bmcr; 105377ecca9SGiuseppe CAVALLARO 106377ecca9SGiuseppe CAVALLARO /* Software Reset PHY */ 1079c9b1f24SGiuseppe CAVALLARO bmcr = phy_read(phydev, MII_BMCR); 108b8e3995aSDavid McKay if (bmcr < 0) 109b8e3995aSDavid McKay return bmcr; 1109c9b1f24SGiuseppe CAVALLARO bmcr |= BMCR_RESET; 111b8e3995aSDavid McKay bmcr = phy_write(phydev, MII_BMCR, bmcr); 112b8e3995aSDavid McKay if (bmcr < 0) 113b8e3995aSDavid McKay return bmcr; 114377ecca9SGiuseppe CAVALLARO 115377ecca9SGiuseppe CAVALLARO do { 1169c9b1f24SGiuseppe CAVALLARO bmcr = phy_read(phydev, MII_BMCR); 117b8e3995aSDavid McKay if (bmcr < 0) 118b8e3995aSDavid McKay return bmcr; 1199c9b1f24SGiuseppe CAVALLARO } while (bmcr & BMCR_RESET); 1209c9b1f24SGiuseppe CAVALLARO 121b8e3995aSDavid McKay return 0; 1229c9b1f24SGiuseppe CAVALLARO } 1239c9b1f24SGiuseppe CAVALLARO 1249c9b1f24SGiuseppe CAVALLARO static int ip1001_config_init(struct phy_device *phydev) 1259c9b1f24SGiuseppe CAVALLARO { 1269c9b1f24SGiuseppe CAVALLARO int c; 1279c9b1f24SGiuseppe CAVALLARO 1289c9b1f24SGiuseppe CAVALLARO c = ip1xx_reset(phydev); 1299c9b1f24SGiuseppe CAVALLARO if (c < 0) 1309c9b1f24SGiuseppe CAVALLARO return c; 1319c9b1f24SGiuseppe CAVALLARO 1329c9b1f24SGiuseppe CAVALLARO /* Enable Auto Power Saving mode */ 1339c9b1f24SGiuseppe CAVALLARO c = phy_read(phydev, IP1001_SPEC_CTRL_STATUS_2); 134b8e3995aSDavid McKay if (c < 0) 135b8e3995aSDavid McKay return c; 1369c9b1f24SGiuseppe CAVALLARO c |= IP1001_APS_ON; 137b8e3995aSDavid McKay c = phy_write(phydev, IP1001_SPEC_CTRL_STATUS_2, c); 1389c9b1f24SGiuseppe CAVALLARO if (c < 0) 1399c9b1f24SGiuseppe CAVALLARO return c; 140377ecca9SGiuseppe CAVALLARO 1419ec0db71SGiuseppe CAVALLARO /* INTR pin used: speed/link/duplex will cause an interrupt */ 1429ec0db71SGiuseppe CAVALLARO c = phy_write(phydev, IP101A_G_IRQ_CONF_STATUS, IP101A_G_IRQ_DEFAULT); 1439ec0db71SGiuseppe CAVALLARO if (c < 0) 1449ec0db71SGiuseppe CAVALLARO return c; 1459ec0db71SGiuseppe CAVALLARO 146a4886d52SGiuseppe CAVALLARO if (phydev->interface == PHY_INTERFACE_MODE_RGMII) { 147377ecca9SGiuseppe CAVALLARO /* Additional delay (2ns) used to adjust RX clock phase 148a4886d52SGiuseppe CAVALLARO * at RGMII interface */ 1499c9b1f24SGiuseppe CAVALLARO c = phy_read(phydev, IP10XX_SPEC_CTRL_STATUS); 150b8e3995aSDavid McKay if (c < 0) 151b8e3995aSDavid McKay return c; 152b8e3995aSDavid McKay 1539c9b1f24SGiuseppe CAVALLARO c |= IP1001_PHASE_SEL_MASK; 154a4886d52SGiuseppe CAVALLARO c = phy_write(phydev, IP10XX_SPEC_CTRL_STATUS, c); 155b8e3995aSDavid McKay if (c < 0) 156b8e3995aSDavid McKay return c; 157a4886d52SGiuseppe CAVALLARO } 158377ecca9SGiuseppe CAVALLARO 159b8e3995aSDavid McKay return 0; 1609c9b1f24SGiuseppe CAVALLARO } 1619c9b1f24SGiuseppe CAVALLARO 162e3e09f26SGiuseppe CAVALLARO static int ip101a_g_config_init(struct phy_device *phydev) 1639c9b1f24SGiuseppe CAVALLARO { 1649c9b1f24SGiuseppe CAVALLARO int c; 1659c9b1f24SGiuseppe CAVALLARO 1669c9b1f24SGiuseppe CAVALLARO c = ip1xx_reset(phydev); 1679c9b1f24SGiuseppe CAVALLARO if (c < 0) 1689c9b1f24SGiuseppe CAVALLARO return c; 1699c9b1f24SGiuseppe CAVALLARO 1709c9b1f24SGiuseppe CAVALLARO /* Enable Auto Power Saving mode */ 1719c9b1f24SGiuseppe CAVALLARO c = phy_read(phydev, IP10XX_SPEC_CTRL_STATUS); 172e3e09f26SGiuseppe CAVALLARO c |= IP101A_G_APS_ON; 173b3300146SSrinivas Kandagatla 174b3300146SSrinivas Kandagatla return phy_write(phydev, IP10XX_SPEC_CTRL_STATUS, c); 175377ecca9SGiuseppe CAVALLARO } 176377ecca9SGiuseppe CAVALLARO 1770cefeebaSMichael Barkowski static int ip175c_read_status(struct phy_device *phydev) 1780cefeebaSMichael Barkowski { 1790cefeebaSMichael Barkowski if (phydev->addr == 4) /* WAN port */ 1800cefeebaSMichael Barkowski genphy_read_status(phydev); 1810cefeebaSMichael Barkowski else 1820cefeebaSMichael Barkowski /* Don't need to read status for switch ports */ 1830cefeebaSMichael Barkowski phydev->irq = PHY_IGNORE_INTERRUPT; 1840cefeebaSMichael Barkowski 1850cefeebaSMichael Barkowski return 0; 1860cefeebaSMichael Barkowski } 1870cefeebaSMichael Barkowski 1880cefeebaSMichael Barkowski static int ip175c_config_aneg(struct phy_device *phydev) 1890cefeebaSMichael Barkowski { 1900cefeebaSMichael Barkowski if (phydev->addr == 4) /* WAN port */ 1910cefeebaSMichael Barkowski genphy_config_aneg(phydev); 1920cefeebaSMichael Barkowski 1930cefeebaSMichael Barkowski return 0; 1940cefeebaSMichael Barkowski } 1950cefeebaSMichael Barkowski 196996f7393SGiuseppe CAVALLARO static int ip101a_g_ack_interrupt(struct phy_device *phydev) 197996f7393SGiuseppe CAVALLARO { 198996f7393SGiuseppe CAVALLARO int err = phy_read(phydev, IP101A_G_IRQ_CONF_STATUS); 199996f7393SGiuseppe CAVALLARO if (err < 0) 200996f7393SGiuseppe CAVALLARO return err; 201996f7393SGiuseppe CAVALLARO 202996f7393SGiuseppe CAVALLARO return 0; 203996f7393SGiuseppe CAVALLARO } 204996f7393SGiuseppe CAVALLARO 205*d5bf9071SChristian Hohnstaedt static struct phy_driver icplus_driver[] = { 206*d5bf9071SChristian Hohnstaedt { 2070cefeebaSMichael Barkowski .phy_id = 0x02430d80, 2080cefeebaSMichael Barkowski .name = "ICPlus IP175C", 2090cefeebaSMichael Barkowski .phy_id_mask = 0x0ffffff0, 2100cefeebaSMichael Barkowski .features = PHY_BASIC_FEATURES, 2110cefeebaSMichael Barkowski .config_init = &ip175c_config_init, 2120cefeebaSMichael Barkowski .config_aneg = &ip175c_config_aneg, 2130cefeebaSMichael Barkowski .read_status = &ip175c_read_status, 214dab10863SGiuseppe Cavallaro .suspend = genphy_suspend, 215dab10863SGiuseppe Cavallaro .resume = genphy_resume, 2160cefeebaSMichael Barkowski .driver = { .owner = THIS_MODULE,}, 217*d5bf9071SChristian Hohnstaedt }, { 218377ecca9SGiuseppe CAVALLARO .phy_id = 0x02430d90, 219377ecca9SGiuseppe CAVALLARO .name = "ICPlus IP1001", 220377ecca9SGiuseppe CAVALLARO .phy_id_mask = 0x0ffffff0, 221377ecca9SGiuseppe CAVALLARO .features = PHY_GBIT_FEATURES | SUPPORTED_Pause | 222377ecca9SGiuseppe CAVALLARO SUPPORTED_Asym_Pause, 223377ecca9SGiuseppe CAVALLARO .config_init = &ip1001_config_init, 224377ecca9SGiuseppe CAVALLARO .config_aneg = &genphy_config_aneg, 225377ecca9SGiuseppe CAVALLARO .read_status = &genphy_read_status, 226377ecca9SGiuseppe CAVALLARO .suspend = genphy_suspend, 227377ecca9SGiuseppe CAVALLARO .resume = genphy_resume, 228377ecca9SGiuseppe CAVALLARO .driver = { .owner = THIS_MODULE,}, 229*d5bf9071SChristian Hohnstaedt }, { 2309c9b1f24SGiuseppe CAVALLARO .phy_id = 0x02430c54, 231e3e09f26SGiuseppe CAVALLARO .name = "ICPlus IP101A/G", 2329c9b1f24SGiuseppe CAVALLARO .phy_id_mask = 0x0ffffff0, 2339c9b1f24SGiuseppe CAVALLARO .features = PHY_BASIC_FEATURES | SUPPORTED_Pause | 2349c9b1f24SGiuseppe CAVALLARO SUPPORTED_Asym_Pause, 235e3e09f26SGiuseppe CAVALLARO .flags = PHY_HAS_INTERRUPT, 236996f7393SGiuseppe CAVALLARO .ack_interrupt = ip101a_g_ack_interrupt, 237e3e09f26SGiuseppe CAVALLARO .config_init = &ip101a_g_config_init, 2389c9b1f24SGiuseppe CAVALLARO .config_aneg = &genphy_config_aneg, 2399c9b1f24SGiuseppe CAVALLARO .read_status = &genphy_read_status, 2409c9b1f24SGiuseppe CAVALLARO .suspend = genphy_suspend, 2419c9b1f24SGiuseppe CAVALLARO .resume = genphy_resume, 2429c9b1f24SGiuseppe CAVALLARO .driver = { .owner = THIS_MODULE,}, 243*d5bf9071SChristian Hohnstaedt } }; 2449c9b1f24SGiuseppe CAVALLARO 245377ecca9SGiuseppe CAVALLARO static int __init icplus_init(void) 2460cefeebaSMichael Barkowski { 247*d5bf9071SChristian Hohnstaedt return phy_drivers_register(icplus_driver, 248*d5bf9071SChristian Hohnstaedt ARRAY_SIZE(icplus_driver)); 2490cefeebaSMichael Barkowski } 2500cefeebaSMichael Barkowski 251377ecca9SGiuseppe CAVALLARO static void __exit icplus_exit(void) 2520cefeebaSMichael Barkowski { 253*d5bf9071SChristian Hohnstaedt phy_drivers_unregister(icplus_driver, 254*d5bf9071SChristian Hohnstaedt ARRAY_SIZE(icplus_driver)); 2550cefeebaSMichael Barkowski } 2560cefeebaSMichael Barkowski 257377ecca9SGiuseppe CAVALLARO module_init(icplus_init); 258377ecca9SGiuseppe CAVALLARO module_exit(icplus_exit); 2594e4f10f6SDavid Woodhouse 260cf93c945SUwe Kleine-König static struct mdio_device_id __maybe_unused icplus_tbl[] = { 2614e4f10f6SDavid Woodhouse { 0x02430d80, 0x0ffffff0 }, 262377ecca9SGiuseppe CAVALLARO { 0x02430d90, 0x0ffffff0 }, 263e3e09f26SGiuseppe CAVALLARO { 0x02430c54, 0x0ffffff0 }, 2644e4f10f6SDavid Woodhouse { } 2654e4f10f6SDavid Woodhouse }; 2664e4f10f6SDavid Woodhouse 2674e4f10f6SDavid Woodhouse MODULE_DEVICE_TABLE(mdio, icplus_tbl); 268