10cefeebaSMichael Barkowski /* 20cefeebaSMichael Barkowski * Driver for ICPlus PHYs 30cefeebaSMichael Barkowski * 40cefeebaSMichael Barkowski * Copyright (c) 2007 Freescale Semiconductor, Inc. 50cefeebaSMichael Barkowski * 60cefeebaSMichael Barkowski * This program is free software; you can redistribute it and/or modify it 70cefeebaSMichael Barkowski * under the terms of the GNU General Public License as published by the 80cefeebaSMichael Barkowski * Free Software Foundation; either version 2 of the License, or (at your 90cefeebaSMichael Barkowski * option) any later version. 100cefeebaSMichael Barkowski * 110cefeebaSMichael Barkowski */ 120cefeebaSMichael Barkowski #include <linux/kernel.h> 130cefeebaSMichael Barkowski #include <linux/string.h> 140cefeebaSMichael Barkowski #include <linux/errno.h> 150cefeebaSMichael Barkowski #include <linux/unistd.h> 160cefeebaSMichael Barkowski #include <linux/interrupt.h> 170cefeebaSMichael Barkowski #include <linux/init.h> 180cefeebaSMichael Barkowski #include <linux/delay.h> 190cefeebaSMichael Barkowski #include <linux/netdevice.h> 200cefeebaSMichael Barkowski #include <linux/etherdevice.h> 210cefeebaSMichael Barkowski #include <linux/skbuff.h> 220cefeebaSMichael Barkowski #include <linux/spinlock.h> 230cefeebaSMichael Barkowski #include <linux/mm.h> 240cefeebaSMichael Barkowski #include <linux/module.h> 250cefeebaSMichael Barkowski #include <linux/mii.h> 260cefeebaSMichael Barkowski #include <linux/ethtool.h> 270cefeebaSMichael Barkowski #include <linux/phy.h> 280cefeebaSMichael Barkowski 290cefeebaSMichael Barkowski #include <asm/io.h> 300cefeebaSMichael Barkowski #include <asm/irq.h> 310cefeebaSMichael Barkowski #include <asm/uaccess.h> 320cefeebaSMichael Barkowski 33e3e09f26SGiuseppe CAVALLARO MODULE_DESCRIPTION("ICPlus IP175C/IP101A/IP101G/IC1001 PHY drivers"); 340cefeebaSMichael Barkowski MODULE_AUTHOR("Michael Barkowski"); 350cefeebaSMichael Barkowski MODULE_LICENSE("GPL"); 360cefeebaSMichael Barkowski 37e3e09f26SGiuseppe CAVALLARO /* IP101A/G - IP1001 */ 389c9b1f24SGiuseppe CAVALLARO #define IP10XX_SPEC_CTRL_STATUS 16 /* Spec. Control Register */ 399c9b1f24SGiuseppe CAVALLARO #define IP1001_SPEC_CTRL_STATUS_2 20 /* IP1001 Spec. Control Reg 2 */ 409c9b1f24SGiuseppe CAVALLARO #define IP1001_PHASE_SEL_MASK 3 /* IP1001 RX/TXPHASE_SEL */ 419c9b1f24SGiuseppe CAVALLARO #define IP1001_APS_ON 11 /* IP1001 APS Mode bit */ 42e3e09f26SGiuseppe CAVALLARO #define IP101A_G_APS_ON 2 /* IP101A/G APS Mode bit */ 439c9b1f24SGiuseppe CAVALLARO 440cefeebaSMichael Barkowski static int ip175c_config_init(struct phy_device *phydev) 450cefeebaSMichael Barkowski { 460cefeebaSMichael Barkowski int err, i; 470cefeebaSMichael Barkowski static int full_reset_performed = 0; 480cefeebaSMichael Barkowski 490cefeebaSMichael Barkowski if (full_reset_performed == 0) { 500cefeebaSMichael Barkowski 510cefeebaSMichael Barkowski /* master reset */ 5276231e02SDavid Daney err = mdiobus_write(phydev->bus, 30, 0, 0x175c); 530cefeebaSMichael Barkowski if (err < 0) 540cefeebaSMichael Barkowski return err; 550cefeebaSMichael Barkowski 560cefeebaSMichael Barkowski /* ensure no bus delays overlap reset period */ 5776231e02SDavid Daney err = mdiobus_read(phydev->bus, 30, 0); 580cefeebaSMichael Barkowski 590cefeebaSMichael Barkowski /* data sheet specifies reset period is 2 msec */ 600cefeebaSMichael Barkowski mdelay(2); 610cefeebaSMichael Barkowski 620cefeebaSMichael Barkowski /* enable IP175C mode */ 6376231e02SDavid Daney err = mdiobus_write(phydev->bus, 29, 31, 0x175c); 640cefeebaSMichael Barkowski if (err < 0) 650cefeebaSMichael Barkowski return err; 660cefeebaSMichael Barkowski 670cefeebaSMichael Barkowski /* Set MII0 speed and duplex (in PHY mode) */ 6876231e02SDavid Daney err = mdiobus_write(phydev->bus, 29, 22, 0x420); 690cefeebaSMichael Barkowski if (err < 0) 700cefeebaSMichael Barkowski return err; 710cefeebaSMichael Barkowski 720cefeebaSMichael Barkowski /* reset switch ports */ 730cefeebaSMichael Barkowski for (i = 0; i < 5; i++) { 7476231e02SDavid Daney err = mdiobus_write(phydev->bus, i, 750cefeebaSMichael Barkowski MII_BMCR, BMCR_RESET); 760cefeebaSMichael Barkowski if (err < 0) 770cefeebaSMichael Barkowski return err; 780cefeebaSMichael Barkowski } 790cefeebaSMichael Barkowski 800cefeebaSMichael Barkowski for (i = 0; i < 5; i++) 8176231e02SDavid Daney err = mdiobus_read(phydev->bus, i, MII_BMCR); 820cefeebaSMichael Barkowski 830cefeebaSMichael Barkowski mdelay(2); 840cefeebaSMichael Barkowski 850cefeebaSMichael Barkowski full_reset_performed = 1; 860cefeebaSMichael Barkowski } 870cefeebaSMichael Barkowski 880cefeebaSMichael Barkowski if (phydev->addr != 4) { 890cefeebaSMichael Barkowski phydev->state = PHY_RUNNING; 900cefeebaSMichael Barkowski phydev->speed = SPEED_100; 910cefeebaSMichael Barkowski phydev->duplex = DUPLEX_FULL; 920cefeebaSMichael Barkowski phydev->link = 1; 930cefeebaSMichael Barkowski netif_carrier_on(phydev->attached_dev); 940cefeebaSMichael Barkowski } 950cefeebaSMichael Barkowski 960cefeebaSMichael Barkowski return 0; 970cefeebaSMichael Barkowski } 980cefeebaSMichael Barkowski 999c9b1f24SGiuseppe CAVALLARO static int ip1xx_reset(struct phy_device *phydev) 100377ecca9SGiuseppe CAVALLARO { 101b8e3995aSDavid McKay int bmcr; 102377ecca9SGiuseppe CAVALLARO 103377ecca9SGiuseppe CAVALLARO /* Software Reset PHY */ 1049c9b1f24SGiuseppe CAVALLARO bmcr = phy_read(phydev, MII_BMCR); 105b8e3995aSDavid McKay if (bmcr < 0) 106b8e3995aSDavid McKay return bmcr; 1079c9b1f24SGiuseppe CAVALLARO bmcr |= BMCR_RESET; 108b8e3995aSDavid McKay bmcr = phy_write(phydev, MII_BMCR, bmcr); 109b8e3995aSDavid McKay if (bmcr < 0) 110b8e3995aSDavid McKay return bmcr; 111377ecca9SGiuseppe CAVALLARO 112377ecca9SGiuseppe CAVALLARO do { 1139c9b1f24SGiuseppe CAVALLARO bmcr = phy_read(phydev, MII_BMCR); 114b8e3995aSDavid McKay if (bmcr < 0) 115b8e3995aSDavid McKay return bmcr; 1169c9b1f24SGiuseppe CAVALLARO } while (bmcr & BMCR_RESET); 1179c9b1f24SGiuseppe CAVALLARO 118b8e3995aSDavid McKay return 0; 1199c9b1f24SGiuseppe CAVALLARO } 1209c9b1f24SGiuseppe CAVALLARO 1219c9b1f24SGiuseppe CAVALLARO static int ip1001_config_init(struct phy_device *phydev) 1229c9b1f24SGiuseppe CAVALLARO { 1239c9b1f24SGiuseppe CAVALLARO int c; 1249c9b1f24SGiuseppe CAVALLARO 1259c9b1f24SGiuseppe CAVALLARO c = ip1xx_reset(phydev); 1269c9b1f24SGiuseppe CAVALLARO if (c < 0) 1279c9b1f24SGiuseppe CAVALLARO return c; 1289c9b1f24SGiuseppe CAVALLARO 1299c9b1f24SGiuseppe CAVALLARO /* Enable Auto Power Saving mode */ 1309c9b1f24SGiuseppe CAVALLARO c = phy_read(phydev, IP1001_SPEC_CTRL_STATUS_2); 131b8e3995aSDavid McKay if (c < 0) 132b8e3995aSDavid McKay return c; 1339c9b1f24SGiuseppe CAVALLARO c |= IP1001_APS_ON; 134b8e3995aSDavid McKay c = phy_write(phydev, IP1001_SPEC_CTRL_STATUS_2, c); 1359c9b1f24SGiuseppe CAVALLARO if (c < 0) 1369c9b1f24SGiuseppe CAVALLARO return c; 137377ecca9SGiuseppe CAVALLARO 138a4886d52SGiuseppe CAVALLARO if (phydev->interface == PHY_INTERFACE_MODE_RGMII) { 139377ecca9SGiuseppe CAVALLARO /* Additional delay (2ns) used to adjust RX clock phase 140a4886d52SGiuseppe CAVALLARO * at RGMII interface */ 1419c9b1f24SGiuseppe CAVALLARO c = phy_read(phydev, IP10XX_SPEC_CTRL_STATUS); 142b8e3995aSDavid McKay if (c < 0) 143b8e3995aSDavid McKay return c; 144b8e3995aSDavid McKay 1459c9b1f24SGiuseppe CAVALLARO c |= IP1001_PHASE_SEL_MASK; 146a4886d52SGiuseppe CAVALLARO c = phy_write(phydev, IP10XX_SPEC_CTRL_STATUS, c); 147b8e3995aSDavid McKay if (c < 0) 148b8e3995aSDavid McKay return c; 149a4886d52SGiuseppe CAVALLARO } 150377ecca9SGiuseppe CAVALLARO 151b8e3995aSDavid McKay return 0; 1529c9b1f24SGiuseppe CAVALLARO } 1539c9b1f24SGiuseppe CAVALLARO 154e3e09f26SGiuseppe CAVALLARO static int ip101a_g_config_init(struct phy_device *phydev) 1559c9b1f24SGiuseppe CAVALLARO { 1569c9b1f24SGiuseppe CAVALLARO int c; 1579c9b1f24SGiuseppe CAVALLARO 1589c9b1f24SGiuseppe CAVALLARO c = ip1xx_reset(phydev); 1599c9b1f24SGiuseppe CAVALLARO if (c < 0) 1609c9b1f24SGiuseppe CAVALLARO return c; 1619c9b1f24SGiuseppe CAVALLARO 1629c9b1f24SGiuseppe CAVALLARO /* Enable Auto Power Saving mode */ 1639c9b1f24SGiuseppe CAVALLARO c = phy_read(phydev, IP10XX_SPEC_CTRL_STATUS); 164e3e09f26SGiuseppe CAVALLARO c |= IP101A_G_APS_ON; 165*b3300146SSrinivas Kandagatla 166*b3300146SSrinivas Kandagatla return phy_write(phydev, IP10XX_SPEC_CTRL_STATUS, c); 167377ecca9SGiuseppe CAVALLARO } 168377ecca9SGiuseppe CAVALLARO 1690cefeebaSMichael Barkowski static int ip175c_read_status(struct phy_device *phydev) 1700cefeebaSMichael Barkowski { 1710cefeebaSMichael Barkowski if (phydev->addr == 4) /* WAN port */ 1720cefeebaSMichael Barkowski genphy_read_status(phydev); 1730cefeebaSMichael Barkowski else 1740cefeebaSMichael Barkowski /* Don't need to read status for switch ports */ 1750cefeebaSMichael Barkowski phydev->irq = PHY_IGNORE_INTERRUPT; 1760cefeebaSMichael Barkowski 1770cefeebaSMichael Barkowski return 0; 1780cefeebaSMichael Barkowski } 1790cefeebaSMichael Barkowski 1800cefeebaSMichael Barkowski static int ip175c_config_aneg(struct phy_device *phydev) 1810cefeebaSMichael Barkowski { 1820cefeebaSMichael Barkowski if (phydev->addr == 4) /* WAN port */ 1830cefeebaSMichael Barkowski genphy_config_aneg(phydev); 1840cefeebaSMichael Barkowski 1850cefeebaSMichael Barkowski return 0; 1860cefeebaSMichael Barkowski } 1870cefeebaSMichael Barkowski 1880cefeebaSMichael Barkowski static struct phy_driver ip175c_driver = { 1890cefeebaSMichael Barkowski .phy_id = 0x02430d80, 1900cefeebaSMichael Barkowski .name = "ICPlus IP175C", 1910cefeebaSMichael Barkowski .phy_id_mask = 0x0ffffff0, 1920cefeebaSMichael Barkowski .features = PHY_BASIC_FEATURES, 1930cefeebaSMichael Barkowski .config_init = &ip175c_config_init, 1940cefeebaSMichael Barkowski .config_aneg = &ip175c_config_aneg, 1950cefeebaSMichael Barkowski .read_status = &ip175c_read_status, 196dab10863SGiuseppe Cavallaro .suspend = genphy_suspend, 197dab10863SGiuseppe Cavallaro .resume = genphy_resume, 1980cefeebaSMichael Barkowski .driver = { .owner = THIS_MODULE,}, 1990cefeebaSMichael Barkowski }; 2000cefeebaSMichael Barkowski 201377ecca9SGiuseppe CAVALLARO static struct phy_driver ip1001_driver = { 202377ecca9SGiuseppe CAVALLARO .phy_id = 0x02430d90, 203377ecca9SGiuseppe CAVALLARO .name = "ICPlus IP1001", 204377ecca9SGiuseppe CAVALLARO .phy_id_mask = 0x0ffffff0, 205377ecca9SGiuseppe CAVALLARO .features = PHY_GBIT_FEATURES | SUPPORTED_Pause | 206377ecca9SGiuseppe CAVALLARO SUPPORTED_Asym_Pause, 207e3e09f26SGiuseppe CAVALLARO .flags = PHY_HAS_INTERRUPT, 208377ecca9SGiuseppe CAVALLARO .config_init = &ip1001_config_init, 209377ecca9SGiuseppe CAVALLARO .config_aneg = &genphy_config_aneg, 210377ecca9SGiuseppe CAVALLARO .read_status = &genphy_read_status, 211377ecca9SGiuseppe CAVALLARO .suspend = genphy_suspend, 212377ecca9SGiuseppe CAVALLARO .resume = genphy_resume, 213377ecca9SGiuseppe CAVALLARO .driver = { .owner = THIS_MODULE,}, 214377ecca9SGiuseppe CAVALLARO }; 215377ecca9SGiuseppe CAVALLARO 216e3e09f26SGiuseppe CAVALLARO static struct phy_driver ip101a_g_driver = { 2179c9b1f24SGiuseppe CAVALLARO .phy_id = 0x02430c54, 218e3e09f26SGiuseppe CAVALLARO .name = "ICPlus IP101A/G", 2199c9b1f24SGiuseppe CAVALLARO .phy_id_mask = 0x0ffffff0, 2209c9b1f24SGiuseppe CAVALLARO .features = PHY_BASIC_FEATURES | SUPPORTED_Pause | 2219c9b1f24SGiuseppe CAVALLARO SUPPORTED_Asym_Pause, 222e3e09f26SGiuseppe CAVALLARO .flags = PHY_HAS_INTERRUPT, 223e3e09f26SGiuseppe CAVALLARO .config_init = &ip101a_g_config_init, 2249c9b1f24SGiuseppe CAVALLARO .config_aneg = &genphy_config_aneg, 2259c9b1f24SGiuseppe CAVALLARO .read_status = &genphy_read_status, 2269c9b1f24SGiuseppe CAVALLARO .suspend = genphy_suspend, 2279c9b1f24SGiuseppe CAVALLARO .resume = genphy_resume, 2289c9b1f24SGiuseppe CAVALLARO .driver = { .owner = THIS_MODULE,}, 2299c9b1f24SGiuseppe CAVALLARO }; 2309c9b1f24SGiuseppe CAVALLARO 231377ecca9SGiuseppe CAVALLARO static int __init icplus_init(void) 2320cefeebaSMichael Barkowski { 233377ecca9SGiuseppe CAVALLARO int ret = 0; 234377ecca9SGiuseppe CAVALLARO 235377ecca9SGiuseppe CAVALLARO ret = phy_driver_register(&ip1001_driver); 236377ecca9SGiuseppe CAVALLARO if (ret < 0) 237377ecca9SGiuseppe CAVALLARO return -ENODEV; 238377ecca9SGiuseppe CAVALLARO 239e3e09f26SGiuseppe CAVALLARO ret = phy_driver_register(&ip101a_g_driver); 2409c9b1f24SGiuseppe CAVALLARO if (ret < 0) 2419c9b1f24SGiuseppe CAVALLARO return -ENODEV; 2429c9b1f24SGiuseppe CAVALLARO 2430cefeebaSMichael Barkowski return phy_driver_register(&ip175c_driver); 2440cefeebaSMichael Barkowski } 2450cefeebaSMichael Barkowski 246377ecca9SGiuseppe CAVALLARO static void __exit icplus_exit(void) 2470cefeebaSMichael Barkowski { 248377ecca9SGiuseppe CAVALLARO phy_driver_unregister(&ip1001_driver); 249e3e09f26SGiuseppe CAVALLARO phy_driver_unregister(&ip101a_g_driver); 2500cefeebaSMichael Barkowski phy_driver_unregister(&ip175c_driver); 2510cefeebaSMichael Barkowski } 2520cefeebaSMichael Barkowski 253377ecca9SGiuseppe CAVALLARO module_init(icplus_init); 254377ecca9SGiuseppe CAVALLARO module_exit(icplus_exit); 2554e4f10f6SDavid Woodhouse 256cf93c945SUwe Kleine-König static struct mdio_device_id __maybe_unused icplus_tbl[] = { 2574e4f10f6SDavid Woodhouse { 0x02430d80, 0x0ffffff0 }, 258377ecca9SGiuseppe CAVALLARO { 0x02430d90, 0x0ffffff0 }, 259e3e09f26SGiuseppe CAVALLARO { 0x02430c54, 0x0ffffff0 }, 2604e4f10f6SDavid Woodhouse { } 2614e4f10f6SDavid Woodhouse }; 2624e4f10f6SDavid Woodhouse 2634e4f10f6SDavid Woodhouse MODULE_DEVICE_TABLE(mdio, icplus_tbl); 264