10cefeebaSMichael Barkowski /* 20cefeebaSMichael Barkowski * Driver for ICPlus PHYs 30cefeebaSMichael Barkowski * 40cefeebaSMichael Barkowski * Copyright (c) 2007 Freescale Semiconductor, Inc. 50cefeebaSMichael Barkowski * 60cefeebaSMichael Barkowski * This program is free software; you can redistribute it and/or modify it 70cefeebaSMichael Barkowski * under the terms of the GNU General Public License as published by the 80cefeebaSMichael Barkowski * Free Software Foundation; either version 2 of the License, or (at your 90cefeebaSMichael Barkowski * option) any later version. 100cefeebaSMichael Barkowski * 110cefeebaSMichael Barkowski */ 120cefeebaSMichael Barkowski #include <linux/kernel.h> 130cefeebaSMichael Barkowski #include <linux/string.h> 140cefeebaSMichael Barkowski #include <linux/errno.h> 150cefeebaSMichael Barkowski #include <linux/unistd.h> 160cefeebaSMichael Barkowski #include <linux/interrupt.h> 170cefeebaSMichael Barkowski #include <linux/init.h> 180cefeebaSMichael Barkowski #include <linux/delay.h> 190cefeebaSMichael Barkowski #include <linux/netdevice.h> 200cefeebaSMichael Barkowski #include <linux/etherdevice.h> 210cefeebaSMichael Barkowski #include <linux/skbuff.h> 220cefeebaSMichael Barkowski #include <linux/spinlock.h> 230cefeebaSMichael Barkowski #include <linux/mm.h> 240cefeebaSMichael Barkowski #include <linux/module.h> 250cefeebaSMichael Barkowski #include <linux/mii.h> 260cefeebaSMichael Barkowski #include <linux/ethtool.h> 270cefeebaSMichael Barkowski #include <linux/phy.h> 280cefeebaSMichael Barkowski 290cefeebaSMichael Barkowski #include <asm/io.h> 300cefeebaSMichael Barkowski #include <asm/irq.h> 310cefeebaSMichael Barkowski #include <asm/uaccess.h> 320cefeebaSMichael Barkowski 33e3e09f26SGiuseppe CAVALLARO MODULE_DESCRIPTION("ICPlus IP175C/IP101A/IP101G/IC1001 PHY drivers"); 340cefeebaSMichael Barkowski MODULE_AUTHOR("Michael Barkowski"); 350cefeebaSMichael Barkowski MODULE_LICENSE("GPL"); 360cefeebaSMichael Barkowski 37e3e09f26SGiuseppe CAVALLARO /* IP101A/G - IP1001 */ 389c9b1f24SGiuseppe CAVALLARO #define IP10XX_SPEC_CTRL_STATUS 16 /* Spec. Control Register */ 399c9b1f24SGiuseppe CAVALLARO #define IP1001_SPEC_CTRL_STATUS_2 20 /* IP1001 Spec. Control Reg 2 */ 409c9b1f24SGiuseppe CAVALLARO #define IP1001_PHASE_SEL_MASK 3 /* IP1001 RX/TXPHASE_SEL */ 419c9b1f24SGiuseppe CAVALLARO #define IP1001_APS_ON 11 /* IP1001 APS Mode bit */ 42e3e09f26SGiuseppe CAVALLARO #define IP101A_G_APS_ON 2 /* IP101A/G APS Mode bit */ 43*996f7393SGiuseppe CAVALLARO #define IP101A_G_IRQ_CONF_STATUS 0x11 /* Conf Info IRQ & Status Reg */ 449c9b1f24SGiuseppe CAVALLARO 450cefeebaSMichael Barkowski static int ip175c_config_init(struct phy_device *phydev) 460cefeebaSMichael Barkowski { 470cefeebaSMichael Barkowski int err, i; 480cefeebaSMichael Barkowski static int full_reset_performed = 0; 490cefeebaSMichael Barkowski 500cefeebaSMichael Barkowski if (full_reset_performed == 0) { 510cefeebaSMichael Barkowski 520cefeebaSMichael Barkowski /* master reset */ 5376231e02SDavid Daney err = mdiobus_write(phydev->bus, 30, 0, 0x175c); 540cefeebaSMichael Barkowski if (err < 0) 550cefeebaSMichael Barkowski return err; 560cefeebaSMichael Barkowski 570cefeebaSMichael Barkowski /* ensure no bus delays overlap reset period */ 5876231e02SDavid Daney err = mdiobus_read(phydev->bus, 30, 0); 590cefeebaSMichael Barkowski 600cefeebaSMichael Barkowski /* data sheet specifies reset period is 2 msec */ 610cefeebaSMichael Barkowski mdelay(2); 620cefeebaSMichael Barkowski 630cefeebaSMichael Barkowski /* enable IP175C mode */ 6476231e02SDavid Daney err = mdiobus_write(phydev->bus, 29, 31, 0x175c); 650cefeebaSMichael Barkowski if (err < 0) 660cefeebaSMichael Barkowski return err; 670cefeebaSMichael Barkowski 680cefeebaSMichael Barkowski /* Set MII0 speed and duplex (in PHY mode) */ 6976231e02SDavid Daney err = mdiobus_write(phydev->bus, 29, 22, 0x420); 700cefeebaSMichael Barkowski if (err < 0) 710cefeebaSMichael Barkowski return err; 720cefeebaSMichael Barkowski 730cefeebaSMichael Barkowski /* reset switch ports */ 740cefeebaSMichael Barkowski for (i = 0; i < 5; i++) { 7576231e02SDavid Daney err = mdiobus_write(phydev->bus, i, 760cefeebaSMichael Barkowski MII_BMCR, BMCR_RESET); 770cefeebaSMichael Barkowski if (err < 0) 780cefeebaSMichael Barkowski return err; 790cefeebaSMichael Barkowski } 800cefeebaSMichael Barkowski 810cefeebaSMichael Barkowski for (i = 0; i < 5; i++) 8276231e02SDavid Daney err = mdiobus_read(phydev->bus, i, MII_BMCR); 830cefeebaSMichael Barkowski 840cefeebaSMichael Barkowski mdelay(2); 850cefeebaSMichael Barkowski 860cefeebaSMichael Barkowski full_reset_performed = 1; 870cefeebaSMichael Barkowski } 880cefeebaSMichael Barkowski 890cefeebaSMichael Barkowski if (phydev->addr != 4) { 900cefeebaSMichael Barkowski phydev->state = PHY_RUNNING; 910cefeebaSMichael Barkowski phydev->speed = SPEED_100; 920cefeebaSMichael Barkowski phydev->duplex = DUPLEX_FULL; 930cefeebaSMichael Barkowski phydev->link = 1; 940cefeebaSMichael Barkowski netif_carrier_on(phydev->attached_dev); 950cefeebaSMichael Barkowski } 960cefeebaSMichael Barkowski 970cefeebaSMichael Barkowski return 0; 980cefeebaSMichael Barkowski } 990cefeebaSMichael Barkowski 1009c9b1f24SGiuseppe CAVALLARO static int ip1xx_reset(struct phy_device *phydev) 101377ecca9SGiuseppe CAVALLARO { 102b8e3995aSDavid McKay int bmcr; 103377ecca9SGiuseppe CAVALLARO 104377ecca9SGiuseppe CAVALLARO /* Software Reset PHY */ 1059c9b1f24SGiuseppe CAVALLARO bmcr = phy_read(phydev, MII_BMCR); 106b8e3995aSDavid McKay if (bmcr < 0) 107b8e3995aSDavid McKay return bmcr; 1089c9b1f24SGiuseppe CAVALLARO bmcr |= BMCR_RESET; 109b8e3995aSDavid McKay bmcr = phy_write(phydev, MII_BMCR, bmcr); 110b8e3995aSDavid McKay if (bmcr < 0) 111b8e3995aSDavid McKay return bmcr; 112377ecca9SGiuseppe CAVALLARO 113377ecca9SGiuseppe CAVALLARO do { 1149c9b1f24SGiuseppe CAVALLARO bmcr = phy_read(phydev, MII_BMCR); 115b8e3995aSDavid McKay if (bmcr < 0) 116b8e3995aSDavid McKay return bmcr; 1179c9b1f24SGiuseppe CAVALLARO } while (bmcr & BMCR_RESET); 1189c9b1f24SGiuseppe CAVALLARO 119b8e3995aSDavid McKay return 0; 1209c9b1f24SGiuseppe CAVALLARO } 1219c9b1f24SGiuseppe CAVALLARO 1229c9b1f24SGiuseppe CAVALLARO static int ip1001_config_init(struct phy_device *phydev) 1239c9b1f24SGiuseppe CAVALLARO { 1249c9b1f24SGiuseppe CAVALLARO int c; 1259c9b1f24SGiuseppe CAVALLARO 1269c9b1f24SGiuseppe CAVALLARO c = ip1xx_reset(phydev); 1279c9b1f24SGiuseppe CAVALLARO if (c < 0) 1289c9b1f24SGiuseppe CAVALLARO return c; 1299c9b1f24SGiuseppe CAVALLARO 1309c9b1f24SGiuseppe CAVALLARO /* Enable Auto Power Saving mode */ 1319c9b1f24SGiuseppe CAVALLARO c = phy_read(phydev, IP1001_SPEC_CTRL_STATUS_2); 132b8e3995aSDavid McKay if (c < 0) 133b8e3995aSDavid McKay return c; 1349c9b1f24SGiuseppe CAVALLARO c |= IP1001_APS_ON; 135b8e3995aSDavid McKay c = phy_write(phydev, IP1001_SPEC_CTRL_STATUS_2, c); 1369c9b1f24SGiuseppe CAVALLARO if (c < 0) 1379c9b1f24SGiuseppe CAVALLARO return c; 138377ecca9SGiuseppe CAVALLARO 139a4886d52SGiuseppe CAVALLARO if (phydev->interface == PHY_INTERFACE_MODE_RGMII) { 140377ecca9SGiuseppe CAVALLARO /* Additional delay (2ns) used to adjust RX clock phase 141a4886d52SGiuseppe CAVALLARO * at RGMII interface */ 1429c9b1f24SGiuseppe CAVALLARO c = phy_read(phydev, IP10XX_SPEC_CTRL_STATUS); 143b8e3995aSDavid McKay if (c < 0) 144b8e3995aSDavid McKay return c; 145b8e3995aSDavid McKay 1469c9b1f24SGiuseppe CAVALLARO c |= IP1001_PHASE_SEL_MASK; 147a4886d52SGiuseppe CAVALLARO c = phy_write(phydev, IP10XX_SPEC_CTRL_STATUS, c); 148b8e3995aSDavid McKay if (c < 0) 149b8e3995aSDavid McKay return c; 150a4886d52SGiuseppe CAVALLARO } 151377ecca9SGiuseppe CAVALLARO 152b8e3995aSDavid McKay return 0; 1539c9b1f24SGiuseppe CAVALLARO } 1549c9b1f24SGiuseppe CAVALLARO 155e3e09f26SGiuseppe CAVALLARO static int ip101a_g_config_init(struct phy_device *phydev) 1569c9b1f24SGiuseppe CAVALLARO { 1579c9b1f24SGiuseppe CAVALLARO int c; 1589c9b1f24SGiuseppe CAVALLARO 1599c9b1f24SGiuseppe CAVALLARO c = ip1xx_reset(phydev); 1609c9b1f24SGiuseppe CAVALLARO if (c < 0) 1619c9b1f24SGiuseppe CAVALLARO return c; 1629c9b1f24SGiuseppe CAVALLARO 1639c9b1f24SGiuseppe CAVALLARO /* Enable Auto Power Saving mode */ 1649c9b1f24SGiuseppe CAVALLARO c = phy_read(phydev, IP10XX_SPEC_CTRL_STATUS); 165e3e09f26SGiuseppe CAVALLARO c |= IP101A_G_APS_ON; 166b3300146SSrinivas Kandagatla 167b3300146SSrinivas Kandagatla return phy_write(phydev, IP10XX_SPEC_CTRL_STATUS, c); 168377ecca9SGiuseppe CAVALLARO } 169377ecca9SGiuseppe CAVALLARO 1700cefeebaSMichael Barkowski static int ip175c_read_status(struct phy_device *phydev) 1710cefeebaSMichael Barkowski { 1720cefeebaSMichael Barkowski if (phydev->addr == 4) /* WAN port */ 1730cefeebaSMichael Barkowski genphy_read_status(phydev); 1740cefeebaSMichael Barkowski else 1750cefeebaSMichael Barkowski /* Don't need to read status for switch ports */ 1760cefeebaSMichael Barkowski phydev->irq = PHY_IGNORE_INTERRUPT; 1770cefeebaSMichael Barkowski 1780cefeebaSMichael Barkowski return 0; 1790cefeebaSMichael Barkowski } 1800cefeebaSMichael Barkowski 1810cefeebaSMichael Barkowski static int ip175c_config_aneg(struct phy_device *phydev) 1820cefeebaSMichael Barkowski { 1830cefeebaSMichael Barkowski if (phydev->addr == 4) /* WAN port */ 1840cefeebaSMichael Barkowski genphy_config_aneg(phydev); 1850cefeebaSMichael Barkowski 1860cefeebaSMichael Barkowski return 0; 1870cefeebaSMichael Barkowski } 1880cefeebaSMichael Barkowski 189*996f7393SGiuseppe CAVALLARO static int ip101a_g_ack_interrupt(struct phy_device *phydev) 190*996f7393SGiuseppe CAVALLARO { 191*996f7393SGiuseppe CAVALLARO int err = phy_read(phydev, IP101A_G_IRQ_CONF_STATUS); 192*996f7393SGiuseppe CAVALLARO if (err < 0) 193*996f7393SGiuseppe CAVALLARO return err; 194*996f7393SGiuseppe CAVALLARO 195*996f7393SGiuseppe CAVALLARO return 0; 196*996f7393SGiuseppe CAVALLARO } 197*996f7393SGiuseppe CAVALLARO 1980cefeebaSMichael Barkowski static struct phy_driver ip175c_driver = { 1990cefeebaSMichael Barkowski .phy_id = 0x02430d80, 2000cefeebaSMichael Barkowski .name = "ICPlus IP175C", 2010cefeebaSMichael Barkowski .phy_id_mask = 0x0ffffff0, 2020cefeebaSMichael Barkowski .features = PHY_BASIC_FEATURES, 2030cefeebaSMichael Barkowski .config_init = &ip175c_config_init, 2040cefeebaSMichael Barkowski .config_aneg = &ip175c_config_aneg, 2050cefeebaSMichael Barkowski .read_status = &ip175c_read_status, 206dab10863SGiuseppe Cavallaro .suspend = genphy_suspend, 207dab10863SGiuseppe Cavallaro .resume = genphy_resume, 2080cefeebaSMichael Barkowski .driver = { .owner = THIS_MODULE,}, 2090cefeebaSMichael Barkowski }; 2100cefeebaSMichael Barkowski 211377ecca9SGiuseppe CAVALLARO static struct phy_driver ip1001_driver = { 212377ecca9SGiuseppe CAVALLARO .phy_id = 0x02430d90, 213377ecca9SGiuseppe CAVALLARO .name = "ICPlus IP1001", 214377ecca9SGiuseppe CAVALLARO .phy_id_mask = 0x0ffffff0, 215377ecca9SGiuseppe CAVALLARO .features = PHY_GBIT_FEATURES | SUPPORTED_Pause | 216377ecca9SGiuseppe CAVALLARO SUPPORTED_Asym_Pause, 217377ecca9SGiuseppe CAVALLARO .config_init = &ip1001_config_init, 218377ecca9SGiuseppe CAVALLARO .config_aneg = &genphy_config_aneg, 219377ecca9SGiuseppe CAVALLARO .read_status = &genphy_read_status, 220377ecca9SGiuseppe CAVALLARO .suspend = genphy_suspend, 221377ecca9SGiuseppe CAVALLARO .resume = genphy_resume, 222377ecca9SGiuseppe CAVALLARO .driver = { .owner = THIS_MODULE,}, 223377ecca9SGiuseppe CAVALLARO }; 224377ecca9SGiuseppe CAVALLARO 225e3e09f26SGiuseppe CAVALLARO static struct phy_driver ip101a_g_driver = { 2269c9b1f24SGiuseppe CAVALLARO .phy_id = 0x02430c54, 227e3e09f26SGiuseppe CAVALLARO .name = "ICPlus IP101A/G", 2289c9b1f24SGiuseppe CAVALLARO .phy_id_mask = 0x0ffffff0, 2299c9b1f24SGiuseppe CAVALLARO .features = PHY_BASIC_FEATURES | SUPPORTED_Pause | 2309c9b1f24SGiuseppe CAVALLARO SUPPORTED_Asym_Pause, 231e3e09f26SGiuseppe CAVALLARO .flags = PHY_HAS_INTERRUPT, 232*996f7393SGiuseppe CAVALLARO .ack_interrupt = ip101a_g_ack_interrupt, 233e3e09f26SGiuseppe CAVALLARO .config_init = &ip101a_g_config_init, 2349c9b1f24SGiuseppe CAVALLARO .config_aneg = &genphy_config_aneg, 2359c9b1f24SGiuseppe CAVALLARO .read_status = &genphy_read_status, 2369c9b1f24SGiuseppe CAVALLARO .suspend = genphy_suspend, 2379c9b1f24SGiuseppe CAVALLARO .resume = genphy_resume, 2389c9b1f24SGiuseppe CAVALLARO .driver = { .owner = THIS_MODULE,}, 2399c9b1f24SGiuseppe CAVALLARO }; 2409c9b1f24SGiuseppe CAVALLARO 241377ecca9SGiuseppe CAVALLARO static int __init icplus_init(void) 2420cefeebaSMichael Barkowski { 243377ecca9SGiuseppe CAVALLARO int ret = 0; 244377ecca9SGiuseppe CAVALLARO 245377ecca9SGiuseppe CAVALLARO ret = phy_driver_register(&ip1001_driver); 246377ecca9SGiuseppe CAVALLARO if (ret < 0) 247377ecca9SGiuseppe CAVALLARO return -ENODEV; 248377ecca9SGiuseppe CAVALLARO 249e3e09f26SGiuseppe CAVALLARO ret = phy_driver_register(&ip101a_g_driver); 2509c9b1f24SGiuseppe CAVALLARO if (ret < 0) 2519c9b1f24SGiuseppe CAVALLARO return -ENODEV; 2529c9b1f24SGiuseppe CAVALLARO 2530cefeebaSMichael Barkowski return phy_driver_register(&ip175c_driver); 2540cefeebaSMichael Barkowski } 2550cefeebaSMichael Barkowski 256377ecca9SGiuseppe CAVALLARO static void __exit icplus_exit(void) 2570cefeebaSMichael Barkowski { 258377ecca9SGiuseppe CAVALLARO phy_driver_unregister(&ip1001_driver); 259e3e09f26SGiuseppe CAVALLARO phy_driver_unregister(&ip101a_g_driver); 2600cefeebaSMichael Barkowski phy_driver_unregister(&ip175c_driver); 2610cefeebaSMichael Barkowski } 2620cefeebaSMichael Barkowski 263377ecca9SGiuseppe CAVALLARO module_init(icplus_init); 264377ecca9SGiuseppe CAVALLARO module_exit(icplus_exit); 2654e4f10f6SDavid Woodhouse 266cf93c945SUwe Kleine-König static struct mdio_device_id __maybe_unused icplus_tbl[] = { 2674e4f10f6SDavid Woodhouse { 0x02430d80, 0x0ffffff0 }, 268377ecca9SGiuseppe CAVALLARO { 0x02430d90, 0x0ffffff0 }, 269e3e09f26SGiuseppe CAVALLARO { 0x02430c54, 0x0ffffff0 }, 2704e4f10f6SDavid Woodhouse { } 2714e4f10f6SDavid Woodhouse }; 2724e4f10f6SDavid Woodhouse 2734e4f10f6SDavid Woodhouse MODULE_DEVICE_TABLE(mdio, icplus_tbl); 274