1*642af0f9SMaxime Chevallier // SPDX-License-Identifier: GPL-2.0-or-later
2*642af0f9SMaxime Chevallier /* Driver for MMIO-Mapped MDIO devices. Some IPs expose internal PHYs or PCS
3*642af0f9SMaxime Chevallier * within the MMIO-mapped area
4*642af0f9SMaxime Chevallier *
5*642af0f9SMaxime Chevallier * Copyright (C) 2023 Maxime Chevallier <maxime.chevallier@bootlin.com>
6*642af0f9SMaxime Chevallier */
7*642af0f9SMaxime Chevallier #include <linux/bitfield.h>
8*642af0f9SMaxime Chevallier #include <linux/delay.h>
9*642af0f9SMaxime Chevallier #include <linux/mdio.h>
10*642af0f9SMaxime Chevallier #include <linux/module.h>
11*642af0f9SMaxime Chevallier #include <linux/of.h>
12*642af0f9SMaxime Chevallier #include <linux/of_mdio.h>
13*642af0f9SMaxime Chevallier #include <linux/phy.h>
14*642af0f9SMaxime Chevallier #include <linux/platform_device.h>
15*642af0f9SMaxime Chevallier #include <linux/regmap.h>
16*642af0f9SMaxime Chevallier #include <linux/mdio/mdio-regmap.h>
17*642af0f9SMaxime Chevallier
18*642af0f9SMaxime Chevallier #define DRV_NAME "mdio-regmap"
19*642af0f9SMaxime Chevallier
20*642af0f9SMaxime Chevallier struct mdio_regmap_priv {
21*642af0f9SMaxime Chevallier struct regmap *regmap;
22*642af0f9SMaxime Chevallier u8 valid_addr;
23*642af0f9SMaxime Chevallier };
24*642af0f9SMaxime Chevallier
mdio_regmap_read_c22(struct mii_bus * bus,int addr,int regnum)25*642af0f9SMaxime Chevallier static int mdio_regmap_read_c22(struct mii_bus *bus, int addr, int regnum)
26*642af0f9SMaxime Chevallier {
27*642af0f9SMaxime Chevallier struct mdio_regmap_priv *ctx = bus->priv;
28*642af0f9SMaxime Chevallier unsigned int val;
29*642af0f9SMaxime Chevallier int ret;
30*642af0f9SMaxime Chevallier
31*642af0f9SMaxime Chevallier if (ctx->valid_addr != addr)
32*642af0f9SMaxime Chevallier return -ENODEV;
33*642af0f9SMaxime Chevallier
34*642af0f9SMaxime Chevallier ret = regmap_read(ctx->regmap, regnum, &val);
35*642af0f9SMaxime Chevallier if (ret < 0)
36*642af0f9SMaxime Chevallier return ret;
37*642af0f9SMaxime Chevallier
38*642af0f9SMaxime Chevallier return val;
39*642af0f9SMaxime Chevallier }
40*642af0f9SMaxime Chevallier
mdio_regmap_write_c22(struct mii_bus * bus,int addr,int regnum,u16 val)41*642af0f9SMaxime Chevallier static int mdio_regmap_write_c22(struct mii_bus *bus, int addr, int regnum,
42*642af0f9SMaxime Chevallier u16 val)
43*642af0f9SMaxime Chevallier {
44*642af0f9SMaxime Chevallier struct mdio_regmap_priv *ctx = bus->priv;
45*642af0f9SMaxime Chevallier
46*642af0f9SMaxime Chevallier if (ctx->valid_addr != addr)
47*642af0f9SMaxime Chevallier return -ENODEV;
48*642af0f9SMaxime Chevallier
49*642af0f9SMaxime Chevallier return regmap_write(ctx->regmap, regnum, val);
50*642af0f9SMaxime Chevallier }
51*642af0f9SMaxime Chevallier
devm_mdio_regmap_register(struct device * dev,const struct mdio_regmap_config * config)52*642af0f9SMaxime Chevallier struct mii_bus *devm_mdio_regmap_register(struct device *dev,
53*642af0f9SMaxime Chevallier const struct mdio_regmap_config *config)
54*642af0f9SMaxime Chevallier {
55*642af0f9SMaxime Chevallier struct mdio_regmap_priv *mr;
56*642af0f9SMaxime Chevallier struct mii_bus *mii;
57*642af0f9SMaxime Chevallier int rc;
58*642af0f9SMaxime Chevallier
59*642af0f9SMaxime Chevallier if (!config->parent)
60*642af0f9SMaxime Chevallier return ERR_PTR(-EINVAL);
61*642af0f9SMaxime Chevallier
62*642af0f9SMaxime Chevallier mii = devm_mdiobus_alloc_size(config->parent, sizeof(*mr));
63*642af0f9SMaxime Chevallier if (!mii)
64*642af0f9SMaxime Chevallier return ERR_PTR(-ENOMEM);
65*642af0f9SMaxime Chevallier
66*642af0f9SMaxime Chevallier mr = mii->priv;
67*642af0f9SMaxime Chevallier mr->regmap = config->regmap;
68*642af0f9SMaxime Chevallier mr->valid_addr = config->valid_addr;
69*642af0f9SMaxime Chevallier
70*642af0f9SMaxime Chevallier mii->name = DRV_NAME;
71*642af0f9SMaxime Chevallier strscpy(mii->id, config->name, MII_BUS_ID_SIZE);
72*642af0f9SMaxime Chevallier mii->parent = config->parent;
73*642af0f9SMaxime Chevallier mii->read = mdio_regmap_read_c22;
74*642af0f9SMaxime Chevallier mii->write = mdio_regmap_write_c22;
75*642af0f9SMaxime Chevallier
76*642af0f9SMaxime Chevallier if (config->autoscan)
77*642af0f9SMaxime Chevallier mii->phy_mask = ~BIT(config->valid_addr);
78*642af0f9SMaxime Chevallier else
79*642af0f9SMaxime Chevallier mii->phy_mask = ~0;
80*642af0f9SMaxime Chevallier
81*642af0f9SMaxime Chevallier rc = devm_mdiobus_register(dev, mii);
82*642af0f9SMaxime Chevallier if (rc) {
83*642af0f9SMaxime Chevallier dev_err(config->parent, "Cannot register MDIO bus![%s] (%d)\n", mii->id, rc);
84*642af0f9SMaxime Chevallier return ERR_PTR(rc);
85*642af0f9SMaxime Chevallier }
86*642af0f9SMaxime Chevallier
87*642af0f9SMaxime Chevallier return mii;
88*642af0f9SMaxime Chevallier }
89*642af0f9SMaxime Chevallier EXPORT_SYMBOL_GPL(devm_mdio_regmap_register);
90*642af0f9SMaxime Chevallier
91*642af0f9SMaxime Chevallier MODULE_DESCRIPTION("MDIO API over regmap");
92*642af0f9SMaxime Chevallier MODULE_AUTHOR("Maxime Chevallier <maxime.chevallier@bootlin.com>");
93*642af0f9SMaxime Chevallier MODULE_LICENSE("GPL");
94