1*a9770eacSAndrew Lunn // SPDX-License-Identifier: GPL-2.0+
2*a9770eacSAndrew Lunn /*
3*a9770eacSAndrew Lunn * Hisilicon Fast Ethernet MDIO Bus Driver
4*a9770eacSAndrew Lunn *
5*a9770eacSAndrew Lunn * Copyright (c) 2016 HiSilicon Technologies Co., Ltd.
6*a9770eacSAndrew Lunn */
7*a9770eacSAndrew Lunn
8*a9770eacSAndrew Lunn #include <linux/clk.h>
9*a9770eacSAndrew Lunn #include <linux/iopoll.h>
10*a9770eacSAndrew Lunn #include <linux/kernel.h>
11*a9770eacSAndrew Lunn #include <linux/module.h>
12*a9770eacSAndrew Lunn #include <linux/of_address.h>
13*a9770eacSAndrew Lunn #include <linux/of_mdio.h>
14*a9770eacSAndrew Lunn #include <linux/platform_device.h>
15*a9770eacSAndrew Lunn
16*a9770eacSAndrew Lunn #define MDIO_RWCTRL 0x00
17*a9770eacSAndrew Lunn #define MDIO_RO_DATA 0x04
18*a9770eacSAndrew Lunn #define MDIO_WRITE BIT(13)
19*a9770eacSAndrew Lunn #define MDIO_RW_FINISH BIT(15)
20*a9770eacSAndrew Lunn #define BIT_PHY_ADDR_OFFSET 8
21*a9770eacSAndrew Lunn #define BIT_WR_DATA_OFFSET 16
22*a9770eacSAndrew Lunn
23*a9770eacSAndrew Lunn struct hisi_femac_mdio_data {
24*a9770eacSAndrew Lunn struct clk *clk;
25*a9770eacSAndrew Lunn void __iomem *membase;
26*a9770eacSAndrew Lunn };
27*a9770eacSAndrew Lunn
hisi_femac_mdio_wait_ready(struct hisi_femac_mdio_data * data)28*a9770eacSAndrew Lunn static int hisi_femac_mdio_wait_ready(struct hisi_femac_mdio_data *data)
29*a9770eacSAndrew Lunn {
30*a9770eacSAndrew Lunn u32 val;
31*a9770eacSAndrew Lunn
32*a9770eacSAndrew Lunn return readl_poll_timeout(data->membase + MDIO_RWCTRL,
33*a9770eacSAndrew Lunn val, val & MDIO_RW_FINISH, 20, 10000);
34*a9770eacSAndrew Lunn }
35*a9770eacSAndrew Lunn
hisi_femac_mdio_read(struct mii_bus * bus,int mii_id,int regnum)36*a9770eacSAndrew Lunn static int hisi_femac_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
37*a9770eacSAndrew Lunn {
38*a9770eacSAndrew Lunn struct hisi_femac_mdio_data *data = bus->priv;
39*a9770eacSAndrew Lunn int ret;
40*a9770eacSAndrew Lunn
41*a9770eacSAndrew Lunn ret = hisi_femac_mdio_wait_ready(data);
42*a9770eacSAndrew Lunn if (ret)
43*a9770eacSAndrew Lunn return ret;
44*a9770eacSAndrew Lunn
45*a9770eacSAndrew Lunn writel((mii_id << BIT_PHY_ADDR_OFFSET) | regnum,
46*a9770eacSAndrew Lunn data->membase + MDIO_RWCTRL);
47*a9770eacSAndrew Lunn
48*a9770eacSAndrew Lunn ret = hisi_femac_mdio_wait_ready(data);
49*a9770eacSAndrew Lunn if (ret)
50*a9770eacSAndrew Lunn return ret;
51*a9770eacSAndrew Lunn
52*a9770eacSAndrew Lunn return readl(data->membase + MDIO_RO_DATA) & 0xFFFF;
53*a9770eacSAndrew Lunn }
54*a9770eacSAndrew Lunn
hisi_femac_mdio_write(struct mii_bus * bus,int mii_id,int regnum,u16 value)55*a9770eacSAndrew Lunn static int hisi_femac_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
56*a9770eacSAndrew Lunn u16 value)
57*a9770eacSAndrew Lunn {
58*a9770eacSAndrew Lunn struct hisi_femac_mdio_data *data = bus->priv;
59*a9770eacSAndrew Lunn int ret;
60*a9770eacSAndrew Lunn
61*a9770eacSAndrew Lunn ret = hisi_femac_mdio_wait_ready(data);
62*a9770eacSAndrew Lunn if (ret)
63*a9770eacSAndrew Lunn return ret;
64*a9770eacSAndrew Lunn
65*a9770eacSAndrew Lunn writel(MDIO_WRITE | (value << BIT_WR_DATA_OFFSET) |
66*a9770eacSAndrew Lunn (mii_id << BIT_PHY_ADDR_OFFSET) | regnum,
67*a9770eacSAndrew Lunn data->membase + MDIO_RWCTRL);
68*a9770eacSAndrew Lunn
69*a9770eacSAndrew Lunn return hisi_femac_mdio_wait_ready(data);
70*a9770eacSAndrew Lunn }
71*a9770eacSAndrew Lunn
hisi_femac_mdio_probe(struct platform_device * pdev)72*a9770eacSAndrew Lunn static int hisi_femac_mdio_probe(struct platform_device *pdev)
73*a9770eacSAndrew Lunn {
74*a9770eacSAndrew Lunn struct device_node *np = pdev->dev.of_node;
75*a9770eacSAndrew Lunn struct mii_bus *bus;
76*a9770eacSAndrew Lunn struct hisi_femac_mdio_data *data;
77*a9770eacSAndrew Lunn int ret;
78*a9770eacSAndrew Lunn
79*a9770eacSAndrew Lunn bus = mdiobus_alloc_size(sizeof(*data));
80*a9770eacSAndrew Lunn if (!bus)
81*a9770eacSAndrew Lunn return -ENOMEM;
82*a9770eacSAndrew Lunn
83*a9770eacSAndrew Lunn bus->name = "hisi_femac_mii_bus";
84*a9770eacSAndrew Lunn bus->read = &hisi_femac_mdio_read;
85*a9770eacSAndrew Lunn bus->write = &hisi_femac_mdio_write;
86*a9770eacSAndrew Lunn snprintf(bus->id, MII_BUS_ID_SIZE, "%s", pdev->name);
87*a9770eacSAndrew Lunn bus->parent = &pdev->dev;
88*a9770eacSAndrew Lunn
89*a9770eacSAndrew Lunn data = bus->priv;
90*a9770eacSAndrew Lunn data->membase = devm_platform_ioremap_resource(pdev, 0);
91*a9770eacSAndrew Lunn if (IS_ERR(data->membase)) {
92*a9770eacSAndrew Lunn ret = PTR_ERR(data->membase);
93*a9770eacSAndrew Lunn goto err_out_free_mdiobus;
94*a9770eacSAndrew Lunn }
95*a9770eacSAndrew Lunn
96*a9770eacSAndrew Lunn data->clk = devm_clk_get(&pdev->dev, NULL);
97*a9770eacSAndrew Lunn if (IS_ERR(data->clk)) {
98*a9770eacSAndrew Lunn ret = PTR_ERR(data->clk);
99*a9770eacSAndrew Lunn goto err_out_free_mdiobus;
100*a9770eacSAndrew Lunn }
101*a9770eacSAndrew Lunn
102*a9770eacSAndrew Lunn ret = clk_prepare_enable(data->clk);
103*a9770eacSAndrew Lunn if (ret)
104*a9770eacSAndrew Lunn goto err_out_free_mdiobus;
105*a9770eacSAndrew Lunn
106*a9770eacSAndrew Lunn ret = of_mdiobus_register(bus, np);
107*a9770eacSAndrew Lunn if (ret)
108*a9770eacSAndrew Lunn goto err_out_disable_clk;
109*a9770eacSAndrew Lunn
110*a9770eacSAndrew Lunn platform_set_drvdata(pdev, bus);
111*a9770eacSAndrew Lunn
112*a9770eacSAndrew Lunn return 0;
113*a9770eacSAndrew Lunn
114*a9770eacSAndrew Lunn err_out_disable_clk:
115*a9770eacSAndrew Lunn clk_disable_unprepare(data->clk);
116*a9770eacSAndrew Lunn err_out_free_mdiobus:
117*a9770eacSAndrew Lunn mdiobus_free(bus);
118*a9770eacSAndrew Lunn return ret;
119*a9770eacSAndrew Lunn }
120*a9770eacSAndrew Lunn
hisi_femac_mdio_remove(struct platform_device * pdev)121*a9770eacSAndrew Lunn static int hisi_femac_mdio_remove(struct platform_device *pdev)
122*a9770eacSAndrew Lunn {
123*a9770eacSAndrew Lunn struct mii_bus *bus = platform_get_drvdata(pdev);
124*a9770eacSAndrew Lunn struct hisi_femac_mdio_data *data = bus->priv;
125*a9770eacSAndrew Lunn
126*a9770eacSAndrew Lunn mdiobus_unregister(bus);
127*a9770eacSAndrew Lunn clk_disable_unprepare(data->clk);
128*a9770eacSAndrew Lunn mdiobus_free(bus);
129*a9770eacSAndrew Lunn
130*a9770eacSAndrew Lunn return 0;
131*a9770eacSAndrew Lunn }
132*a9770eacSAndrew Lunn
133*a9770eacSAndrew Lunn static const struct of_device_id hisi_femac_mdio_dt_ids[] = {
134*a9770eacSAndrew Lunn { .compatible = "hisilicon,hisi-femac-mdio" },
135*a9770eacSAndrew Lunn { }
136*a9770eacSAndrew Lunn };
137*a9770eacSAndrew Lunn MODULE_DEVICE_TABLE(of, hisi_femac_mdio_dt_ids);
138*a9770eacSAndrew Lunn
139*a9770eacSAndrew Lunn static struct platform_driver hisi_femac_mdio_driver = {
140*a9770eacSAndrew Lunn .probe = hisi_femac_mdio_probe,
141*a9770eacSAndrew Lunn .remove = hisi_femac_mdio_remove,
142*a9770eacSAndrew Lunn .driver = {
143*a9770eacSAndrew Lunn .name = "hisi-femac-mdio",
144*a9770eacSAndrew Lunn .of_match_table = hisi_femac_mdio_dt_ids,
145*a9770eacSAndrew Lunn },
146*a9770eacSAndrew Lunn };
147*a9770eacSAndrew Lunn
148*a9770eacSAndrew Lunn module_platform_driver(hisi_femac_mdio_driver);
149*a9770eacSAndrew Lunn
150*a9770eacSAndrew Lunn MODULE_DESCRIPTION("Hisilicon Fast Ethernet MAC MDIO interface driver");
151*a9770eacSAndrew Lunn MODULE_AUTHOR("Dongpo Li <lidongpo@hisilicon.com>");
152*a9770eacSAndrew Lunn MODULE_LICENSE("GPL");
153