xref: /openbmc/linux/drivers/net/ipa/reg/gsi_reg-v3.1.c (revision edc6158b18af81e6f48268479996a16ca7599a4e) 
1 // SPDX-License-Identifier: GPL-2.0
2 
3 /* Copyright (C) 2023 Linaro Ltd. */
4 
5 #include <linux/types.h>
6 
7 #include "../gsi.h"
8 #include "../reg.h"
9 #include "../gsi_reg.h"
10 
11 /* The inter-EE IRQ registers are relative to gsi->virt_raw (IPA v3.5+) */
12 
13 REG(INTER_EE_SRC_CH_IRQ_MSK, inter_ee_src_ch_irq_msk,
14     0x0000c020 + 0x1000 * GSI_EE_AP);
15 
16 REG(INTER_EE_SRC_EV_CH_IRQ_MSK, inter_ee_src_ev_ch_irq_msk,
17     0x0000c024 + 0x1000 * GSI_EE_AP);
18 
19 /* All other register offsets are relative to gsi->virt */
20 
21 static const u32 reg_ch_c_cntxt_0_fmask[] = {
22 	[CHTYPE_PROTOCOL]				= GENMASK(2, 0),
23 	[CHTYPE_DIR]					= BIT(3),
24 	[CH_EE]						= GENMASK(7, 4),
25 	[CHID]						= GENMASK(12, 8),
26 						/* Bit 13 reserved */
27 	[ERINDEX]					= GENMASK(18, 14),
28 						/* Bit 19 reserved */
29 	[CHSTATE]					= GENMASK(23, 20),
30 	[ELEMENT_SIZE]					= GENMASK(31, 24),
31 };
32 
33 REG_STRIDE_FIELDS(CH_C_CNTXT_0, ch_c_cntxt_0,
34 		  0x0001c000 + 0x4000 * GSI_EE_AP, 0x80);
35 
36 static const u32 reg_ch_c_cntxt_1_fmask[] = {
37 	[CH_R_LENGTH]					= GENMASK(15, 0),
38 						/* Bits 16-31 reserved */
39 };
40 
41 REG_STRIDE_FIELDS(CH_C_CNTXT_1, ch_c_cntxt_1,
42 		  0x0001c004 + 0x4000 * GSI_EE_AP, 0x80);
43 
44 REG_STRIDE(CH_C_CNTXT_2, ch_c_cntxt_2, 0x0001c008 + 0x4000 * GSI_EE_AP, 0x80);
45 
46 REG_STRIDE(CH_C_CNTXT_3, ch_c_cntxt_3, 0x0001c00c + 0x4000 * GSI_EE_AP, 0x80);
47 
48 static const u32 reg_ch_c_qos_fmask[] = {
49 	[WRR_WEIGHT]					= GENMASK(3, 0),
50 						/* Bits 4-7 reserved */
51 	[MAX_PREFETCH]					= BIT(8),
52 	[USE_DB_ENG]					= BIT(9),
53 						/* Bits 10-31 reserved */
54 };
55 
56 REG_STRIDE_FIELDS(CH_C_QOS, ch_c_qos, 0x0001c05c + 0x4000 * GSI_EE_AP, 0x80);
57 
58 REG(ERROR_LOG, error_log, 0x0001f200 + 0x4000 * GSI_EE_AP);
59 
60 REG(ERROR_LOG_CLR, error_log_clr, 0x0001f210 + 0x4000 * GSI_EE_AP);
61 
62 REG_STRIDE(CH_C_SCRATCH_0, ch_c_scratch_0,
63 	   0x0001c060 + 0x4000 * GSI_EE_AP, 0x80);
64 
65 REG_STRIDE(CH_C_SCRATCH_1, ch_c_scratch_1,
66 	   0x0001c064 + 0x4000 * GSI_EE_AP, 0x80);
67 
68 REG_STRIDE(CH_C_SCRATCH_2, ch_c_scratch_2,
69 	   0x0001c068 + 0x4000 * GSI_EE_AP, 0x80);
70 
71 REG_STRIDE(CH_C_SCRATCH_3, ch_c_scratch_3,
72 	   0x0001c06c + 0x4000 * GSI_EE_AP, 0x80);
73 
74 static const u32 reg_ev_ch_e_cntxt_0_fmask[] = {
75 	[EV_CHTYPE]					= GENMASK(3, 0),
76 	[EV_EE]						= GENMASK(7, 4),
77 	[EV_EVCHID]					= GENMASK(15, 8),
78 	[EV_INTYPE]					= BIT(16),
79 						/* Bits 17-19 reserved */
80 	[EV_CHSTATE]					= GENMASK(23, 20),
81 	[EV_ELEMENT_SIZE]				= GENMASK(31, 24),
82 };
83 
84 REG_STRIDE_FIELDS(EV_CH_E_CNTXT_0, ev_ch_e_cntxt_0,
85 		  0x0001d000 + 0x4000 * GSI_EE_AP, 0x80);
86 
87 REG_STRIDE(EV_CH_E_CNTXT_1, ev_ch_e_cntxt_1,
88 	   0x0001d004 + 0x4000 * GSI_EE_AP, 0x80);
89 
90 REG_STRIDE(EV_CH_E_CNTXT_2, ev_ch_e_cntxt_2,
91 	   0x0001d008 + 0x4000 * GSI_EE_AP, 0x80);
92 
93 REG_STRIDE(EV_CH_E_CNTXT_3, ev_ch_e_cntxt_3,
94 	   0x0001d00c + 0x4000 * GSI_EE_AP, 0x80);
95 
96 REG_STRIDE(EV_CH_E_CNTXT_4, ev_ch_e_cntxt_4,
97 	   0x0001d010 + 0x4000 * GSI_EE_AP, 0x80);
98 
99 static const u32 reg_ev_ch_e_cntxt_8_fmask[] = {
100 	[EV_MODT]					= GENMASK(15, 0),
101 	[EV_MODC]					= GENMASK(23, 16),
102 	[EV_MOD_CNT]					= GENMASK(31, 24),
103 };
104 
105 REG_STRIDE_FIELDS(EV_CH_E_CNTXT_8, ev_ch_e_cntxt_8,
106 		  0x0001d020 + 0x4000 * GSI_EE_AP, 0x80);
107 
108 REG_STRIDE(EV_CH_E_CNTXT_9, ev_ch_e_cntxt_9,
109 	   0x0001d024 + 0x4000 * GSI_EE_AP, 0x80);
110 
111 REG_STRIDE(EV_CH_E_CNTXT_10, ev_ch_e_cntxt_10,
112 	   0x0001d028 + 0x4000 * GSI_EE_AP, 0x80);
113 
114 REG_STRIDE(EV_CH_E_CNTXT_11, ev_ch_e_cntxt_11,
115 	   0x0001d02c + 0x4000 * GSI_EE_AP, 0x80);
116 
117 REG_STRIDE(EV_CH_E_CNTXT_12, ev_ch_e_cntxt_12,
118 	   0x0001d030 + 0x4000 * GSI_EE_AP, 0x80);
119 
120 REG_STRIDE(EV_CH_E_CNTXT_13, ev_ch_e_cntxt_13,
121 	   0x0001d034 + 0x4000 * GSI_EE_AP, 0x80);
122 
123 REG_STRIDE(EV_CH_E_SCRATCH_0, ev_ch_e_scratch_0,
124 	   0x0001d048 + 0x4000 * GSI_EE_AP, 0x80);
125 
126 REG_STRIDE(EV_CH_E_SCRATCH_1, ev_ch_e_scratch_1,
127 	   0x0001d04c + 0x4000 * GSI_EE_AP, 0x80);
128 
129 REG_STRIDE(CH_C_DOORBELL_0, ch_c_doorbell_0,
130 	   0x0001e000 + 0x4000 * GSI_EE_AP, 0x08);
131 
132 REG_STRIDE(EV_CH_E_DOORBELL_0, ev_ch_e_doorbell_0,
133 	   0x0001e100 + 0x4000 * GSI_EE_AP, 0x08);
134 
135 REG(GSI_STATUS, gsi_status, 0x0001f000 + 0x4000 * GSI_EE_AP);
136 
137 REG(CH_CMD, ch_cmd, 0x0001f008 + 0x4000 * GSI_EE_AP);
138 
139 REG(EV_CH_CMD, ev_ch_cmd, 0x0001f010 + 0x4000 * GSI_EE_AP);
140 
141 REG(GENERIC_CMD, generic_cmd, 0x0001f018 + 0x4000 * GSI_EE_AP);
142 
143 REG(CNTXT_TYPE_IRQ, cntxt_type_irq, 0x0001f080 + 0x4000 * GSI_EE_AP);
144 
145 REG(CNTXT_TYPE_IRQ_MSK, cntxt_type_irq_msk, 0x0001f088 + 0x4000 * GSI_EE_AP);
146 
147 REG(CNTXT_SRC_CH_IRQ, cntxt_src_ch_irq, 0x0001f090 + 0x4000 * GSI_EE_AP);
148 
149 REG(CNTXT_SRC_EV_CH_IRQ, cntxt_src_ev_ch_irq, 0x0001f094 + 0x4000 * GSI_EE_AP);
150 
151 REG(CNTXT_SRC_CH_IRQ_MSK, cntxt_src_ch_irq_msk,
152     0x0001f098 + 0x4000 * GSI_EE_AP);
153 
154 REG(CNTXT_SRC_EV_CH_IRQ_MSK, cntxt_src_ev_ch_irq_msk,
155     0x0001f09c + 0x4000 * GSI_EE_AP);
156 
157 REG(CNTXT_SRC_CH_IRQ_CLR, cntxt_src_ch_irq_clr,
158     0x0001f0a0 + 0x4000 * GSI_EE_AP);
159 
160 REG(CNTXT_SRC_EV_CH_IRQ_CLR, cntxt_src_ev_ch_irq_clr,
161     0x0001f0a4 + 0x4000 * GSI_EE_AP);
162 
163 REG(CNTXT_SRC_IEOB_IRQ, cntxt_src_ieob_irq, 0x0001f0b0 + 0x4000 * GSI_EE_AP);
164 
165 REG(CNTXT_SRC_IEOB_IRQ_MSK, cntxt_src_ieob_irq_msk,
166     0x0001f0b8 + 0x4000 * GSI_EE_AP);
167 
168 REG(CNTXT_SRC_IEOB_IRQ_CLR, cntxt_src_ieob_irq_clr,
169     0x0001f0c0 + 0x4000 * GSI_EE_AP);
170 
171 REG(CNTXT_GLOB_IRQ_STTS, cntxt_glob_irq_stts, 0x0001f100 + 0x4000 * GSI_EE_AP);
172 
173 REG(CNTXT_GLOB_IRQ_EN, cntxt_glob_irq_en, 0x0001f108 + 0x4000 * GSI_EE_AP);
174 
175 REG(CNTXT_GLOB_IRQ_CLR, cntxt_glob_irq_clr, 0x0001f110 + 0x4000 * GSI_EE_AP);
176 
177 REG(CNTXT_GSI_IRQ_STTS, cntxt_gsi_irq_stts, 0x0001f118 + 0x4000 * GSI_EE_AP);
178 
179 REG(CNTXT_GSI_IRQ_EN, cntxt_gsi_irq_en, 0x0001f120 + 0x4000 * GSI_EE_AP);
180 
181 REG(CNTXT_GSI_IRQ_CLR, cntxt_gsi_irq_clr, 0x0001f128 + 0x4000 * GSI_EE_AP);
182 
183 REG(CNTXT_INTSET, cntxt_intset, 0x0001f180 + 0x4000 * GSI_EE_AP);
184 
185 REG(CNTXT_SCRATCH_0, cntxt_scratch_0, 0x0001f400 + 0x4000 * GSI_EE_AP);
186 
187 static const struct reg *reg_array[] = {
188 	[INTER_EE_SRC_CH_IRQ_MSK]	= &reg_inter_ee_src_ch_irq_msk,
189 	[INTER_EE_SRC_EV_CH_IRQ_MSK]	= &reg_inter_ee_src_ev_ch_irq_msk,
190 	[CH_C_CNTXT_0]			= &reg_ch_c_cntxt_0,
191 	[CH_C_CNTXT_1]			= &reg_ch_c_cntxt_1,
192 	[CH_C_CNTXT_2]			= &reg_ch_c_cntxt_2,
193 	[CH_C_CNTXT_3]			= &reg_ch_c_cntxt_3,
194 	[CH_C_QOS]			= &reg_ch_c_qos,
195 	[CH_C_SCRATCH_0]		= &reg_ch_c_scratch_0,
196 	[CH_C_SCRATCH_1]		= &reg_ch_c_scratch_1,
197 	[CH_C_SCRATCH_2]		= &reg_ch_c_scratch_2,
198 	[CH_C_SCRATCH_3]		= &reg_ch_c_scratch_3,
199 	[EV_CH_E_CNTXT_0]		= &reg_ev_ch_e_cntxt_0,
200 	[EV_CH_E_CNTXT_1]		= &reg_ev_ch_e_cntxt_1,
201 	[EV_CH_E_CNTXT_2]		= &reg_ev_ch_e_cntxt_2,
202 	[EV_CH_E_CNTXT_3]		= &reg_ev_ch_e_cntxt_3,
203 	[EV_CH_E_CNTXT_4]		= &reg_ev_ch_e_cntxt_4,
204 	[EV_CH_E_CNTXT_8]		= &reg_ev_ch_e_cntxt_8,
205 	[EV_CH_E_CNTXT_9]		= &reg_ev_ch_e_cntxt_9,
206 	[EV_CH_E_CNTXT_10]		= &reg_ev_ch_e_cntxt_10,
207 	[EV_CH_E_CNTXT_11]		= &reg_ev_ch_e_cntxt_11,
208 	[EV_CH_E_CNTXT_12]		= &reg_ev_ch_e_cntxt_12,
209 	[EV_CH_E_CNTXT_13]		= &reg_ev_ch_e_cntxt_13,
210 	[EV_CH_E_SCRATCH_0]		= &reg_ev_ch_e_scratch_0,
211 	[EV_CH_E_SCRATCH_1]		= &reg_ev_ch_e_scratch_1,
212 	[CH_C_DOORBELL_0]		= &reg_ch_c_doorbell_0,
213 	[EV_CH_E_DOORBELL_0]		= &reg_ev_ch_e_doorbell_0,
214 	[GSI_STATUS]			= &reg_gsi_status,
215 	[CH_CMD]			= &reg_ch_cmd,
216 	[EV_CH_CMD]			= &reg_ev_ch_cmd,
217 	[GENERIC_CMD]			= &reg_generic_cmd,
218 	[CNTXT_TYPE_IRQ]		= &reg_cntxt_type_irq,
219 	[CNTXT_TYPE_IRQ_MSK]		= &reg_cntxt_type_irq_msk,
220 	[CNTXT_SRC_CH_IRQ]		= &reg_cntxt_src_ch_irq,
221 	[CNTXT_SRC_EV_CH_IRQ]		= &reg_cntxt_src_ev_ch_irq,
222 	[CNTXT_SRC_CH_IRQ_MSK]		= &reg_cntxt_src_ch_irq_msk,
223 	[CNTXT_SRC_EV_CH_IRQ_MSK]	= &reg_cntxt_src_ev_ch_irq_msk,
224 	[CNTXT_SRC_CH_IRQ_CLR]		= &reg_cntxt_src_ch_irq_clr,
225 	[CNTXT_SRC_EV_CH_IRQ_CLR]	= &reg_cntxt_src_ev_ch_irq_clr,
226 	[CNTXT_SRC_IEOB_IRQ]		= &reg_cntxt_src_ieob_irq,
227 	[CNTXT_SRC_IEOB_IRQ_MSK]	= &reg_cntxt_src_ieob_irq_msk,
228 	[CNTXT_SRC_IEOB_IRQ_CLR]	= &reg_cntxt_src_ieob_irq_clr,
229 	[CNTXT_GLOB_IRQ_STTS]		= &reg_cntxt_glob_irq_stts,
230 	[CNTXT_GLOB_IRQ_EN]		= &reg_cntxt_glob_irq_en,
231 	[CNTXT_GLOB_IRQ_CLR]		= &reg_cntxt_glob_irq_clr,
232 	[CNTXT_GSI_IRQ_STTS]		= &reg_cntxt_gsi_irq_stts,
233 	[CNTXT_GSI_IRQ_EN]		= &reg_cntxt_gsi_irq_en,
234 	[CNTXT_GSI_IRQ_CLR]		= &reg_cntxt_gsi_irq_clr,
235 	[CNTXT_INTSET]			= &reg_cntxt_intset,
236 	[ERROR_LOG]			= &reg_error_log,
237 	[ERROR_LOG_CLR]			= &reg_error_log_clr,
238 	[CNTXT_SCRATCH_0]		= &reg_cntxt_scratch_0,
239 };
240 
241 const struct regs gsi_regs_v3_1 = {
242 	.reg_count	= ARRAY_SIZE(reg_array),
243 	.reg		= reg_array,
244 };
245