xref: /openbmc/linux/drivers/net/ipa/reg/gsi_reg-v3.1.c (revision 59b12b1d27f3f82e56462f0da6413e1849a06d3a) 
1 // SPDX-License-Identifier: GPL-2.0
2 
3 /* Copyright (C) 2023 Linaro Ltd. */
4 
5 #include <linux/types.h>
6 
7 #include "../gsi.h"
8 #include "../reg.h"
9 #include "../gsi_reg.h"
10 
11 REG(INTER_EE_SRC_CH_IRQ_MSK, inter_ee_src_ch_irq_msk,
12     0x0000c020 + 0x1000 * GSI_EE_AP);
13 
14 REG(INTER_EE_SRC_EV_CH_IRQ_MSK, inter_ee_src_ev_ch_irq_msk,
15     0x0000c024 + 0x1000 * GSI_EE_AP);
16 
17 static const u32 reg_ch_c_cntxt_0_fmask[] = {
18 	[CHTYPE_PROTOCOL]				= GENMASK(2, 0),
19 	[CHTYPE_DIR]					= BIT(3),
20 	[CH_EE]						= GENMASK(7, 4),
21 	[CHID]						= GENMASK(12, 8),
22 						/* Bit 13 reserved */
23 	[ERINDEX]					= GENMASK(18, 14),
24 						/* Bit 19 reserved */
25 	[CHSTATE]					= GENMASK(23, 20),
26 	[ELEMENT_SIZE]					= GENMASK(31, 24),
27 };
28 
29 REG_STRIDE_FIELDS(CH_C_CNTXT_0, ch_c_cntxt_0,
30 		  0x0001c000 + 0x4000 * GSI_EE_AP, 0x80);
31 
32 static const u32 reg_ch_c_cntxt_1_fmask[] = {
33 	[CH_R_LENGTH]					= GENMASK(15, 0),
34 						/* Bits 16-31 reserved */
35 };
36 
37 REG_STRIDE_FIELDS(CH_C_CNTXT_1, ch_c_cntxt_1,
38 		  0x0001c004 + 0x4000 * GSI_EE_AP, 0x80);
39 
40 REG_STRIDE(CH_C_CNTXT_2, ch_c_cntxt_2, 0x0001c008 + 0x4000 * GSI_EE_AP, 0x80);
41 
42 REG_STRIDE(CH_C_CNTXT_3, ch_c_cntxt_3, 0x0001c00c + 0x4000 * GSI_EE_AP, 0x80);
43 
44 static const u32 reg_ch_c_qos_fmask[] = {
45 	[WRR_WEIGHT]					= GENMASK(3, 0),
46 						/* Bits 4-7 reserved */
47 	[MAX_PREFETCH]					= BIT(8),
48 	[USE_DB_ENG]					= BIT(9),
49 						/* Bits 10-31 reserved */
50 };
51 
52 REG_STRIDE_FIELDS(CH_C_QOS, ch_c_qos, 0x0001c05c + 0x4000 * GSI_EE_AP, 0x80);
53 
54 static const u32 reg_error_log_fmask[] = {
55 	[ERR_ARG3]					= GENMASK(3, 0),
56 	[ERR_ARG2]					= GENMASK(7, 4),
57 	[ERR_ARG1]					= GENMASK(11, 8),
58 	[ERR_CODE]					= GENMASK(15, 12),
59 						/* Bits 16-18 reserved */
60 	[ERR_VIRT_IDX]					= GENMASK(23, 19),
61 	[ERR_TYPE]					= GENMASK(27, 24),
62 	[ERR_EE]					= GENMASK(31, 28),
63 };
64 
65 REG_STRIDE(CH_C_SCRATCH_0, ch_c_scratch_0,
66 	   0x0001c060 + 0x4000 * GSI_EE_AP, 0x80);
67 
68 REG_STRIDE(CH_C_SCRATCH_1, ch_c_scratch_1,
69 	   0x0001c064 + 0x4000 * GSI_EE_AP, 0x80);
70 
71 REG_STRIDE(CH_C_SCRATCH_2, ch_c_scratch_2,
72 	   0x0001c068 + 0x4000 * GSI_EE_AP, 0x80);
73 
74 REG_STRIDE(CH_C_SCRATCH_3, ch_c_scratch_3,
75 	   0x0001c06c + 0x4000 * GSI_EE_AP, 0x80);
76 
77 static const u32 reg_ev_ch_e_cntxt_0_fmask[] = {
78 	[EV_CHTYPE]					= GENMASK(3, 0),
79 	[EV_EE]						= GENMASK(7, 4),
80 	[EV_EVCHID]					= GENMASK(15, 8),
81 	[EV_INTYPE]					= BIT(16),
82 						/* Bits 17-19 reserved */
83 	[EV_CHSTATE]					= GENMASK(23, 20),
84 	[EV_ELEMENT_SIZE]				= GENMASK(31, 24),
85 };
86 
87 REG_STRIDE_FIELDS(EV_CH_E_CNTXT_0, ev_ch_e_cntxt_0,
88 		  0x0001d000 + 0x4000 * GSI_EE_AP, 0x80);
89 
90 REG_STRIDE(EV_CH_E_CNTXT_1, ev_ch_e_cntxt_1,
91 	   0x0001d004 + 0x4000 * GSI_EE_AP, 0x80);
92 
93 REG_STRIDE(EV_CH_E_CNTXT_2, ev_ch_e_cntxt_2,
94 	   0x0001d008 + 0x4000 * GSI_EE_AP, 0x80);
95 
96 REG_STRIDE(EV_CH_E_CNTXT_3, ev_ch_e_cntxt_3,
97 	   0x0001d00c + 0x4000 * GSI_EE_AP, 0x80);
98 
99 REG_STRIDE(EV_CH_E_CNTXT_4, ev_ch_e_cntxt_4,
100 	   0x0001d010 + 0x4000 * GSI_EE_AP, 0x80);
101 
102 static const u32 reg_ev_ch_e_cntxt_8_fmask[] = {
103 	[EV_MODT]					= GENMASK(15, 0),
104 	[EV_MODC]					= GENMASK(23, 16),
105 	[EV_MOD_CNT]					= GENMASK(31, 24),
106 };
107 
108 REG_STRIDE_FIELDS(EV_CH_E_CNTXT_8, ev_ch_e_cntxt_8,
109 		  0x0001d020 + 0x4000 * GSI_EE_AP, 0x80);
110 
111 REG_STRIDE(EV_CH_E_CNTXT_9, ev_ch_e_cntxt_9,
112 	   0x0001d024 + 0x4000 * GSI_EE_AP, 0x80);
113 
114 REG_STRIDE(EV_CH_E_CNTXT_10, ev_ch_e_cntxt_10,
115 	   0x0001d028 + 0x4000 * GSI_EE_AP, 0x80);
116 
117 REG_STRIDE(EV_CH_E_CNTXT_11, ev_ch_e_cntxt_11,
118 	   0x0001d02c + 0x4000 * GSI_EE_AP, 0x80);
119 
120 REG_STRIDE(EV_CH_E_CNTXT_12, ev_ch_e_cntxt_12,
121 	   0x0001d030 + 0x4000 * GSI_EE_AP, 0x80);
122 
123 REG_STRIDE(EV_CH_E_CNTXT_13, ev_ch_e_cntxt_13,
124 	   0x0001d034 + 0x4000 * GSI_EE_AP, 0x80);
125 
126 REG_STRIDE(EV_CH_E_SCRATCH_0, ev_ch_e_scratch_0,
127 	   0x0001d048 + 0x4000 * GSI_EE_AP, 0x80);
128 
129 REG_STRIDE(EV_CH_E_SCRATCH_1, ev_ch_e_scratch_1,
130 	   0x0001d04c + 0x4000 * GSI_EE_AP, 0x80);
131 
132 REG_STRIDE(CH_C_DOORBELL_0, ch_c_doorbell_0,
133 	   0x0001e000 + 0x4000 * GSI_EE_AP, 0x08);
134 
135 REG_STRIDE(EV_CH_E_DOORBELL_0, ev_ch_e_doorbell_0,
136 	   0x0001e100 + 0x4000 * GSI_EE_AP, 0x08);
137 
138 static const u32 reg_gsi_status_fmask[] = {
139 	[ENABLED]					= BIT(0),
140 						/* Bits 1-31 reserved */
141 };
142 
143 REG_FIELDS(GSI_STATUS, gsi_status, 0x0001f000 + 0x4000 * GSI_EE_AP);
144 
145 static const u32 reg_ch_cmd_fmask[] = {
146 	[CH_CHID]					= GENMASK(7, 0),
147 						/* Bits 8-23 reserved */
148 	[CH_OPCODE]					= GENMASK(31, 24),
149 };
150 
151 REG_FIELDS(CH_CMD, ch_cmd, 0x0001f008 + 0x4000 * GSI_EE_AP);
152 
153 static const u32 reg_ev_ch_cmd_fmask[] = {
154 	[EV_CHID]					= GENMASK(7, 0),
155 						/* Bits 8-23 reserved */
156 	[EV_OPCODE]					= GENMASK(31, 24),
157 };
158 
159 REG_FIELDS(EV_CH_CMD, ev_ch_cmd, 0x0001f010 + 0x4000 * GSI_EE_AP);
160 
161 static const u32 reg_generic_cmd_fmask[] = {
162 	[GENERIC_OPCODE]				= GENMASK(4, 0),
163 	[GENERIC_CHID]					= GENMASK(9, 5),
164 	[GENERIC_EE]					= GENMASK(13, 10),
165 						/* Bits 14-31 reserved */
166 };
167 
168 REG_FIELDS(GENERIC_CMD, generic_cmd, 0x0001f018 + 0x4000 * GSI_EE_AP);
169 
170 REG(CNTXT_TYPE_IRQ, cntxt_type_irq, 0x0001f080 + 0x4000 * GSI_EE_AP);
171 
172 REG(CNTXT_TYPE_IRQ_MSK, cntxt_type_irq_msk, 0x0001f088 + 0x4000 * GSI_EE_AP);
173 
174 REG(CNTXT_SRC_CH_IRQ, cntxt_src_ch_irq, 0x0001f090 + 0x4000 * GSI_EE_AP);
175 
176 REG(CNTXT_SRC_EV_CH_IRQ, cntxt_src_ev_ch_irq, 0x0001f094 + 0x4000 * GSI_EE_AP);
177 
178 REG(CNTXT_SRC_CH_IRQ_MSK, cntxt_src_ch_irq_msk,
179     0x0001f098 + 0x4000 * GSI_EE_AP);
180 
181 REG(CNTXT_SRC_EV_CH_IRQ_MSK, cntxt_src_ev_ch_irq_msk,
182     0x0001f09c + 0x4000 * GSI_EE_AP);
183 
184 REG(CNTXT_SRC_CH_IRQ_CLR, cntxt_src_ch_irq_clr,
185     0x0001f0a0 + 0x4000 * GSI_EE_AP);
186 
187 REG(CNTXT_SRC_EV_CH_IRQ_CLR, cntxt_src_ev_ch_irq_clr,
188     0x0001f0a4 + 0x4000 * GSI_EE_AP);
189 
190 REG(CNTXT_SRC_IEOB_IRQ, cntxt_src_ieob_irq, 0x0001f0b0 + 0x4000 * GSI_EE_AP);
191 
192 REG(CNTXT_SRC_IEOB_IRQ_MSK, cntxt_src_ieob_irq_msk,
193     0x0001f0b8 + 0x4000 * GSI_EE_AP);
194 
195 REG(CNTXT_SRC_IEOB_IRQ_CLR, cntxt_src_ieob_irq_clr,
196     0x0001f0c0 + 0x4000 * GSI_EE_AP);
197 
198 REG(CNTXT_GLOB_IRQ_STTS, cntxt_glob_irq_stts, 0x0001f100 + 0x4000 * GSI_EE_AP);
199 
200 REG(CNTXT_GLOB_IRQ_EN, cntxt_glob_irq_en, 0x0001f108 + 0x4000 * GSI_EE_AP);
201 
202 REG(CNTXT_GLOB_IRQ_CLR, cntxt_glob_irq_clr, 0x0001f110 + 0x4000 * GSI_EE_AP);
203 
204 REG(CNTXT_GSI_IRQ_STTS, cntxt_gsi_irq_stts, 0x0001f118 + 0x4000 * GSI_EE_AP);
205 
206 REG(CNTXT_GSI_IRQ_EN, cntxt_gsi_irq_en, 0x0001f120 + 0x4000 * GSI_EE_AP);
207 
208 REG(CNTXT_GSI_IRQ_CLR, cntxt_gsi_irq_clr, 0x0001f128 + 0x4000 * GSI_EE_AP);
209 
210 static const u32 reg_cntxt_intset_fmask[] = {
211 	[INTYPE]					= BIT(0)
212 						/* Bits 1-31 reserved */
213 };
214 
215 REG_FIELDS(CNTXT_INTSET, cntxt_intset, 0x0001f180 + 0x4000 * GSI_EE_AP);
216 
217 REG_FIELDS(ERROR_LOG, error_log, 0x0001f200 + 0x4000 * GSI_EE_AP);
218 
219 REG(ERROR_LOG_CLR, error_log_clr, 0x0001f210 + 0x4000 * GSI_EE_AP);
220 
221 static const u32 reg_cntxt_scratch_0_fmask[] = {
222 	[INTER_EE_RESULT]				= GENMASK(2, 0),
223 						/* Bits 3-4 reserved */
224 	[GENERIC_EE_RESULT]				= GENMASK(7, 5),
225 						/* Bits 8-31 reserved */
226 };
227 
228 REG_FIELDS(CNTXT_SCRATCH_0, cntxt_scratch_0, 0x0001f400 + 0x4000 * GSI_EE_AP);
229 
230 static const struct reg *reg_array[] = {
231 	[INTER_EE_SRC_CH_IRQ_MSK]	= &reg_inter_ee_src_ch_irq_msk,
232 	[INTER_EE_SRC_EV_CH_IRQ_MSK]	= &reg_inter_ee_src_ev_ch_irq_msk,
233 	[CH_C_CNTXT_0]			= &reg_ch_c_cntxt_0,
234 	[CH_C_CNTXT_1]			= &reg_ch_c_cntxt_1,
235 	[CH_C_CNTXT_2]			= &reg_ch_c_cntxt_2,
236 	[CH_C_CNTXT_3]			= &reg_ch_c_cntxt_3,
237 	[CH_C_QOS]			= &reg_ch_c_qos,
238 	[CH_C_SCRATCH_0]		= &reg_ch_c_scratch_0,
239 	[CH_C_SCRATCH_1]		= &reg_ch_c_scratch_1,
240 	[CH_C_SCRATCH_2]		= &reg_ch_c_scratch_2,
241 	[CH_C_SCRATCH_3]		= &reg_ch_c_scratch_3,
242 	[EV_CH_E_CNTXT_0]		= &reg_ev_ch_e_cntxt_0,
243 	[EV_CH_E_CNTXT_1]		= &reg_ev_ch_e_cntxt_1,
244 	[EV_CH_E_CNTXT_2]		= &reg_ev_ch_e_cntxt_2,
245 	[EV_CH_E_CNTXT_3]		= &reg_ev_ch_e_cntxt_3,
246 	[EV_CH_E_CNTXT_4]		= &reg_ev_ch_e_cntxt_4,
247 	[EV_CH_E_CNTXT_8]		= &reg_ev_ch_e_cntxt_8,
248 	[EV_CH_E_CNTXT_9]		= &reg_ev_ch_e_cntxt_9,
249 	[EV_CH_E_CNTXT_10]		= &reg_ev_ch_e_cntxt_10,
250 	[EV_CH_E_CNTXT_11]		= &reg_ev_ch_e_cntxt_11,
251 	[EV_CH_E_CNTXT_12]		= &reg_ev_ch_e_cntxt_12,
252 	[EV_CH_E_CNTXT_13]		= &reg_ev_ch_e_cntxt_13,
253 	[EV_CH_E_SCRATCH_0]		= &reg_ev_ch_e_scratch_0,
254 	[EV_CH_E_SCRATCH_1]		= &reg_ev_ch_e_scratch_1,
255 	[CH_C_DOORBELL_0]		= &reg_ch_c_doorbell_0,
256 	[EV_CH_E_DOORBELL_0]		= &reg_ev_ch_e_doorbell_0,
257 	[GSI_STATUS]			= &reg_gsi_status,
258 	[CH_CMD]			= &reg_ch_cmd,
259 	[EV_CH_CMD]			= &reg_ev_ch_cmd,
260 	[GENERIC_CMD]			= &reg_generic_cmd,
261 	[CNTXT_TYPE_IRQ]		= &reg_cntxt_type_irq,
262 	[CNTXT_TYPE_IRQ_MSK]		= &reg_cntxt_type_irq_msk,
263 	[CNTXT_SRC_CH_IRQ]		= &reg_cntxt_src_ch_irq,
264 	[CNTXT_SRC_EV_CH_IRQ]		= &reg_cntxt_src_ev_ch_irq,
265 	[CNTXT_SRC_CH_IRQ_MSK]		= &reg_cntxt_src_ch_irq_msk,
266 	[CNTXT_SRC_EV_CH_IRQ_MSK]	= &reg_cntxt_src_ev_ch_irq_msk,
267 	[CNTXT_SRC_CH_IRQ_CLR]		= &reg_cntxt_src_ch_irq_clr,
268 	[CNTXT_SRC_EV_CH_IRQ_CLR]	= &reg_cntxt_src_ev_ch_irq_clr,
269 	[CNTXT_SRC_IEOB_IRQ]		= &reg_cntxt_src_ieob_irq,
270 	[CNTXT_SRC_IEOB_IRQ_MSK]	= &reg_cntxt_src_ieob_irq_msk,
271 	[CNTXT_SRC_IEOB_IRQ_CLR]	= &reg_cntxt_src_ieob_irq_clr,
272 	[CNTXT_GLOB_IRQ_STTS]		= &reg_cntxt_glob_irq_stts,
273 	[CNTXT_GLOB_IRQ_EN]		= &reg_cntxt_glob_irq_en,
274 	[CNTXT_GLOB_IRQ_CLR]		= &reg_cntxt_glob_irq_clr,
275 	[CNTXT_GSI_IRQ_STTS]		= &reg_cntxt_gsi_irq_stts,
276 	[CNTXT_GSI_IRQ_EN]		= &reg_cntxt_gsi_irq_en,
277 	[CNTXT_GSI_IRQ_CLR]		= &reg_cntxt_gsi_irq_clr,
278 	[CNTXT_INTSET]			= &reg_cntxt_intset,
279 	[ERROR_LOG]			= &reg_error_log,
280 	[ERROR_LOG_CLR]			= &reg_error_log_clr,
281 	[CNTXT_SCRATCH_0]		= &reg_cntxt_scratch_0,
282 };
283 
284 const struct regs gsi_regs_v3_1 = {
285 	.reg_count	= ARRAY_SIZE(reg_array),
286 	.reg		= reg_array,
287 };
288