xref: /openbmc/linux/drivers/net/ipa/reg/gsi_reg-v3.1.c (revision 3f3741c9039fe20ff2512301af05c83c06f06165) 
1 // SPDX-License-Identifier: GPL-2.0
2 
3 /* Copyright (C) 2023 Linaro Ltd. */
4 
5 #include <linux/types.h>
6 
7 #include "../gsi.h"
8 #include "../reg.h"
9 #include "../gsi_reg.h"
10 
11 /* The inter-EE IRQ registers are relative to gsi->virt_raw (IPA v3.5+) */
12 
13 REG(INTER_EE_SRC_CH_IRQ_MSK, inter_ee_src_ch_irq_msk,
14     0x0000c020 + 0x1000 * GSI_EE_AP);
15 
16 REG(INTER_EE_SRC_EV_CH_IRQ_MSK, inter_ee_src_ev_ch_irq_msk,
17     0x0000c024 + 0x1000 * GSI_EE_AP);
18 
19 /* All other register offsets are relative to gsi->virt */
20 
21 static const u32 reg_ch_c_cntxt_0_fmask[] = {
22 	[CHTYPE_PROTOCOL]				= GENMASK(2, 0),
23 	[CHTYPE_DIR]					= BIT(3),
24 	[CH_EE]						= GENMASK(7, 4),
25 	[CHID]						= GENMASK(12, 8),
26 						/* Bit 13 reserved */
27 	[ERINDEX]					= GENMASK(18, 14),
28 						/* Bit 19 reserved */
29 	[CHSTATE]					= GENMASK(23, 20),
30 	[ELEMENT_SIZE]					= GENMASK(31, 24),
31 };
32 
33 REG_STRIDE_FIELDS(CH_C_CNTXT_0, ch_c_cntxt_0,
34 		  0x0001c000 + 0x4000 * GSI_EE_AP, 0x80);
35 
36 static const u32 reg_ch_c_cntxt_1_fmask[] = {
37 	[CH_R_LENGTH]					= GENMASK(15, 0),
38 						/* Bits 16-31 reserved */
39 };
40 
41 REG_STRIDE_FIELDS(CH_C_CNTXT_1, ch_c_cntxt_1,
42 		  0x0001c004 + 0x4000 * GSI_EE_AP, 0x80);
43 
44 REG_STRIDE(CH_C_CNTXT_2, ch_c_cntxt_2, 0x0001c008 + 0x4000 * GSI_EE_AP, 0x80);
45 
46 REG_STRIDE(CH_C_CNTXT_3, ch_c_cntxt_3, 0x0001c00c + 0x4000 * GSI_EE_AP, 0x80);
47 
48 static const u32 reg_ch_c_qos_fmask[] = {
49 	[WRR_WEIGHT]					= GENMASK(3, 0),
50 						/* Bits 4-7 reserved */
51 	[MAX_PREFETCH]					= BIT(8),
52 	[USE_DB_ENG]					= BIT(9),
53 						/* Bits 10-31 reserved */
54 };
55 
56 REG_STRIDE_FIELDS(CH_C_QOS, ch_c_qos, 0x0001c05c + 0x4000 * GSI_EE_AP, 0x80);
57 
58 static const u32 reg_error_log_fmask[] = {
59 	[ERR_ARG3]					= GENMASK(3, 0),
60 	[ERR_ARG2]					= GENMASK(7, 4),
61 	[ERR_ARG1]					= GENMASK(11, 8),
62 	[ERR_CODE]					= GENMASK(15, 12),
63 						/* Bits 16-18 reserved */
64 	[ERR_VIRT_IDX]					= GENMASK(23, 19),
65 	[ERR_TYPE]					= GENMASK(27, 24),
66 	[ERR_EE]					= GENMASK(31, 28),
67 };
68 
69 REG_FIELDS(ERROR_LOG, error_log, 0x0001f200 + 0x4000 * GSI_EE_AP);
70 
71 REG(ERROR_LOG_CLR, error_log_clr, 0x0001f210 + 0x4000 * GSI_EE_AP);
72 
73 REG_STRIDE(CH_C_SCRATCH_0, ch_c_scratch_0,
74 	   0x0001c060 + 0x4000 * GSI_EE_AP, 0x80);
75 
76 REG_STRIDE(CH_C_SCRATCH_1, ch_c_scratch_1,
77 	   0x0001c064 + 0x4000 * GSI_EE_AP, 0x80);
78 
79 REG_STRIDE(CH_C_SCRATCH_2, ch_c_scratch_2,
80 	   0x0001c068 + 0x4000 * GSI_EE_AP, 0x80);
81 
82 REG_STRIDE(CH_C_SCRATCH_3, ch_c_scratch_3,
83 	   0x0001c06c + 0x4000 * GSI_EE_AP, 0x80);
84 
85 static const u32 reg_ev_ch_e_cntxt_0_fmask[] = {
86 	[EV_CHTYPE]					= GENMASK(3, 0),
87 	[EV_EE]						= GENMASK(7, 4),
88 	[EV_EVCHID]					= GENMASK(15, 8),
89 	[EV_INTYPE]					= BIT(16),
90 						/* Bits 17-19 reserved */
91 	[EV_CHSTATE]					= GENMASK(23, 20),
92 	[EV_ELEMENT_SIZE]				= GENMASK(31, 24),
93 };
94 
95 REG_STRIDE_FIELDS(EV_CH_E_CNTXT_0, ev_ch_e_cntxt_0,
96 		  0x0001d000 + 0x4000 * GSI_EE_AP, 0x80);
97 
98 REG_STRIDE(EV_CH_E_CNTXT_1, ev_ch_e_cntxt_1,
99 	   0x0001d004 + 0x4000 * GSI_EE_AP, 0x80);
100 
101 REG_STRIDE(EV_CH_E_CNTXT_2, ev_ch_e_cntxt_2,
102 	   0x0001d008 + 0x4000 * GSI_EE_AP, 0x80);
103 
104 REG_STRIDE(EV_CH_E_CNTXT_3, ev_ch_e_cntxt_3,
105 	   0x0001d00c + 0x4000 * GSI_EE_AP, 0x80);
106 
107 REG_STRIDE(EV_CH_E_CNTXT_4, ev_ch_e_cntxt_4,
108 	   0x0001d010 + 0x4000 * GSI_EE_AP, 0x80);
109 
110 static const u32 reg_ev_ch_e_cntxt_8_fmask[] = {
111 	[EV_MODT]					= GENMASK(15, 0),
112 	[EV_MODC]					= GENMASK(23, 16),
113 	[EV_MOD_CNT]					= GENMASK(31, 24),
114 };
115 
116 REG_STRIDE_FIELDS(EV_CH_E_CNTXT_8, ev_ch_e_cntxt_8,
117 		  0x0001d020 + 0x4000 * GSI_EE_AP, 0x80);
118 
119 REG_STRIDE(EV_CH_E_CNTXT_9, ev_ch_e_cntxt_9,
120 	   0x0001d024 + 0x4000 * GSI_EE_AP, 0x80);
121 
122 REG_STRIDE(EV_CH_E_CNTXT_10, ev_ch_e_cntxt_10,
123 	   0x0001d028 + 0x4000 * GSI_EE_AP, 0x80);
124 
125 REG_STRIDE(EV_CH_E_CNTXT_11, ev_ch_e_cntxt_11,
126 	   0x0001d02c + 0x4000 * GSI_EE_AP, 0x80);
127 
128 REG_STRIDE(EV_CH_E_CNTXT_12, ev_ch_e_cntxt_12,
129 	   0x0001d030 + 0x4000 * GSI_EE_AP, 0x80);
130 
131 REG_STRIDE(EV_CH_E_CNTXT_13, ev_ch_e_cntxt_13,
132 	   0x0001d034 + 0x4000 * GSI_EE_AP, 0x80);
133 
134 REG_STRIDE(EV_CH_E_SCRATCH_0, ev_ch_e_scratch_0,
135 	   0x0001d048 + 0x4000 * GSI_EE_AP, 0x80);
136 
137 REG_STRIDE(EV_CH_E_SCRATCH_1, ev_ch_e_scratch_1,
138 	   0x0001d04c + 0x4000 * GSI_EE_AP, 0x80);
139 
140 REG_STRIDE(CH_C_DOORBELL_0, ch_c_doorbell_0,
141 	   0x0001e000 + 0x4000 * GSI_EE_AP, 0x08);
142 
143 REG_STRIDE(EV_CH_E_DOORBELL_0, ev_ch_e_doorbell_0,
144 	   0x0001e100 + 0x4000 * GSI_EE_AP, 0x08);
145 
146 static const u32 reg_gsi_status_fmask[] = {
147 	[ENABLED]					= BIT(0),
148 						/* Bits 1-31 reserved */
149 };
150 
151 REG_FIELDS(GSI_STATUS, gsi_status, 0x0001f000 + 0x4000 * GSI_EE_AP);
152 
153 static const u32 reg_ch_cmd_fmask[] = {
154 	[CH_CHID]					= GENMASK(7, 0),
155 	[CH_OPCODE]					= GENMASK(31, 24),
156 };
157 
158 REG_FIELDS(CH_CMD, ch_cmd, 0x0001f008 + 0x4000 * GSI_EE_AP);
159 
160 static const u32 reg_ev_ch_cmd_fmask[] = {
161 	[EV_CHID]					= GENMASK(7, 0),
162 	[EV_OPCODE]					= GENMASK(31, 24),
163 };
164 
165 REG_FIELDS(EV_CH_CMD, ev_ch_cmd, 0x0001f010 + 0x4000 * GSI_EE_AP);
166 
167 static const u32 reg_generic_cmd_fmask[] = {
168 	[GENERIC_OPCODE]				= GENMASK(4, 0),
169 	[GENERIC_CHID]					= GENMASK(9, 5),
170 	[GENERIC_EE]					= GENMASK(13, 10),
171 						/* Bits 14-31 reserved */
172 };
173 
174 REG_FIELDS(GENERIC_CMD, generic_cmd, 0x0001f018 + 0x4000 * GSI_EE_AP);
175 
176 REG(CNTXT_TYPE_IRQ, cntxt_type_irq, 0x0001f080 + 0x4000 * GSI_EE_AP);
177 
178 REG(CNTXT_TYPE_IRQ_MSK, cntxt_type_irq_msk, 0x0001f088 + 0x4000 * GSI_EE_AP);
179 
180 REG(CNTXT_SRC_CH_IRQ, cntxt_src_ch_irq, 0x0001f090 + 0x4000 * GSI_EE_AP);
181 
182 REG(CNTXT_SRC_EV_CH_IRQ, cntxt_src_ev_ch_irq, 0x0001f094 + 0x4000 * GSI_EE_AP);
183 
184 REG(CNTXT_SRC_CH_IRQ_MSK, cntxt_src_ch_irq_msk,
185     0x0001f098 + 0x4000 * GSI_EE_AP);
186 
187 REG(CNTXT_SRC_EV_CH_IRQ_MSK, cntxt_src_ev_ch_irq_msk,
188     0x0001f09c + 0x4000 * GSI_EE_AP);
189 
190 REG(CNTXT_SRC_CH_IRQ_CLR, cntxt_src_ch_irq_clr,
191     0x0001f0a0 + 0x4000 * GSI_EE_AP);
192 
193 REG(CNTXT_SRC_EV_CH_IRQ_CLR, cntxt_src_ev_ch_irq_clr,
194     0x0001f0a4 + 0x4000 * GSI_EE_AP);
195 
196 REG(CNTXT_SRC_IEOB_IRQ, cntxt_src_ieob_irq, 0x0001f0b0 + 0x4000 * GSI_EE_AP);
197 
198 REG(CNTXT_SRC_IEOB_IRQ_MSK, cntxt_src_ieob_irq_msk,
199     0x0001f0b8 + 0x4000 * GSI_EE_AP);
200 
201 REG(CNTXT_SRC_IEOB_IRQ_CLR, cntxt_src_ieob_irq_clr,
202     0x0001f0c0 + 0x4000 * GSI_EE_AP);
203 
204 REG(CNTXT_GLOB_IRQ_STTS, cntxt_glob_irq_stts, 0x0001f100 + 0x4000 * GSI_EE_AP);
205 
206 REG(CNTXT_GLOB_IRQ_EN, cntxt_glob_irq_en, 0x0001f108 + 0x4000 * GSI_EE_AP);
207 
208 REG(CNTXT_GLOB_IRQ_CLR, cntxt_glob_irq_clr, 0x0001f110 + 0x4000 * GSI_EE_AP);
209 
210 REG(CNTXT_GSI_IRQ_STTS, cntxt_gsi_irq_stts, 0x0001f118 + 0x4000 * GSI_EE_AP);
211 
212 REG(CNTXT_GSI_IRQ_EN, cntxt_gsi_irq_en, 0x0001f120 + 0x4000 * GSI_EE_AP);
213 
214 REG(CNTXT_GSI_IRQ_CLR, cntxt_gsi_irq_clr, 0x0001f128 + 0x4000 * GSI_EE_AP);
215 
216 static const u32 reg_cntxt_intset_fmask[] = {
217 	[INTYPE]					= BIT(0)
218 						/* Bits 1-31 reserved */
219 };
220 
221 REG_FIELDS(CNTXT_INTSET, cntxt_intset, 0x0001f180 + 0x4000 * GSI_EE_AP);
222 
223 static const u32 reg_cntxt_scratch_0_fmask[] = {
224 	[INTER_EE_RESULT]				= GENMASK(2, 0),
225 						/* Bits 3-4 reserved */
226 	[GENERIC_EE_RESULT]				= GENMASK(7, 5),
227 						/* Bits 8-31 reserved */
228 };
229 
230 REG_FIELDS(CNTXT_SCRATCH_0, cntxt_scratch_0, 0x0001f400 + 0x4000 * GSI_EE_AP);
231 
232 static const struct reg *reg_array[] = {
233 	[INTER_EE_SRC_CH_IRQ_MSK]	= &reg_inter_ee_src_ch_irq_msk,
234 	[INTER_EE_SRC_EV_CH_IRQ_MSK]	= &reg_inter_ee_src_ev_ch_irq_msk,
235 	[CH_C_CNTXT_0]			= &reg_ch_c_cntxt_0,
236 	[CH_C_CNTXT_1]			= &reg_ch_c_cntxt_1,
237 	[CH_C_CNTXT_2]			= &reg_ch_c_cntxt_2,
238 	[CH_C_CNTXT_3]			= &reg_ch_c_cntxt_3,
239 	[CH_C_QOS]			= &reg_ch_c_qos,
240 	[CH_C_SCRATCH_0]		= &reg_ch_c_scratch_0,
241 	[CH_C_SCRATCH_1]		= &reg_ch_c_scratch_1,
242 	[CH_C_SCRATCH_2]		= &reg_ch_c_scratch_2,
243 	[CH_C_SCRATCH_3]		= &reg_ch_c_scratch_3,
244 	[EV_CH_E_CNTXT_0]		= &reg_ev_ch_e_cntxt_0,
245 	[EV_CH_E_CNTXT_1]		= &reg_ev_ch_e_cntxt_1,
246 	[EV_CH_E_CNTXT_2]		= &reg_ev_ch_e_cntxt_2,
247 	[EV_CH_E_CNTXT_3]		= &reg_ev_ch_e_cntxt_3,
248 	[EV_CH_E_CNTXT_4]		= &reg_ev_ch_e_cntxt_4,
249 	[EV_CH_E_CNTXT_8]		= &reg_ev_ch_e_cntxt_8,
250 	[EV_CH_E_CNTXT_9]		= &reg_ev_ch_e_cntxt_9,
251 	[EV_CH_E_CNTXT_10]		= &reg_ev_ch_e_cntxt_10,
252 	[EV_CH_E_CNTXT_11]		= &reg_ev_ch_e_cntxt_11,
253 	[EV_CH_E_CNTXT_12]		= &reg_ev_ch_e_cntxt_12,
254 	[EV_CH_E_CNTXT_13]		= &reg_ev_ch_e_cntxt_13,
255 	[EV_CH_E_SCRATCH_0]		= &reg_ev_ch_e_scratch_0,
256 	[EV_CH_E_SCRATCH_1]		= &reg_ev_ch_e_scratch_1,
257 	[CH_C_DOORBELL_0]		= &reg_ch_c_doorbell_0,
258 	[EV_CH_E_DOORBELL_0]		= &reg_ev_ch_e_doorbell_0,
259 	[GSI_STATUS]			= &reg_gsi_status,
260 	[CH_CMD]			= &reg_ch_cmd,
261 	[EV_CH_CMD]			= &reg_ev_ch_cmd,
262 	[GENERIC_CMD]			= &reg_generic_cmd,
263 	[CNTXT_TYPE_IRQ]		= &reg_cntxt_type_irq,
264 	[CNTXT_TYPE_IRQ_MSK]		= &reg_cntxt_type_irq_msk,
265 	[CNTXT_SRC_CH_IRQ]		= &reg_cntxt_src_ch_irq,
266 	[CNTXT_SRC_EV_CH_IRQ]		= &reg_cntxt_src_ev_ch_irq,
267 	[CNTXT_SRC_CH_IRQ_MSK]		= &reg_cntxt_src_ch_irq_msk,
268 	[CNTXT_SRC_EV_CH_IRQ_MSK]	= &reg_cntxt_src_ev_ch_irq_msk,
269 	[CNTXT_SRC_CH_IRQ_CLR]		= &reg_cntxt_src_ch_irq_clr,
270 	[CNTXT_SRC_EV_CH_IRQ_CLR]	= &reg_cntxt_src_ev_ch_irq_clr,
271 	[CNTXT_SRC_IEOB_IRQ]		= &reg_cntxt_src_ieob_irq,
272 	[CNTXT_SRC_IEOB_IRQ_MSK]	= &reg_cntxt_src_ieob_irq_msk,
273 	[CNTXT_SRC_IEOB_IRQ_CLR]	= &reg_cntxt_src_ieob_irq_clr,
274 	[CNTXT_GLOB_IRQ_STTS]		= &reg_cntxt_glob_irq_stts,
275 	[CNTXT_GLOB_IRQ_EN]		= &reg_cntxt_glob_irq_en,
276 	[CNTXT_GLOB_IRQ_CLR]		= &reg_cntxt_glob_irq_clr,
277 	[CNTXT_GSI_IRQ_STTS]		= &reg_cntxt_gsi_irq_stts,
278 	[CNTXT_GSI_IRQ_EN]		= &reg_cntxt_gsi_irq_en,
279 	[CNTXT_GSI_IRQ_CLR]		= &reg_cntxt_gsi_irq_clr,
280 	[CNTXT_INTSET]			= &reg_cntxt_intset,
281 	[ERROR_LOG]			= &reg_error_log,
282 	[ERROR_LOG_CLR]			= &reg_error_log_clr,
283 	[CNTXT_SCRATCH_0]		= &reg_cntxt_scratch_0,
284 };
285 
286 const struct regs gsi_regs_v3_1 = {
287 	.reg_count	= ARRAY_SIZE(reg_array),
288 	.reg		= reg_array,
289 };
290