1 // SPDX-License-Identifier: GPL-2.0 2 3 /* Copyright (C) 2023 Linaro Ltd. */ 4 5 #include <linux/types.h> 6 7 #include "../gsi.h" 8 #include "../reg.h" 9 #include "../gsi_reg.h" 10 11 /* The inter-EE IRQ registers are relative to gsi->virt_raw (IPA v3.5+) */ 12 13 REG(INTER_EE_SRC_CH_IRQ_MSK, inter_ee_src_ch_irq_msk, 14 0x0000c020 + 0x1000 * GSI_EE_AP); 15 16 REG(INTER_EE_SRC_EV_CH_IRQ_MSK, inter_ee_src_ev_ch_irq_msk, 17 0x0000c024 + 0x1000 * GSI_EE_AP); 18 19 /* All other register offsets are relative to gsi->virt */ 20 21 static const u32 reg_ch_c_cntxt_0_fmask[] = { 22 [CHTYPE_PROTOCOL] = GENMASK(2, 0), 23 [CHTYPE_DIR] = BIT(3), 24 [CH_EE] = GENMASK(7, 4), 25 [CHID] = GENMASK(12, 8), 26 /* Bit 13 reserved */ 27 [ERINDEX] = GENMASK(18, 14), 28 /* Bit 19 reserved */ 29 [CHSTATE] = GENMASK(23, 20), 30 [ELEMENT_SIZE] = GENMASK(31, 24), 31 }; 32 33 REG_STRIDE_FIELDS(CH_C_CNTXT_0, ch_c_cntxt_0, 34 0x0001c000 + 0x4000 * GSI_EE_AP, 0x80); 35 36 static const u32 reg_ch_c_cntxt_1_fmask[] = { 37 [CH_R_LENGTH] = GENMASK(15, 0), 38 /* Bits 16-31 reserved */ 39 }; 40 41 REG_STRIDE_FIELDS(CH_C_CNTXT_1, ch_c_cntxt_1, 42 0x0001c004 + 0x4000 * GSI_EE_AP, 0x80); 43 44 REG_STRIDE(CH_C_CNTXT_2, ch_c_cntxt_2, 0x0001c008 + 0x4000 * GSI_EE_AP, 0x80); 45 46 REG_STRIDE(CH_C_CNTXT_3, ch_c_cntxt_3, 0x0001c00c + 0x4000 * GSI_EE_AP, 0x80); 47 48 static const u32 reg_ch_c_qos_fmask[] = { 49 [WRR_WEIGHT] = GENMASK(3, 0), 50 /* Bits 4-7 reserved */ 51 [MAX_PREFETCH] = BIT(8), 52 [USE_DB_ENG] = BIT(9), 53 /* Bits 10-31 reserved */ 54 }; 55 56 REG_STRIDE_FIELDS(CH_C_QOS, ch_c_qos, 0x0001c05c + 0x4000 * GSI_EE_AP, 0x80); 57 58 REG(ERROR_LOG, error_log, 0x0001f200 + 0x4000 * GSI_EE_AP); 59 60 REG(ERROR_LOG_CLR, error_log_clr, 0x0001f210 + 0x4000 * GSI_EE_AP); 61 62 REG_STRIDE(CH_C_SCRATCH_0, ch_c_scratch_0, 63 0x0001c060 + 0x4000 * GSI_EE_AP, 0x80); 64 65 REG_STRIDE(CH_C_SCRATCH_1, ch_c_scratch_1, 66 0x0001c064 + 0x4000 * GSI_EE_AP, 0x80); 67 68 REG_STRIDE(CH_C_SCRATCH_2, ch_c_scratch_2, 69 0x0001c068 + 0x4000 * GSI_EE_AP, 0x80); 70 71 REG_STRIDE(CH_C_SCRATCH_3, ch_c_scratch_3, 72 0x0001c06c + 0x4000 * GSI_EE_AP, 0x80); 73 74 REG_STRIDE(EV_CH_E_CNTXT_0, ev_ch_e_cntxt_0, 75 0x0001d000 + 0x4000 * GSI_EE_AP, 0x80); 76 77 REG_STRIDE(EV_CH_E_CNTXT_1, ev_ch_e_cntxt_1, 78 0x0001d004 + 0x4000 * GSI_EE_AP, 0x80); 79 80 REG_STRIDE(EV_CH_E_CNTXT_2, ev_ch_e_cntxt_2, 81 0x0001d008 + 0x4000 * GSI_EE_AP, 0x80); 82 83 REG_STRIDE(EV_CH_E_CNTXT_3, ev_ch_e_cntxt_3, 84 0x0001d00c + 0x4000 * GSI_EE_AP, 0x80); 85 86 REG_STRIDE(EV_CH_E_CNTXT_4, ev_ch_e_cntxt_4, 87 0x0001d010 + 0x4000 * GSI_EE_AP, 0x80); 88 89 REG_STRIDE(EV_CH_E_CNTXT_8, ev_ch_e_cntxt_8, 90 0x0001d020 + 0x4000 * GSI_EE_AP, 0x80); 91 92 REG_STRIDE(EV_CH_E_CNTXT_9, ev_ch_e_cntxt_9, 93 0x0001d024 + 0x4000 * GSI_EE_AP, 0x80); 94 95 REG_STRIDE(EV_CH_E_CNTXT_10, ev_ch_e_cntxt_10, 96 0x0001d028 + 0x4000 * GSI_EE_AP, 0x80); 97 98 REG_STRIDE(EV_CH_E_CNTXT_11, ev_ch_e_cntxt_11, 99 0x0001d02c + 0x4000 * GSI_EE_AP, 0x80); 100 101 REG_STRIDE(EV_CH_E_CNTXT_12, ev_ch_e_cntxt_12, 102 0x0001d030 + 0x4000 * GSI_EE_AP, 0x80); 103 104 REG_STRIDE(EV_CH_E_CNTXT_13, ev_ch_e_cntxt_13, 105 0x0001d034 + 0x4000 * GSI_EE_AP, 0x80); 106 107 REG_STRIDE(EV_CH_E_SCRATCH_0, ev_ch_e_scratch_0, 108 0x0001d048 + 0x4000 * GSI_EE_AP, 0x80); 109 110 REG_STRIDE(EV_CH_E_SCRATCH_1, ev_ch_e_scratch_1, 111 0x0001d04c + 0x4000 * GSI_EE_AP, 0x80); 112 113 REG_STRIDE(CH_C_DOORBELL_0, ch_c_doorbell_0, 114 0x0001e000 + 0x4000 * GSI_EE_AP, 0x08); 115 116 REG_STRIDE(EV_CH_E_DOORBELL_0, ev_ch_e_doorbell_0, 117 0x0001e100 + 0x4000 * GSI_EE_AP, 0x08); 118 119 REG(GSI_STATUS, gsi_status, 0x0001f000 + 0x4000 * GSI_EE_AP); 120 121 REG(CH_CMD, ch_cmd, 0x0001f008 + 0x4000 * GSI_EE_AP); 122 123 REG(EV_CH_CMD, ev_ch_cmd, 0x0001f010 + 0x4000 * GSI_EE_AP); 124 125 REG(GENERIC_CMD, generic_cmd, 0x0001f018 + 0x4000 * GSI_EE_AP); 126 127 REG(CNTXT_TYPE_IRQ, cntxt_type_irq, 0x0001f080 + 0x4000 * GSI_EE_AP); 128 129 REG(CNTXT_TYPE_IRQ_MSK, cntxt_type_irq_msk, 0x0001f088 + 0x4000 * GSI_EE_AP); 130 131 REG(CNTXT_SRC_CH_IRQ, cntxt_src_ch_irq, 0x0001f090 + 0x4000 * GSI_EE_AP); 132 133 REG(CNTXT_SRC_EV_CH_IRQ, cntxt_src_ev_ch_irq, 0x0001f094 + 0x4000 * GSI_EE_AP); 134 135 REG(CNTXT_SRC_CH_IRQ_MSK, cntxt_src_ch_irq_msk, 136 0x0001f098 + 0x4000 * GSI_EE_AP); 137 138 REG(CNTXT_SRC_EV_CH_IRQ_MSK, cntxt_src_ev_ch_irq_msk, 139 0x0001f09c + 0x4000 * GSI_EE_AP); 140 141 REG(CNTXT_SRC_CH_IRQ_CLR, cntxt_src_ch_irq_clr, 142 0x0001f0a0 + 0x4000 * GSI_EE_AP); 143 144 REG(CNTXT_SRC_EV_CH_IRQ_CLR, cntxt_src_ev_ch_irq_clr, 145 0x0001f0a4 + 0x4000 * GSI_EE_AP); 146 147 REG(CNTXT_SRC_IEOB_IRQ, cntxt_src_ieob_irq, 0x0001f0b0 + 0x4000 * GSI_EE_AP); 148 149 REG(CNTXT_SRC_IEOB_IRQ_MSK, cntxt_src_ieob_irq_msk, 150 0x0001f0b8 + 0x4000 * GSI_EE_AP); 151 152 REG(CNTXT_SRC_IEOB_IRQ_CLR, cntxt_src_ieob_irq_clr, 153 0x0001f0c0 + 0x4000 * GSI_EE_AP); 154 155 REG(CNTXT_GLOB_IRQ_STTS, cntxt_glob_irq_stts, 0x0001f100 + 0x4000 * GSI_EE_AP); 156 157 REG(CNTXT_GLOB_IRQ_EN, cntxt_glob_irq_en, 0x0001f108 + 0x4000 * GSI_EE_AP); 158 159 REG(CNTXT_GLOB_IRQ_CLR, cntxt_glob_irq_clr, 0x0001f110 + 0x4000 * GSI_EE_AP); 160 161 REG(CNTXT_GSI_IRQ_STTS, cntxt_gsi_irq_stts, 0x0001f118 + 0x4000 * GSI_EE_AP); 162 163 REG(CNTXT_GSI_IRQ_EN, cntxt_gsi_irq_en, 0x0001f120 + 0x4000 * GSI_EE_AP); 164 165 REG(CNTXT_GSI_IRQ_CLR, cntxt_gsi_irq_clr, 0x0001f128 + 0x4000 * GSI_EE_AP); 166 167 REG(CNTXT_INTSET, cntxt_intset, 0x0001f180 + 0x4000 * GSI_EE_AP); 168 169 REG(CNTXT_SCRATCH_0, cntxt_scratch_0, 0x0001f400 + 0x4000 * GSI_EE_AP); 170 171 static const struct reg *reg_array[] = { 172 [INTER_EE_SRC_CH_IRQ_MSK] = ®_inter_ee_src_ch_irq_msk, 173 [INTER_EE_SRC_EV_CH_IRQ_MSK] = ®_inter_ee_src_ev_ch_irq_msk, 174 [CH_C_CNTXT_0] = ®_ch_c_cntxt_0, 175 [CH_C_CNTXT_1] = ®_ch_c_cntxt_1, 176 [CH_C_CNTXT_2] = ®_ch_c_cntxt_2, 177 [CH_C_CNTXT_3] = ®_ch_c_cntxt_3, 178 [CH_C_QOS] = ®_ch_c_qos, 179 [CH_C_SCRATCH_0] = ®_ch_c_scratch_0, 180 [CH_C_SCRATCH_1] = ®_ch_c_scratch_1, 181 [CH_C_SCRATCH_2] = ®_ch_c_scratch_2, 182 [CH_C_SCRATCH_3] = ®_ch_c_scratch_3, 183 [EV_CH_E_CNTXT_0] = ®_ev_ch_e_cntxt_0, 184 [EV_CH_E_CNTXT_1] = ®_ev_ch_e_cntxt_1, 185 [EV_CH_E_CNTXT_2] = ®_ev_ch_e_cntxt_2, 186 [EV_CH_E_CNTXT_3] = ®_ev_ch_e_cntxt_3, 187 [EV_CH_E_CNTXT_4] = ®_ev_ch_e_cntxt_4, 188 [EV_CH_E_CNTXT_8] = ®_ev_ch_e_cntxt_8, 189 [EV_CH_E_CNTXT_9] = ®_ev_ch_e_cntxt_9, 190 [EV_CH_E_CNTXT_10] = ®_ev_ch_e_cntxt_10, 191 [EV_CH_E_CNTXT_11] = ®_ev_ch_e_cntxt_11, 192 [EV_CH_E_CNTXT_12] = ®_ev_ch_e_cntxt_12, 193 [EV_CH_E_CNTXT_13] = ®_ev_ch_e_cntxt_13, 194 [EV_CH_E_SCRATCH_0] = ®_ev_ch_e_scratch_0, 195 [EV_CH_E_SCRATCH_1] = ®_ev_ch_e_scratch_1, 196 [CH_C_DOORBELL_0] = ®_ch_c_doorbell_0, 197 [EV_CH_E_DOORBELL_0] = ®_ev_ch_e_doorbell_0, 198 [GSI_STATUS] = ®_gsi_status, 199 [CH_CMD] = ®_ch_cmd, 200 [EV_CH_CMD] = ®_ev_ch_cmd, 201 [GENERIC_CMD] = ®_generic_cmd, 202 [CNTXT_TYPE_IRQ] = ®_cntxt_type_irq, 203 [CNTXT_TYPE_IRQ_MSK] = ®_cntxt_type_irq_msk, 204 [CNTXT_SRC_CH_IRQ] = ®_cntxt_src_ch_irq, 205 [CNTXT_SRC_EV_CH_IRQ] = ®_cntxt_src_ev_ch_irq, 206 [CNTXT_SRC_CH_IRQ_MSK] = ®_cntxt_src_ch_irq_msk, 207 [CNTXT_SRC_EV_CH_IRQ_MSK] = ®_cntxt_src_ev_ch_irq_msk, 208 [CNTXT_SRC_CH_IRQ_CLR] = ®_cntxt_src_ch_irq_clr, 209 [CNTXT_SRC_EV_CH_IRQ_CLR] = ®_cntxt_src_ev_ch_irq_clr, 210 [CNTXT_SRC_IEOB_IRQ] = ®_cntxt_src_ieob_irq, 211 [CNTXT_SRC_IEOB_IRQ_MSK] = ®_cntxt_src_ieob_irq_msk, 212 [CNTXT_SRC_IEOB_IRQ_CLR] = ®_cntxt_src_ieob_irq_clr, 213 [CNTXT_GLOB_IRQ_STTS] = ®_cntxt_glob_irq_stts, 214 [CNTXT_GLOB_IRQ_EN] = ®_cntxt_glob_irq_en, 215 [CNTXT_GLOB_IRQ_CLR] = ®_cntxt_glob_irq_clr, 216 [CNTXT_GSI_IRQ_STTS] = ®_cntxt_gsi_irq_stts, 217 [CNTXT_GSI_IRQ_EN] = ®_cntxt_gsi_irq_en, 218 [CNTXT_GSI_IRQ_CLR] = ®_cntxt_gsi_irq_clr, 219 [CNTXT_INTSET] = ®_cntxt_intset, 220 [ERROR_LOG] = ®_error_log, 221 [ERROR_LOG_CLR] = ®_error_log_clr, 222 [CNTXT_SCRATCH_0] = ®_cntxt_scratch_0, 223 }; 224 225 const struct regs gsi_regs_v3_1 = { 226 .reg_count = ARRAY_SIZE(reg_array), 227 .reg = reg_array, 228 }; 229