12c7b9b93SAlex Elder // SPDX-License-Identifier: GPL-2.0 22c7b9b93SAlex Elder 32c7b9b93SAlex Elder /* Copyright (C) 2021 Linaro Ltd. */ 42c7b9b93SAlex Elder 52c7b9b93SAlex Elder #include <linux/log2.h> 62c7b9b93SAlex Elder 732d00f62SPaolo Abeni #include "../gsi.h" 832d00f62SPaolo Abeni #include "../ipa_data.h" 932d00f62SPaolo Abeni #include "../ipa_endpoint.h" 1032d00f62SPaolo Abeni #include "../ipa_mem.h" 112c7b9b93SAlex Elder 122c7b9b93SAlex Elder /** enum ipa_resource_type - IPA resource types for an SoC having IPA v4.5 */ 132c7b9b93SAlex Elder enum ipa_resource_type { 142c7b9b93SAlex Elder /* Source resource types; first must have value 0 */ 152c7b9b93SAlex Elder IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS = 0, 162c7b9b93SAlex Elder IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS, 172c7b9b93SAlex Elder IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF, 182c7b9b93SAlex Elder IPA_RESOURCE_TYPE_SRC_HPS_DMARS, 192c7b9b93SAlex Elder IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES, 202c7b9b93SAlex Elder 212c7b9b93SAlex Elder /* Destination resource types; first must have value 0 */ 222c7b9b93SAlex Elder IPA_RESOURCE_TYPE_DST_DATA_SECTORS = 0, 232c7b9b93SAlex Elder IPA_RESOURCE_TYPE_DST_DPS_DMARS, 242c7b9b93SAlex Elder }; 252c7b9b93SAlex Elder 262c7b9b93SAlex Elder /* Resource groups used for an SoC having IPA v4.5 */ 272c7b9b93SAlex Elder enum ipa_rsrc_group_id { 282c7b9b93SAlex Elder /* Source resource group identifiers */ 292c7b9b93SAlex Elder IPA_RSRC_GROUP_SRC_UNUSED_0 = 0, 302c7b9b93SAlex Elder IPA_RSRC_GROUP_SRC_UL_DL, 312c7b9b93SAlex Elder IPA_RSRC_GROUP_SRC_UNUSED_2, 322c7b9b93SAlex Elder IPA_RSRC_GROUP_SRC_UNUSED_3, 332c7b9b93SAlex Elder IPA_RSRC_GROUP_SRC_UC_RX_Q, 342c7b9b93SAlex Elder IPA_RSRC_GROUP_SRC_COUNT, /* Last in set; not a source group */ 352c7b9b93SAlex Elder 362c7b9b93SAlex Elder /* Destination resource group identifiers */ 372c7b9b93SAlex Elder IPA_RSRC_GROUP_DST_UNUSED_0 = 0, 382c7b9b93SAlex Elder IPA_RSRC_GROUP_DST_UL_DL_DPL, 392c7b9b93SAlex Elder IPA_RSRC_GROUP_DST_UNUSED_2, 402c7b9b93SAlex Elder IPA_RSRC_GROUP_DST_UNUSED_3, 412c7b9b93SAlex Elder IPA_RSRC_GROUP_DST_UC, 422c7b9b93SAlex Elder IPA_RSRC_GROUP_DST_COUNT, /* Last; not a destination group */ 432c7b9b93SAlex Elder }; 442c7b9b93SAlex Elder 452c7b9b93SAlex Elder /* QSB configuration data for an SoC having IPA v4.5 */ 462c7b9b93SAlex Elder static const struct ipa_qsb_data ipa_qsb_data[] = { 472c7b9b93SAlex Elder [IPA_QSB_MASTER_DDR] = { 482c7b9b93SAlex Elder .max_writes = 8, 492c7b9b93SAlex Elder .max_reads = 0, /* no limit (hardware max) */ 502c7b9b93SAlex Elder .max_reads_beats = 120, 512c7b9b93SAlex Elder }, 522c7b9b93SAlex Elder [IPA_QSB_MASTER_PCIE] = { 532c7b9b93SAlex Elder .max_writes = 8, 542c7b9b93SAlex Elder .max_reads = 12, 552c7b9b93SAlex Elder /* no outstanding read byte (beat) limit */ 562c7b9b93SAlex Elder }, 572c7b9b93SAlex Elder }; 582c7b9b93SAlex Elder 592c7b9b93SAlex Elder /* Endpoint configuration data for an SoC having IPA v4.5 */ 602c7b9b93SAlex Elder static const struct ipa_gsi_endpoint_data ipa_gsi_endpoint_data[] = { 612c7b9b93SAlex Elder [IPA_ENDPOINT_AP_COMMAND_TX] = { 622c7b9b93SAlex Elder .ee_id = GSI_EE_AP, 632c7b9b93SAlex Elder .channel_id = 9, 642c7b9b93SAlex Elder .endpoint_id = 7, 652c7b9b93SAlex Elder .toward_ipa = true, 662c7b9b93SAlex Elder .channel = { 672c7b9b93SAlex Elder .tre_count = 256, 682c7b9b93SAlex Elder .event_count = 256, 692c7b9b93SAlex Elder .tlv_count = 20, 702c7b9b93SAlex Elder }, 712c7b9b93SAlex Elder .endpoint = { 722c7b9b93SAlex Elder .config = { 732c7b9b93SAlex Elder .resource_group = IPA_RSRC_GROUP_SRC_UL_DL, 742c7b9b93SAlex Elder .dma_mode = true, 752c7b9b93SAlex Elder .dma_endpoint = IPA_ENDPOINT_AP_LAN_RX, 762c7b9b93SAlex Elder .tx = { 772c7b9b93SAlex Elder .seq_type = IPA_SEQ_DMA, 782c7b9b93SAlex Elder }, 792c7b9b93SAlex Elder }, 802c7b9b93SAlex Elder }, 812c7b9b93SAlex Elder }, 822c7b9b93SAlex Elder [IPA_ENDPOINT_AP_LAN_RX] = { 832c7b9b93SAlex Elder .ee_id = GSI_EE_AP, 842c7b9b93SAlex Elder .channel_id = 10, 852c7b9b93SAlex Elder .endpoint_id = 16, 862c7b9b93SAlex Elder .toward_ipa = false, 872c7b9b93SAlex Elder .channel = { 882c7b9b93SAlex Elder .tre_count = 256, 892c7b9b93SAlex Elder .event_count = 256, 902c7b9b93SAlex Elder .tlv_count = 9, 912c7b9b93SAlex Elder }, 922c7b9b93SAlex Elder .endpoint = { 932c7b9b93SAlex Elder .config = { 942c7b9b93SAlex Elder .resource_group = IPA_RSRC_GROUP_DST_UL_DL_DPL, 952c7b9b93SAlex Elder .aggregation = true, 962c7b9b93SAlex Elder .status_enable = true, 972c7b9b93SAlex Elder .rx = { 982c7b9b93SAlex Elder .buffer_size = 8192, 992c7b9b93SAlex Elder .pad_align = ilog2(sizeof(u32)), 1002c7b9b93SAlex Elder .aggr_time_limit = 500, 1012c7b9b93SAlex Elder }, 1022c7b9b93SAlex Elder }, 1032c7b9b93SAlex Elder }, 1042c7b9b93SAlex Elder }, 1052c7b9b93SAlex Elder [IPA_ENDPOINT_AP_MODEM_TX] = { 1062c7b9b93SAlex Elder .ee_id = GSI_EE_AP, 1072c7b9b93SAlex Elder .channel_id = 7, 1082c7b9b93SAlex Elder .endpoint_id = 2, 1092c7b9b93SAlex Elder .toward_ipa = true, 1102c7b9b93SAlex Elder .channel = { 1112c7b9b93SAlex Elder .tre_count = 512, 1122c7b9b93SAlex Elder .event_count = 512, 1132c7b9b93SAlex Elder .tlv_count = 16, 1142c7b9b93SAlex Elder }, 1152c7b9b93SAlex Elder .endpoint = { 1162c7b9b93SAlex Elder .filter_support = true, 1172c7b9b93SAlex Elder .config = { 1182c7b9b93SAlex Elder .resource_group = IPA_RSRC_GROUP_SRC_UL_DL, 1192c7b9b93SAlex Elder .checksum = true, 1202c7b9b93SAlex Elder .qmap = true, 1212c7b9b93SAlex Elder .status_enable = true, 1222c7b9b93SAlex Elder .tx = { 1232c7b9b93SAlex Elder .seq_type = IPA_SEQ_2_PASS_SKIP_LAST_UC, 1242c7b9b93SAlex Elder .status_endpoint = 1252c7b9b93SAlex Elder IPA_ENDPOINT_MODEM_AP_RX, 1262c7b9b93SAlex Elder }, 1272c7b9b93SAlex Elder }, 1282c7b9b93SAlex Elder }, 1292c7b9b93SAlex Elder }, 1302c7b9b93SAlex Elder [IPA_ENDPOINT_AP_MODEM_RX] = { 1312c7b9b93SAlex Elder .ee_id = GSI_EE_AP, 1322c7b9b93SAlex Elder .channel_id = 1, 1332c7b9b93SAlex Elder .endpoint_id = 14, 1342c7b9b93SAlex Elder .toward_ipa = false, 1352c7b9b93SAlex Elder .channel = { 1362c7b9b93SAlex Elder .tre_count = 256, 1372c7b9b93SAlex Elder .event_count = 256, 1382c7b9b93SAlex Elder .tlv_count = 9, 1392c7b9b93SAlex Elder }, 1402c7b9b93SAlex Elder .endpoint = { 1412c7b9b93SAlex Elder .config = { 1422c7b9b93SAlex Elder .resource_group = IPA_RSRC_GROUP_DST_UL_DL_DPL, 1432c7b9b93SAlex Elder .checksum = true, 1442c7b9b93SAlex Elder .qmap = true, 1452c7b9b93SAlex Elder .aggregation = true, 1462c7b9b93SAlex Elder .rx = { 1472c7b9b93SAlex Elder .buffer_size = 8192, 1482c7b9b93SAlex Elder .aggr_time_limit = 500, 1492c7b9b93SAlex Elder .aggr_close_eof = true, 1502c7b9b93SAlex Elder }, 1512c7b9b93SAlex Elder }, 1522c7b9b93SAlex Elder }, 1532c7b9b93SAlex Elder }, 1542c7b9b93SAlex Elder [IPA_ENDPOINT_MODEM_AP_TX] = { 1552c7b9b93SAlex Elder .ee_id = GSI_EE_MODEM, 1562c7b9b93SAlex Elder .channel_id = 0, 1572c7b9b93SAlex Elder .endpoint_id = 5, 1582c7b9b93SAlex Elder .toward_ipa = true, 1592c7b9b93SAlex Elder .endpoint = { 1602c7b9b93SAlex Elder .filter_support = true, 1612c7b9b93SAlex Elder }, 1622c7b9b93SAlex Elder }, 1632c7b9b93SAlex Elder [IPA_ENDPOINT_MODEM_AP_RX] = { 1642c7b9b93SAlex Elder .ee_id = GSI_EE_MODEM, 1652c7b9b93SAlex Elder .channel_id = 7, 1662c7b9b93SAlex Elder .endpoint_id = 21, 1672c7b9b93SAlex Elder .toward_ipa = false, 1682c7b9b93SAlex Elder }, 1692c7b9b93SAlex Elder [IPA_ENDPOINT_MODEM_DL_NLO_TX] = { 1702c7b9b93SAlex Elder .ee_id = GSI_EE_MODEM, 1712c7b9b93SAlex Elder .channel_id = 2, 1722c7b9b93SAlex Elder .endpoint_id = 8, 1732c7b9b93SAlex Elder .toward_ipa = true, 1742c7b9b93SAlex Elder .endpoint = { 1752c7b9b93SAlex Elder .filter_support = true, 1762c7b9b93SAlex Elder }, 1772c7b9b93SAlex Elder }, 1782c7b9b93SAlex Elder }; 1792c7b9b93SAlex Elder 1802c7b9b93SAlex Elder /* Source resource configuration data for an SoC having IPA v4.5 */ 1812c7b9b93SAlex Elder static const struct ipa_resource ipa_resource_src[] = { 1822c7b9b93SAlex Elder [IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS] = { 1832c7b9b93SAlex Elder .limits[IPA_RSRC_GROUP_SRC_UL_DL] = { 1842c7b9b93SAlex Elder .min = 1, .max = 11, 1852c7b9b93SAlex Elder }, 1862c7b9b93SAlex Elder .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = { 1872c7b9b93SAlex Elder .min = 1, .max = 63, 1882c7b9b93SAlex Elder }, 1892c7b9b93SAlex Elder }, 1902c7b9b93SAlex Elder [IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS] = { 1912c7b9b93SAlex Elder .limits[IPA_RSRC_GROUP_SRC_UL_DL] = { 1922c7b9b93SAlex Elder .min = 14, .max = 14, 1932c7b9b93SAlex Elder }, 1942c7b9b93SAlex Elder .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = { 1952c7b9b93SAlex Elder .min = 3, .max = 3, 1962c7b9b93SAlex Elder }, 1972c7b9b93SAlex Elder }, 1982c7b9b93SAlex Elder [IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF] = { 1992c7b9b93SAlex Elder .limits[IPA_RSRC_GROUP_SRC_UL_DL] = { 2002c7b9b93SAlex Elder .min = 18, .max = 18, 2012c7b9b93SAlex Elder }, 2022c7b9b93SAlex Elder .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = { 2032c7b9b93SAlex Elder .min = 8, .max = 8, 2042c7b9b93SAlex Elder }, 2052c7b9b93SAlex Elder }, 2062c7b9b93SAlex Elder [IPA_RESOURCE_TYPE_SRC_HPS_DMARS] = { 2072c7b9b93SAlex Elder .limits[IPA_RSRC_GROUP_SRC_UNUSED_0] = { 2082c7b9b93SAlex Elder .min = 0, .max = 63, 2092c7b9b93SAlex Elder }, 2102c7b9b93SAlex Elder .limits[IPA_RSRC_GROUP_SRC_UL_DL] = { 2112c7b9b93SAlex Elder .min = 0, .max = 63, 2122c7b9b93SAlex Elder }, 2132c7b9b93SAlex Elder .limits[IPA_RSRC_GROUP_SRC_UNUSED_2] = { 2142c7b9b93SAlex Elder .min = 0, .max = 63, 2152c7b9b93SAlex Elder }, 2162c7b9b93SAlex Elder .limits[IPA_RSRC_GROUP_SRC_UNUSED_3] = { 2172c7b9b93SAlex Elder .min = 0, .max = 63, 2182c7b9b93SAlex Elder }, 2192c7b9b93SAlex Elder .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = { 2202c7b9b93SAlex Elder .min = 0, .max = 63, 2212c7b9b93SAlex Elder }, 2222c7b9b93SAlex Elder }, 2232c7b9b93SAlex Elder [IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES] = { 2242c7b9b93SAlex Elder .limits[IPA_RSRC_GROUP_SRC_UL_DL] = { 2252c7b9b93SAlex Elder .min = 24, .max = 24, 2262c7b9b93SAlex Elder }, 2272c7b9b93SAlex Elder .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = { 2282c7b9b93SAlex Elder .min = 8, .max = 8, 2292c7b9b93SAlex Elder }, 2302c7b9b93SAlex Elder }, 2312c7b9b93SAlex Elder }; 2322c7b9b93SAlex Elder 2332c7b9b93SAlex Elder /* Destination resource configuration data for an SoC having IPA v4.5 */ 2342c7b9b93SAlex Elder static const struct ipa_resource ipa_resource_dst[] = { 2352c7b9b93SAlex Elder [IPA_RESOURCE_TYPE_DST_DATA_SECTORS] = { 2362c7b9b93SAlex Elder .limits[IPA_RSRC_GROUP_DST_UL_DL_DPL] = { 2372c7b9b93SAlex Elder .min = 16, .max = 16, 2382c7b9b93SAlex Elder }, 2392c7b9b93SAlex Elder .limits[IPA_RSRC_GROUP_DST_UNUSED_2] = { 2402c7b9b93SAlex Elder .min = 2, .max = 2, 2412c7b9b93SAlex Elder }, 2422c7b9b93SAlex Elder .limits[IPA_RSRC_GROUP_DST_UNUSED_3] = { 2432c7b9b93SAlex Elder .min = 2, .max = 2, 2442c7b9b93SAlex Elder }, 2452c7b9b93SAlex Elder }, 2462c7b9b93SAlex Elder [IPA_RESOURCE_TYPE_DST_DPS_DMARS] = { 2472c7b9b93SAlex Elder .limits[IPA_RSRC_GROUP_DST_UL_DL_DPL] = { 2482c7b9b93SAlex Elder .min = 2, .max = 63, 2492c7b9b93SAlex Elder }, 2502c7b9b93SAlex Elder .limits[IPA_RSRC_GROUP_DST_UNUSED_2] = { 2512c7b9b93SAlex Elder .min = 1, .max = 2, 2522c7b9b93SAlex Elder }, 2532c7b9b93SAlex Elder .limits[IPA_RSRC_GROUP_DST_UNUSED_3] = { 2542c7b9b93SAlex Elder .min = 1, .max = 2, 2552c7b9b93SAlex Elder }, 2562c7b9b93SAlex Elder .limits[IPA_RSRC_GROUP_DST_UC] = { 2572c7b9b93SAlex Elder .min = 0, .max = 2, 2582c7b9b93SAlex Elder }, 2592c7b9b93SAlex Elder }, 2602c7b9b93SAlex Elder }; 2612c7b9b93SAlex Elder 2622c7b9b93SAlex Elder /* Resource configuration data for an SoC having IPA v4.5 */ 2632c7b9b93SAlex Elder static const struct ipa_resource_data ipa_resource_data = { 2642c7b9b93SAlex Elder .rsrc_group_src_count = IPA_RSRC_GROUP_SRC_COUNT, 2652c7b9b93SAlex Elder .rsrc_group_dst_count = IPA_RSRC_GROUP_DST_COUNT, 2662c7b9b93SAlex Elder .resource_src_count = ARRAY_SIZE(ipa_resource_src), 2672c7b9b93SAlex Elder .resource_src = ipa_resource_src, 2682c7b9b93SAlex Elder .resource_dst_count = ARRAY_SIZE(ipa_resource_dst), 2692c7b9b93SAlex Elder .resource_dst = ipa_resource_dst, 2702c7b9b93SAlex Elder }; 2712c7b9b93SAlex Elder 2722c7b9b93SAlex Elder /* IPA-resident memory region data for an SoC having IPA v4.5 */ 2732c7b9b93SAlex Elder static const struct ipa_mem ipa_mem_local_data[] = { 2742c7b9b93SAlex Elder { 2752c7b9b93SAlex Elder .id = IPA_MEM_UC_SHARED, 2762c7b9b93SAlex Elder .offset = 0x0000, 2772c7b9b93SAlex Elder .size = 0x0080, 2782c7b9b93SAlex Elder .canary_count = 0, 2792c7b9b93SAlex Elder }, 2802c7b9b93SAlex Elder { 2812c7b9b93SAlex Elder .id = IPA_MEM_UC_INFO, 2822c7b9b93SAlex Elder .offset = 0x0080, 2832c7b9b93SAlex Elder .size = 0x0200, 2842c7b9b93SAlex Elder .canary_count = 0, 2852c7b9b93SAlex Elder }, 2862c7b9b93SAlex Elder { 2872c7b9b93SAlex Elder .id = IPA_MEM_V4_FILTER_HASHED, 2882c7b9b93SAlex Elder .offset = 0x0288, 2892c7b9b93SAlex Elder .size = 0x0078, 2902c7b9b93SAlex Elder .canary_count = 2, 2912c7b9b93SAlex Elder }, 2922c7b9b93SAlex Elder { 2932c7b9b93SAlex Elder .id = IPA_MEM_V4_FILTER, 2942c7b9b93SAlex Elder .offset = 0x0308, 2952c7b9b93SAlex Elder .size = 0x0078, 2962c7b9b93SAlex Elder .canary_count = 2, 2972c7b9b93SAlex Elder }, 2982c7b9b93SAlex Elder { 2992c7b9b93SAlex Elder .id = IPA_MEM_V6_FILTER_HASHED, 3002c7b9b93SAlex Elder .offset = 0x0388, 3012c7b9b93SAlex Elder .size = 0x0078, 3022c7b9b93SAlex Elder .canary_count = 2, 3032c7b9b93SAlex Elder }, 3042c7b9b93SAlex Elder { 3052c7b9b93SAlex Elder .id = IPA_MEM_V6_FILTER, 3062c7b9b93SAlex Elder .offset = 0x0408, 3072c7b9b93SAlex Elder .size = 0x0078, 3082c7b9b93SAlex Elder .canary_count = 2, 3092c7b9b93SAlex Elder }, 3102c7b9b93SAlex Elder { 3112c7b9b93SAlex Elder .id = IPA_MEM_V4_ROUTE_HASHED, 3122c7b9b93SAlex Elder .offset = 0x0488, 3132c7b9b93SAlex Elder .size = 0x0078, 3142c7b9b93SAlex Elder .canary_count = 2, 3152c7b9b93SAlex Elder }, 3162c7b9b93SAlex Elder { 3172c7b9b93SAlex Elder .id = IPA_MEM_V4_ROUTE, 3182c7b9b93SAlex Elder .offset = 0x0508, 3192c7b9b93SAlex Elder .size = 0x0078, 3202c7b9b93SAlex Elder .canary_count = 2, 3212c7b9b93SAlex Elder }, 3222c7b9b93SAlex Elder { 3232c7b9b93SAlex Elder .id = IPA_MEM_V6_ROUTE_HASHED, 3242c7b9b93SAlex Elder .offset = 0x0588, 3252c7b9b93SAlex Elder .size = 0x0078, 3262c7b9b93SAlex Elder .canary_count = 2, 3272c7b9b93SAlex Elder }, 3282c7b9b93SAlex Elder { 3292c7b9b93SAlex Elder .id = IPA_MEM_V6_ROUTE, 3302c7b9b93SAlex Elder .offset = 0x0608, 3312c7b9b93SAlex Elder .size = 0x0078, 3322c7b9b93SAlex Elder .canary_count = 2, 3332c7b9b93SAlex Elder }, 3342c7b9b93SAlex Elder { 3352c7b9b93SAlex Elder .id = IPA_MEM_MODEM_HEADER, 3362c7b9b93SAlex Elder .offset = 0x0688, 3372c7b9b93SAlex Elder .size = 0x0240, 3382c7b9b93SAlex Elder .canary_count = 2, 3392c7b9b93SAlex Elder }, 3402c7b9b93SAlex Elder { 3412c7b9b93SAlex Elder .id = IPA_MEM_AP_HEADER, 3422c7b9b93SAlex Elder .offset = 0x08c8, 3432c7b9b93SAlex Elder .size = 0x0200, 3442c7b9b93SAlex Elder .canary_count = 0, 3452c7b9b93SAlex Elder }, 3462c7b9b93SAlex Elder { 3472c7b9b93SAlex Elder .id = IPA_MEM_MODEM_PROC_CTX, 3482c7b9b93SAlex Elder .offset = 0x0ad0, 3492c7b9b93SAlex Elder .size = 0x0b20, 3502c7b9b93SAlex Elder .canary_count = 2, 3512c7b9b93SAlex Elder }, 3522c7b9b93SAlex Elder { 3532c7b9b93SAlex Elder .id = IPA_MEM_AP_PROC_CTX, 3542c7b9b93SAlex Elder .offset = 0x15f0, 3552c7b9b93SAlex Elder .size = 0x0200, 3562c7b9b93SAlex Elder .canary_count = 0, 3572c7b9b93SAlex Elder }, 3582c7b9b93SAlex Elder { 3592c7b9b93SAlex Elder .id = IPA_MEM_NAT_TABLE, 3602c7b9b93SAlex Elder .offset = 0x1800, 3612c7b9b93SAlex Elder .size = 0x0d00, 3622c7b9b93SAlex Elder .canary_count = 4, 3632c7b9b93SAlex Elder }, 3642c7b9b93SAlex Elder { 3652c7b9b93SAlex Elder .id = IPA_MEM_STATS_QUOTA_MODEM, 3662c7b9b93SAlex Elder .offset = 0x2510, 3672c7b9b93SAlex Elder .size = 0x0030, 3682c7b9b93SAlex Elder .canary_count = 4, 3692c7b9b93SAlex Elder }, 3702c7b9b93SAlex Elder { 3712c7b9b93SAlex Elder .id = IPA_MEM_STATS_QUOTA_AP, 3722c7b9b93SAlex Elder .offset = 0x2540, 3732c7b9b93SAlex Elder .size = 0x0048, 3742c7b9b93SAlex Elder .canary_count = 0, 3752c7b9b93SAlex Elder }, 3762c7b9b93SAlex Elder { 3772c7b9b93SAlex Elder .id = IPA_MEM_STATS_TETHERING, 3782c7b9b93SAlex Elder .offset = 0x2588, 3792c7b9b93SAlex Elder .size = 0x0238, 3802c7b9b93SAlex Elder .canary_count = 0, 3812c7b9b93SAlex Elder }, 3822c7b9b93SAlex Elder { 3832c7b9b93SAlex Elder .id = IPA_MEM_STATS_FILTER_ROUTE, 3842c7b9b93SAlex Elder .offset = 0x27c0, 3852c7b9b93SAlex Elder .size = 0x0800, 3862c7b9b93SAlex Elder .canary_count = 0, 3872c7b9b93SAlex Elder }, 3882c7b9b93SAlex Elder { 3892c7b9b93SAlex Elder .id = IPA_MEM_STATS_DROP, 3902c7b9b93SAlex Elder .offset = 0x2fc0, 3912c7b9b93SAlex Elder .size = 0x0020, 3922c7b9b93SAlex Elder .canary_count = 0, 3932c7b9b93SAlex Elder }, 3942c7b9b93SAlex Elder { 3952c7b9b93SAlex Elder .id = IPA_MEM_MODEM, 3962c7b9b93SAlex Elder .offset = 0x2fe8, 3972c7b9b93SAlex Elder .size = 0x0800, 3982c7b9b93SAlex Elder .canary_count = 2, 3992c7b9b93SAlex Elder }, 4002c7b9b93SAlex Elder { 4012c7b9b93SAlex Elder .id = IPA_MEM_UC_EVENT_RING, 4022c7b9b93SAlex Elder .offset = 0x3800, 4032c7b9b93SAlex Elder .size = 0x1000, 4042c7b9b93SAlex Elder .canary_count = 1, 4052c7b9b93SAlex Elder }, 4062c7b9b93SAlex Elder { 4072c7b9b93SAlex Elder .id = IPA_MEM_PDN_CONFIG, 4082c7b9b93SAlex Elder .offset = 0x4800, 4092c7b9b93SAlex Elder .size = 0x0050, 4102c7b9b93SAlex Elder .canary_count = 0, 4112c7b9b93SAlex Elder }, 4122c7b9b93SAlex Elder }; 4132c7b9b93SAlex Elder 4142c7b9b93SAlex Elder /* Memory configuration data for an SoC having IPA v4.5 */ 4152c7b9b93SAlex Elder static const struct ipa_mem_data ipa_mem_data = { 4162c7b9b93SAlex Elder .local_count = ARRAY_SIZE(ipa_mem_local_data), 4172c7b9b93SAlex Elder .local = ipa_mem_local_data, 4182c7b9b93SAlex Elder .imem_addr = 0x14688000, 4192c7b9b93SAlex Elder .imem_size = 0x00003000, 4202c7b9b93SAlex Elder .smem_id = 497, 4212c7b9b93SAlex Elder .smem_size = 0x00009000, 4222c7b9b93SAlex Elder }; 4232c7b9b93SAlex Elder 4242c7b9b93SAlex Elder /* Interconnect rates are in 1000 byte/second units */ 4252c7b9b93SAlex Elder static const struct ipa_interconnect_data ipa_interconnect_data[] = { 4262c7b9b93SAlex Elder { 4272c7b9b93SAlex Elder .name = "memory", 4282c7b9b93SAlex Elder .peak_bandwidth = 600000, /* 600 MBps */ 4292c7b9b93SAlex Elder .average_bandwidth = 150000, /* 150 MBps */ 4302c7b9b93SAlex Elder }, 4312c7b9b93SAlex Elder /* Average rate is unused for the next two interconnects */ 4322c7b9b93SAlex Elder { 4332c7b9b93SAlex Elder .name = "imem", 4342c7b9b93SAlex Elder .peak_bandwidth = 450000, /* 450 MBps */ 4352c7b9b93SAlex Elder .average_bandwidth = 75000, /* 75 MBps (unused?) */ 4362c7b9b93SAlex Elder }, 4372c7b9b93SAlex Elder { 4382c7b9b93SAlex Elder .name = "config", 4392c7b9b93SAlex Elder .peak_bandwidth = 171400, /* 171.4 MBps */ 4402c7b9b93SAlex Elder .average_bandwidth = 0, /* unused */ 4412c7b9b93SAlex Elder }, 4422c7b9b93SAlex Elder }; 4432c7b9b93SAlex Elder 4442c7b9b93SAlex Elder /* Clock and interconnect configuration data for an SoC having IPA v4.5 */ 4452c7b9b93SAlex Elder static const struct ipa_power_data ipa_power_data = { 4462c7b9b93SAlex Elder .core_clock_rate = 150 * 1000 * 1000, /* Hz (150? 60?) */ 4472c7b9b93SAlex Elder .interconnect_count = ARRAY_SIZE(ipa_interconnect_data), 4482c7b9b93SAlex Elder .interconnect_data = ipa_interconnect_data, 4492c7b9b93SAlex Elder }; 4502c7b9b93SAlex Elder 4512c7b9b93SAlex Elder /* Configuration data for an SoC having IPA v4.5 */ 4522c7b9b93SAlex Elder const struct ipa_data ipa_data_v4_5 = { 4532c7b9b93SAlex Elder .version = IPA_VERSION_4_5, 4542c7b9b93SAlex Elder .qsb_count = ARRAY_SIZE(ipa_qsb_data), 4552c7b9b93SAlex Elder .qsb_data = ipa_qsb_data, 456*8defab8bSAlex Elder .modem_route_count = 8, 4572c7b9b93SAlex Elder .endpoint_count = ARRAY_SIZE(ipa_gsi_endpoint_data), 4582c7b9b93SAlex Elder .endpoint_data = ipa_gsi_endpoint_data, 4592c7b9b93SAlex Elder .resource_data = &ipa_resource_data, 4602c7b9b93SAlex Elder .mem_data = &ipa_mem_data, 4612c7b9b93SAlex Elder .power_data = &ipa_power_data, 4622c7b9b93SAlex Elder }; 463