1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Xilinx Axi Ethernet device driver 4 * 5 * Copyright (c) 2008 Nissin Systems Co., Ltd., Yoshio Kashiwagi 6 * Copyright (c) 2005-2008 DLA Systems, David H. Lynch Jr. <dhlii@dlasys.net> 7 * Copyright (c) 2008-2009 Secret Lab Technologies Ltd. 8 * Copyright (c) 2010 - 2011 Michal Simek <monstr@monstr.eu> 9 * Copyright (c) 2010 - 2011 PetaLogix 10 * Copyright (c) 2019 - 2022 Calian Advanced Technologies 11 * Copyright (c) 2010 - 2012 Xilinx, Inc. All rights reserved. 12 * 13 * This is a driver for the Xilinx Axi Ethernet which is used in the Virtex6 14 * and Spartan6. 15 * 16 * TODO: 17 * - Add Axi Fifo support. 18 * - Factor out Axi DMA code into separate driver. 19 * - Test and fix basic multicast filtering. 20 * - Add support for extended multicast filtering. 21 * - Test basic VLAN support. 22 * - Add support for extended VLAN support. 23 */ 24 25 #include <linux/clk.h> 26 #include <linux/delay.h> 27 #include <linux/etherdevice.h> 28 #include <linux/module.h> 29 #include <linux/netdevice.h> 30 #include <linux/of.h> 31 #include <linux/of_mdio.h> 32 #include <linux/of_net.h> 33 #include <linux/of_irq.h> 34 #include <linux/of_address.h> 35 #include <linux/platform_device.h> 36 #include <linux/skbuff.h> 37 #include <linux/math64.h> 38 #include <linux/phy.h> 39 #include <linux/mii.h> 40 #include <linux/ethtool.h> 41 42 #include "xilinx_axienet.h" 43 44 /* Descriptors defines for Tx and Rx DMA */ 45 #define TX_BD_NUM_DEFAULT 128 46 #define RX_BD_NUM_DEFAULT 1024 47 #define TX_BD_NUM_MIN (MAX_SKB_FRAGS + 1) 48 #define TX_BD_NUM_MAX 4096 49 #define RX_BD_NUM_MAX 4096 50 51 /* Must be shorter than length of ethtool_drvinfo.driver field to fit */ 52 #define DRIVER_NAME "xaxienet" 53 #define DRIVER_DESCRIPTION "Xilinx Axi Ethernet driver" 54 #define DRIVER_VERSION "1.00a" 55 56 #define AXIENET_REGS_N 40 57 58 /* Match table for of_platform binding */ 59 static const struct of_device_id axienet_of_match[] = { 60 { .compatible = "xlnx,axi-ethernet-1.00.a", }, 61 { .compatible = "xlnx,axi-ethernet-1.01.a", }, 62 { .compatible = "xlnx,axi-ethernet-2.01.a", }, 63 {}, 64 }; 65 66 MODULE_DEVICE_TABLE(of, axienet_of_match); 67 68 /* Option table for setting up Axi Ethernet hardware options */ 69 static struct axienet_option axienet_options[] = { 70 /* Turn on jumbo packet support for both Rx and Tx */ 71 { 72 .opt = XAE_OPTION_JUMBO, 73 .reg = XAE_TC_OFFSET, 74 .m_or = XAE_TC_JUM_MASK, 75 }, { 76 .opt = XAE_OPTION_JUMBO, 77 .reg = XAE_RCW1_OFFSET, 78 .m_or = XAE_RCW1_JUM_MASK, 79 }, { /* Turn on VLAN packet support for both Rx and Tx */ 80 .opt = XAE_OPTION_VLAN, 81 .reg = XAE_TC_OFFSET, 82 .m_or = XAE_TC_VLAN_MASK, 83 }, { 84 .opt = XAE_OPTION_VLAN, 85 .reg = XAE_RCW1_OFFSET, 86 .m_or = XAE_RCW1_VLAN_MASK, 87 }, { /* Turn on FCS stripping on receive packets */ 88 .opt = XAE_OPTION_FCS_STRIP, 89 .reg = XAE_RCW1_OFFSET, 90 .m_or = XAE_RCW1_FCS_MASK, 91 }, { /* Turn on FCS insertion on transmit packets */ 92 .opt = XAE_OPTION_FCS_INSERT, 93 .reg = XAE_TC_OFFSET, 94 .m_or = XAE_TC_FCS_MASK, 95 }, { /* Turn off length/type field checking on receive packets */ 96 .opt = XAE_OPTION_LENTYPE_ERR, 97 .reg = XAE_RCW1_OFFSET, 98 .m_or = XAE_RCW1_LT_DIS_MASK, 99 }, { /* Turn on Rx flow control */ 100 .opt = XAE_OPTION_FLOW_CONTROL, 101 .reg = XAE_FCC_OFFSET, 102 .m_or = XAE_FCC_FCRX_MASK, 103 }, { /* Turn on Tx flow control */ 104 .opt = XAE_OPTION_FLOW_CONTROL, 105 .reg = XAE_FCC_OFFSET, 106 .m_or = XAE_FCC_FCTX_MASK, 107 }, { /* Turn on promiscuous frame filtering */ 108 .opt = XAE_OPTION_PROMISC, 109 .reg = XAE_FMI_OFFSET, 110 .m_or = XAE_FMI_PM_MASK, 111 }, { /* Enable transmitter */ 112 .opt = XAE_OPTION_TXEN, 113 .reg = XAE_TC_OFFSET, 114 .m_or = XAE_TC_TX_MASK, 115 }, { /* Enable receiver */ 116 .opt = XAE_OPTION_RXEN, 117 .reg = XAE_RCW1_OFFSET, 118 .m_or = XAE_RCW1_RX_MASK, 119 }, 120 {} 121 }; 122 123 /** 124 * axienet_dma_in32 - Memory mapped Axi DMA register read 125 * @lp: Pointer to axienet local structure 126 * @reg: Address offset from the base address of the Axi DMA core 127 * 128 * Return: The contents of the Axi DMA register 129 * 130 * This function returns the contents of the corresponding Axi DMA register. 131 */ 132 static inline u32 axienet_dma_in32(struct axienet_local *lp, off_t reg) 133 { 134 return ioread32(lp->dma_regs + reg); 135 } 136 137 static void desc_set_phys_addr(struct axienet_local *lp, dma_addr_t addr, 138 struct axidma_bd *desc) 139 { 140 desc->phys = lower_32_bits(addr); 141 if (lp->features & XAE_FEATURE_DMA_64BIT) 142 desc->phys_msb = upper_32_bits(addr); 143 } 144 145 static dma_addr_t desc_get_phys_addr(struct axienet_local *lp, 146 struct axidma_bd *desc) 147 { 148 dma_addr_t ret = desc->phys; 149 150 if (lp->features & XAE_FEATURE_DMA_64BIT) 151 ret |= ((dma_addr_t)desc->phys_msb << 16) << 16; 152 153 return ret; 154 } 155 156 /** 157 * axienet_dma_bd_release - Release buffer descriptor rings 158 * @ndev: Pointer to the net_device structure 159 * 160 * This function is used to release the descriptors allocated in 161 * axienet_dma_bd_init. axienet_dma_bd_release is called when Axi Ethernet 162 * driver stop api is called. 163 */ 164 static void axienet_dma_bd_release(struct net_device *ndev) 165 { 166 int i; 167 struct axienet_local *lp = netdev_priv(ndev); 168 169 /* If we end up here, tx_bd_v must have been DMA allocated. */ 170 dma_free_coherent(lp->dev, 171 sizeof(*lp->tx_bd_v) * lp->tx_bd_num, 172 lp->tx_bd_v, 173 lp->tx_bd_p); 174 175 if (!lp->rx_bd_v) 176 return; 177 178 for (i = 0; i < lp->rx_bd_num; i++) { 179 dma_addr_t phys; 180 181 /* A NULL skb means this descriptor has not been initialised 182 * at all. 183 */ 184 if (!lp->rx_bd_v[i].skb) 185 break; 186 187 dev_kfree_skb(lp->rx_bd_v[i].skb); 188 189 /* For each descriptor, we programmed cntrl with the (non-zero) 190 * descriptor size, after it had been successfully allocated. 191 * So a non-zero value in there means we need to unmap it. 192 */ 193 if (lp->rx_bd_v[i].cntrl) { 194 phys = desc_get_phys_addr(lp, &lp->rx_bd_v[i]); 195 dma_unmap_single(lp->dev, phys, 196 lp->max_frm_size, DMA_FROM_DEVICE); 197 } 198 } 199 200 dma_free_coherent(lp->dev, 201 sizeof(*lp->rx_bd_v) * lp->rx_bd_num, 202 lp->rx_bd_v, 203 lp->rx_bd_p); 204 } 205 206 /** 207 * axienet_usec_to_timer - Calculate IRQ delay timer value 208 * @lp: Pointer to the axienet_local structure 209 * @coalesce_usec: Microseconds to convert into timer value 210 */ 211 static u32 axienet_usec_to_timer(struct axienet_local *lp, u32 coalesce_usec) 212 { 213 u32 result; 214 u64 clk_rate = 125000000; /* arbitrary guess if no clock rate set */ 215 216 if (lp->axi_clk) 217 clk_rate = clk_get_rate(lp->axi_clk); 218 219 /* 1 Timeout Interval = 125 * (clock period of SG clock) */ 220 result = DIV64_U64_ROUND_CLOSEST((u64)coalesce_usec * clk_rate, 221 (u64)125000000); 222 if (result > 255) 223 result = 255; 224 225 return result; 226 } 227 228 /** 229 * axienet_dma_start - Set up DMA registers and start DMA operation 230 * @lp: Pointer to the axienet_local structure 231 */ 232 static void axienet_dma_start(struct axienet_local *lp) 233 { 234 /* Start updating the Rx channel control register */ 235 lp->rx_dma_cr = (lp->coalesce_count_rx << XAXIDMA_COALESCE_SHIFT) | 236 XAXIDMA_IRQ_IOC_MASK | XAXIDMA_IRQ_ERROR_MASK; 237 /* Only set interrupt delay timer if not generating an interrupt on 238 * the first RX packet. Otherwise leave at 0 to disable delay interrupt. 239 */ 240 if (lp->coalesce_count_rx > 1) 241 lp->rx_dma_cr |= (axienet_usec_to_timer(lp, lp->coalesce_usec_rx) 242 << XAXIDMA_DELAY_SHIFT) | 243 XAXIDMA_IRQ_DELAY_MASK; 244 axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET, lp->rx_dma_cr); 245 246 /* Start updating the Tx channel control register */ 247 lp->tx_dma_cr = (lp->coalesce_count_tx << XAXIDMA_COALESCE_SHIFT) | 248 XAXIDMA_IRQ_IOC_MASK | XAXIDMA_IRQ_ERROR_MASK; 249 /* Only set interrupt delay timer if not generating an interrupt on 250 * the first TX packet. Otherwise leave at 0 to disable delay interrupt. 251 */ 252 if (lp->coalesce_count_tx > 1) 253 lp->tx_dma_cr |= (axienet_usec_to_timer(lp, lp->coalesce_usec_tx) 254 << XAXIDMA_DELAY_SHIFT) | 255 XAXIDMA_IRQ_DELAY_MASK; 256 axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, lp->tx_dma_cr); 257 258 /* Populate the tail pointer and bring the Rx Axi DMA engine out of 259 * halted state. This will make the Rx side ready for reception. 260 */ 261 axienet_dma_out_addr(lp, XAXIDMA_RX_CDESC_OFFSET, lp->rx_bd_p); 262 lp->rx_dma_cr |= XAXIDMA_CR_RUNSTOP_MASK; 263 axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET, lp->rx_dma_cr); 264 axienet_dma_out_addr(lp, XAXIDMA_RX_TDESC_OFFSET, lp->rx_bd_p + 265 (sizeof(*lp->rx_bd_v) * (lp->rx_bd_num - 1))); 266 267 /* Write to the RS (Run-stop) bit in the Tx channel control register. 268 * Tx channel is now ready to run. But only after we write to the 269 * tail pointer register that the Tx channel will start transmitting. 270 */ 271 axienet_dma_out_addr(lp, XAXIDMA_TX_CDESC_OFFSET, lp->tx_bd_p); 272 lp->tx_dma_cr |= XAXIDMA_CR_RUNSTOP_MASK; 273 axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, lp->tx_dma_cr); 274 } 275 276 /** 277 * axienet_dma_bd_init - Setup buffer descriptor rings for Axi DMA 278 * @ndev: Pointer to the net_device structure 279 * 280 * Return: 0, on success -ENOMEM, on failure 281 * 282 * This function is called to initialize the Rx and Tx DMA descriptor 283 * rings. This initializes the descriptors with required default values 284 * and is called when Axi Ethernet driver reset is called. 285 */ 286 static int axienet_dma_bd_init(struct net_device *ndev) 287 { 288 int i; 289 struct sk_buff *skb; 290 struct axienet_local *lp = netdev_priv(ndev); 291 292 /* Reset the indexes which are used for accessing the BDs */ 293 lp->tx_bd_ci = 0; 294 lp->tx_bd_tail = 0; 295 lp->rx_bd_ci = 0; 296 297 /* Allocate the Tx and Rx buffer descriptors. */ 298 lp->tx_bd_v = dma_alloc_coherent(lp->dev, 299 sizeof(*lp->tx_bd_v) * lp->tx_bd_num, 300 &lp->tx_bd_p, GFP_KERNEL); 301 if (!lp->tx_bd_v) 302 return -ENOMEM; 303 304 lp->rx_bd_v = dma_alloc_coherent(lp->dev, 305 sizeof(*lp->rx_bd_v) * lp->rx_bd_num, 306 &lp->rx_bd_p, GFP_KERNEL); 307 if (!lp->rx_bd_v) 308 goto out; 309 310 for (i = 0; i < lp->tx_bd_num; i++) { 311 dma_addr_t addr = lp->tx_bd_p + 312 sizeof(*lp->tx_bd_v) * 313 ((i + 1) % lp->tx_bd_num); 314 315 lp->tx_bd_v[i].next = lower_32_bits(addr); 316 if (lp->features & XAE_FEATURE_DMA_64BIT) 317 lp->tx_bd_v[i].next_msb = upper_32_bits(addr); 318 } 319 320 for (i = 0; i < lp->rx_bd_num; i++) { 321 dma_addr_t addr; 322 323 addr = lp->rx_bd_p + sizeof(*lp->rx_bd_v) * 324 ((i + 1) % lp->rx_bd_num); 325 lp->rx_bd_v[i].next = lower_32_bits(addr); 326 if (lp->features & XAE_FEATURE_DMA_64BIT) 327 lp->rx_bd_v[i].next_msb = upper_32_bits(addr); 328 329 skb = netdev_alloc_skb_ip_align(ndev, lp->max_frm_size); 330 if (!skb) 331 goto out; 332 333 lp->rx_bd_v[i].skb = skb; 334 addr = dma_map_single(lp->dev, skb->data, 335 lp->max_frm_size, DMA_FROM_DEVICE); 336 if (dma_mapping_error(lp->dev, addr)) { 337 netdev_err(ndev, "DMA mapping error\n"); 338 goto out; 339 } 340 desc_set_phys_addr(lp, addr, &lp->rx_bd_v[i]); 341 342 lp->rx_bd_v[i].cntrl = lp->max_frm_size; 343 } 344 345 axienet_dma_start(lp); 346 347 return 0; 348 out: 349 axienet_dma_bd_release(ndev); 350 return -ENOMEM; 351 } 352 353 /** 354 * axienet_set_mac_address - Write the MAC address 355 * @ndev: Pointer to the net_device structure 356 * @address: 6 byte Address to be written as MAC address 357 * 358 * This function is called to initialize the MAC address of the Axi Ethernet 359 * core. It writes to the UAW0 and UAW1 registers of the core. 360 */ 361 static void axienet_set_mac_address(struct net_device *ndev, 362 const void *address) 363 { 364 struct axienet_local *lp = netdev_priv(ndev); 365 366 if (address) 367 eth_hw_addr_set(ndev, address); 368 if (!is_valid_ether_addr(ndev->dev_addr)) 369 eth_hw_addr_random(ndev); 370 371 /* Set up unicast MAC address filter set its mac address */ 372 axienet_iow(lp, XAE_UAW0_OFFSET, 373 (ndev->dev_addr[0]) | 374 (ndev->dev_addr[1] << 8) | 375 (ndev->dev_addr[2] << 16) | 376 (ndev->dev_addr[3] << 24)); 377 axienet_iow(lp, XAE_UAW1_OFFSET, 378 (((axienet_ior(lp, XAE_UAW1_OFFSET)) & 379 ~XAE_UAW1_UNICASTADDR_MASK) | 380 (ndev->dev_addr[4] | 381 (ndev->dev_addr[5] << 8)))); 382 } 383 384 /** 385 * netdev_set_mac_address - Write the MAC address (from outside the driver) 386 * @ndev: Pointer to the net_device structure 387 * @p: 6 byte Address to be written as MAC address 388 * 389 * Return: 0 for all conditions. Presently, there is no failure case. 390 * 391 * This function is called to initialize the MAC address of the Axi Ethernet 392 * core. It calls the core specific axienet_set_mac_address. This is the 393 * function that goes into net_device_ops structure entry ndo_set_mac_address. 394 */ 395 static int netdev_set_mac_address(struct net_device *ndev, void *p) 396 { 397 struct sockaddr *addr = p; 398 axienet_set_mac_address(ndev, addr->sa_data); 399 return 0; 400 } 401 402 /** 403 * axienet_set_multicast_list - Prepare the multicast table 404 * @ndev: Pointer to the net_device structure 405 * 406 * This function is called to initialize the multicast table during 407 * initialization. The Axi Ethernet basic multicast support has a four-entry 408 * multicast table which is initialized here. Additionally this function 409 * goes into the net_device_ops structure entry ndo_set_multicast_list. This 410 * means whenever the multicast table entries need to be updated this 411 * function gets called. 412 */ 413 static void axienet_set_multicast_list(struct net_device *ndev) 414 { 415 int i; 416 u32 reg, af0reg, af1reg; 417 struct axienet_local *lp = netdev_priv(ndev); 418 419 if (ndev->flags & (IFF_ALLMULTI | IFF_PROMISC) || 420 netdev_mc_count(ndev) > XAE_MULTICAST_CAM_TABLE_NUM) { 421 /* We must make the kernel realize we had to move into 422 * promiscuous mode. If it was a promiscuous mode request 423 * the flag is already set. If not we set it. 424 */ 425 ndev->flags |= IFF_PROMISC; 426 reg = axienet_ior(lp, XAE_FMI_OFFSET); 427 reg |= XAE_FMI_PM_MASK; 428 axienet_iow(lp, XAE_FMI_OFFSET, reg); 429 dev_info(&ndev->dev, "Promiscuous mode enabled.\n"); 430 } else if (!netdev_mc_empty(ndev)) { 431 struct netdev_hw_addr *ha; 432 433 reg = axienet_ior(lp, XAE_FMI_OFFSET); 434 reg &= ~XAE_FMI_PM_MASK; 435 axienet_iow(lp, XAE_FMI_OFFSET, reg); 436 437 i = 0; 438 netdev_for_each_mc_addr(ha, ndev) { 439 if (i >= XAE_MULTICAST_CAM_TABLE_NUM) 440 break; 441 442 af0reg = (ha->addr[0]); 443 af0reg |= (ha->addr[1] << 8); 444 af0reg |= (ha->addr[2] << 16); 445 af0reg |= (ha->addr[3] << 24); 446 447 af1reg = (ha->addr[4]); 448 af1reg |= (ha->addr[5] << 8); 449 450 reg = axienet_ior(lp, XAE_FMI_OFFSET) & 0xFFFFFF00; 451 reg |= i; 452 453 axienet_iow(lp, XAE_FMI_OFFSET, reg); 454 axienet_iow(lp, XAE_AF0_OFFSET, af0reg); 455 axienet_iow(lp, XAE_AF1_OFFSET, af1reg); 456 i++; 457 } 458 } else { 459 reg = axienet_ior(lp, XAE_FMI_OFFSET); 460 reg &= ~XAE_FMI_PM_MASK; 461 462 axienet_iow(lp, XAE_FMI_OFFSET, reg); 463 464 for (i = 0; i < XAE_MULTICAST_CAM_TABLE_NUM; i++) { 465 reg = axienet_ior(lp, XAE_FMI_OFFSET) & 0xFFFFFF00; 466 reg |= i; 467 468 axienet_iow(lp, XAE_FMI_OFFSET, reg); 469 axienet_iow(lp, XAE_AF0_OFFSET, 0); 470 axienet_iow(lp, XAE_AF1_OFFSET, 0); 471 } 472 473 dev_info(&ndev->dev, "Promiscuous mode disabled.\n"); 474 } 475 } 476 477 /** 478 * axienet_setoptions - Set an Axi Ethernet option 479 * @ndev: Pointer to the net_device structure 480 * @options: Option to be enabled/disabled 481 * 482 * The Axi Ethernet core has multiple features which can be selectively turned 483 * on or off. The typical options could be jumbo frame option, basic VLAN 484 * option, promiscuous mode option etc. This function is used to set or clear 485 * these options in the Axi Ethernet hardware. This is done through 486 * axienet_option structure . 487 */ 488 static void axienet_setoptions(struct net_device *ndev, u32 options) 489 { 490 int reg; 491 struct axienet_local *lp = netdev_priv(ndev); 492 struct axienet_option *tp = &axienet_options[0]; 493 494 while (tp->opt) { 495 reg = ((axienet_ior(lp, tp->reg)) & ~(tp->m_or)); 496 if (options & tp->opt) 497 reg |= tp->m_or; 498 axienet_iow(lp, tp->reg, reg); 499 tp++; 500 } 501 502 lp->options |= options; 503 } 504 505 static int __axienet_device_reset(struct axienet_local *lp) 506 { 507 u32 value; 508 int ret; 509 510 /* Reset Axi DMA. This would reset Axi Ethernet core as well. The reset 511 * process of Axi DMA takes a while to complete as all pending 512 * commands/transfers will be flushed or completed during this 513 * reset process. 514 * Note that even though both TX and RX have their own reset register, 515 * they both reset the entire DMA core, so only one needs to be used. 516 */ 517 axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, XAXIDMA_CR_RESET_MASK); 518 ret = read_poll_timeout(axienet_dma_in32, value, 519 !(value & XAXIDMA_CR_RESET_MASK), 520 DELAY_OF_ONE_MILLISEC, 50000, false, lp, 521 XAXIDMA_TX_CR_OFFSET); 522 if (ret) { 523 dev_err(lp->dev, "%s: DMA reset timeout!\n", __func__); 524 return ret; 525 } 526 527 /* Wait for PhyRstCmplt bit to be set, indicating the PHY reset has finished */ 528 ret = read_poll_timeout(axienet_ior, value, 529 value & XAE_INT_PHYRSTCMPLT_MASK, 530 DELAY_OF_ONE_MILLISEC, 50000, false, lp, 531 XAE_IS_OFFSET); 532 if (ret) { 533 dev_err(lp->dev, "%s: timeout waiting for PhyRstCmplt\n", __func__); 534 return ret; 535 } 536 537 return 0; 538 } 539 540 /** 541 * axienet_dma_stop - Stop DMA operation 542 * @lp: Pointer to the axienet_local structure 543 */ 544 static void axienet_dma_stop(struct axienet_local *lp) 545 { 546 int count; 547 u32 cr, sr; 548 549 cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET); 550 cr &= ~(XAXIDMA_CR_RUNSTOP_MASK | XAXIDMA_IRQ_ALL_MASK); 551 axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET, cr); 552 synchronize_irq(lp->rx_irq); 553 554 cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET); 555 cr &= ~(XAXIDMA_CR_RUNSTOP_MASK | XAXIDMA_IRQ_ALL_MASK); 556 axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, cr); 557 synchronize_irq(lp->tx_irq); 558 559 /* Give DMAs a chance to halt gracefully */ 560 sr = axienet_dma_in32(lp, XAXIDMA_RX_SR_OFFSET); 561 for (count = 0; !(sr & XAXIDMA_SR_HALT_MASK) && count < 5; ++count) { 562 msleep(20); 563 sr = axienet_dma_in32(lp, XAXIDMA_RX_SR_OFFSET); 564 } 565 566 sr = axienet_dma_in32(lp, XAXIDMA_TX_SR_OFFSET); 567 for (count = 0; !(sr & XAXIDMA_SR_HALT_MASK) && count < 5; ++count) { 568 msleep(20); 569 sr = axienet_dma_in32(lp, XAXIDMA_TX_SR_OFFSET); 570 } 571 572 /* Do a reset to ensure DMA is really stopped */ 573 axienet_lock_mii(lp); 574 __axienet_device_reset(lp); 575 axienet_unlock_mii(lp); 576 } 577 578 /** 579 * axienet_device_reset - Reset and initialize the Axi Ethernet hardware. 580 * @ndev: Pointer to the net_device structure 581 * 582 * This function is called to reset and initialize the Axi Ethernet core. This 583 * is typically called during initialization. It does a reset of the Axi DMA 584 * Rx/Tx channels and initializes the Axi DMA BDs. Since Axi DMA reset lines 585 * are connected to Axi Ethernet reset lines, this in turn resets the Axi 586 * Ethernet core. No separate hardware reset is done for the Axi Ethernet 587 * core. 588 * Returns 0 on success or a negative error number otherwise. 589 */ 590 static int axienet_device_reset(struct net_device *ndev) 591 { 592 u32 axienet_status; 593 struct axienet_local *lp = netdev_priv(ndev); 594 int ret; 595 596 ret = __axienet_device_reset(lp); 597 if (ret) 598 return ret; 599 600 lp->max_frm_size = XAE_MAX_VLAN_FRAME_SIZE; 601 lp->options |= XAE_OPTION_VLAN; 602 lp->options &= (~XAE_OPTION_JUMBO); 603 604 if ((ndev->mtu > XAE_MTU) && 605 (ndev->mtu <= XAE_JUMBO_MTU)) { 606 lp->max_frm_size = ndev->mtu + VLAN_ETH_HLEN + 607 XAE_TRL_SIZE; 608 609 if (lp->max_frm_size <= lp->rxmem) 610 lp->options |= XAE_OPTION_JUMBO; 611 } 612 613 ret = axienet_dma_bd_init(ndev); 614 if (ret) { 615 netdev_err(ndev, "%s: descriptor allocation failed\n", 616 __func__); 617 return ret; 618 } 619 620 axienet_status = axienet_ior(lp, XAE_RCW1_OFFSET); 621 axienet_status &= ~XAE_RCW1_RX_MASK; 622 axienet_iow(lp, XAE_RCW1_OFFSET, axienet_status); 623 624 axienet_status = axienet_ior(lp, XAE_IP_OFFSET); 625 if (axienet_status & XAE_INT_RXRJECT_MASK) 626 axienet_iow(lp, XAE_IS_OFFSET, XAE_INT_RXRJECT_MASK); 627 axienet_iow(lp, XAE_IE_OFFSET, lp->eth_irq > 0 ? 628 XAE_INT_RECV_ERROR_MASK : 0); 629 630 axienet_iow(lp, XAE_FCC_OFFSET, XAE_FCC_FCRX_MASK); 631 632 /* Sync default options with HW but leave receiver and 633 * transmitter disabled. 634 */ 635 axienet_setoptions(ndev, lp->options & 636 ~(XAE_OPTION_TXEN | XAE_OPTION_RXEN)); 637 axienet_set_mac_address(ndev, NULL); 638 axienet_set_multicast_list(ndev); 639 axienet_setoptions(ndev, lp->options); 640 641 netif_trans_update(ndev); 642 643 return 0; 644 } 645 646 /** 647 * axienet_free_tx_chain - Clean up a series of linked TX descriptors. 648 * @lp: Pointer to the axienet_local structure 649 * @first_bd: Index of first descriptor to clean up 650 * @nr_bds: Max number of descriptors to clean up 651 * @force: Whether to clean descriptors even if not complete 652 * @sizep: Pointer to a u32 filled with the total sum of all bytes 653 * in all cleaned-up descriptors. Ignored if NULL. 654 * @budget: NAPI budget (use 0 when not called from NAPI poll) 655 * 656 * Would either be called after a successful transmit operation, or after 657 * there was an error when setting up the chain. 658 * Returns the number of descriptors handled. 659 */ 660 static int axienet_free_tx_chain(struct axienet_local *lp, u32 first_bd, 661 int nr_bds, bool force, u32 *sizep, int budget) 662 { 663 struct axidma_bd *cur_p; 664 unsigned int status; 665 dma_addr_t phys; 666 int i; 667 668 for (i = 0; i < nr_bds; i++) { 669 cur_p = &lp->tx_bd_v[(first_bd + i) % lp->tx_bd_num]; 670 status = cur_p->status; 671 672 /* If force is not specified, clean up only descriptors 673 * that have been completed by the MAC. 674 */ 675 if (!force && !(status & XAXIDMA_BD_STS_COMPLETE_MASK)) 676 break; 677 678 /* Ensure we see complete descriptor update */ 679 dma_rmb(); 680 phys = desc_get_phys_addr(lp, cur_p); 681 dma_unmap_single(lp->dev, phys, 682 (cur_p->cntrl & XAXIDMA_BD_CTRL_LENGTH_MASK), 683 DMA_TO_DEVICE); 684 685 if (cur_p->skb && (status & XAXIDMA_BD_STS_COMPLETE_MASK)) 686 napi_consume_skb(cur_p->skb, budget); 687 688 cur_p->app0 = 0; 689 cur_p->app1 = 0; 690 cur_p->app2 = 0; 691 cur_p->app4 = 0; 692 cur_p->skb = NULL; 693 /* ensure our transmit path and device don't prematurely see status cleared */ 694 wmb(); 695 cur_p->cntrl = 0; 696 cur_p->status = 0; 697 698 if (sizep) 699 *sizep += status & XAXIDMA_BD_STS_ACTUAL_LEN_MASK; 700 } 701 702 return i; 703 } 704 705 /** 706 * axienet_check_tx_bd_space - Checks if a BD/group of BDs are currently busy 707 * @lp: Pointer to the axienet_local structure 708 * @num_frag: The number of BDs to check for 709 * 710 * Return: 0, on success 711 * NETDEV_TX_BUSY, if any of the descriptors are not free 712 * 713 * This function is invoked before BDs are allocated and transmission starts. 714 * This function returns 0 if a BD or group of BDs can be allocated for 715 * transmission. If the BD or any of the BDs are not free the function 716 * returns a busy status. 717 */ 718 static inline int axienet_check_tx_bd_space(struct axienet_local *lp, 719 int num_frag) 720 { 721 struct axidma_bd *cur_p; 722 723 /* Ensure we see all descriptor updates from device or TX polling */ 724 rmb(); 725 cur_p = &lp->tx_bd_v[(READ_ONCE(lp->tx_bd_tail) + num_frag) % 726 lp->tx_bd_num]; 727 if (cur_p->cntrl) 728 return NETDEV_TX_BUSY; 729 return 0; 730 } 731 732 /** 733 * axienet_tx_poll - Invoked once a transmit is completed by the 734 * Axi DMA Tx channel. 735 * @napi: Pointer to NAPI structure. 736 * @budget: Max number of TX packets to process. 737 * 738 * Return: Number of TX packets processed. 739 * 740 * This function is invoked from the NAPI processing to notify the completion 741 * of transmit operation. It clears fields in the corresponding Tx BDs and 742 * unmaps the corresponding buffer so that CPU can regain ownership of the 743 * buffer. It finally invokes "netif_wake_queue" to restart transmission if 744 * required. 745 */ 746 static int axienet_tx_poll(struct napi_struct *napi, int budget) 747 { 748 struct axienet_local *lp = container_of(napi, struct axienet_local, napi_tx); 749 struct net_device *ndev = lp->ndev; 750 u32 size = 0; 751 int packets; 752 753 packets = axienet_free_tx_chain(lp, lp->tx_bd_ci, budget, false, &size, budget); 754 755 if (packets) { 756 lp->tx_bd_ci += packets; 757 if (lp->tx_bd_ci >= lp->tx_bd_num) 758 lp->tx_bd_ci %= lp->tx_bd_num; 759 760 u64_stats_update_begin(&lp->tx_stat_sync); 761 u64_stats_add(&lp->tx_packets, packets); 762 u64_stats_add(&lp->tx_bytes, size); 763 u64_stats_update_end(&lp->tx_stat_sync); 764 765 /* Matches barrier in axienet_start_xmit */ 766 smp_mb(); 767 768 if (!axienet_check_tx_bd_space(lp, MAX_SKB_FRAGS + 1)) 769 netif_wake_queue(ndev); 770 } 771 772 if (packets < budget && napi_complete_done(napi, packets)) { 773 /* Re-enable TX completion interrupts. This should 774 * cause an immediate interrupt if any TX packets are 775 * already pending. 776 */ 777 axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, lp->tx_dma_cr); 778 } 779 return packets; 780 } 781 782 /** 783 * axienet_start_xmit - Starts the transmission. 784 * @skb: sk_buff pointer that contains data to be Txed. 785 * @ndev: Pointer to net_device structure. 786 * 787 * Return: NETDEV_TX_OK, on success 788 * NETDEV_TX_BUSY, if any of the descriptors are not free 789 * 790 * This function is invoked from upper layers to initiate transmission. The 791 * function uses the next available free BDs and populates their fields to 792 * start the transmission. Additionally if checksum offloading is supported, 793 * it populates AXI Stream Control fields with appropriate values. 794 */ 795 static netdev_tx_t 796 axienet_start_xmit(struct sk_buff *skb, struct net_device *ndev) 797 { 798 u32 ii; 799 u32 num_frag; 800 u32 csum_start_off; 801 u32 csum_index_off; 802 skb_frag_t *frag; 803 dma_addr_t tail_p, phys; 804 u32 orig_tail_ptr, new_tail_ptr; 805 struct axienet_local *lp = netdev_priv(ndev); 806 struct axidma_bd *cur_p; 807 808 orig_tail_ptr = lp->tx_bd_tail; 809 new_tail_ptr = orig_tail_ptr; 810 811 num_frag = skb_shinfo(skb)->nr_frags; 812 cur_p = &lp->tx_bd_v[orig_tail_ptr]; 813 814 if (axienet_check_tx_bd_space(lp, num_frag + 1)) { 815 /* Should not happen as last start_xmit call should have 816 * checked for sufficient space and queue should only be 817 * woken when sufficient space is available. 818 */ 819 netif_stop_queue(ndev); 820 if (net_ratelimit()) 821 netdev_warn(ndev, "TX ring unexpectedly full\n"); 822 return NETDEV_TX_BUSY; 823 } 824 825 if (skb->ip_summed == CHECKSUM_PARTIAL) { 826 if (lp->features & XAE_FEATURE_FULL_TX_CSUM) { 827 /* Tx Full Checksum Offload Enabled */ 828 cur_p->app0 |= 2; 829 } else if (lp->features & XAE_FEATURE_PARTIAL_TX_CSUM) { 830 csum_start_off = skb_transport_offset(skb); 831 csum_index_off = csum_start_off + skb->csum_offset; 832 /* Tx Partial Checksum Offload Enabled */ 833 cur_p->app0 |= 1; 834 cur_p->app1 = (csum_start_off << 16) | csum_index_off; 835 } 836 } else if (skb->ip_summed == CHECKSUM_UNNECESSARY) { 837 cur_p->app0 |= 2; /* Tx Full Checksum Offload Enabled */ 838 } 839 840 phys = dma_map_single(lp->dev, skb->data, 841 skb_headlen(skb), DMA_TO_DEVICE); 842 if (unlikely(dma_mapping_error(lp->dev, phys))) { 843 if (net_ratelimit()) 844 netdev_err(ndev, "TX DMA mapping error\n"); 845 ndev->stats.tx_dropped++; 846 return NETDEV_TX_OK; 847 } 848 desc_set_phys_addr(lp, phys, cur_p); 849 cur_p->cntrl = skb_headlen(skb) | XAXIDMA_BD_CTRL_TXSOF_MASK; 850 851 for (ii = 0; ii < num_frag; ii++) { 852 if (++new_tail_ptr >= lp->tx_bd_num) 853 new_tail_ptr = 0; 854 cur_p = &lp->tx_bd_v[new_tail_ptr]; 855 frag = &skb_shinfo(skb)->frags[ii]; 856 phys = dma_map_single(lp->dev, 857 skb_frag_address(frag), 858 skb_frag_size(frag), 859 DMA_TO_DEVICE); 860 if (unlikely(dma_mapping_error(lp->dev, phys))) { 861 if (net_ratelimit()) 862 netdev_err(ndev, "TX DMA mapping error\n"); 863 ndev->stats.tx_dropped++; 864 axienet_free_tx_chain(lp, orig_tail_ptr, ii + 1, 865 true, NULL, 0); 866 return NETDEV_TX_OK; 867 } 868 desc_set_phys_addr(lp, phys, cur_p); 869 cur_p->cntrl = skb_frag_size(frag); 870 } 871 872 cur_p->cntrl |= XAXIDMA_BD_CTRL_TXEOF_MASK; 873 cur_p->skb = skb; 874 875 tail_p = lp->tx_bd_p + sizeof(*lp->tx_bd_v) * new_tail_ptr; 876 if (++new_tail_ptr >= lp->tx_bd_num) 877 new_tail_ptr = 0; 878 WRITE_ONCE(lp->tx_bd_tail, new_tail_ptr); 879 880 /* Start the transfer */ 881 axienet_dma_out_addr(lp, XAXIDMA_TX_TDESC_OFFSET, tail_p); 882 883 /* Stop queue if next transmit may not have space */ 884 if (axienet_check_tx_bd_space(lp, MAX_SKB_FRAGS + 1)) { 885 netif_stop_queue(ndev); 886 887 /* Matches barrier in axienet_tx_poll */ 888 smp_mb(); 889 890 /* Space might have just been freed - check again */ 891 if (!axienet_check_tx_bd_space(lp, MAX_SKB_FRAGS + 1)) 892 netif_wake_queue(ndev); 893 } 894 895 return NETDEV_TX_OK; 896 } 897 898 /** 899 * axienet_rx_poll - Triggered by RX ISR to complete the BD processing. 900 * @napi: Pointer to NAPI structure. 901 * @budget: Max number of RX packets to process. 902 * 903 * Return: Number of RX packets processed. 904 */ 905 static int axienet_rx_poll(struct napi_struct *napi, int budget) 906 { 907 u32 length; 908 u32 csumstatus; 909 u32 size = 0; 910 int packets = 0; 911 dma_addr_t tail_p = 0; 912 struct axidma_bd *cur_p; 913 struct sk_buff *skb, *new_skb; 914 struct axienet_local *lp = container_of(napi, struct axienet_local, napi_rx); 915 916 cur_p = &lp->rx_bd_v[lp->rx_bd_ci]; 917 918 while (packets < budget && (cur_p->status & XAXIDMA_BD_STS_COMPLETE_MASK)) { 919 dma_addr_t phys; 920 921 /* Ensure we see complete descriptor update */ 922 dma_rmb(); 923 924 skb = cur_p->skb; 925 cur_p->skb = NULL; 926 927 /* skb could be NULL if a previous pass already received the 928 * packet for this slot in the ring, but failed to refill it 929 * with a newly allocated buffer. In this case, don't try to 930 * receive it again. 931 */ 932 if (likely(skb)) { 933 length = cur_p->app4 & 0x0000FFFF; 934 935 phys = desc_get_phys_addr(lp, cur_p); 936 dma_unmap_single(lp->dev, phys, lp->max_frm_size, 937 DMA_FROM_DEVICE); 938 939 skb_put(skb, length); 940 skb->protocol = eth_type_trans(skb, lp->ndev); 941 /*skb_checksum_none_assert(skb);*/ 942 skb->ip_summed = CHECKSUM_NONE; 943 944 /* if we're doing Rx csum offload, set it up */ 945 if (lp->features & XAE_FEATURE_FULL_RX_CSUM) { 946 csumstatus = (cur_p->app2 & 947 XAE_FULL_CSUM_STATUS_MASK) >> 3; 948 if (csumstatus == XAE_IP_TCP_CSUM_VALIDATED || 949 csumstatus == XAE_IP_UDP_CSUM_VALIDATED) { 950 skb->ip_summed = CHECKSUM_UNNECESSARY; 951 } 952 } else if ((lp->features & XAE_FEATURE_PARTIAL_RX_CSUM) != 0 && 953 skb->protocol == htons(ETH_P_IP) && 954 skb->len > 64) { 955 skb->csum = be32_to_cpu(cur_p->app3 & 0xFFFF); 956 skb->ip_summed = CHECKSUM_COMPLETE; 957 } 958 959 napi_gro_receive(napi, skb); 960 961 size += length; 962 packets++; 963 } 964 965 new_skb = napi_alloc_skb(napi, lp->max_frm_size); 966 if (!new_skb) 967 break; 968 969 phys = dma_map_single(lp->dev, new_skb->data, 970 lp->max_frm_size, 971 DMA_FROM_DEVICE); 972 if (unlikely(dma_mapping_error(lp->dev, phys))) { 973 if (net_ratelimit()) 974 netdev_err(lp->ndev, "RX DMA mapping error\n"); 975 dev_kfree_skb(new_skb); 976 break; 977 } 978 desc_set_phys_addr(lp, phys, cur_p); 979 980 cur_p->cntrl = lp->max_frm_size; 981 cur_p->status = 0; 982 cur_p->skb = new_skb; 983 984 /* Only update tail_p to mark this slot as usable after it has 985 * been successfully refilled. 986 */ 987 tail_p = lp->rx_bd_p + sizeof(*lp->rx_bd_v) * lp->rx_bd_ci; 988 989 if (++lp->rx_bd_ci >= lp->rx_bd_num) 990 lp->rx_bd_ci = 0; 991 cur_p = &lp->rx_bd_v[lp->rx_bd_ci]; 992 } 993 994 u64_stats_update_begin(&lp->rx_stat_sync); 995 u64_stats_add(&lp->rx_packets, packets); 996 u64_stats_add(&lp->rx_bytes, size); 997 u64_stats_update_end(&lp->rx_stat_sync); 998 999 if (tail_p) 1000 axienet_dma_out_addr(lp, XAXIDMA_RX_TDESC_OFFSET, tail_p); 1001 1002 if (packets < budget && napi_complete_done(napi, packets)) { 1003 /* Re-enable RX completion interrupts. This should 1004 * cause an immediate interrupt if any RX packets are 1005 * already pending. 1006 */ 1007 axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET, lp->rx_dma_cr); 1008 } 1009 return packets; 1010 } 1011 1012 /** 1013 * axienet_tx_irq - Tx Done Isr. 1014 * @irq: irq number 1015 * @_ndev: net_device pointer 1016 * 1017 * Return: IRQ_HANDLED if device generated a TX interrupt, IRQ_NONE otherwise. 1018 * 1019 * This is the Axi DMA Tx done Isr. It invokes NAPI polling to complete the 1020 * TX BD processing. 1021 */ 1022 static irqreturn_t axienet_tx_irq(int irq, void *_ndev) 1023 { 1024 unsigned int status; 1025 struct net_device *ndev = _ndev; 1026 struct axienet_local *lp = netdev_priv(ndev); 1027 1028 status = axienet_dma_in32(lp, XAXIDMA_TX_SR_OFFSET); 1029 1030 if (!(status & XAXIDMA_IRQ_ALL_MASK)) 1031 return IRQ_NONE; 1032 1033 axienet_dma_out32(lp, XAXIDMA_TX_SR_OFFSET, status); 1034 1035 if (unlikely(status & XAXIDMA_IRQ_ERROR_MASK)) { 1036 netdev_err(ndev, "DMA Tx error 0x%x\n", status); 1037 netdev_err(ndev, "Current BD is at: 0x%x%08x\n", 1038 (lp->tx_bd_v[lp->tx_bd_ci]).phys_msb, 1039 (lp->tx_bd_v[lp->tx_bd_ci]).phys); 1040 schedule_work(&lp->dma_err_task); 1041 } else { 1042 /* Disable further TX completion interrupts and schedule 1043 * NAPI to handle the completions. 1044 */ 1045 u32 cr = lp->tx_dma_cr; 1046 1047 cr &= ~(XAXIDMA_IRQ_IOC_MASK | XAXIDMA_IRQ_DELAY_MASK); 1048 axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, cr); 1049 1050 napi_schedule(&lp->napi_tx); 1051 } 1052 1053 return IRQ_HANDLED; 1054 } 1055 1056 /** 1057 * axienet_rx_irq - Rx Isr. 1058 * @irq: irq number 1059 * @_ndev: net_device pointer 1060 * 1061 * Return: IRQ_HANDLED if device generated a RX interrupt, IRQ_NONE otherwise. 1062 * 1063 * This is the Axi DMA Rx Isr. It invokes NAPI polling to complete the RX BD 1064 * processing. 1065 */ 1066 static irqreturn_t axienet_rx_irq(int irq, void *_ndev) 1067 { 1068 unsigned int status; 1069 struct net_device *ndev = _ndev; 1070 struct axienet_local *lp = netdev_priv(ndev); 1071 1072 status = axienet_dma_in32(lp, XAXIDMA_RX_SR_OFFSET); 1073 1074 if (!(status & XAXIDMA_IRQ_ALL_MASK)) 1075 return IRQ_NONE; 1076 1077 axienet_dma_out32(lp, XAXIDMA_RX_SR_OFFSET, status); 1078 1079 if (unlikely(status & XAXIDMA_IRQ_ERROR_MASK)) { 1080 netdev_err(ndev, "DMA Rx error 0x%x\n", status); 1081 netdev_err(ndev, "Current BD is at: 0x%x%08x\n", 1082 (lp->rx_bd_v[lp->rx_bd_ci]).phys_msb, 1083 (lp->rx_bd_v[lp->rx_bd_ci]).phys); 1084 schedule_work(&lp->dma_err_task); 1085 } else { 1086 /* Disable further RX completion interrupts and schedule 1087 * NAPI receive. 1088 */ 1089 u32 cr = lp->rx_dma_cr; 1090 1091 cr &= ~(XAXIDMA_IRQ_IOC_MASK | XAXIDMA_IRQ_DELAY_MASK); 1092 axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET, cr); 1093 1094 napi_schedule(&lp->napi_rx); 1095 } 1096 1097 return IRQ_HANDLED; 1098 } 1099 1100 /** 1101 * axienet_eth_irq - Ethernet core Isr. 1102 * @irq: irq number 1103 * @_ndev: net_device pointer 1104 * 1105 * Return: IRQ_HANDLED if device generated a core interrupt, IRQ_NONE otherwise. 1106 * 1107 * Handle miscellaneous conditions indicated by Ethernet core IRQ. 1108 */ 1109 static irqreturn_t axienet_eth_irq(int irq, void *_ndev) 1110 { 1111 struct net_device *ndev = _ndev; 1112 struct axienet_local *lp = netdev_priv(ndev); 1113 unsigned int pending; 1114 1115 pending = axienet_ior(lp, XAE_IP_OFFSET); 1116 if (!pending) 1117 return IRQ_NONE; 1118 1119 if (pending & XAE_INT_RXFIFOOVR_MASK) 1120 ndev->stats.rx_missed_errors++; 1121 1122 if (pending & XAE_INT_RXRJECT_MASK) 1123 ndev->stats.rx_frame_errors++; 1124 1125 axienet_iow(lp, XAE_IS_OFFSET, pending); 1126 return IRQ_HANDLED; 1127 } 1128 1129 static void axienet_dma_err_handler(struct work_struct *work); 1130 1131 /** 1132 * axienet_open - Driver open routine. 1133 * @ndev: Pointer to net_device structure 1134 * 1135 * Return: 0, on success. 1136 * non-zero error value on failure 1137 * 1138 * This is the driver open routine. It calls phylink_start to start the 1139 * PHY device. 1140 * It also allocates interrupt service routines, enables the interrupt lines 1141 * and ISR handling. Axi Ethernet core is reset through Axi DMA core. Buffer 1142 * descriptors are initialized. 1143 */ 1144 static int axienet_open(struct net_device *ndev) 1145 { 1146 int ret; 1147 struct axienet_local *lp = netdev_priv(ndev); 1148 1149 dev_dbg(&ndev->dev, "axienet_open()\n"); 1150 1151 /* When we do an Axi Ethernet reset, it resets the complete core 1152 * including the MDIO. MDIO must be disabled before resetting. 1153 * Hold MDIO bus lock to avoid MDIO accesses during the reset. 1154 */ 1155 axienet_lock_mii(lp); 1156 ret = axienet_device_reset(ndev); 1157 axienet_unlock_mii(lp); 1158 1159 ret = phylink_of_phy_connect(lp->phylink, lp->dev->of_node, 0); 1160 if (ret) { 1161 dev_err(lp->dev, "phylink_of_phy_connect() failed: %d\n", ret); 1162 return ret; 1163 } 1164 1165 phylink_start(lp->phylink); 1166 1167 /* Enable worker thread for Axi DMA error handling */ 1168 INIT_WORK(&lp->dma_err_task, axienet_dma_err_handler); 1169 1170 napi_enable(&lp->napi_rx); 1171 napi_enable(&lp->napi_tx); 1172 1173 /* Enable interrupts for Axi DMA Tx */ 1174 ret = request_irq(lp->tx_irq, axienet_tx_irq, IRQF_SHARED, 1175 ndev->name, ndev); 1176 if (ret) 1177 goto err_tx_irq; 1178 /* Enable interrupts for Axi DMA Rx */ 1179 ret = request_irq(lp->rx_irq, axienet_rx_irq, IRQF_SHARED, 1180 ndev->name, ndev); 1181 if (ret) 1182 goto err_rx_irq; 1183 /* Enable interrupts for Axi Ethernet core (if defined) */ 1184 if (lp->eth_irq > 0) { 1185 ret = request_irq(lp->eth_irq, axienet_eth_irq, IRQF_SHARED, 1186 ndev->name, ndev); 1187 if (ret) 1188 goto err_eth_irq; 1189 } 1190 1191 return 0; 1192 1193 err_eth_irq: 1194 free_irq(lp->rx_irq, ndev); 1195 err_rx_irq: 1196 free_irq(lp->tx_irq, ndev); 1197 err_tx_irq: 1198 napi_disable(&lp->napi_tx); 1199 napi_disable(&lp->napi_rx); 1200 phylink_stop(lp->phylink); 1201 phylink_disconnect_phy(lp->phylink); 1202 cancel_work_sync(&lp->dma_err_task); 1203 dev_err(lp->dev, "request_irq() failed\n"); 1204 return ret; 1205 } 1206 1207 /** 1208 * axienet_stop - Driver stop routine. 1209 * @ndev: Pointer to net_device structure 1210 * 1211 * Return: 0, on success. 1212 * 1213 * This is the driver stop routine. It calls phylink_disconnect to stop the PHY 1214 * device. It also removes the interrupt handlers and disables the interrupts. 1215 * The Axi DMA Tx/Rx BDs are released. 1216 */ 1217 static int axienet_stop(struct net_device *ndev) 1218 { 1219 struct axienet_local *lp = netdev_priv(ndev); 1220 1221 dev_dbg(&ndev->dev, "axienet_close()\n"); 1222 1223 napi_disable(&lp->napi_tx); 1224 napi_disable(&lp->napi_rx); 1225 1226 phylink_stop(lp->phylink); 1227 phylink_disconnect_phy(lp->phylink); 1228 1229 axienet_setoptions(ndev, lp->options & 1230 ~(XAE_OPTION_TXEN | XAE_OPTION_RXEN)); 1231 1232 axienet_dma_stop(lp); 1233 1234 axienet_iow(lp, XAE_IE_OFFSET, 0); 1235 1236 cancel_work_sync(&lp->dma_err_task); 1237 1238 if (lp->eth_irq > 0) 1239 free_irq(lp->eth_irq, ndev); 1240 free_irq(lp->tx_irq, ndev); 1241 free_irq(lp->rx_irq, ndev); 1242 1243 axienet_dma_bd_release(ndev); 1244 return 0; 1245 } 1246 1247 /** 1248 * axienet_change_mtu - Driver change mtu routine. 1249 * @ndev: Pointer to net_device structure 1250 * @new_mtu: New mtu value to be applied 1251 * 1252 * Return: Always returns 0 (success). 1253 * 1254 * This is the change mtu driver routine. It checks if the Axi Ethernet 1255 * hardware supports jumbo frames before changing the mtu. This can be 1256 * called only when the device is not up. 1257 */ 1258 static int axienet_change_mtu(struct net_device *ndev, int new_mtu) 1259 { 1260 struct axienet_local *lp = netdev_priv(ndev); 1261 1262 if (netif_running(ndev)) 1263 return -EBUSY; 1264 1265 if ((new_mtu + VLAN_ETH_HLEN + 1266 XAE_TRL_SIZE) > lp->rxmem) 1267 return -EINVAL; 1268 1269 ndev->mtu = new_mtu; 1270 1271 return 0; 1272 } 1273 1274 #ifdef CONFIG_NET_POLL_CONTROLLER 1275 /** 1276 * axienet_poll_controller - Axi Ethernet poll mechanism. 1277 * @ndev: Pointer to net_device structure 1278 * 1279 * This implements Rx/Tx ISR poll mechanisms. The interrupts are disabled prior 1280 * to polling the ISRs and are enabled back after the polling is done. 1281 */ 1282 static void axienet_poll_controller(struct net_device *ndev) 1283 { 1284 struct axienet_local *lp = netdev_priv(ndev); 1285 disable_irq(lp->tx_irq); 1286 disable_irq(lp->rx_irq); 1287 axienet_rx_irq(lp->tx_irq, ndev); 1288 axienet_tx_irq(lp->rx_irq, ndev); 1289 enable_irq(lp->tx_irq); 1290 enable_irq(lp->rx_irq); 1291 } 1292 #endif 1293 1294 static int axienet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 1295 { 1296 struct axienet_local *lp = netdev_priv(dev); 1297 1298 if (!netif_running(dev)) 1299 return -EINVAL; 1300 1301 return phylink_mii_ioctl(lp->phylink, rq, cmd); 1302 } 1303 1304 static void 1305 axienet_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) 1306 { 1307 struct axienet_local *lp = netdev_priv(dev); 1308 unsigned int start; 1309 1310 netdev_stats_to_stats64(stats, &dev->stats); 1311 1312 do { 1313 start = u64_stats_fetch_begin(&lp->rx_stat_sync); 1314 stats->rx_packets = u64_stats_read(&lp->rx_packets); 1315 stats->rx_bytes = u64_stats_read(&lp->rx_bytes); 1316 } while (u64_stats_fetch_retry(&lp->rx_stat_sync, start)); 1317 1318 do { 1319 start = u64_stats_fetch_begin(&lp->tx_stat_sync); 1320 stats->tx_packets = u64_stats_read(&lp->tx_packets); 1321 stats->tx_bytes = u64_stats_read(&lp->tx_bytes); 1322 } while (u64_stats_fetch_retry(&lp->tx_stat_sync, start)); 1323 } 1324 1325 static const struct net_device_ops axienet_netdev_ops = { 1326 .ndo_open = axienet_open, 1327 .ndo_stop = axienet_stop, 1328 .ndo_start_xmit = axienet_start_xmit, 1329 .ndo_get_stats64 = axienet_get_stats64, 1330 .ndo_change_mtu = axienet_change_mtu, 1331 .ndo_set_mac_address = netdev_set_mac_address, 1332 .ndo_validate_addr = eth_validate_addr, 1333 .ndo_eth_ioctl = axienet_ioctl, 1334 .ndo_set_rx_mode = axienet_set_multicast_list, 1335 #ifdef CONFIG_NET_POLL_CONTROLLER 1336 .ndo_poll_controller = axienet_poll_controller, 1337 #endif 1338 }; 1339 1340 /** 1341 * axienet_ethtools_get_drvinfo - Get various Axi Ethernet driver information. 1342 * @ndev: Pointer to net_device structure 1343 * @ed: Pointer to ethtool_drvinfo structure 1344 * 1345 * This implements ethtool command for getting the driver information. 1346 * Issue "ethtool -i ethX" under linux prompt to execute this function. 1347 */ 1348 static void axienet_ethtools_get_drvinfo(struct net_device *ndev, 1349 struct ethtool_drvinfo *ed) 1350 { 1351 strscpy(ed->driver, DRIVER_NAME, sizeof(ed->driver)); 1352 strscpy(ed->version, DRIVER_VERSION, sizeof(ed->version)); 1353 } 1354 1355 /** 1356 * axienet_ethtools_get_regs_len - Get the total regs length present in the 1357 * AxiEthernet core. 1358 * @ndev: Pointer to net_device structure 1359 * 1360 * This implements ethtool command for getting the total register length 1361 * information. 1362 * 1363 * Return: the total regs length 1364 */ 1365 static int axienet_ethtools_get_regs_len(struct net_device *ndev) 1366 { 1367 return sizeof(u32) * AXIENET_REGS_N; 1368 } 1369 1370 /** 1371 * axienet_ethtools_get_regs - Dump the contents of all registers present 1372 * in AxiEthernet core. 1373 * @ndev: Pointer to net_device structure 1374 * @regs: Pointer to ethtool_regs structure 1375 * @ret: Void pointer used to return the contents of the registers. 1376 * 1377 * This implements ethtool command for getting the Axi Ethernet register dump. 1378 * Issue "ethtool -d ethX" to execute this function. 1379 */ 1380 static void axienet_ethtools_get_regs(struct net_device *ndev, 1381 struct ethtool_regs *regs, void *ret) 1382 { 1383 u32 *data = (u32 *)ret; 1384 size_t len = sizeof(u32) * AXIENET_REGS_N; 1385 struct axienet_local *lp = netdev_priv(ndev); 1386 1387 regs->version = 0; 1388 regs->len = len; 1389 1390 memset(data, 0, len); 1391 data[0] = axienet_ior(lp, XAE_RAF_OFFSET); 1392 data[1] = axienet_ior(lp, XAE_TPF_OFFSET); 1393 data[2] = axienet_ior(lp, XAE_IFGP_OFFSET); 1394 data[3] = axienet_ior(lp, XAE_IS_OFFSET); 1395 data[4] = axienet_ior(lp, XAE_IP_OFFSET); 1396 data[5] = axienet_ior(lp, XAE_IE_OFFSET); 1397 data[6] = axienet_ior(lp, XAE_TTAG_OFFSET); 1398 data[7] = axienet_ior(lp, XAE_RTAG_OFFSET); 1399 data[8] = axienet_ior(lp, XAE_UAWL_OFFSET); 1400 data[9] = axienet_ior(lp, XAE_UAWU_OFFSET); 1401 data[10] = axienet_ior(lp, XAE_TPID0_OFFSET); 1402 data[11] = axienet_ior(lp, XAE_TPID1_OFFSET); 1403 data[12] = axienet_ior(lp, XAE_PPST_OFFSET); 1404 data[13] = axienet_ior(lp, XAE_RCW0_OFFSET); 1405 data[14] = axienet_ior(lp, XAE_RCW1_OFFSET); 1406 data[15] = axienet_ior(lp, XAE_TC_OFFSET); 1407 data[16] = axienet_ior(lp, XAE_FCC_OFFSET); 1408 data[17] = axienet_ior(lp, XAE_EMMC_OFFSET); 1409 data[18] = axienet_ior(lp, XAE_PHYC_OFFSET); 1410 data[19] = axienet_ior(lp, XAE_MDIO_MC_OFFSET); 1411 data[20] = axienet_ior(lp, XAE_MDIO_MCR_OFFSET); 1412 data[21] = axienet_ior(lp, XAE_MDIO_MWD_OFFSET); 1413 data[22] = axienet_ior(lp, XAE_MDIO_MRD_OFFSET); 1414 data[27] = axienet_ior(lp, XAE_UAW0_OFFSET); 1415 data[28] = axienet_ior(lp, XAE_UAW1_OFFSET); 1416 data[29] = axienet_ior(lp, XAE_FMI_OFFSET); 1417 data[30] = axienet_ior(lp, XAE_AF0_OFFSET); 1418 data[31] = axienet_ior(lp, XAE_AF1_OFFSET); 1419 data[32] = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET); 1420 data[33] = axienet_dma_in32(lp, XAXIDMA_TX_SR_OFFSET); 1421 data[34] = axienet_dma_in32(lp, XAXIDMA_TX_CDESC_OFFSET); 1422 data[35] = axienet_dma_in32(lp, XAXIDMA_TX_TDESC_OFFSET); 1423 data[36] = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET); 1424 data[37] = axienet_dma_in32(lp, XAXIDMA_RX_SR_OFFSET); 1425 data[38] = axienet_dma_in32(lp, XAXIDMA_RX_CDESC_OFFSET); 1426 data[39] = axienet_dma_in32(lp, XAXIDMA_RX_TDESC_OFFSET); 1427 } 1428 1429 static void 1430 axienet_ethtools_get_ringparam(struct net_device *ndev, 1431 struct ethtool_ringparam *ering, 1432 struct kernel_ethtool_ringparam *kernel_ering, 1433 struct netlink_ext_ack *extack) 1434 { 1435 struct axienet_local *lp = netdev_priv(ndev); 1436 1437 ering->rx_max_pending = RX_BD_NUM_MAX; 1438 ering->rx_mini_max_pending = 0; 1439 ering->rx_jumbo_max_pending = 0; 1440 ering->tx_max_pending = TX_BD_NUM_MAX; 1441 ering->rx_pending = lp->rx_bd_num; 1442 ering->rx_mini_pending = 0; 1443 ering->rx_jumbo_pending = 0; 1444 ering->tx_pending = lp->tx_bd_num; 1445 } 1446 1447 static int 1448 axienet_ethtools_set_ringparam(struct net_device *ndev, 1449 struct ethtool_ringparam *ering, 1450 struct kernel_ethtool_ringparam *kernel_ering, 1451 struct netlink_ext_ack *extack) 1452 { 1453 struct axienet_local *lp = netdev_priv(ndev); 1454 1455 if (ering->rx_pending > RX_BD_NUM_MAX || 1456 ering->rx_mini_pending || 1457 ering->rx_jumbo_pending || 1458 ering->tx_pending < TX_BD_NUM_MIN || 1459 ering->tx_pending > TX_BD_NUM_MAX) 1460 return -EINVAL; 1461 1462 if (netif_running(ndev)) 1463 return -EBUSY; 1464 1465 lp->rx_bd_num = ering->rx_pending; 1466 lp->tx_bd_num = ering->tx_pending; 1467 return 0; 1468 } 1469 1470 /** 1471 * axienet_ethtools_get_pauseparam - Get the pause parameter setting for 1472 * Tx and Rx paths. 1473 * @ndev: Pointer to net_device structure 1474 * @epauseparm: Pointer to ethtool_pauseparam structure. 1475 * 1476 * This implements ethtool command for getting axi ethernet pause frame 1477 * setting. Issue "ethtool -a ethX" to execute this function. 1478 */ 1479 static void 1480 axienet_ethtools_get_pauseparam(struct net_device *ndev, 1481 struct ethtool_pauseparam *epauseparm) 1482 { 1483 struct axienet_local *lp = netdev_priv(ndev); 1484 1485 phylink_ethtool_get_pauseparam(lp->phylink, epauseparm); 1486 } 1487 1488 /** 1489 * axienet_ethtools_set_pauseparam - Set device pause parameter(flow control) 1490 * settings. 1491 * @ndev: Pointer to net_device structure 1492 * @epauseparm:Pointer to ethtool_pauseparam structure 1493 * 1494 * This implements ethtool command for enabling flow control on Rx and Tx 1495 * paths. Issue "ethtool -A ethX tx on|off" under linux prompt to execute this 1496 * function. 1497 * 1498 * Return: 0 on success, -EFAULT if device is running 1499 */ 1500 static int 1501 axienet_ethtools_set_pauseparam(struct net_device *ndev, 1502 struct ethtool_pauseparam *epauseparm) 1503 { 1504 struct axienet_local *lp = netdev_priv(ndev); 1505 1506 return phylink_ethtool_set_pauseparam(lp->phylink, epauseparm); 1507 } 1508 1509 /** 1510 * axienet_ethtools_get_coalesce - Get DMA interrupt coalescing count. 1511 * @ndev: Pointer to net_device structure 1512 * @ecoalesce: Pointer to ethtool_coalesce structure 1513 * @kernel_coal: ethtool CQE mode setting structure 1514 * @extack: extack for reporting error messages 1515 * 1516 * This implements ethtool command for getting the DMA interrupt coalescing 1517 * count on Tx and Rx paths. Issue "ethtool -c ethX" under linux prompt to 1518 * execute this function. 1519 * 1520 * Return: 0 always 1521 */ 1522 static int 1523 axienet_ethtools_get_coalesce(struct net_device *ndev, 1524 struct ethtool_coalesce *ecoalesce, 1525 struct kernel_ethtool_coalesce *kernel_coal, 1526 struct netlink_ext_ack *extack) 1527 { 1528 struct axienet_local *lp = netdev_priv(ndev); 1529 1530 ecoalesce->rx_max_coalesced_frames = lp->coalesce_count_rx; 1531 ecoalesce->rx_coalesce_usecs = lp->coalesce_usec_rx; 1532 ecoalesce->tx_max_coalesced_frames = lp->coalesce_count_tx; 1533 ecoalesce->tx_coalesce_usecs = lp->coalesce_usec_tx; 1534 return 0; 1535 } 1536 1537 /** 1538 * axienet_ethtools_set_coalesce - Set DMA interrupt coalescing count. 1539 * @ndev: Pointer to net_device structure 1540 * @ecoalesce: Pointer to ethtool_coalesce structure 1541 * @kernel_coal: ethtool CQE mode setting structure 1542 * @extack: extack for reporting error messages 1543 * 1544 * This implements ethtool command for setting the DMA interrupt coalescing 1545 * count on Tx and Rx paths. Issue "ethtool -C ethX rx-frames 5" under linux 1546 * prompt to execute this function. 1547 * 1548 * Return: 0, on success, Non-zero error value on failure. 1549 */ 1550 static int 1551 axienet_ethtools_set_coalesce(struct net_device *ndev, 1552 struct ethtool_coalesce *ecoalesce, 1553 struct kernel_ethtool_coalesce *kernel_coal, 1554 struct netlink_ext_ack *extack) 1555 { 1556 struct axienet_local *lp = netdev_priv(ndev); 1557 1558 if (netif_running(ndev)) { 1559 netdev_err(ndev, 1560 "Please stop netif before applying configuration\n"); 1561 return -EFAULT; 1562 } 1563 1564 if (ecoalesce->rx_max_coalesced_frames) 1565 lp->coalesce_count_rx = ecoalesce->rx_max_coalesced_frames; 1566 if (ecoalesce->rx_coalesce_usecs) 1567 lp->coalesce_usec_rx = ecoalesce->rx_coalesce_usecs; 1568 if (ecoalesce->tx_max_coalesced_frames) 1569 lp->coalesce_count_tx = ecoalesce->tx_max_coalesced_frames; 1570 if (ecoalesce->tx_coalesce_usecs) 1571 lp->coalesce_usec_tx = ecoalesce->tx_coalesce_usecs; 1572 1573 return 0; 1574 } 1575 1576 static int 1577 axienet_ethtools_get_link_ksettings(struct net_device *ndev, 1578 struct ethtool_link_ksettings *cmd) 1579 { 1580 struct axienet_local *lp = netdev_priv(ndev); 1581 1582 return phylink_ethtool_ksettings_get(lp->phylink, cmd); 1583 } 1584 1585 static int 1586 axienet_ethtools_set_link_ksettings(struct net_device *ndev, 1587 const struct ethtool_link_ksettings *cmd) 1588 { 1589 struct axienet_local *lp = netdev_priv(ndev); 1590 1591 return phylink_ethtool_ksettings_set(lp->phylink, cmd); 1592 } 1593 1594 static int axienet_ethtools_nway_reset(struct net_device *dev) 1595 { 1596 struct axienet_local *lp = netdev_priv(dev); 1597 1598 return phylink_ethtool_nway_reset(lp->phylink); 1599 } 1600 1601 static const struct ethtool_ops axienet_ethtool_ops = { 1602 .supported_coalesce_params = ETHTOOL_COALESCE_MAX_FRAMES | 1603 ETHTOOL_COALESCE_USECS, 1604 .get_drvinfo = axienet_ethtools_get_drvinfo, 1605 .get_regs_len = axienet_ethtools_get_regs_len, 1606 .get_regs = axienet_ethtools_get_regs, 1607 .get_link = ethtool_op_get_link, 1608 .get_ringparam = axienet_ethtools_get_ringparam, 1609 .set_ringparam = axienet_ethtools_set_ringparam, 1610 .get_pauseparam = axienet_ethtools_get_pauseparam, 1611 .set_pauseparam = axienet_ethtools_set_pauseparam, 1612 .get_coalesce = axienet_ethtools_get_coalesce, 1613 .set_coalesce = axienet_ethtools_set_coalesce, 1614 .get_link_ksettings = axienet_ethtools_get_link_ksettings, 1615 .set_link_ksettings = axienet_ethtools_set_link_ksettings, 1616 .nway_reset = axienet_ethtools_nway_reset, 1617 }; 1618 1619 static struct axienet_local *pcs_to_axienet_local(struct phylink_pcs *pcs) 1620 { 1621 return container_of(pcs, struct axienet_local, pcs); 1622 } 1623 1624 static void axienet_pcs_get_state(struct phylink_pcs *pcs, 1625 struct phylink_link_state *state) 1626 { 1627 struct mdio_device *pcs_phy = pcs_to_axienet_local(pcs)->pcs_phy; 1628 1629 phylink_mii_c22_pcs_get_state(pcs_phy, state); 1630 } 1631 1632 static void axienet_pcs_an_restart(struct phylink_pcs *pcs) 1633 { 1634 struct mdio_device *pcs_phy = pcs_to_axienet_local(pcs)->pcs_phy; 1635 1636 phylink_mii_c22_pcs_an_restart(pcs_phy); 1637 } 1638 1639 static int axienet_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode, 1640 phy_interface_t interface, 1641 const unsigned long *advertising, 1642 bool permit_pause_to_mac) 1643 { 1644 struct mdio_device *pcs_phy = pcs_to_axienet_local(pcs)->pcs_phy; 1645 struct net_device *ndev = pcs_to_axienet_local(pcs)->ndev; 1646 struct axienet_local *lp = netdev_priv(ndev); 1647 int ret; 1648 1649 if (lp->switch_x_sgmii) { 1650 ret = mdiodev_write(pcs_phy, XLNX_MII_STD_SELECT_REG, 1651 interface == PHY_INTERFACE_MODE_SGMII ? 1652 XLNX_MII_STD_SELECT_SGMII : 0); 1653 if (ret < 0) { 1654 netdev_warn(ndev, 1655 "Failed to switch PHY interface: %d\n", 1656 ret); 1657 return ret; 1658 } 1659 } 1660 1661 ret = phylink_mii_c22_pcs_config(pcs_phy, interface, advertising, 1662 neg_mode); 1663 if (ret < 0) 1664 netdev_warn(ndev, "Failed to configure PCS: %d\n", ret); 1665 1666 return ret; 1667 } 1668 1669 static const struct phylink_pcs_ops axienet_pcs_ops = { 1670 .pcs_get_state = axienet_pcs_get_state, 1671 .pcs_config = axienet_pcs_config, 1672 .pcs_an_restart = axienet_pcs_an_restart, 1673 }; 1674 1675 static struct phylink_pcs *axienet_mac_select_pcs(struct phylink_config *config, 1676 phy_interface_t interface) 1677 { 1678 struct net_device *ndev = to_net_dev(config->dev); 1679 struct axienet_local *lp = netdev_priv(ndev); 1680 1681 if (interface == PHY_INTERFACE_MODE_1000BASEX || 1682 interface == PHY_INTERFACE_MODE_SGMII) 1683 return &lp->pcs; 1684 1685 return NULL; 1686 } 1687 1688 static void axienet_mac_config(struct phylink_config *config, unsigned int mode, 1689 const struct phylink_link_state *state) 1690 { 1691 /* nothing meaningful to do */ 1692 } 1693 1694 static void axienet_mac_link_down(struct phylink_config *config, 1695 unsigned int mode, 1696 phy_interface_t interface) 1697 { 1698 /* nothing meaningful to do */ 1699 } 1700 1701 static void axienet_mac_link_up(struct phylink_config *config, 1702 struct phy_device *phy, 1703 unsigned int mode, phy_interface_t interface, 1704 int speed, int duplex, 1705 bool tx_pause, bool rx_pause) 1706 { 1707 struct net_device *ndev = to_net_dev(config->dev); 1708 struct axienet_local *lp = netdev_priv(ndev); 1709 u32 emmc_reg, fcc_reg; 1710 1711 emmc_reg = axienet_ior(lp, XAE_EMMC_OFFSET); 1712 emmc_reg &= ~XAE_EMMC_LINKSPEED_MASK; 1713 1714 switch (speed) { 1715 case SPEED_1000: 1716 emmc_reg |= XAE_EMMC_LINKSPD_1000; 1717 break; 1718 case SPEED_100: 1719 emmc_reg |= XAE_EMMC_LINKSPD_100; 1720 break; 1721 case SPEED_10: 1722 emmc_reg |= XAE_EMMC_LINKSPD_10; 1723 break; 1724 default: 1725 dev_err(&ndev->dev, 1726 "Speed other than 10, 100 or 1Gbps is not supported\n"); 1727 break; 1728 } 1729 1730 axienet_iow(lp, XAE_EMMC_OFFSET, emmc_reg); 1731 1732 fcc_reg = axienet_ior(lp, XAE_FCC_OFFSET); 1733 if (tx_pause) 1734 fcc_reg |= XAE_FCC_FCTX_MASK; 1735 else 1736 fcc_reg &= ~XAE_FCC_FCTX_MASK; 1737 if (rx_pause) 1738 fcc_reg |= XAE_FCC_FCRX_MASK; 1739 else 1740 fcc_reg &= ~XAE_FCC_FCRX_MASK; 1741 axienet_iow(lp, XAE_FCC_OFFSET, fcc_reg); 1742 } 1743 1744 static const struct phylink_mac_ops axienet_phylink_ops = { 1745 .mac_select_pcs = axienet_mac_select_pcs, 1746 .mac_config = axienet_mac_config, 1747 .mac_link_down = axienet_mac_link_down, 1748 .mac_link_up = axienet_mac_link_up, 1749 }; 1750 1751 /** 1752 * axienet_dma_err_handler - Work queue task for Axi DMA Error 1753 * @work: pointer to work_struct 1754 * 1755 * Resets the Axi DMA and Axi Ethernet devices, and reconfigures the 1756 * Tx/Rx BDs. 1757 */ 1758 static void axienet_dma_err_handler(struct work_struct *work) 1759 { 1760 u32 i; 1761 u32 axienet_status; 1762 struct axidma_bd *cur_p; 1763 struct axienet_local *lp = container_of(work, struct axienet_local, 1764 dma_err_task); 1765 struct net_device *ndev = lp->ndev; 1766 1767 napi_disable(&lp->napi_tx); 1768 napi_disable(&lp->napi_rx); 1769 1770 axienet_setoptions(ndev, lp->options & 1771 ~(XAE_OPTION_TXEN | XAE_OPTION_RXEN)); 1772 1773 axienet_dma_stop(lp); 1774 1775 for (i = 0; i < lp->tx_bd_num; i++) { 1776 cur_p = &lp->tx_bd_v[i]; 1777 if (cur_p->cntrl) { 1778 dma_addr_t addr = desc_get_phys_addr(lp, cur_p); 1779 1780 dma_unmap_single(lp->dev, addr, 1781 (cur_p->cntrl & 1782 XAXIDMA_BD_CTRL_LENGTH_MASK), 1783 DMA_TO_DEVICE); 1784 } 1785 if (cur_p->skb) 1786 dev_kfree_skb_irq(cur_p->skb); 1787 cur_p->phys = 0; 1788 cur_p->phys_msb = 0; 1789 cur_p->cntrl = 0; 1790 cur_p->status = 0; 1791 cur_p->app0 = 0; 1792 cur_p->app1 = 0; 1793 cur_p->app2 = 0; 1794 cur_p->app3 = 0; 1795 cur_p->app4 = 0; 1796 cur_p->skb = NULL; 1797 } 1798 1799 for (i = 0; i < lp->rx_bd_num; i++) { 1800 cur_p = &lp->rx_bd_v[i]; 1801 cur_p->status = 0; 1802 cur_p->app0 = 0; 1803 cur_p->app1 = 0; 1804 cur_p->app2 = 0; 1805 cur_p->app3 = 0; 1806 cur_p->app4 = 0; 1807 } 1808 1809 lp->tx_bd_ci = 0; 1810 lp->tx_bd_tail = 0; 1811 lp->rx_bd_ci = 0; 1812 1813 axienet_dma_start(lp); 1814 1815 axienet_status = axienet_ior(lp, XAE_RCW1_OFFSET); 1816 axienet_status &= ~XAE_RCW1_RX_MASK; 1817 axienet_iow(lp, XAE_RCW1_OFFSET, axienet_status); 1818 1819 axienet_status = axienet_ior(lp, XAE_IP_OFFSET); 1820 if (axienet_status & XAE_INT_RXRJECT_MASK) 1821 axienet_iow(lp, XAE_IS_OFFSET, XAE_INT_RXRJECT_MASK); 1822 axienet_iow(lp, XAE_IE_OFFSET, lp->eth_irq > 0 ? 1823 XAE_INT_RECV_ERROR_MASK : 0); 1824 axienet_iow(lp, XAE_FCC_OFFSET, XAE_FCC_FCRX_MASK); 1825 1826 /* Sync default options with HW but leave receiver and 1827 * transmitter disabled. 1828 */ 1829 axienet_setoptions(ndev, lp->options & 1830 ~(XAE_OPTION_TXEN | XAE_OPTION_RXEN)); 1831 axienet_set_mac_address(ndev, NULL); 1832 axienet_set_multicast_list(ndev); 1833 napi_enable(&lp->napi_rx); 1834 napi_enable(&lp->napi_tx); 1835 axienet_setoptions(ndev, lp->options); 1836 } 1837 1838 /** 1839 * axienet_probe - Axi Ethernet probe function. 1840 * @pdev: Pointer to platform device structure. 1841 * 1842 * Return: 0, on success 1843 * Non-zero error value on failure. 1844 * 1845 * This is the probe routine for Axi Ethernet driver. This is called before 1846 * any other driver routines are invoked. It allocates and sets up the Ethernet 1847 * device. Parses through device tree and populates fields of 1848 * axienet_local. It registers the Ethernet device. 1849 */ 1850 static int axienet_probe(struct platform_device *pdev) 1851 { 1852 int ret; 1853 struct device_node *np; 1854 struct axienet_local *lp; 1855 struct net_device *ndev; 1856 struct resource *ethres; 1857 u8 mac_addr[ETH_ALEN]; 1858 int addr_width = 32; 1859 u32 value; 1860 1861 ndev = alloc_etherdev(sizeof(*lp)); 1862 if (!ndev) 1863 return -ENOMEM; 1864 1865 platform_set_drvdata(pdev, ndev); 1866 1867 SET_NETDEV_DEV(ndev, &pdev->dev); 1868 ndev->flags &= ~IFF_MULTICAST; /* clear multicast */ 1869 ndev->features = NETIF_F_SG; 1870 ndev->netdev_ops = &axienet_netdev_ops; 1871 ndev->ethtool_ops = &axienet_ethtool_ops; 1872 1873 /* MTU range: 64 - 9000 */ 1874 ndev->min_mtu = 64; 1875 ndev->max_mtu = XAE_JUMBO_MTU; 1876 1877 lp = netdev_priv(ndev); 1878 lp->ndev = ndev; 1879 lp->dev = &pdev->dev; 1880 lp->options = XAE_OPTION_DEFAULTS; 1881 lp->rx_bd_num = RX_BD_NUM_DEFAULT; 1882 lp->tx_bd_num = TX_BD_NUM_DEFAULT; 1883 1884 u64_stats_init(&lp->rx_stat_sync); 1885 u64_stats_init(&lp->tx_stat_sync); 1886 1887 netif_napi_add(ndev, &lp->napi_rx, axienet_rx_poll); 1888 netif_napi_add(ndev, &lp->napi_tx, axienet_tx_poll); 1889 1890 lp->axi_clk = devm_clk_get_optional(&pdev->dev, "s_axi_lite_clk"); 1891 if (!lp->axi_clk) { 1892 /* For backward compatibility, if named AXI clock is not present, 1893 * treat the first clock specified as the AXI clock. 1894 */ 1895 lp->axi_clk = devm_clk_get_optional(&pdev->dev, NULL); 1896 } 1897 if (IS_ERR(lp->axi_clk)) { 1898 ret = PTR_ERR(lp->axi_clk); 1899 goto free_netdev; 1900 } 1901 ret = clk_prepare_enable(lp->axi_clk); 1902 if (ret) { 1903 dev_err(&pdev->dev, "Unable to enable AXI clock: %d\n", ret); 1904 goto free_netdev; 1905 } 1906 1907 lp->misc_clks[0].id = "axis_clk"; 1908 lp->misc_clks[1].id = "ref_clk"; 1909 lp->misc_clks[2].id = "mgt_clk"; 1910 1911 ret = devm_clk_bulk_get_optional(&pdev->dev, XAE_NUM_MISC_CLOCKS, lp->misc_clks); 1912 if (ret) 1913 goto cleanup_clk; 1914 1915 ret = clk_bulk_prepare_enable(XAE_NUM_MISC_CLOCKS, lp->misc_clks); 1916 if (ret) 1917 goto cleanup_clk; 1918 1919 /* Map device registers */ 1920 lp->regs = devm_platform_get_and_ioremap_resource(pdev, 0, ðres); 1921 if (IS_ERR(lp->regs)) { 1922 ret = PTR_ERR(lp->regs); 1923 goto cleanup_clk; 1924 } 1925 lp->regs_start = ethres->start; 1926 1927 /* Setup checksum offload, but default to off if not specified */ 1928 lp->features = 0; 1929 1930 ret = of_property_read_u32(pdev->dev.of_node, "xlnx,txcsum", &value); 1931 if (!ret) { 1932 switch (value) { 1933 case 1: 1934 lp->csum_offload_on_tx_path = 1935 XAE_FEATURE_PARTIAL_TX_CSUM; 1936 lp->features |= XAE_FEATURE_PARTIAL_TX_CSUM; 1937 /* Can checksum TCP/UDP over IPv4. */ 1938 ndev->features |= NETIF_F_IP_CSUM; 1939 break; 1940 case 2: 1941 lp->csum_offload_on_tx_path = 1942 XAE_FEATURE_FULL_TX_CSUM; 1943 lp->features |= XAE_FEATURE_FULL_TX_CSUM; 1944 /* Can checksum TCP/UDP over IPv4. */ 1945 ndev->features |= NETIF_F_IP_CSUM; 1946 break; 1947 default: 1948 lp->csum_offload_on_tx_path = XAE_NO_CSUM_OFFLOAD; 1949 } 1950 } 1951 ret = of_property_read_u32(pdev->dev.of_node, "xlnx,rxcsum", &value); 1952 if (!ret) { 1953 switch (value) { 1954 case 1: 1955 lp->csum_offload_on_rx_path = 1956 XAE_FEATURE_PARTIAL_RX_CSUM; 1957 lp->features |= XAE_FEATURE_PARTIAL_RX_CSUM; 1958 break; 1959 case 2: 1960 lp->csum_offload_on_rx_path = 1961 XAE_FEATURE_FULL_RX_CSUM; 1962 lp->features |= XAE_FEATURE_FULL_RX_CSUM; 1963 break; 1964 default: 1965 lp->csum_offload_on_rx_path = XAE_NO_CSUM_OFFLOAD; 1966 } 1967 } 1968 /* For supporting jumbo frames, the Axi Ethernet hardware must have 1969 * a larger Rx/Tx Memory. Typically, the size must be large so that 1970 * we can enable jumbo option and start supporting jumbo frames. 1971 * Here we check for memory allocated for Rx/Tx in the hardware from 1972 * the device-tree and accordingly set flags. 1973 */ 1974 of_property_read_u32(pdev->dev.of_node, "xlnx,rxmem", &lp->rxmem); 1975 1976 lp->switch_x_sgmii = of_property_read_bool(pdev->dev.of_node, 1977 "xlnx,switch-x-sgmii"); 1978 1979 /* Start with the proprietary, and broken phy_type */ 1980 ret = of_property_read_u32(pdev->dev.of_node, "xlnx,phy-type", &value); 1981 if (!ret) { 1982 netdev_warn(ndev, "Please upgrade your device tree binary blob to use phy-mode"); 1983 switch (value) { 1984 case XAE_PHY_TYPE_MII: 1985 lp->phy_mode = PHY_INTERFACE_MODE_MII; 1986 break; 1987 case XAE_PHY_TYPE_GMII: 1988 lp->phy_mode = PHY_INTERFACE_MODE_GMII; 1989 break; 1990 case XAE_PHY_TYPE_RGMII_2_0: 1991 lp->phy_mode = PHY_INTERFACE_MODE_RGMII_ID; 1992 break; 1993 case XAE_PHY_TYPE_SGMII: 1994 lp->phy_mode = PHY_INTERFACE_MODE_SGMII; 1995 break; 1996 case XAE_PHY_TYPE_1000BASE_X: 1997 lp->phy_mode = PHY_INTERFACE_MODE_1000BASEX; 1998 break; 1999 default: 2000 ret = -EINVAL; 2001 goto cleanup_clk; 2002 } 2003 } else { 2004 ret = of_get_phy_mode(pdev->dev.of_node, &lp->phy_mode); 2005 if (ret) 2006 goto cleanup_clk; 2007 } 2008 if (lp->switch_x_sgmii && lp->phy_mode != PHY_INTERFACE_MODE_SGMII && 2009 lp->phy_mode != PHY_INTERFACE_MODE_1000BASEX) { 2010 dev_err(&pdev->dev, "xlnx,switch-x-sgmii only supported with SGMII or 1000BaseX\n"); 2011 ret = -EINVAL; 2012 goto cleanup_clk; 2013 } 2014 2015 /* Find the DMA node, map the DMA registers, and decode the DMA IRQs */ 2016 np = of_parse_phandle(pdev->dev.of_node, "axistream-connected", 0); 2017 if (np) { 2018 struct resource dmares; 2019 2020 ret = of_address_to_resource(np, 0, &dmares); 2021 if (ret) { 2022 dev_err(&pdev->dev, 2023 "unable to get DMA resource\n"); 2024 of_node_put(np); 2025 goto cleanup_clk; 2026 } 2027 lp->dma_regs = devm_ioremap_resource(&pdev->dev, 2028 &dmares); 2029 lp->rx_irq = irq_of_parse_and_map(np, 1); 2030 lp->tx_irq = irq_of_parse_and_map(np, 0); 2031 of_node_put(np); 2032 lp->eth_irq = platform_get_irq_optional(pdev, 0); 2033 } else { 2034 /* Check for these resources directly on the Ethernet node. */ 2035 lp->dma_regs = devm_platform_get_and_ioremap_resource(pdev, 1, NULL); 2036 lp->rx_irq = platform_get_irq(pdev, 1); 2037 lp->tx_irq = platform_get_irq(pdev, 0); 2038 lp->eth_irq = platform_get_irq_optional(pdev, 2); 2039 } 2040 if (IS_ERR(lp->dma_regs)) { 2041 dev_err(&pdev->dev, "could not map DMA regs\n"); 2042 ret = PTR_ERR(lp->dma_regs); 2043 goto cleanup_clk; 2044 } 2045 if ((lp->rx_irq <= 0) || (lp->tx_irq <= 0)) { 2046 dev_err(&pdev->dev, "could not determine irqs\n"); 2047 ret = -ENOMEM; 2048 goto cleanup_clk; 2049 } 2050 2051 /* Reset core now that clocks are enabled, prior to accessing MDIO */ 2052 ret = __axienet_device_reset(lp); 2053 if (ret) 2054 goto cleanup_clk; 2055 2056 /* Autodetect the need for 64-bit DMA pointers. 2057 * When the IP is configured for a bus width bigger than 32 bits, 2058 * writing the MSB registers is mandatory, even if they are all 0. 2059 * We can detect this case by writing all 1's to one such register 2060 * and see if that sticks: when the IP is configured for 32 bits 2061 * only, those registers are RES0. 2062 * Those MSB registers were introduced in IP v7.1, which we check first. 2063 */ 2064 if ((axienet_ior(lp, XAE_ID_OFFSET) >> 24) >= 0x9) { 2065 void __iomem *desc = lp->dma_regs + XAXIDMA_TX_CDESC_OFFSET + 4; 2066 2067 iowrite32(0x0, desc); 2068 if (ioread32(desc) == 0) { /* sanity check */ 2069 iowrite32(0xffffffff, desc); 2070 if (ioread32(desc) > 0) { 2071 lp->features |= XAE_FEATURE_DMA_64BIT; 2072 addr_width = 64; 2073 dev_info(&pdev->dev, 2074 "autodetected 64-bit DMA range\n"); 2075 } 2076 iowrite32(0x0, desc); 2077 } 2078 } 2079 if (!IS_ENABLED(CONFIG_64BIT) && lp->features & XAE_FEATURE_DMA_64BIT) { 2080 dev_err(&pdev->dev, "64-bit addressable DMA is not compatible with 32-bit archecture\n"); 2081 ret = -EINVAL; 2082 goto cleanup_clk; 2083 } 2084 2085 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(addr_width)); 2086 if (ret) { 2087 dev_err(&pdev->dev, "No suitable DMA available\n"); 2088 goto cleanup_clk; 2089 } 2090 2091 /* Check for Ethernet core IRQ (optional) */ 2092 if (lp->eth_irq <= 0) 2093 dev_info(&pdev->dev, "Ethernet core IRQ not defined\n"); 2094 2095 /* Retrieve the MAC address */ 2096 ret = of_get_mac_address(pdev->dev.of_node, mac_addr); 2097 if (!ret) { 2098 axienet_set_mac_address(ndev, mac_addr); 2099 } else { 2100 dev_warn(&pdev->dev, "could not find MAC address property: %d\n", 2101 ret); 2102 axienet_set_mac_address(ndev, NULL); 2103 } 2104 2105 lp->coalesce_count_rx = XAXIDMA_DFT_RX_THRESHOLD; 2106 lp->coalesce_usec_rx = XAXIDMA_DFT_RX_USEC; 2107 lp->coalesce_count_tx = XAXIDMA_DFT_TX_THRESHOLD; 2108 lp->coalesce_usec_tx = XAXIDMA_DFT_TX_USEC; 2109 2110 ret = axienet_mdio_setup(lp); 2111 if (ret) 2112 dev_warn(&pdev->dev, 2113 "error registering MDIO bus: %d\n", ret); 2114 2115 if (lp->phy_mode == PHY_INTERFACE_MODE_SGMII || 2116 lp->phy_mode == PHY_INTERFACE_MODE_1000BASEX) { 2117 np = of_parse_phandle(pdev->dev.of_node, "pcs-handle", 0); 2118 if (!np) { 2119 /* Deprecated: Always use "pcs-handle" for pcs_phy. 2120 * Falling back to "phy-handle" here is only for 2121 * backward compatibility with old device trees. 2122 */ 2123 np = of_parse_phandle(pdev->dev.of_node, "phy-handle", 0); 2124 } 2125 if (!np) { 2126 dev_err(&pdev->dev, "pcs-handle (preferred) or phy-handle required for 1000BaseX/SGMII\n"); 2127 ret = -EINVAL; 2128 goto cleanup_mdio; 2129 } 2130 lp->pcs_phy = of_mdio_find_device(np); 2131 if (!lp->pcs_phy) { 2132 ret = -EPROBE_DEFER; 2133 of_node_put(np); 2134 goto cleanup_mdio; 2135 } 2136 of_node_put(np); 2137 lp->pcs.ops = &axienet_pcs_ops; 2138 lp->pcs.neg_mode = true; 2139 lp->pcs.poll = true; 2140 } 2141 2142 lp->phylink_config.dev = &ndev->dev; 2143 lp->phylink_config.type = PHYLINK_NETDEV; 2144 lp->phylink_config.mac_capabilities = MAC_SYM_PAUSE | MAC_ASYM_PAUSE | 2145 MAC_10FD | MAC_100FD | MAC_1000FD; 2146 2147 __set_bit(lp->phy_mode, lp->phylink_config.supported_interfaces); 2148 if (lp->switch_x_sgmii) { 2149 __set_bit(PHY_INTERFACE_MODE_1000BASEX, 2150 lp->phylink_config.supported_interfaces); 2151 __set_bit(PHY_INTERFACE_MODE_SGMII, 2152 lp->phylink_config.supported_interfaces); 2153 } 2154 2155 lp->phylink = phylink_create(&lp->phylink_config, pdev->dev.fwnode, 2156 lp->phy_mode, 2157 &axienet_phylink_ops); 2158 if (IS_ERR(lp->phylink)) { 2159 ret = PTR_ERR(lp->phylink); 2160 dev_err(&pdev->dev, "phylink_create error (%i)\n", ret); 2161 goto cleanup_mdio; 2162 } 2163 2164 ret = register_netdev(lp->ndev); 2165 if (ret) { 2166 dev_err(lp->dev, "register_netdev() error (%i)\n", ret); 2167 goto cleanup_phylink; 2168 } 2169 2170 return 0; 2171 2172 cleanup_phylink: 2173 phylink_destroy(lp->phylink); 2174 2175 cleanup_mdio: 2176 if (lp->pcs_phy) 2177 put_device(&lp->pcs_phy->dev); 2178 if (lp->mii_bus) 2179 axienet_mdio_teardown(lp); 2180 cleanup_clk: 2181 clk_bulk_disable_unprepare(XAE_NUM_MISC_CLOCKS, lp->misc_clks); 2182 clk_disable_unprepare(lp->axi_clk); 2183 2184 free_netdev: 2185 free_netdev(ndev); 2186 2187 return ret; 2188 } 2189 2190 static int axienet_remove(struct platform_device *pdev) 2191 { 2192 struct net_device *ndev = platform_get_drvdata(pdev); 2193 struct axienet_local *lp = netdev_priv(ndev); 2194 2195 unregister_netdev(ndev); 2196 2197 if (lp->phylink) 2198 phylink_destroy(lp->phylink); 2199 2200 if (lp->pcs_phy) 2201 put_device(&lp->pcs_phy->dev); 2202 2203 axienet_mdio_teardown(lp); 2204 2205 clk_bulk_disable_unprepare(XAE_NUM_MISC_CLOCKS, lp->misc_clks); 2206 clk_disable_unprepare(lp->axi_clk); 2207 2208 free_netdev(ndev); 2209 2210 return 0; 2211 } 2212 2213 static void axienet_shutdown(struct platform_device *pdev) 2214 { 2215 struct net_device *ndev = platform_get_drvdata(pdev); 2216 2217 rtnl_lock(); 2218 netif_device_detach(ndev); 2219 2220 if (netif_running(ndev)) 2221 dev_close(ndev); 2222 2223 rtnl_unlock(); 2224 } 2225 2226 static int axienet_suspend(struct device *dev) 2227 { 2228 struct net_device *ndev = dev_get_drvdata(dev); 2229 2230 if (!netif_running(ndev)) 2231 return 0; 2232 2233 netif_device_detach(ndev); 2234 2235 rtnl_lock(); 2236 axienet_stop(ndev); 2237 rtnl_unlock(); 2238 2239 return 0; 2240 } 2241 2242 static int axienet_resume(struct device *dev) 2243 { 2244 struct net_device *ndev = dev_get_drvdata(dev); 2245 2246 if (!netif_running(ndev)) 2247 return 0; 2248 2249 rtnl_lock(); 2250 axienet_open(ndev); 2251 rtnl_unlock(); 2252 2253 netif_device_attach(ndev); 2254 2255 return 0; 2256 } 2257 2258 static DEFINE_SIMPLE_DEV_PM_OPS(axienet_pm_ops, 2259 axienet_suspend, axienet_resume); 2260 2261 static struct platform_driver axienet_driver = { 2262 .probe = axienet_probe, 2263 .remove = axienet_remove, 2264 .shutdown = axienet_shutdown, 2265 .driver = { 2266 .name = "xilinx_axienet", 2267 .pm = &axienet_pm_ops, 2268 .of_match_table = axienet_of_match, 2269 }, 2270 }; 2271 2272 module_platform_driver(axienet_driver); 2273 2274 MODULE_DESCRIPTION("Xilinx Axi Ethernet driver"); 2275 MODULE_AUTHOR("Xilinx"); 2276 MODULE_LICENSE("GPL"); 2277