1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2015 - 2023 Beijing WangXun Technology Co., Ltd. */ 3 4 #include <linux/gpio/machine.h> 5 #include <linux/gpio/driver.h> 6 #include <linux/gpio/property.h> 7 #include <linux/clk-provider.h> 8 #include <linux/clkdev.h> 9 #include <linux/i2c.h> 10 #include <linux/pci.h> 11 #include <linux/platform_device.h> 12 #include <linux/regmap.h> 13 #include <linux/pcs/pcs-xpcs.h> 14 15 #include "../libwx/wx_type.h" 16 #include "../libwx/wx_hw.h" 17 #include "txgbe_type.h" 18 #include "txgbe_phy.h" 19 20 static int txgbe_swnodes_register(struct txgbe *txgbe) 21 { 22 struct txgbe_nodes *nodes = &txgbe->nodes; 23 struct pci_dev *pdev = txgbe->wx->pdev; 24 struct software_node *swnodes; 25 u32 id; 26 27 id = (pdev->bus->number << 8) | pdev->devfn; 28 29 snprintf(nodes->gpio_name, sizeof(nodes->gpio_name), "txgbe_gpio-%x", id); 30 snprintf(nodes->i2c_name, sizeof(nodes->i2c_name), "txgbe_i2c-%x", id); 31 snprintf(nodes->sfp_name, sizeof(nodes->sfp_name), "txgbe_sfp-%x", id); 32 snprintf(nodes->phylink_name, sizeof(nodes->phylink_name), "txgbe_phylink-%x", id); 33 34 swnodes = nodes->swnodes; 35 36 /* GPIO 0: tx fault 37 * GPIO 1: tx disable 38 * GPIO 2: sfp module absent 39 * GPIO 3: rx signal lost 40 * GPIO 4: rate select, 1G(0) 10G(1) 41 * GPIO 5: rate select, 1G(0) 10G(1) 42 */ 43 nodes->gpio_props[0] = PROPERTY_ENTRY_STRING("pinctrl-names", "default"); 44 swnodes[SWNODE_GPIO] = NODE_PROP(nodes->gpio_name, nodes->gpio_props); 45 nodes->gpio0_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_GPIO], 0, GPIO_ACTIVE_HIGH); 46 nodes->gpio1_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_GPIO], 1, GPIO_ACTIVE_HIGH); 47 nodes->gpio2_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_GPIO], 2, GPIO_ACTIVE_LOW); 48 nodes->gpio3_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_GPIO], 3, GPIO_ACTIVE_HIGH); 49 nodes->gpio4_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_GPIO], 4, GPIO_ACTIVE_HIGH); 50 nodes->gpio5_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_GPIO], 5, GPIO_ACTIVE_HIGH); 51 52 nodes->i2c_props[0] = PROPERTY_ENTRY_STRING("compatible", "snps,designware-i2c"); 53 nodes->i2c_props[1] = PROPERTY_ENTRY_BOOL("wx,i2c-snps-model"); 54 nodes->i2c_props[2] = PROPERTY_ENTRY_U32("clock-frequency", I2C_MAX_STANDARD_MODE_FREQ); 55 swnodes[SWNODE_I2C] = NODE_PROP(nodes->i2c_name, nodes->i2c_props); 56 nodes->i2c_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_I2C]); 57 58 nodes->sfp_props[0] = PROPERTY_ENTRY_STRING("compatible", "sff,sfp"); 59 nodes->sfp_props[1] = PROPERTY_ENTRY_REF_ARRAY("i2c-bus", nodes->i2c_ref); 60 nodes->sfp_props[2] = PROPERTY_ENTRY_REF_ARRAY("tx-fault-gpios", nodes->gpio0_ref); 61 nodes->sfp_props[3] = PROPERTY_ENTRY_REF_ARRAY("tx-disable-gpios", nodes->gpio1_ref); 62 nodes->sfp_props[4] = PROPERTY_ENTRY_REF_ARRAY("mod-def0-gpios", nodes->gpio2_ref); 63 nodes->sfp_props[5] = PROPERTY_ENTRY_REF_ARRAY("los-gpios", nodes->gpio3_ref); 64 nodes->sfp_props[6] = PROPERTY_ENTRY_REF_ARRAY("rate-select1-gpios", nodes->gpio4_ref); 65 nodes->sfp_props[7] = PROPERTY_ENTRY_REF_ARRAY("rate-select0-gpios", nodes->gpio5_ref); 66 swnodes[SWNODE_SFP] = NODE_PROP(nodes->sfp_name, nodes->sfp_props); 67 nodes->sfp_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_SFP]); 68 69 nodes->phylink_props[0] = PROPERTY_ENTRY_STRING("managed", "in-band-status"); 70 nodes->phylink_props[1] = PROPERTY_ENTRY_REF_ARRAY("sfp", nodes->sfp_ref); 71 swnodes[SWNODE_PHYLINK] = NODE_PROP(nodes->phylink_name, nodes->phylink_props); 72 73 nodes->group[SWNODE_GPIO] = &swnodes[SWNODE_GPIO]; 74 nodes->group[SWNODE_I2C] = &swnodes[SWNODE_I2C]; 75 nodes->group[SWNODE_SFP] = &swnodes[SWNODE_SFP]; 76 nodes->group[SWNODE_PHYLINK] = &swnodes[SWNODE_PHYLINK]; 77 78 return software_node_register_node_group(nodes->group); 79 } 80 81 static int txgbe_pcs_read(struct mii_bus *bus, int addr, int devnum, int regnum) 82 { 83 struct wx *wx = bus->priv; 84 u32 offset, val; 85 86 if (addr) 87 return -EOPNOTSUPP; 88 89 offset = devnum << 16 | regnum; 90 91 /* Set the LAN port indicator to IDA_ADDR */ 92 wr32(wx, TXGBE_XPCS_IDA_ADDR, offset); 93 94 /* Read the data from IDA_DATA register */ 95 val = rd32(wx, TXGBE_XPCS_IDA_DATA); 96 97 return (u16)val; 98 } 99 100 static int txgbe_pcs_write(struct mii_bus *bus, int addr, int devnum, int regnum, u16 val) 101 { 102 struct wx *wx = bus->priv; 103 u32 offset; 104 105 if (addr) 106 return -EOPNOTSUPP; 107 108 offset = devnum << 16 | regnum; 109 110 /* Set the LAN port indicator to IDA_ADDR */ 111 wr32(wx, TXGBE_XPCS_IDA_ADDR, offset); 112 113 /* Write the data to IDA_DATA register */ 114 wr32(wx, TXGBE_XPCS_IDA_DATA, val); 115 116 return 0; 117 } 118 119 static int txgbe_mdio_pcs_init(struct txgbe *txgbe) 120 { 121 struct mii_bus *mii_bus; 122 struct dw_xpcs *xpcs; 123 struct pci_dev *pdev; 124 struct wx *wx; 125 int ret = 0; 126 127 wx = txgbe->wx; 128 pdev = wx->pdev; 129 130 mii_bus = devm_mdiobus_alloc(&pdev->dev); 131 if (!mii_bus) 132 return -ENOMEM; 133 134 mii_bus->name = "txgbe_pcs_mdio_bus"; 135 mii_bus->read_c45 = &txgbe_pcs_read; 136 mii_bus->write_c45 = &txgbe_pcs_write; 137 mii_bus->parent = &pdev->dev; 138 mii_bus->phy_mask = ~0; 139 mii_bus->priv = wx; 140 snprintf(mii_bus->id, MII_BUS_ID_SIZE, "txgbe_pcs-%x", 141 (pdev->bus->number << 8) | pdev->devfn); 142 143 ret = devm_mdiobus_register(&pdev->dev, mii_bus); 144 if (ret) 145 return ret; 146 147 xpcs = xpcs_create_mdiodev(mii_bus, 0, PHY_INTERFACE_MODE_10GBASER); 148 if (IS_ERR(xpcs)) 149 return PTR_ERR(xpcs); 150 151 txgbe->xpcs = xpcs; 152 153 return 0; 154 } 155 156 static int txgbe_gpio_get(struct gpio_chip *chip, unsigned int offset) 157 { 158 struct wx *wx = gpiochip_get_data(chip); 159 int val; 160 161 val = rd32m(wx, WX_GPIO_EXT, BIT(offset)); 162 163 return !!(val & BIT(offset)); 164 } 165 166 static int txgbe_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) 167 { 168 struct wx *wx = gpiochip_get_data(chip); 169 u32 val; 170 171 val = rd32(wx, WX_GPIO_DDR); 172 if (BIT(offset) & val) 173 return GPIO_LINE_DIRECTION_OUT; 174 175 return GPIO_LINE_DIRECTION_IN; 176 } 177 178 static int txgbe_gpio_direction_in(struct gpio_chip *chip, unsigned int offset) 179 { 180 struct wx *wx = gpiochip_get_data(chip); 181 unsigned long flags; 182 183 raw_spin_lock_irqsave(&wx->gpio_lock, flags); 184 wr32m(wx, WX_GPIO_DDR, BIT(offset), 0); 185 raw_spin_unlock_irqrestore(&wx->gpio_lock, flags); 186 187 return 0; 188 } 189 190 static int txgbe_gpio_direction_out(struct gpio_chip *chip, unsigned int offset, 191 int val) 192 { 193 struct wx *wx = gpiochip_get_data(chip); 194 unsigned long flags; 195 u32 set; 196 197 set = val ? BIT(offset) : 0; 198 199 raw_spin_lock_irqsave(&wx->gpio_lock, flags); 200 wr32m(wx, WX_GPIO_DR, BIT(offset), set); 201 wr32m(wx, WX_GPIO_DDR, BIT(offset), BIT(offset)); 202 raw_spin_unlock_irqrestore(&wx->gpio_lock, flags); 203 204 return 0; 205 } 206 207 static void txgbe_gpio_irq_ack(struct irq_data *d) 208 { 209 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 210 irq_hw_number_t hwirq = irqd_to_hwirq(d); 211 struct wx *wx = gpiochip_get_data(gc); 212 unsigned long flags; 213 214 raw_spin_lock_irqsave(&wx->gpio_lock, flags); 215 wr32(wx, WX_GPIO_EOI, BIT(hwirq)); 216 raw_spin_unlock_irqrestore(&wx->gpio_lock, flags); 217 } 218 219 static void txgbe_gpio_irq_mask(struct irq_data *d) 220 { 221 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 222 irq_hw_number_t hwirq = irqd_to_hwirq(d); 223 struct wx *wx = gpiochip_get_data(gc); 224 unsigned long flags; 225 226 gpiochip_disable_irq(gc, hwirq); 227 228 raw_spin_lock_irqsave(&wx->gpio_lock, flags); 229 wr32m(wx, WX_GPIO_INTMASK, BIT(hwirq), BIT(hwirq)); 230 raw_spin_unlock_irqrestore(&wx->gpio_lock, flags); 231 } 232 233 static void txgbe_gpio_irq_unmask(struct irq_data *d) 234 { 235 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 236 irq_hw_number_t hwirq = irqd_to_hwirq(d); 237 struct wx *wx = gpiochip_get_data(gc); 238 unsigned long flags; 239 240 gpiochip_enable_irq(gc, hwirq); 241 242 raw_spin_lock_irqsave(&wx->gpio_lock, flags); 243 wr32m(wx, WX_GPIO_INTMASK, BIT(hwirq), 0); 244 raw_spin_unlock_irqrestore(&wx->gpio_lock, flags); 245 } 246 247 static void txgbe_toggle_trigger(struct gpio_chip *gc, unsigned int offset) 248 { 249 struct wx *wx = gpiochip_get_data(gc); 250 u32 pol, val; 251 252 pol = rd32(wx, WX_GPIO_POLARITY); 253 val = rd32(wx, WX_GPIO_EXT); 254 255 if (val & BIT(offset)) 256 pol &= ~BIT(offset); 257 else 258 pol |= BIT(offset); 259 260 wr32(wx, WX_GPIO_POLARITY, pol); 261 } 262 263 static int txgbe_gpio_set_type(struct irq_data *d, unsigned int type) 264 { 265 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 266 irq_hw_number_t hwirq = irqd_to_hwirq(d); 267 struct wx *wx = gpiochip_get_data(gc); 268 u32 level, polarity, mask; 269 unsigned long flags; 270 271 mask = BIT(hwirq); 272 273 if (type & IRQ_TYPE_LEVEL_MASK) { 274 level = 0; 275 irq_set_handler_locked(d, handle_level_irq); 276 } else { 277 level = mask; 278 irq_set_handler_locked(d, handle_edge_irq); 279 } 280 281 if (type == IRQ_TYPE_EDGE_RISING || type == IRQ_TYPE_LEVEL_HIGH) 282 polarity = mask; 283 else 284 polarity = 0; 285 286 raw_spin_lock_irqsave(&wx->gpio_lock, flags); 287 288 wr32m(wx, WX_GPIO_INTEN, mask, mask); 289 wr32m(wx, WX_GPIO_INTTYPE_LEVEL, mask, level); 290 if (type == IRQ_TYPE_EDGE_BOTH) 291 txgbe_toggle_trigger(gc, hwirq); 292 else 293 wr32m(wx, WX_GPIO_POLARITY, mask, polarity); 294 295 raw_spin_unlock_irqrestore(&wx->gpio_lock, flags); 296 297 return 0; 298 } 299 300 static const struct irq_chip txgbe_gpio_irq_chip = { 301 .name = "txgbe_gpio_irq", 302 .irq_ack = txgbe_gpio_irq_ack, 303 .irq_mask = txgbe_gpio_irq_mask, 304 .irq_unmask = txgbe_gpio_irq_unmask, 305 .irq_set_type = txgbe_gpio_set_type, 306 .flags = IRQCHIP_IMMUTABLE, 307 GPIOCHIP_IRQ_RESOURCE_HELPERS, 308 }; 309 310 static void txgbe_irq_handler(struct irq_desc *desc) 311 { 312 struct irq_chip *chip = irq_desc_get_chip(desc); 313 struct wx *wx = irq_desc_get_handler_data(desc); 314 struct txgbe *txgbe = wx->priv; 315 irq_hw_number_t hwirq; 316 unsigned long gpioirq; 317 struct gpio_chip *gc; 318 unsigned long flags; 319 320 chained_irq_enter(chip, desc); 321 322 gpioirq = rd32(wx, WX_GPIO_INTSTATUS); 323 324 gc = txgbe->gpio; 325 for_each_set_bit(hwirq, &gpioirq, gc->ngpio) { 326 int gpio = irq_find_mapping(gc->irq.domain, hwirq); 327 u32 irq_type = irq_get_trigger_type(gpio); 328 329 generic_handle_domain_irq(gc->irq.domain, hwirq); 330 331 if ((irq_type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) { 332 raw_spin_lock_irqsave(&wx->gpio_lock, flags); 333 txgbe_toggle_trigger(gc, hwirq); 334 raw_spin_unlock_irqrestore(&wx->gpio_lock, flags); 335 } 336 } 337 338 chained_irq_exit(chip, desc); 339 340 /* unmask interrupt */ 341 wx_intr_enable(wx, TXGBE_INTR_MISC(wx)); 342 } 343 344 static int txgbe_gpio_init(struct txgbe *txgbe) 345 { 346 struct gpio_irq_chip *girq; 347 struct gpio_chip *gc; 348 struct device *dev; 349 struct wx *wx; 350 int ret; 351 352 wx = txgbe->wx; 353 dev = &wx->pdev->dev; 354 355 raw_spin_lock_init(&wx->gpio_lock); 356 357 gc = devm_kzalloc(dev, sizeof(*gc), GFP_KERNEL); 358 if (!gc) 359 return -ENOMEM; 360 361 gc->label = devm_kasprintf(dev, GFP_KERNEL, "txgbe_gpio-%x", 362 (wx->pdev->bus->number << 8) | wx->pdev->devfn); 363 if (!gc->label) 364 return -ENOMEM; 365 366 gc->base = -1; 367 gc->ngpio = 6; 368 gc->owner = THIS_MODULE; 369 gc->parent = dev; 370 gc->fwnode = software_node_fwnode(txgbe->nodes.group[SWNODE_GPIO]); 371 gc->get = txgbe_gpio_get; 372 gc->get_direction = txgbe_gpio_get_direction; 373 gc->direction_input = txgbe_gpio_direction_in; 374 gc->direction_output = txgbe_gpio_direction_out; 375 376 girq = &gc->irq; 377 gpio_irq_chip_set_chip(girq, &txgbe_gpio_irq_chip); 378 girq->parent_handler = txgbe_irq_handler; 379 girq->parent_handler_data = wx; 380 girq->num_parents = 1; 381 girq->parents = devm_kcalloc(dev, girq->num_parents, 382 sizeof(*girq->parents), GFP_KERNEL); 383 if (!girq->parents) 384 return -ENOMEM; 385 girq->parents[0] = wx->msix_entries[wx->num_q_vectors].vector; 386 girq->default_type = IRQ_TYPE_NONE; 387 girq->handler = handle_bad_irq; 388 389 ret = devm_gpiochip_add_data(dev, gc, wx); 390 if (ret) 391 return ret; 392 393 txgbe->gpio = gc; 394 395 return 0; 396 } 397 398 static int txgbe_clock_register(struct txgbe *txgbe) 399 { 400 struct pci_dev *pdev = txgbe->wx->pdev; 401 struct clk_lookup *clock; 402 char clk_name[32]; 403 struct clk *clk; 404 405 snprintf(clk_name, sizeof(clk_name), "i2c_designware.%d", 406 (pdev->bus->number << 8) | pdev->devfn); 407 408 clk = clk_register_fixed_rate(NULL, clk_name, NULL, 0, 156250000); 409 if (IS_ERR(clk)) 410 return PTR_ERR(clk); 411 412 clock = clkdev_create(clk, NULL, clk_name); 413 if (!clock) { 414 clk_unregister(clk); 415 return -ENOMEM; 416 } 417 418 txgbe->clk = clk; 419 txgbe->clock = clock; 420 421 return 0; 422 } 423 424 static int txgbe_i2c_read(void *context, unsigned int reg, unsigned int *val) 425 { 426 struct wx *wx = context; 427 428 *val = rd32(wx, reg + TXGBE_I2C_BASE); 429 430 return 0; 431 } 432 433 static int txgbe_i2c_write(void *context, unsigned int reg, unsigned int val) 434 { 435 struct wx *wx = context; 436 437 wr32(wx, reg + TXGBE_I2C_BASE, val); 438 439 return 0; 440 } 441 442 static const struct regmap_config i2c_regmap_config = { 443 .reg_bits = 32, 444 .val_bits = 32, 445 .reg_read = txgbe_i2c_read, 446 .reg_write = txgbe_i2c_write, 447 .fast_io = true, 448 }; 449 450 static int txgbe_i2c_register(struct txgbe *txgbe) 451 { 452 struct platform_device_info info = {}; 453 struct platform_device *i2c_dev; 454 struct regmap *i2c_regmap; 455 struct pci_dev *pdev; 456 struct wx *wx; 457 458 wx = txgbe->wx; 459 pdev = wx->pdev; 460 i2c_regmap = devm_regmap_init(&pdev->dev, NULL, wx, &i2c_regmap_config); 461 if (IS_ERR(i2c_regmap)) { 462 wx_err(wx, "failed to init I2C regmap\n"); 463 return PTR_ERR(i2c_regmap); 464 } 465 466 info.parent = &pdev->dev; 467 info.fwnode = software_node_fwnode(txgbe->nodes.group[SWNODE_I2C]); 468 info.name = "i2c_designware"; 469 info.id = (pdev->bus->number << 8) | pdev->devfn; 470 471 info.res = &DEFINE_RES_IRQ(pdev->irq); 472 info.num_res = 1; 473 i2c_dev = platform_device_register_full(&info); 474 if (IS_ERR(i2c_dev)) 475 return PTR_ERR(i2c_dev); 476 477 txgbe->i2c_dev = i2c_dev; 478 479 return 0; 480 } 481 482 static int txgbe_sfp_register(struct txgbe *txgbe) 483 { 484 struct pci_dev *pdev = txgbe->wx->pdev; 485 struct platform_device_info info = {}; 486 struct platform_device *sfp_dev; 487 488 info.parent = &pdev->dev; 489 info.fwnode = software_node_fwnode(txgbe->nodes.group[SWNODE_SFP]); 490 info.name = "sfp"; 491 info.id = (pdev->bus->number << 8) | pdev->devfn; 492 sfp_dev = platform_device_register_full(&info); 493 if (IS_ERR(sfp_dev)) 494 return PTR_ERR(sfp_dev); 495 496 txgbe->sfp_dev = sfp_dev; 497 498 return 0; 499 } 500 501 int txgbe_init_phy(struct txgbe *txgbe) 502 { 503 int ret; 504 505 ret = txgbe_swnodes_register(txgbe); 506 if (ret) { 507 wx_err(txgbe->wx, "failed to register software nodes\n"); 508 return ret; 509 } 510 511 ret = txgbe_mdio_pcs_init(txgbe); 512 if (ret) { 513 wx_err(txgbe->wx, "failed to init mdio pcs: %d\n", ret); 514 goto err_unregister_swnode; 515 } 516 517 ret = txgbe_gpio_init(txgbe); 518 if (ret) { 519 wx_err(txgbe->wx, "failed to init gpio\n"); 520 goto err_destroy_xpcs; 521 } 522 523 ret = txgbe_clock_register(txgbe); 524 if (ret) { 525 wx_err(txgbe->wx, "failed to register clock: %d\n", ret); 526 goto err_destroy_xpcs; 527 } 528 529 ret = txgbe_i2c_register(txgbe); 530 if (ret) { 531 wx_err(txgbe->wx, "failed to init i2c interface: %d\n", ret); 532 goto err_unregister_clk; 533 } 534 535 ret = txgbe_sfp_register(txgbe); 536 if (ret) { 537 wx_err(txgbe->wx, "failed to register sfp\n"); 538 goto err_unregister_i2c; 539 } 540 541 return 0; 542 543 err_unregister_i2c: 544 platform_device_unregister(txgbe->i2c_dev); 545 err_unregister_clk: 546 clkdev_drop(txgbe->clock); 547 clk_unregister(txgbe->clk); 548 err_destroy_xpcs: 549 xpcs_destroy(txgbe->xpcs); 550 err_unregister_swnode: 551 software_node_unregister_node_group(txgbe->nodes.group); 552 553 return ret; 554 } 555 556 void txgbe_remove_phy(struct txgbe *txgbe) 557 { 558 platform_device_unregister(txgbe->sfp_dev); 559 platform_device_unregister(txgbe->i2c_dev); 560 clkdev_drop(txgbe->clock); 561 clk_unregister(txgbe->clk); 562 xpcs_destroy(txgbe->xpcs); 563 software_node_unregister_node_group(txgbe->nodes.group); 564 } 565