1*a71a18f2SGrygorii Strashko /* SPDX-License-Identifier: GPL-2.0 */ 2*a71a18f2SGrygorii Strashko /* 3*a71a18f2SGrygorii Strashko * Texas Instruments Ethernet Switch media-access-controller (MAC) submodule/ 4*a71a18f2SGrygorii Strashko * Ethernet MAC Sliver (CPGMAC_SL) APIs 5*a71a18f2SGrygorii Strashko * 6*a71a18f2SGrygorii Strashko * Copyright (C) 2019 Texas Instruments 7*a71a18f2SGrygorii Strashko * 8*a71a18f2SGrygorii Strashko */ 9*a71a18f2SGrygorii Strashko 10*a71a18f2SGrygorii Strashko #ifndef __TI_CPSW_SL_H__ 11*a71a18f2SGrygorii Strashko #define __TI_CPSW_SL_H__ 12*a71a18f2SGrygorii Strashko 13*a71a18f2SGrygorii Strashko #include <linux/device.h> 14*a71a18f2SGrygorii Strashko 15*a71a18f2SGrygorii Strashko enum cpsw_sl_regs { 16*a71a18f2SGrygorii Strashko CPSW_SL_IDVER, 17*a71a18f2SGrygorii Strashko CPSW_SL_MACCONTROL, 18*a71a18f2SGrygorii Strashko CPSW_SL_MACSTATUS, 19*a71a18f2SGrygorii Strashko CPSW_SL_SOFT_RESET, 20*a71a18f2SGrygorii Strashko CPSW_SL_RX_MAXLEN, 21*a71a18f2SGrygorii Strashko CPSW_SL_BOFFTEST, 22*a71a18f2SGrygorii Strashko CPSW_SL_RX_PAUSE, 23*a71a18f2SGrygorii Strashko CPSW_SL_TX_PAUSE, 24*a71a18f2SGrygorii Strashko CPSW_SL_EMCONTROL, 25*a71a18f2SGrygorii Strashko CPSW_SL_RX_PRI_MAP, 26*a71a18f2SGrygorii Strashko CPSW_SL_TX_GAP, 27*a71a18f2SGrygorii Strashko }; 28*a71a18f2SGrygorii Strashko 29*a71a18f2SGrygorii Strashko enum { 30*a71a18f2SGrygorii Strashko CPSW_SL_CTL_FULLDUPLEX = BIT(0), /* Full Duplex mode */ 31*a71a18f2SGrygorii Strashko CPSW_SL_CTL_LOOPBACK = BIT(1), /* Loop Back Mode */ 32*a71a18f2SGrygorii Strashko CPSW_SL_CTL_MTEST = BIT(2), /* Manufacturing Test mode */ 33*a71a18f2SGrygorii Strashko CPSW_SL_CTL_RX_FLOW_EN = BIT(3), /* Receive Flow Control Enable */ 34*a71a18f2SGrygorii Strashko CPSW_SL_CTL_TX_FLOW_EN = BIT(4), /* Transmit Flow Control Enable */ 35*a71a18f2SGrygorii Strashko CPSW_SL_CTL_GMII_EN = BIT(5), /* GMII Enable */ 36*a71a18f2SGrygorii Strashko CPSW_SL_CTL_TX_PACE = BIT(6), /* Transmit Pacing Enable */ 37*a71a18f2SGrygorii Strashko CPSW_SL_CTL_GIG = BIT(7), /* Gigabit Mode */ 38*a71a18f2SGrygorii Strashko CPSW_SL_CTL_XGIG = BIT(8), /* 10 Gigabit Mode */ 39*a71a18f2SGrygorii Strashko CPSW_SL_CTL_TX_SHORT_GAP_EN = BIT(10), /* Transmit Short Gap Enable */ 40*a71a18f2SGrygorii Strashko CPSW_SL_CTL_CMD_IDLE = BIT(11), /* Command Idle */ 41*a71a18f2SGrygorii Strashko CPSW_SL_CTL_CRC_TYPE = BIT(12), /* Port CRC Type */ 42*a71a18f2SGrygorii Strashko CPSW_SL_CTL_XGMII_EN = BIT(13), /* XGMII Enable */ 43*a71a18f2SGrygorii Strashko CPSW_SL_CTL_IFCTL_A = BIT(15), /* Interface Control A */ 44*a71a18f2SGrygorii Strashko CPSW_SL_CTL_IFCTL_B = BIT(16), /* Interface Control B */ 45*a71a18f2SGrygorii Strashko CPSW_SL_CTL_GIG_FORCE = BIT(17), /* Gigabit Mode Force */ 46*a71a18f2SGrygorii Strashko CPSW_SL_CTL_EXT_EN = BIT(18), /* External Control Enable */ 47*a71a18f2SGrygorii Strashko CPSW_SL_CTL_EXT_EN_RX_FLO = BIT(19), /* Ext RX Flow Control Enable */ 48*a71a18f2SGrygorii Strashko CPSW_SL_CTL_EXT_EN_TX_FLO = BIT(20), /* Ext TX Flow Control Enable */ 49*a71a18f2SGrygorii Strashko CPSW_SL_CTL_TX_SG_LIM_EN = BIT(21), /* TXt Short Gap Limit Enable */ 50*a71a18f2SGrygorii Strashko CPSW_SL_CTL_RX_CEF_EN = BIT(22), /* RX Copy Error Frames Enable */ 51*a71a18f2SGrygorii Strashko CPSW_SL_CTL_RX_CSF_EN = BIT(23), /* RX Copy Short Frames Enable */ 52*a71a18f2SGrygorii Strashko CPSW_SL_CTL_RX_CMF_EN = BIT(24), /* RX Copy MAC Control Frames Enable */ 53*a71a18f2SGrygorii Strashko CPSW_SL_CTL_EXT_EN_XGIG = BIT(25), /* Ext XGIG Control En, k3 only */ 54*a71a18f2SGrygorii Strashko 55*a71a18f2SGrygorii Strashko CPSW_SL_CTL_FUNCS_COUNT 56*a71a18f2SGrygorii Strashko }; 57*a71a18f2SGrygorii Strashko 58*a71a18f2SGrygorii Strashko struct cpsw_sl; 59*a71a18f2SGrygorii Strashko 60*a71a18f2SGrygorii Strashko struct cpsw_sl *cpsw_sl_get(const char *device_id, struct device *dev, 61*a71a18f2SGrygorii Strashko void __iomem *sl_base); 62*a71a18f2SGrygorii Strashko 63*a71a18f2SGrygorii Strashko void cpsw_sl_reset(struct cpsw_sl *sl, unsigned long tmo); 64*a71a18f2SGrygorii Strashko 65*a71a18f2SGrygorii Strashko u32 cpsw_sl_ctl_set(struct cpsw_sl *sl, u32 ctl_funcs); 66*a71a18f2SGrygorii Strashko u32 cpsw_sl_ctl_clr(struct cpsw_sl *sl, u32 ctl_funcs); 67*a71a18f2SGrygorii Strashko void cpsw_sl_ctl_reset(struct cpsw_sl *sl); 68*a71a18f2SGrygorii Strashko int cpsw_sl_wait_for_idle(struct cpsw_sl *sl, unsigned long tmo); 69*a71a18f2SGrygorii Strashko 70*a71a18f2SGrygorii Strashko u32 cpsw_sl_reg_read(struct cpsw_sl *sl, enum cpsw_sl_regs reg); 71*a71a18f2SGrygorii Strashko void cpsw_sl_reg_write(struct cpsw_sl *sl, enum cpsw_sl_regs reg, u32 val); 72*a71a18f2SGrygorii Strashko 73*a71a18f2SGrygorii Strashko #endif /* __TI_CPSW_SL_H__ */ 74