1 // SPDX-License-Identifier: GPL-2.0 2 /* Texas Instruments K3 AM65 Ethernet Switch SubSystem Driver 3 * 4 * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ 5 * 6 */ 7 8 #include <linux/etherdevice.h> 9 #include <linux/if_vlan.h> 10 #include <linux/interrupt.h> 11 #include <linux/kernel.h> 12 #include <linux/kmemleak.h> 13 #include <linux/module.h> 14 #include <linux/netdevice.h> 15 #include <linux/net_tstamp.h> 16 #include <linux/of.h> 17 #include <linux/of_mdio.h> 18 #include <linux/of_net.h> 19 #include <linux/of_device.h> 20 #include <linux/phy.h> 21 #include <linux/phy/phy.h> 22 #include <linux/platform_device.h> 23 #include <linux/pm_runtime.h> 24 #include <linux/regmap.h> 25 #include <linux/mfd/syscon.h> 26 #include <linux/dma/ti-cppi5.h> 27 #include <linux/dma/k3-udma-glue.h> 28 29 #include "cpsw_ale.h" 30 #include "cpsw_sl.h" 31 #include "am65-cpsw-nuss.h" 32 #include "k3-cppi-desc-pool.h" 33 #include "am65-cpts.h" 34 35 #define AM65_CPSW_SS_BASE 0x0 36 #define AM65_CPSW_SGMII_BASE 0x100 37 #define AM65_CPSW_XGMII_BASE 0x2100 38 #define AM65_CPSW_CPSW_NU_BASE 0x20000 39 #define AM65_CPSW_NU_PORTS_BASE 0x1000 40 #define AM65_CPSW_NU_FRAM_BASE 0x12000 41 #define AM65_CPSW_NU_STATS_BASE 0x1a000 42 #define AM65_CPSW_NU_ALE_BASE 0x1e000 43 #define AM65_CPSW_NU_CPTS_BASE 0x1d000 44 45 #define AM65_CPSW_NU_PORTS_OFFSET 0x1000 46 #define AM65_CPSW_NU_STATS_PORT_OFFSET 0x200 47 #define AM65_CPSW_NU_FRAM_PORT_OFFSET 0x200 48 49 #define AM65_CPSW_MAX_PORTS 8 50 51 #define AM65_CPSW_MIN_PACKET_SIZE VLAN_ETH_ZLEN 52 #define AM65_CPSW_MAX_PACKET_SIZE (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN) 53 54 #define AM65_CPSW_REG_CTL 0x004 55 #define AM65_CPSW_REG_STAT_PORT_EN 0x014 56 #define AM65_CPSW_REG_PTYPE 0x018 57 58 #define AM65_CPSW_P0_REG_CTL 0x004 59 #define AM65_CPSW_PORT0_REG_FLOW_ID_OFFSET 0x008 60 61 #define AM65_CPSW_PORT_REG_PRI_CTL 0x01c 62 #define AM65_CPSW_PORT_REG_RX_PRI_MAP 0x020 63 #define AM65_CPSW_PORT_REG_RX_MAXLEN 0x024 64 65 #define AM65_CPSW_PORTN_REG_SA_L 0x308 66 #define AM65_CPSW_PORTN_REG_SA_H 0x30c 67 #define AM65_CPSW_PORTN_REG_TS_CTL 0x310 68 #define AM65_CPSW_PORTN_REG_TS_SEQ_LTYPE_REG 0x314 69 #define AM65_CPSW_PORTN_REG_TS_VLAN_LTYPE_REG 0x318 70 #define AM65_CPSW_PORTN_REG_TS_CTL_LTYPE2 0x31C 71 72 #define AM65_CPSW_CTL_VLAN_AWARE BIT(1) 73 #define AM65_CPSW_CTL_P0_ENABLE BIT(2) 74 #define AM65_CPSW_CTL_P0_TX_CRC_REMOVE BIT(13) 75 #define AM65_CPSW_CTL_P0_RX_PAD BIT(14) 76 77 /* AM65_CPSW_P0_REG_CTL */ 78 #define AM65_CPSW_P0_REG_CTL_RX_CHECKSUM_EN BIT(0) 79 80 /* AM65_CPSW_PORT_REG_PRI_CTL */ 81 #define AM65_CPSW_PORT_REG_PRI_CTL_RX_PTYPE_RROBIN BIT(8) 82 83 /* AM65_CPSW_PN_TS_CTL register fields */ 84 #define AM65_CPSW_PN_TS_CTL_TX_ANX_F_EN BIT(4) 85 #define AM65_CPSW_PN_TS_CTL_TX_VLAN_LT1_EN BIT(5) 86 #define AM65_CPSW_PN_TS_CTL_TX_VLAN_LT2_EN BIT(6) 87 #define AM65_CPSW_PN_TS_CTL_TX_ANX_D_EN BIT(7) 88 #define AM65_CPSW_PN_TS_CTL_TX_ANX_E_EN BIT(10) 89 #define AM65_CPSW_PN_TS_CTL_TX_HOST_TS_EN BIT(11) 90 #define AM65_CPSW_PN_TS_CTL_MSG_TYPE_EN_SHIFT 16 91 92 /* AM65_CPSW_PORTN_REG_TS_SEQ_LTYPE_REG register fields */ 93 #define AM65_CPSW_PN_TS_SEQ_ID_OFFSET_SHIFT 16 94 95 /* AM65_CPSW_PORTN_REG_TS_CTL_LTYPE2 */ 96 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_107 BIT(16) 97 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_129 BIT(17) 98 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_130 BIT(18) 99 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_131 BIT(19) 100 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_132 BIT(20) 101 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_319 BIT(21) 102 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_320 BIT(22) 103 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_TTL_NONZERO BIT(23) 104 105 /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */ 106 #define AM65_CPSW_TS_EVENT_MSG_TYPE_BITS (BIT(0) | BIT(1) | BIT(2) | BIT(3)) 107 108 #define AM65_CPSW_TS_SEQ_ID_OFFSET (0x1e) 109 110 #define AM65_CPSW_TS_TX_ANX_ALL_EN \ 111 (AM65_CPSW_PN_TS_CTL_TX_ANX_D_EN | \ 112 AM65_CPSW_PN_TS_CTL_TX_ANX_E_EN | \ 113 AM65_CPSW_PN_TS_CTL_TX_ANX_F_EN) 114 115 #define AM65_CPSW_ALE_AGEOUT_DEFAULT 30 116 /* Number of TX/RX descriptors */ 117 #define AM65_CPSW_MAX_TX_DESC 500 118 #define AM65_CPSW_MAX_RX_DESC 500 119 120 #define AM65_CPSW_NAV_PS_DATA_SIZE 16 121 #define AM65_CPSW_NAV_SW_DATA_SIZE 16 122 123 #define AM65_CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_DRV | NETIF_MSG_LINK | \ 124 NETIF_MSG_IFUP | NETIF_MSG_PROBE | NETIF_MSG_IFDOWN | \ 125 NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR) 126 127 static void am65_cpsw_port_set_sl_mac(struct am65_cpsw_port *slave, 128 const u8 *dev_addr) 129 { 130 u32 mac_hi = (dev_addr[0] << 0) | (dev_addr[1] << 8) | 131 (dev_addr[2] << 16) | (dev_addr[3] << 24); 132 u32 mac_lo = (dev_addr[4] << 0) | (dev_addr[5] << 8); 133 134 writel(mac_hi, slave->port_base + AM65_CPSW_PORTN_REG_SA_H); 135 writel(mac_lo, slave->port_base + AM65_CPSW_PORTN_REG_SA_L); 136 } 137 138 static void am65_cpsw_sl_ctl_reset(struct am65_cpsw_port *port) 139 { 140 cpsw_sl_reset(port->slave.mac_sl, 100); 141 /* Max length register has to be restored after MAC SL reset */ 142 writel(AM65_CPSW_MAX_PACKET_SIZE, 143 port->port_base + AM65_CPSW_PORT_REG_RX_MAXLEN); 144 } 145 146 static void am65_cpsw_nuss_get_ver(struct am65_cpsw_common *common) 147 { 148 common->nuss_ver = readl(common->ss_base); 149 common->cpsw_ver = readl(common->cpsw_base); 150 dev_info(common->dev, 151 "initializing am65 cpsw nuss version 0x%08X, cpsw version 0x%08X Ports: %u\n", 152 common->nuss_ver, 153 common->cpsw_ver, 154 common->port_num + 1); 155 } 156 157 void am65_cpsw_nuss_adjust_link(struct net_device *ndev) 158 { 159 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 160 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 161 struct phy_device *phy = port->slave.phy; 162 u32 mac_control = 0; 163 164 if (!phy) 165 return; 166 167 if (phy->link) { 168 mac_control = CPSW_SL_CTL_GMII_EN; 169 170 if (phy->speed == 1000) 171 mac_control |= CPSW_SL_CTL_GIG; 172 if (phy->speed == 10 && phy_interface_is_rgmii(phy)) 173 /* Can be used with in band mode only */ 174 mac_control |= CPSW_SL_CTL_EXT_EN; 175 if (phy->duplex) 176 mac_control |= CPSW_SL_CTL_FULLDUPLEX; 177 178 /* RGMII speed is 100M if !CPSW_SL_CTL_GIG*/ 179 180 /* rx_pause/tx_pause */ 181 if (port->slave.rx_pause) 182 mac_control |= CPSW_SL_CTL_RX_FLOW_EN; 183 184 if (port->slave.tx_pause) 185 mac_control |= CPSW_SL_CTL_TX_FLOW_EN; 186 187 cpsw_sl_ctl_set(port->slave.mac_sl, mac_control); 188 189 /* enable forwarding */ 190 cpsw_ale_control_set(common->ale, port->port_id, 191 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); 192 193 am65_cpsw_qos_link_up(ndev, phy->speed); 194 netif_tx_wake_all_queues(ndev); 195 } else { 196 int tmo; 197 198 /* disable forwarding */ 199 cpsw_ale_control_set(common->ale, port->port_id, 200 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 201 202 cpsw_sl_ctl_set(port->slave.mac_sl, CPSW_SL_CTL_CMD_IDLE); 203 204 tmo = cpsw_sl_wait_for_idle(port->slave.mac_sl, 100); 205 dev_dbg(common->dev, "donw msc_sl %08x tmo %d\n", 206 cpsw_sl_reg_read(port->slave.mac_sl, CPSW_SL_MACSTATUS), 207 tmo); 208 209 cpsw_sl_ctl_reset(port->slave.mac_sl); 210 211 am65_cpsw_qos_link_down(ndev); 212 netif_tx_stop_all_queues(ndev); 213 } 214 215 phy_print_status(phy); 216 } 217 218 static int am65_cpsw_nuss_ndo_slave_add_vid(struct net_device *ndev, 219 __be16 proto, u16 vid) 220 { 221 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 222 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 223 u32 port_mask, unreg_mcast = 0; 224 int ret; 225 226 if (!netif_running(ndev) || !vid) 227 return 0; 228 229 ret = pm_runtime_get_sync(common->dev); 230 if (ret < 0) { 231 pm_runtime_put_noidle(common->dev); 232 return ret; 233 } 234 235 port_mask = BIT(port->port_id) | ALE_PORT_HOST; 236 if (!vid) 237 unreg_mcast = port_mask; 238 dev_info(common->dev, "Adding vlan %d to vlan filter\n", vid); 239 ret = cpsw_ale_add_vlan(common->ale, vid, port_mask, 240 unreg_mcast, port_mask, 0); 241 242 pm_runtime_put(common->dev); 243 return ret; 244 } 245 246 static int am65_cpsw_nuss_ndo_slave_kill_vid(struct net_device *ndev, 247 __be16 proto, u16 vid) 248 { 249 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 250 int ret; 251 252 if (!netif_running(ndev) || !vid) 253 return 0; 254 255 ret = pm_runtime_get_sync(common->dev); 256 if (ret < 0) { 257 pm_runtime_put_noidle(common->dev); 258 return ret; 259 } 260 261 dev_info(common->dev, "Removing vlan %d from vlan filter\n", vid); 262 ret = cpsw_ale_del_vlan(common->ale, vid, 0); 263 264 pm_runtime_put(common->dev); 265 return ret; 266 } 267 268 static void am65_cpsw_slave_set_promisc_2g(struct am65_cpsw_port *port, 269 bool promisc) 270 { 271 struct am65_cpsw_common *common = port->common; 272 273 if (promisc) { 274 /* Enable promiscuous mode */ 275 cpsw_ale_control_set(common->ale, port->port_id, 276 ALE_PORT_MACONLY_CAF, 1); 277 dev_dbg(common->dev, "promisc enabled\n"); 278 } else { 279 /* Disable promiscuous mode */ 280 cpsw_ale_control_set(common->ale, port->port_id, 281 ALE_PORT_MACONLY_CAF, 0); 282 dev_dbg(common->dev, "promisc disabled\n"); 283 } 284 } 285 286 static void am65_cpsw_nuss_ndo_slave_set_rx_mode(struct net_device *ndev) 287 { 288 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 289 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 290 u32 port_mask; 291 bool promisc; 292 293 promisc = !!(ndev->flags & IFF_PROMISC); 294 am65_cpsw_slave_set_promisc_2g(port, promisc); 295 296 if (promisc) 297 return; 298 299 /* Restore allmulti on vlans if necessary */ 300 cpsw_ale_set_allmulti(common->ale, 301 ndev->flags & IFF_ALLMULTI, port->port_id); 302 303 port_mask = ALE_PORT_HOST; 304 /* Clear all mcast from ALE */ 305 cpsw_ale_flush_multicast(common->ale, port_mask, -1); 306 307 if (!netdev_mc_empty(ndev)) { 308 struct netdev_hw_addr *ha; 309 310 /* program multicast address list into ALE register */ 311 netdev_for_each_mc_addr(ha, ndev) { 312 cpsw_ale_add_mcast(common->ale, ha->addr, 313 port_mask, 0, 0, 0); 314 } 315 } 316 } 317 318 static void am65_cpsw_nuss_ndo_host_tx_timeout(struct net_device *ndev, 319 unsigned int txqueue) 320 { 321 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 322 struct am65_cpsw_tx_chn *tx_chn; 323 struct netdev_queue *netif_txq; 324 unsigned long trans_start; 325 326 netif_txq = netdev_get_tx_queue(ndev, txqueue); 327 tx_chn = &common->tx_chns[txqueue]; 328 trans_start = netif_txq->trans_start; 329 330 netdev_err(ndev, "txq:%d DRV_XOFF:%d tmo:%u dql_avail:%d free_desc:%zu\n", 331 txqueue, 332 netif_tx_queue_stopped(netif_txq), 333 jiffies_to_msecs(jiffies - trans_start), 334 dql_avail(&netif_txq->dql), 335 k3_cppi_desc_pool_avail(tx_chn->desc_pool)); 336 337 if (netif_tx_queue_stopped(netif_txq)) { 338 /* try recover if stopped by us */ 339 txq_trans_update(netif_txq); 340 netif_tx_wake_queue(netif_txq); 341 } 342 } 343 344 static int am65_cpsw_nuss_rx_push(struct am65_cpsw_common *common, 345 struct sk_buff *skb) 346 { 347 struct am65_cpsw_rx_chn *rx_chn = &common->rx_chns; 348 struct cppi5_host_desc_t *desc_rx; 349 struct device *dev = common->dev; 350 u32 pkt_len = skb_tailroom(skb); 351 dma_addr_t desc_dma; 352 dma_addr_t buf_dma; 353 void *swdata; 354 355 desc_rx = k3_cppi_desc_pool_alloc(rx_chn->desc_pool); 356 if (!desc_rx) { 357 dev_err(dev, "Failed to allocate RXFDQ descriptor\n"); 358 return -ENOMEM; 359 } 360 desc_dma = k3_cppi_desc_pool_virt2dma(rx_chn->desc_pool, desc_rx); 361 362 buf_dma = dma_map_single(dev, skb->data, pkt_len, DMA_FROM_DEVICE); 363 if (unlikely(dma_mapping_error(dev, buf_dma))) { 364 k3_cppi_desc_pool_free(rx_chn->desc_pool, desc_rx); 365 dev_err(dev, "Failed to map rx skb buffer\n"); 366 return -EINVAL; 367 } 368 369 cppi5_hdesc_init(desc_rx, CPPI5_INFO0_HDESC_EPIB_PRESENT, 370 AM65_CPSW_NAV_PS_DATA_SIZE); 371 cppi5_hdesc_attach_buf(desc_rx, 0, 0, buf_dma, skb_tailroom(skb)); 372 swdata = cppi5_hdesc_get_swdata(desc_rx); 373 *((void **)swdata) = skb; 374 375 return k3_udma_glue_push_rx_chn(rx_chn->rx_chn, 0, desc_rx, desc_dma); 376 } 377 378 void am65_cpsw_nuss_set_p0_ptype(struct am65_cpsw_common *common) 379 { 380 struct am65_cpsw_host *host_p = am65_common_get_host(common); 381 u32 val, pri_map; 382 383 /* P0 set Receive Priority Type */ 384 val = readl(host_p->port_base + AM65_CPSW_PORT_REG_PRI_CTL); 385 386 if (common->pf_p0_rx_ptype_rrobin) { 387 val |= AM65_CPSW_PORT_REG_PRI_CTL_RX_PTYPE_RROBIN; 388 /* Enet Ports fifos works in fixed priority mode only, so 389 * reset P0_Rx_Pri_Map so all packet will go in Enet fifo 0 390 */ 391 pri_map = 0x0; 392 } else { 393 val &= ~AM65_CPSW_PORT_REG_PRI_CTL_RX_PTYPE_RROBIN; 394 /* restore P0_Rx_Pri_Map */ 395 pri_map = 0x76543210; 396 } 397 398 writel(pri_map, host_p->port_base + AM65_CPSW_PORT_REG_RX_PRI_MAP); 399 writel(val, host_p->port_base + AM65_CPSW_PORT_REG_PRI_CTL); 400 } 401 402 static int am65_cpsw_nuss_common_open(struct am65_cpsw_common *common, 403 netdev_features_t features) 404 { 405 struct am65_cpsw_host *host_p = am65_common_get_host(common); 406 int port_idx, i, ret; 407 struct sk_buff *skb; 408 u32 val, port_mask; 409 410 if (common->usage_count) 411 return 0; 412 413 /* Control register */ 414 writel(AM65_CPSW_CTL_P0_ENABLE | AM65_CPSW_CTL_P0_TX_CRC_REMOVE | 415 AM65_CPSW_CTL_VLAN_AWARE | AM65_CPSW_CTL_P0_RX_PAD, 416 common->cpsw_base + AM65_CPSW_REG_CTL); 417 /* Max length register */ 418 writel(AM65_CPSW_MAX_PACKET_SIZE, 419 host_p->port_base + AM65_CPSW_PORT_REG_RX_MAXLEN); 420 /* set base flow_id */ 421 writel(common->rx_flow_id_base, 422 host_p->port_base + AM65_CPSW_PORT0_REG_FLOW_ID_OFFSET); 423 /* en tx crc offload */ 424 if (features & NETIF_F_HW_CSUM) 425 writel(AM65_CPSW_P0_REG_CTL_RX_CHECKSUM_EN, 426 host_p->port_base + AM65_CPSW_P0_REG_CTL); 427 428 am65_cpsw_nuss_set_p0_ptype(common); 429 430 /* enable statistic */ 431 val = BIT(HOST_PORT_NUM); 432 for (port_idx = 0; port_idx < common->port_num; port_idx++) { 433 struct am65_cpsw_port *port = &common->ports[port_idx]; 434 435 if (!port->disabled) 436 val |= BIT(port->port_id); 437 } 438 writel(val, common->cpsw_base + AM65_CPSW_REG_STAT_PORT_EN); 439 440 /* disable priority elevation */ 441 writel(0, common->cpsw_base + AM65_CPSW_REG_PTYPE); 442 443 cpsw_ale_start(common->ale); 444 445 /* limit to one RX flow only */ 446 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, 447 ALE_DEFAULT_THREAD_ID, 0); 448 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, 449 ALE_DEFAULT_THREAD_ENABLE, 1); 450 if (AM65_CPSW_IS_CPSW2G(common)) 451 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, 452 ALE_PORT_NOLEARN, 1); 453 /* switch to vlan unaware mode */ 454 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_VLAN_AWARE, 1); 455 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, 456 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); 457 458 /* default vlan cfg: create mask based on enabled ports */ 459 port_mask = GENMASK(common->port_num, 0) & 460 ~common->disabled_ports_mask; 461 462 cpsw_ale_add_vlan(common->ale, 0, port_mask, 463 port_mask, port_mask, 464 port_mask & ~ALE_PORT_HOST); 465 466 for (i = 0; i < common->rx_chns.descs_num; i++) { 467 skb = __netdev_alloc_skb_ip_align(NULL, 468 AM65_CPSW_MAX_PACKET_SIZE, 469 GFP_KERNEL); 470 if (!skb) { 471 dev_err(common->dev, "cannot allocate skb\n"); 472 return -ENOMEM; 473 } 474 475 ret = am65_cpsw_nuss_rx_push(common, skb); 476 if (ret < 0) { 477 dev_err(common->dev, 478 "cannot submit skb to channel rx, error %d\n", 479 ret); 480 kfree_skb(skb); 481 return ret; 482 } 483 kmemleak_not_leak(skb); 484 } 485 k3_udma_glue_enable_rx_chn(common->rx_chns.rx_chn); 486 487 for (i = 0; i < common->tx_ch_num; i++) { 488 ret = k3_udma_glue_enable_tx_chn(common->tx_chns[i].tx_chn); 489 if (ret) 490 return ret; 491 napi_enable(&common->tx_chns[i].napi_tx); 492 } 493 494 napi_enable(&common->napi_rx); 495 496 dev_dbg(common->dev, "cpsw_nuss started\n"); 497 return 0; 498 } 499 500 static void am65_cpsw_nuss_tx_cleanup(void *data, dma_addr_t desc_dma); 501 static void am65_cpsw_nuss_rx_cleanup(void *data, dma_addr_t desc_dma); 502 503 static int am65_cpsw_nuss_common_stop(struct am65_cpsw_common *common) 504 { 505 int i; 506 507 if (common->usage_count != 1) 508 return 0; 509 510 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, 511 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 512 513 /* shutdown tx channels */ 514 atomic_set(&common->tdown_cnt, common->tx_ch_num); 515 /* ensure new tdown_cnt value is visible */ 516 smp_mb__after_atomic(); 517 reinit_completion(&common->tdown_complete); 518 519 for (i = 0; i < common->tx_ch_num; i++) 520 k3_udma_glue_tdown_tx_chn(common->tx_chns[i].tx_chn, false); 521 522 i = wait_for_completion_timeout(&common->tdown_complete, 523 msecs_to_jiffies(1000)); 524 if (!i) 525 dev_err(common->dev, "tx timeout\n"); 526 for (i = 0; i < common->tx_ch_num; i++) 527 napi_disable(&common->tx_chns[i].napi_tx); 528 529 for (i = 0; i < common->tx_ch_num; i++) { 530 k3_udma_glue_reset_tx_chn(common->tx_chns[i].tx_chn, 531 &common->tx_chns[i], 532 am65_cpsw_nuss_tx_cleanup); 533 k3_udma_glue_disable_tx_chn(common->tx_chns[i].tx_chn); 534 } 535 536 k3_udma_glue_tdown_rx_chn(common->rx_chns.rx_chn, true); 537 napi_disable(&common->napi_rx); 538 539 for (i = 0; i < AM65_CPSW_MAX_RX_FLOWS; i++) 540 k3_udma_glue_reset_rx_chn(common->rx_chns.rx_chn, i, 541 &common->rx_chns, 542 am65_cpsw_nuss_rx_cleanup, !!i); 543 544 k3_udma_glue_disable_rx_chn(common->rx_chns.rx_chn); 545 546 cpsw_ale_stop(common->ale); 547 548 writel(0, common->cpsw_base + AM65_CPSW_REG_CTL); 549 writel(0, common->cpsw_base + AM65_CPSW_REG_STAT_PORT_EN); 550 551 dev_dbg(common->dev, "cpsw_nuss stopped\n"); 552 return 0; 553 } 554 555 static int am65_cpsw_nuss_ndo_slave_stop(struct net_device *ndev) 556 { 557 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 558 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 559 int ret; 560 561 if (port->slave.phy) 562 phy_stop(port->slave.phy); 563 564 netif_tx_stop_all_queues(ndev); 565 566 if (port->slave.phy) { 567 phy_disconnect(port->slave.phy); 568 port->slave.phy = NULL; 569 } 570 571 ret = am65_cpsw_nuss_common_stop(common); 572 if (ret) 573 return ret; 574 575 common->usage_count--; 576 pm_runtime_put(common->dev); 577 return 0; 578 } 579 580 static int cpsw_restore_vlans(struct net_device *vdev, int vid, void *arg) 581 { 582 struct am65_cpsw_port *port = arg; 583 584 if (!vdev) 585 return 0; 586 587 return am65_cpsw_nuss_ndo_slave_add_vid(port->ndev, 0, vid); 588 } 589 590 static int am65_cpsw_nuss_ndo_slave_open(struct net_device *ndev) 591 { 592 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 593 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 594 u32 port_mask; 595 int ret, i; 596 597 ret = pm_runtime_get_sync(common->dev); 598 if (ret < 0) { 599 pm_runtime_put_noidle(common->dev); 600 return ret; 601 } 602 603 /* Notify the stack of the actual queue counts. */ 604 ret = netif_set_real_num_tx_queues(ndev, common->tx_ch_num); 605 if (ret) { 606 dev_err(common->dev, "cannot set real number of tx queues\n"); 607 return ret; 608 } 609 610 ret = netif_set_real_num_rx_queues(ndev, AM65_CPSW_MAX_RX_QUEUES); 611 if (ret) { 612 dev_err(common->dev, "cannot set real number of rx queues\n"); 613 return ret; 614 } 615 616 for (i = 0; i < common->tx_ch_num; i++) 617 netdev_tx_reset_queue(netdev_get_tx_queue(ndev, i)); 618 619 ret = am65_cpsw_nuss_common_open(common, ndev->features); 620 if (ret) 621 return ret; 622 623 common->usage_count++; 624 625 am65_cpsw_port_set_sl_mac(port, ndev->dev_addr); 626 627 if (port->slave.mac_only) 628 /* enable mac-only mode on port */ 629 cpsw_ale_control_set(common->ale, port->port_id, 630 ALE_PORT_MACONLY, 1); 631 if (AM65_CPSW_IS_CPSW2G(common)) 632 cpsw_ale_control_set(common->ale, port->port_id, 633 ALE_PORT_NOLEARN, 1); 634 635 port_mask = BIT(port->port_id) | ALE_PORT_HOST; 636 cpsw_ale_add_ucast(common->ale, ndev->dev_addr, 637 HOST_PORT_NUM, ALE_SECURE, 0); 638 cpsw_ale_add_mcast(common->ale, ndev->broadcast, 639 port_mask, 0, 0, ALE_MCAST_FWD_2); 640 641 /* mac_sl should be configured via phy-link interface */ 642 am65_cpsw_sl_ctl_reset(port); 643 644 ret = phy_set_mode_ext(port->slave.ifphy, PHY_MODE_ETHERNET, 645 port->slave.phy_if); 646 if (ret) 647 goto error_cleanup; 648 649 if (port->slave.phy_node) { 650 port->slave.phy = of_phy_connect(ndev, 651 port->slave.phy_node, 652 &am65_cpsw_nuss_adjust_link, 653 0, port->slave.phy_if); 654 if (!port->slave.phy) { 655 dev_err(common->dev, "phy %pOF not found on slave %d\n", 656 port->slave.phy_node, 657 port->port_id); 658 ret = -ENODEV; 659 goto error_cleanup; 660 } 661 } 662 663 /* restore vlan configurations */ 664 vlan_for_each(ndev, cpsw_restore_vlans, port); 665 666 phy_attached_info(port->slave.phy); 667 phy_start(port->slave.phy); 668 669 return 0; 670 671 error_cleanup: 672 am65_cpsw_nuss_ndo_slave_stop(ndev); 673 return ret; 674 } 675 676 static void am65_cpsw_nuss_rx_cleanup(void *data, dma_addr_t desc_dma) 677 { 678 struct am65_cpsw_rx_chn *rx_chn = data; 679 struct cppi5_host_desc_t *desc_rx; 680 struct sk_buff *skb; 681 dma_addr_t buf_dma; 682 u32 buf_dma_len; 683 void **swdata; 684 685 desc_rx = k3_cppi_desc_pool_dma2virt(rx_chn->desc_pool, desc_dma); 686 swdata = cppi5_hdesc_get_swdata(desc_rx); 687 skb = *swdata; 688 cppi5_hdesc_get_obuf(desc_rx, &buf_dma, &buf_dma_len); 689 690 dma_unmap_single(rx_chn->dev, buf_dma, buf_dma_len, DMA_FROM_DEVICE); 691 k3_cppi_desc_pool_free(rx_chn->desc_pool, desc_rx); 692 693 dev_kfree_skb_any(skb); 694 } 695 696 static void am65_cpsw_nuss_rx_ts(struct sk_buff *skb, u32 *psdata) 697 { 698 struct skb_shared_hwtstamps *ssh; 699 u64 ns; 700 701 ns = ((u64)psdata[1] << 32) | psdata[0]; 702 703 ssh = skb_hwtstamps(skb); 704 memset(ssh, 0, sizeof(*ssh)); 705 ssh->hwtstamp = ns_to_ktime(ns); 706 } 707 708 /* RX psdata[2] word format - checksum information */ 709 #define AM65_CPSW_RX_PSD_CSUM_ADD GENMASK(15, 0) 710 #define AM65_CPSW_RX_PSD_CSUM_ERR BIT(16) 711 #define AM65_CPSW_RX_PSD_IS_FRAGMENT BIT(17) 712 #define AM65_CPSW_RX_PSD_IS_TCP BIT(18) 713 #define AM65_CPSW_RX_PSD_IPV6_VALID BIT(19) 714 #define AM65_CPSW_RX_PSD_IPV4_VALID BIT(20) 715 716 static void am65_cpsw_nuss_rx_csum(struct sk_buff *skb, u32 csum_info) 717 { 718 /* HW can verify IPv4/IPv6 TCP/UDP packets checksum 719 * csum information provides in psdata[2] word: 720 * AM65_CPSW_RX_PSD_CSUM_ERR bit - indicates csum error 721 * AM65_CPSW_RX_PSD_IPV6_VALID and AM65_CPSW_RX_PSD_IPV4_VALID 722 * bits - indicates IPv4/IPv6 packet 723 * AM65_CPSW_RX_PSD_IS_FRAGMENT bit - indicates fragmented packet 724 * AM65_CPSW_RX_PSD_CSUM_ADD has value 0xFFFF for non fragmented packets 725 * or csum value for fragmented packets if !AM65_CPSW_RX_PSD_CSUM_ERR 726 */ 727 skb_checksum_none_assert(skb); 728 729 if (unlikely(!(skb->dev->features & NETIF_F_RXCSUM))) 730 return; 731 732 if ((csum_info & (AM65_CPSW_RX_PSD_IPV6_VALID | 733 AM65_CPSW_RX_PSD_IPV4_VALID)) && 734 !(csum_info & AM65_CPSW_RX_PSD_CSUM_ERR)) { 735 /* csum for fragmented packets is unsupported */ 736 if (!(csum_info & AM65_CPSW_RX_PSD_IS_FRAGMENT)) 737 skb->ip_summed = CHECKSUM_UNNECESSARY; 738 } 739 } 740 741 static int am65_cpsw_nuss_rx_packets(struct am65_cpsw_common *common, 742 u32 flow_idx) 743 { 744 struct am65_cpsw_rx_chn *rx_chn = &common->rx_chns; 745 u32 buf_dma_len, pkt_len, port_id = 0, csum_info; 746 struct am65_cpsw_ndev_priv *ndev_priv; 747 struct am65_cpsw_ndev_stats *stats; 748 struct cppi5_host_desc_t *desc_rx; 749 struct device *dev = common->dev; 750 struct sk_buff *skb, *new_skb; 751 dma_addr_t desc_dma, buf_dma; 752 struct am65_cpsw_port *port; 753 struct net_device *ndev; 754 void **swdata; 755 u32 *psdata; 756 int ret = 0; 757 758 ret = k3_udma_glue_pop_rx_chn(rx_chn->rx_chn, flow_idx, &desc_dma); 759 if (ret) { 760 if (ret != -ENODATA) 761 dev_err(dev, "RX: pop chn fail %d\n", ret); 762 return ret; 763 } 764 765 if (desc_dma & 0x1) { 766 dev_dbg(dev, "%s RX tdown flow: %u\n", __func__, flow_idx); 767 return 0; 768 } 769 770 desc_rx = k3_cppi_desc_pool_dma2virt(rx_chn->desc_pool, desc_dma); 771 dev_dbg(dev, "%s flow_idx: %u desc %pad\n", 772 __func__, flow_idx, &desc_dma); 773 774 swdata = cppi5_hdesc_get_swdata(desc_rx); 775 skb = *swdata; 776 cppi5_hdesc_get_obuf(desc_rx, &buf_dma, &buf_dma_len); 777 pkt_len = cppi5_hdesc_get_pktlen(desc_rx); 778 cppi5_desc_get_tags_ids(&desc_rx->hdr, &port_id, NULL); 779 dev_dbg(dev, "%s rx port_id:%d\n", __func__, port_id); 780 port = am65_common_get_port(common, port_id); 781 ndev = port->ndev; 782 skb->dev = ndev; 783 784 psdata = cppi5_hdesc_get_psdata(desc_rx); 785 /* add RX timestamp */ 786 if (port->rx_ts_enabled) 787 am65_cpsw_nuss_rx_ts(skb, psdata); 788 csum_info = psdata[2]; 789 dev_dbg(dev, "%s rx csum_info:%#x\n", __func__, csum_info); 790 791 dma_unmap_single(dev, buf_dma, buf_dma_len, DMA_FROM_DEVICE); 792 793 k3_cppi_desc_pool_free(rx_chn->desc_pool, desc_rx); 794 795 new_skb = netdev_alloc_skb_ip_align(ndev, AM65_CPSW_MAX_PACKET_SIZE); 796 if (new_skb) { 797 skb_put(skb, pkt_len); 798 skb->protocol = eth_type_trans(skb, ndev); 799 am65_cpsw_nuss_rx_csum(skb, csum_info); 800 napi_gro_receive(&common->napi_rx, skb); 801 802 ndev_priv = netdev_priv(ndev); 803 stats = this_cpu_ptr(ndev_priv->stats); 804 805 u64_stats_update_begin(&stats->syncp); 806 stats->rx_packets++; 807 stats->rx_bytes += pkt_len; 808 u64_stats_update_end(&stats->syncp); 809 kmemleak_not_leak(new_skb); 810 } else { 811 ndev->stats.rx_dropped++; 812 new_skb = skb; 813 } 814 815 if (netif_dormant(ndev)) { 816 dev_kfree_skb_any(new_skb); 817 ndev->stats.rx_dropped++; 818 return 0; 819 } 820 821 ret = am65_cpsw_nuss_rx_push(common, new_skb); 822 if (WARN_ON(ret < 0)) { 823 dev_kfree_skb_any(new_skb); 824 ndev->stats.rx_errors++; 825 ndev->stats.rx_dropped++; 826 } 827 828 return ret; 829 } 830 831 static int am65_cpsw_nuss_rx_poll(struct napi_struct *napi_rx, int budget) 832 { 833 struct am65_cpsw_common *common = am65_cpsw_napi_to_common(napi_rx); 834 int flow = AM65_CPSW_MAX_RX_FLOWS; 835 int cur_budget, ret; 836 int num_rx = 0; 837 838 /* process every flow */ 839 while (flow--) { 840 cur_budget = budget - num_rx; 841 842 while (cur_budget--) { 843 ret = am65_cpsw_nuss_rx_packets(common, flow); 844 if (ret) 845 break; 846 num_rx++; 847 } 848 849 if (num_rx >= budget) 850 break; 851 } 852 853 dev_dbg(common->dev, "%s num_rx:%d %d\n", __func__, num_rx, budget); 854 855 if (num_rx < budget && napi_complete_done(napi_rx, num_rx)) 856 enable_irq(common->rx_chns.irq); 857 858 return num_rx; 859 } 860 861 static void am65_cpsw_nuss_xmit_free(struct am65_cpsw_tx_chn *tx_chn, 862 struct device *dev, 863 struct cppi5_host_desc_t *desc) 864 { 865 struct cppi5_host_desc_t *first_desc, *next_desc; 866 dma_addr_t buf_dma, next_desc_dma; 867 u32 buf_dma_len; 868 869 first_desc = desc; 870 next_desc = first_desc; 871 872 cppi5_hdesc_get_obuf(first_desc, &buf_dma, &buf_dma_len); 873 874 dma_unmap_single(dev, buf_dma, buf_dma_len, 875 DMA_TO_DEVICE); 876 877 next_desc_dma = cppi5_hdesc_get_next_hbdesc(first_desc); 878 while (next_desc_dma) { 879 next_desc = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool, 880 next_desc_dma); 881 cppi5_hdesc_get_obuf(next_desc, &buf_dma, &buf_dma_len); 882 883 dma_unmap_page(dev, buf_dma, buf_dma_len, 884 DMA_TO_DEVICE); 885 886 next_desc_dma = cppi5_hdesc_get_next_hbdesc(next_desc); 887 888 k3_cppi_desc_pool_free(tx_chn->desc_pool, next_desc); 889 } 890 891 k3_cppi_desc_pool_free(tx_chn->desc_pool, first_desc); 892 } 893 894 static void am65_cpsw_nuss_tx_cleanup(void *data, dma_addr_t desc_dma) 895 { 896 struct am65_cpsw_tx_chn *tx_chn = data; 897 struct cppi5_host_desc_t *desc_tx; 898 struct sk_buff *skb; 899 void **swdata; 900 901 desc_tx = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool, desc_dma); 902 swdata = cppi5_hdesc_get_swdata(desc_tx); 903 skb = *(swdata); 904 am65_cpsw_nuss_xmit_free(tx_chn, tx_chn->common->dev, desc_tx); 905 906 dev_kfree_skb_any(skb); 907 } 908 909 static int am65_cpsw_nuss_tx_compl_packets(struct am65_cpsw_common *common, 910 int chn, unsigned int budget) 911 { 912 struct cppi5_host_desc_t *desc_tx; 913 struct device *dev = common->dev; 914 struct am65_cpsw_tx_chn *tx_chn; 915 struct netdev_queue *netif_txq; 916 unsigned int total_bytes = 0; 917 struct net_device *ndev; 918 struct sk_buff *skb; 919 dma_addr_t desc_dma; 920 int res, num_tx = 0; 921 void **swdata; 922 923 tx_chn = &common->tx_chns[chn]; 924 925 while (true) { 926 struct am65_cpsw_ndev_priv *ndev_priv; 927 struct am65_cpsw_ndev_stats *stats; 928 929 res = k3_udma_glue_pop_tx_chn(tx_chn->tx_chn, &desc_dma); 930 if (res == -ENODATA) 931 break; 932 933 if (desc_dma & 0x1) { 934 if (atomic_dec_and_test(&common->tdown_cnt)) 935 complete(&common->tdown_complete); 936 break; 937 } 938 939 desc_tx = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool, 940 desc_dma); 941 swdata = cppi5_hdesc_get_swdata(desc_tx); 942 skb = *(swdata); 943 am65_cpsw_nuss_xmit_free(tx_chn, dev, desc_tx); 944 945 ndev = skb->dev; 946 947 am65_cpts_tx_timestamp(common->cpts, skb); 948 949 ndev_priv = netdev_priv(ndev); 950 stats = this_cpu_ptr(ndev_priv->stats); 951 u64_stats_update_begin(&stats->syncp); 952 stats->tx_packets++; 953 stats->tx_bytes += skb->len; 954 u64_stats_update_end(&stats->syncp); 955 956 total_bytes += skb->len; 957 napi_consume_skb(skb, budget); 958 num_tx++; 959 } 960 961 if (!num_tx) 962 return 0; 963 964 netif_txq = netdev_get_tx_queue(ndev, chn); 965 966 netdev_tx_completed_queue(netif_txq, num_tx, total_bytes); 967 968 if (netif_tx_queue_stopped(netif_txq)) { 969 /* Check whether the queue is stopped due to stalled tx dma, 970 * if the queue is stopped then wake the queue as 971 * we have free desc for tx 972 */ 973 __netif_tx_lock(netif_txq, smp_processor_id()); 974 if (netif_running(ndev) && 975 (k3_cppi_desc_pool_avail(tx_chn->desc_pool) >= 976 MAX_SKB_FRAGS)) 977 netif_tx_wake_queue(netif_txq); 978 979 __netif_tx_unlock(netif_txq); 980 } 981 dev_dbg(dev, "%s:%u pkt:%d\n", __func__, chn, num_tx); 982 983 return num_tx; 984 } 985 986 static int am65_cpsw_nuss_tx_poll(struct napi_struct *napi_tx, int budget) 987 { 988 struct am65_cpsw_tx_chn *tx_chn = am65_cpsw_napi_to_tx_chn(napi_tx); 989 int num_tx; 990 991 num_tx = am65_cpsw_nuss_tx_compl_packets(tx_chn->common, tx_chn->id, 992 budget); 993 num_tx = min(num_tx, budget); 994 if (num_tx < budget) { 995 napi_complete(napi_tx); 996 enable_irq(tx_chn->irq); 997 } 998 999 return num_tx; 1000 } 1001 1002 static irqreturn_t am65_cpsw_nuss_rx_irq(int irq, void *dev_id) 1003 { 1004 struct am65_cpsw_common *common = dev_id; 1005 1006 disable_irq_nosync(irq); 1007 napi_schedule(&common->napi_rx); 1008 1009 return IRQ_HANDLED; 1010 } 1011 1012 static irqreturn_t am65_cpsw_nuss_tx_irq(int irq, void *dev_id) 1013 { 1014 struct am65_cpsw_tx_chn *tx_chn = dev_id; 1015 1016 disable_irq_nosync(irq); 1017 napi_schedule(&tx_chn->napi_tx); 1018 1019 return IRQ_HANDLED; 1020 } 1021 1022 static netdev_tx_t am65_cpsw_nuss_ndo_slave_xmit(struct sk_buff *skb, 1023 struct net_device *ndev) 1024 { 1025 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 1026 struct cppi5_host_desc_t *first_desc, *next_desc, *cur_desc; 1027 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1028 struct device *dev = common->dev; 1029 struct am65_cpsw_tx_chn *tx_chn; 1030 struct netdev_queue *netif_txq; 1031 dma_addr_t desc_dma, buf_dma; 1032 int ret, q_idx, i; 1033 void **swdata; 1034 u32 *psdata; 1035 u32 pkt_len; 1036 1037 /* padding enabled in hw */ 1038 pkt_len = skb_headlen(skb); 1039 1040 /* SKB TX timestamp */ 1041 if (port->tx_ts_enabled) 1042 am65_cpts_prep_tx_timestamp(common->cpts, skb); 1043 1044 q_idx = skb_get_queue_mapping(skb); 1045 dev_dbg(dev, "%s skb_queue:%d\n", __func__, q_idx); 1046 1047 tx_chn = &common->tx_chns[q_idx]; 1048 netif_txq = netdev_get_tx_queue(ndev, q_idx); 1049 1050 /* Map the linear buffer */ 1051 buf_dma = dma_map_single(dev, skb->data, pkt_len, 1052 DMA_TO_DEVICE); 1053 if (unlikely(dma_mapping_error(dev, buf_dma))) { 1054 dev_err(dev, "Failed to map tx skb buffer\n"); 1055 ndev->stats.tx_errors++; 1056 goto err_free_skb; 1057 } 1058 1059 first_desc = k3_cppi_desc_pool_alloc(tx_chn->desc_pool); 1060 if (!first_desc) { 1061 dev_dbg(dev, "Failed to allocate descriptor\n"); 1062 dma_unmap_single(dev, buf_dma, pkt_len, DMA_TO_DEVICE); 1063 goto busy_stop_q; 1064 } 1065 1066 cppi5_hdesc_init(first_desc, CPPI5_INFO0_HDESC_EPIB_PRESENT, 1067 AM65_CPSW_NAV_PS_DATA_SIZE); 1068 cppi5_desc_set_pktids(&first_desc->hdr, 0, 0x3FFF); 1069 cppi5_hdesc_set_pkttype(first_desc, 0x7); 1070 cppi5_desc_set_tags_ids(&first_desc->hdr, 0, port->port_id); 1071 1072 cppi5_hdesc_attach_buf(first_desc, buf_dma, pkt_len, buf_dma, pkt_len); 1073 swdata = cppi5_hdesc_get_swdata(first_desc); 1074 *(swdata) = skb; 1075 psdata = cppi5_hdesc_get_psdata(first_desc); 1076 1077 /* HW csum offload if enabled */ 1078 psdata[2] = 0; 1079 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) { 1080 unsigned int cs_start, cs_offset; 1081 1082 cs_start = skb_transport_offset(skb); 1083 cs_offset = cs_start + skb->csum_offset; 1084 /* HW numerates bytes starting from 1 */ 1085 psdata[2] = ((cs_offset + 1) << 24) | 1086 ((cs_start + 1) << 16) | (skb->len - cs_start); 1087 dev_dbg(dev, "%s tx psdata:%#x\n", __func__, psdata[2]); 1088 } 1089 1090 if (!skb_is_nonlinear(skb)) 1091 goto done_tx; 1092 1093 dev_dbg(dev, "fragmented SKB\n"); 1094 1095 /* Handle the case where skb is fragmented in pages */ 1096 cur_desc = first_desc; 1097 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1098 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1099 u32 frag_size = skb_frag_size(frag); 1100 1101 next_desc = k3_cppi_desc_pool_alloc(tx_chn->desc_pool); 1102 if (!next_desc) { 1103 dev_err(dev, "Failed to allocate descriptor\n"); 1104 goto busy_free_descs; 1105 } 1106 1107 buf_dma = skb_frag_dma_map(dev, frag, 0, frag_size, 1108 DMA_TO_DEVICE); 1109 if (unlikely(dma_mapping_error(dev, buf_dma))) { 1110 dev_err(dev, "Failed to map tx skb page\n"); 1111 k3_cppi_desc_pool_free(tx_chn->desc_pool, next_desc); 1112 ndev->stats.tx_errors++; 1113 goto err_free_descs; 1114 } 1115 1116 cppi5_hdesc_reset_hbdesc(next_desc); 1117 cppi5_hdesc_attach_buf(next_desc, 1118 buf_dma, frag_size, buf_dma, frag_size); 1119 1120 desc_dma = k3_cppi_desc_pool_virt2dma(tx_chn->desc_pool, 1121 next_desc); 1122 cppi5_hdesc_link_hbdesc(cur_desc, desc_dma); 1123 1124 pkt_len += frag_size; 1125 cur_desc = next_desc; 1126 } 1127 WARN_ON(pkt_len != skb->len); 1128 1129 done_tx: 1130 skb_tx_timestamp(skb); 1131 1132 /* report bql before sending packet */ 1133 netdev_tx_sent_queue(netif_txq, pkt_len); 1134 1135 cppi5_hdesc_set_pktlen(first_desc, pkt_len); 1136 desc_dma = k3_cppi_desc_pool_virt2dma(tx_chn->desc_pool, first_desc); 1137 ret = k3_udma_glue_push_tx_chn(tx_chn->tx_chn, first_desc, desc_dma); 1138 if (ret) { 1139 dev_err(dev, "can't push desc %d\n", ret); 1140 /* inform bql */ 1141 netdev_tx_completed_queue(netif_txq, 1, pkt_len); 1142 ndev->stats.tx_errors++; 1143 goto err_free_descs; 1144 } 1145 1146 if (k3_cppi_desc_pool_avail(tx_chn->desc_pool) < MAX_SKB_FRAGS) { 1147 netif_tx_stop_queue(netif_txq); 1148 /* Barrier, so that stop_queue visible to other cpus */ 1149 smp_mb__after_atomic(); 1150 dev_dbg(dev, "netif_tx_stop_queue %d\n", q_idx); 1151 1152 /* re-check for smp */ 1153 if (k3_cppi_desc_pool_avail(tx_chn->desc_pool) >= 1154 MAX_SKB_FRAGS) { 1155 netif_tx_wake_queue(netif_txq); 1156 dev_dbg(dev, "netif_tx_wake_queue %d\n", q_idx); 1157 } 1158 } 1159 1160 return NETDEV_TX_OK; 1161 1162 err_free_descs: 1163 am65_cpsw_nuss_xmit_free(tx_chn, dev, first_desc); 1164 err_free_skb: 1165 ndev->stats.tx_dropped++; 1166 dev_kfree_skb_any(skb); 1167 return NETDEV_TX_OK; 1168 1169 busy_free_descs: 1170 am65_cpsw_nuss_xmit_free(tx_chn, dev, first_desc); 1171 busy_stop_q: 1172 netif_tx_stop_queue(netif_txq); 1173 return NETDEV_TX_BUSY; 1174 } 1175 1176 static int am65_cpsw_nuss_ndo_slave_set_mac_address(struct net_device *ndev, 1177 void *addr) 1178 { 1179 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 1180 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1181 struct sockaddr *sockaddr = (struct sockaddr *)addr; 1182 int ret; 1183 1184 ret = eth_prepare_mac_addr_change(ndev, addr); 1185 if (ret < 0) 1186 return ret; 1187 1188 ret = pm_runtime_get_sync(common->dev); 1189 if (ret < 0) { 1190 pm_runtime_put_noidle(common->dev); 1191 return ret; 1192 } 1193 1194 cpsw_ale_del_ucast(common->ale, ndev->dev_addr, 1195 HOST_PORT_NUM, 0, 0); 1196 cpsw_ale_add_ucast(common->ale, sockaddr->sa_data, 1197 HOST_PORT_NUM, ALE_SECURE, 0); 1198 1199 am65_cpsw_port_set_sl_mac(port, addr); 1200 eth_commit_mac_addr_change(ndev, sockaddr); 1201 1202 pm_runtime_put(common->dev); 1203 1204 return 0; 1205 } 1206 1207 static int am65_cpsw_nuss_hwtstamp_set(struct net_device *ndev, 1208 struct ifreq *ifr) 1209 { 1210 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 1211 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1212 u32 ts_ctrl, seq_id, ts_ctrl_ltype2, ts_vlan_ltype; 1213 struct hwtstamp_config cfg; 1214 1215 if (!IS_ENABLED(CONFIG_TI_K3_AM65_CPTS)) 1216 return -EOPNOTSUPP; 1217 1218 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg))) 1219 return -EFAULT; 1220 1221 /* TX HW timestamp */ 1222 switch (cfg.tx_type) { 1223 case HWTSTAMP_TX_OFF: 1224 case HWTSTAMP_TX_ON: 1225 break; 1226 default: 1227 return -ERANGE; 1228 } 1229 1230 switch (cfg.rx_filter) { 1231 case HWTSTAMP_FILTER_NONE: 1232 port->rx_ts_enabled = false; 1233 break; 1234 case HWTSTAMP_FILTER_ALL: 1235 case HWTSTAMP_FILTER_SOME: 1236 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 1237 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 1238 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 1239 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 1240 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 1241 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 1242 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 1243 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 1244 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 1245 case HWTSTAMP_FILTER_PTP_V2_EVENT: 1246 case HWTSTAMP_FILTER_PTP_V2_SYNC: 1247 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 1248 case HWTSTAMP_FILTER_NTP_ALL: 1249 port->rx_ts_enabled = true; 1250 cfg.rx_filter = HWTSTAMP_FILTER_ALL; 1251 break; 1252 default: 1253 return -ERANGE; 1254 } 1255 1256 port->tx_ts_enabled = (cfg.tx_type == HWTSTAMP_TX_ON); 1257 1258 /* cfg TX timestamp */ 1259 seq_id = (AM65_CPSW_TS_SEQ_ID_OFFSET << 1260 AM65_CPSW_PN_TS_SEQ_ID_OFFSET_SHIFT) | ETH_P_1588; 1261 1262 ts_vlan_ltype = ETH_P_8021Q; 1263 1264 ts_ctrl_ltype2 = ETH_P_1588 | 1265 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_107 | 1266 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_129 | 1267 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_130 | 1268 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_131 | 1269 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_132 | 1270 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_319 | 1271 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_320 | 1272 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_TTL_NONZERO; 1273 1274 ts_ctrl = AM65_CPSW_TS_EVENT_MSG_TYPE_BITS << 1275 AM65_CPSW_PN_TS_CTL_MSG_TYPE_EN_SHIFT; 1276 1277 if (port->tx_ts_enabled) 1278 ts_ctrl |= AM65_CPSW_TS_TX_ANX_ALL_EN | 1279 AM65_CPSW_PN_TS_CTL_TX_VLAN_LT1_EN; 1280 1281 writel(seq_id, port->port_base + AM65_CPSW_PORTN_REG_TS_SEQ_LTYPE_REG); 1282 writel(ts_vlan_ltype, port->port_base + 1283 AM65_CPSW_PORTN_REG_TS_VLAN_LTYPE_REG); 1284 writel(ts_ctrl_ltype2, port->port_base + 1285 AM65_CPSW_PORTN_REG_TS_CTL_LTYPE2); 1286 writel(ts_ctrl, port->port_base + AM65_CPSW_PORTN_REG_TS_CTL); 1287 1288 /* en/dis RX timestamp */ 1289 am65_cpts_rx_enable(common->cpts, port->rx_ts_enabled); 1290 1291 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 1292 } 1293 1294 static int am65_cpsw_nuss_hwtstamp_get(struct net_device *ndev, 1295 struct ifreq *ifr) 1296 { 1297 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1298 struct hwtstamp_config cfg; 1299 1300 if (!IS_ENABLED(CONFIG_TI_K3_AM65_CPTS)) 1301 return -EOPNOTSUPP; 1302 1303 cfg.flags = 0; 1304 cfg.tx_type = port->tx_ts_enabled ? 1305 HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF; 1306 cfg.rx_filter = port->rx_ts_enabled ? 1307 HWTSTAMP_FILTER_ALL : HWTSTAMP_FILTER_NONE; 1308 1309 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 1310 } 1311 1312 static int am65_cpsw_nuss_ndo_slave_ioctl(struct net_device *ndev, 1313 struct ifreq *req, int cmd) 1314 { 1315 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1316 1317 if (!netif_running(ndev)) 1318 return -EINVAL; 1319 1320 switch (cmd) { 1321 case SIOCSHWTSTAMP: 1322 return am65_cpsw_nuss_hwtstamp_set(ndev, req); 1323 case SIOCGHWTSTAMP: 1324 return am65_cpsw_nuss_hwtstamp_get(ndev, req); 1325 } 1326 1327 if (!port->slave.phy) 1328 return -EOPNOTSUPP; 1329 1330 return phy_mii_ioctl(port->slave.phy, req, cmd); 1331 } 1332 1333 static void am65_cpsw_nuss_ndo_get_stats(struct net_device *dev, 1334 struct rtnl_link_stats64 *stats) 1335 { 1336 struct am65_cpsw_ndev_priv *ndev_priv = netdev_priv(dev); 1337 unsigned int start; 1338 int cpu; 1339 1340 for_each_possible_cpu(cpu) { 1341 struct am65_cpsw_ndev_stats *cpu_stats; 1342 u64 rx_packets; 1343 u64 rx_bytes; 1344 u64 tx_packets; 1345 u64 tx_bytes; 1346 1347 cpu_stats = per_cpu_ptr(ndev_priv->stats, cpu); 1348 do { 1349 start = u64_stats_fetch_begin_irq(&cpu_stats->syncp); 1350 rx_packets = cpu_stats->rx_packets; 1351 rx_bytes = cpu_stats->rx_bytes; 1352 tx_packets = cpu_stats->tx_packets; 1353 tx_bytes = cpu_stats->tx_bytes; 1354 } while (u64_stats_fetch_retry_irq(&cpu_stats->syncp, start)); 1355 1356 stats->rx_packets += rx_packets; 1357 stats->rx_bytes += rx_bytes; 1358 stats->tx_packets += tx_packets; 1359 stats->tx_bytes += tx_bytes; 1360 } 1361 1362 stats->rx_errors = dev->stats.rx_errors; 1363 stats->rx_dropped = dev->stats.rx_dropped; 1364 stats->tx_dropped = dev->stats.tx_dropped; 1365 } 1366 1367 static int am65_cpsw_nuss_ndo_slave_set_features(struct net_device *ndev, 1368 netdev_features_t features) 1369 { 1370 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 1371 netdev_features_t changes = features ^ ndev->features; 1372 struct am65_cpsw_host *host_p; 1373 1374 host_p = am65_common_get_host(common); 1375 1376 if (changes & NETIF_F_HW_CSUM) { 1377 bool enable = !!(features & NETIF_F_HW_CSUM); 1378 1379 dev_info(common->dev, "Turn %s tx-checksum-ip-generic\n", 1380 enable ? "ON" : "OFF"); 1381 if (enable) 1382 writel(AM65_CPSW_P0_REG_CTL_RX_CHECKSUM_EN, 1383 host_p->port_base + AM65_CPSW_P0_REG_CTL); 1384 else 1385 writel(0, 1386 host_p->port_base + AM65_CPSW_P0_REG_CTL); 1387 } 1388 1389 return 0; 1390 } 1391 1392 static const struct net_device_ops am65_cpsw_nuss_netdev_ops_2g = { 1393 .ndo_open = am65_cpsw_nuss_ndo_slave_open, 1394 .ndo_stop = am65_cpsw_nuss_ndo_slave_stop, 1395 .ndo_start_xmit = am65_cpsw_nuss_ndo_slave_xmit, 1396 .ndo_set_rx_mode = am65_cpsw_nuss_ndo_slave_set_rx_mode, 1397 .ndo_get_stats64 = am65_cpsw_nuss_ndo_get_stats, 1398 .ndo_validate_addr = eth_validate_addr, 1399 .ndo_set_mac_address = am65_cpsw_nuss_ndo_slave_set_mac_address, 1400 .ndo_tx_timeout = am65_cpsw_nuss_ndo_host_tx_timeout, 1401 .ndo_vlan_rx_add_vid = am65_cpsw_nuss_ndo_slave_add_vid, 1402 .ndo_vlan_rx_kill_vid = am65_cpsw_nuss_ndo_slave_kill_vid, 1403 .ndo_do_ioctl = am65_cpsw_nuss_ndo_slave_ioctl, 1404 .ndo_set_features = am65_cpsw_nuss_ndo_slave_set_features, 1405 .ndo_setup_tc = am65_cpsw_qos_ndo_setup_tc, 1406 }; 1407 1408 static void am65_cpsw_nuss_slave_disable_unused(struct am65_cpsw_port *port) 1409 { 1410 struct am65_cpsw_common *common = port->common; 1411 1412 if (!port->disabled) 1413 return; 1414 1415 common->disabled_ports_mask |= BIT(port->port_id); 1416 cpsw_ale_control_set(common->ale, port->port_id, 1417 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 1418 1419 cpsw_sl_reset(port->slave.mac_sl, 100); 1420 cpsw_sl_ctl_reset(port->slave.mac_sl); 1421 } 1422 1423 static void am65_cpsw_nuss_free_tx_chns(void *data) 1424 { 1425 struct am65_cpsw_common *common = data; 1426 int i; 1427 1428 for (i = 0; i < common->tx_ch_num; i++) { 1429 struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[i]; 1430 1431 if (!IS_ERR_OR_NULL(tx_chn->tx_chn)) 1432 k3_udma_glue_release_tx_chn(tx_chn->tx_chn); 1433 1434 if (!IS_ERR_OR_NULL(tx_chn->desc_pool)) 1435 k3_cppi_desc_pool_destroy(tx_chn->desc_pool); 1436 1437 memset(tx_chn, 0, sizeof(*tx_chn)); 1438 } 1439 } 1440 1441 void am65_cpsw_nuss_remove_tx_chns(struct am65_cpsw_common *common) 1442 { 1443 struct device *dev = common->dev; 1444 int i; 1445 1446 devm_remove_action(dev, am65_cpsw_nuss_free_tx_chns, common); 1447 1448 for (i = 0; i < common->tx_ch_num; i++) { 1449 struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[i]; 1450 1451 if (tx_chn->irq) 1452 devm_free_irq(dev, tx_chn->irq, tx_chn); 1453 1454 netif_napi_del(&tx_chn->napi_tx); 1455 1456 if (!IS_ERR_OR_NULL(tx_chn->tx_chn)) 1457 k3_udma_glue_release_tx_chn(tx_chn->tx_chn); 1458 1459 if (!IS_ERR_OR_NULL(tx_chn->desc_pool)) 1460 k3_cppi_desc_pool_destroy(tx_chn->desc_pool); 1461 1462 memset(tx_chn, 0, sizeof(*tx_chn)); 1463 } 1464 } 1465 1466 static int am65_cpsw_nuss_init_tx_chns(struct am65_cpsw_common *common) 1467 { 1468 u32 max_desc_num = ALIGN(AM65_CPSW_MAX_TX_DESC, MAX_SKB_FRAGS); 1469 struct k3_udma_glue_tx_channel_cfg tx_cfg = { 0 }; 1470 struct device *dev = common->dev; 1471 struct k3_ring_cfg ring_cfg = { 1472 .elm_size = K3_RINGACC_RING_ELSIZE_8, 1473 .mode = K3_RINGACC_RING_MODE_RING, 1474 .flags = 0 1475 }; 1476 u32 hdesc_size; 1477 int i, ret = 0; 1478 1479 hdesc_size = cppi5_hdesc_calc_size(true, AM65_CPSW_NAV_PS_DATA_SIZE, 1480 AM65_CPSW_NAV_SW_DATA_SIZE); 1481 1482 tx_cfg.swdata_size = AM65_CPSW_NAV_SW_DATA_SIZE; 1483 tx_cfg.tx_cfg = ring_cfg; 1484 tx_cfg.txcq_cfg = ring_cfg; 1485 tx_cfg.tx_cfg.size = max_desc_num; 1486 tx_cfg.txcq_cfg.size = max_desc_num; 1487 1488 for (i = 0; i < common->tx_ch_num; i++) { 1489 struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[i]; 1490 1491 snprintf(tx_chn->tx_chn_name, 1492 sizeof(tx_chn->tx_chn_name), "tx%d", i); 1493 1494 tx_chn->common = common; 1495 tx_chn->id = i; 1496 tx_chn->descs_num = max_desc_num; 1497 tx_chn->desc_pool = 1498 k3_cppi_desc_pool_create_name(dev, 1499 tx_chn->descs_num, 1500 hdesc_size, 1501 tx_chn->tx_chn_name); 1502 if (IS_ERR(tx_chn->desc_pool)) { 1503 ret = PTR_ERR(tx_chn->desc_pool); 1504 dev_err(dev, "Failed to create poll %d\n", ret); 1505 goto err; 1506 } 1507 1508 tx_chn->tx_chn = 1509 k3_udma_glue_request_tx_chn(dev, 1510 tx_chn->tx_chn_name, 1511 &tx_cfg); 1512 if (IS_ERR(tx_chn->tx_chn)) { 1513 ret = PTR_ERR(tx_chn->tx_chn); 1514 dev_err(dev, "Failed to request tx dma channel %d\n", 1515 ret); 1516 goto err; 1517 } 1518 1519 tx_chn->irq = k3_udma_glue_tx_get_irq(tx_chn->tx_chn); 1520 if (tx_chn->irq <= 0) { 1521 dev_err(dev, "Failed to get tx dma irq %d\n", 1522 tx_chn->irq); 1523 goto err; 1524 } 1525 1526 snprintf(tx_chn->tx_chn_name, 1527 sizeof(tx_chn->tx_chn_name), "%s-tx%d", 1528 dev_name(dev), tx_chn->id); 1529 } 1530 1531 err: 1532 i = devm_add_action(dev, am65_cpsw_nuss_free_tx_chns, common); 1533 if (i) { 1534 dev_err(dev, "Failed to add free_tx_chns action %d\n", i); 1535 return i; 1536 } 1537 1538 return ret; 1539 } 1540 1541 static void am65_cpsw_nuss_free_rx_chns(void *data) 1542 { 1543 struct am65_cpsw_common *common = data; 1544 struct am65_cpsw_rx_chn *rx_chn; 1545 1546 rx_chn = &common->rx_chns; 1547 1548 if (!IS_ERR_OR_NULL(rx_chn->rx_chn)) 1549 k3_udma_glue_release_rx_chn(rx_chn->rx_chn); 1550 1551 if (!IS_ERR_OR_NULL(rx_chn->desc_pool)) 1552 k3_cppi_desc_pool_destroy(rx_chn->desc_pool); 1553 } 1554 1555 static int am65_cpsw_nuss_init_rx_chns(struct am65_cpsw_common *common) 1556 { 1557 struct am65_cpsw_rx_chn *rx_chn = &common->rx_chns; 1558 struct k3_udma_glue_rx_channel_cfg rx_cfg = { 0 }; 1559 u32 max_desc_num = AM65_CPSW_MAX_RX_DESC; 1560 struct device *dev = common->dev; 1561 u32 hdesc_size; 1562 u32 fdqring_id; 1563 int i, ret = 0; 1564 1565 hdesc_size = cppi5_hdesc_calc_size(true, AM65_CPSW_NAV_PS_DATA_SIZE, 1566 AM65_CPSW_NAV_SW_DATA_SIZE); 1567 1568 rx_cfg.swdata_size = AM65_CPSW_NAV_SW_DATA_SIZE; 1569 rx_cfg.flow_id_num = AM65_CPSW_MAX_RX_FLOWS; 1570 rx_cfg.flow_id_base = common->rx_flow_id_base; 1571 1572 /* init all flows */ 1573 rx_chn->dev = dev; 1574 rx_chn->descs_num = max_desc_num; 1575 rx_chn->desc_pool = k3_cppi_desc_pool_create_name(dev, 1576 rx_chn->descs_num, 1577 hdesc_size, "rx"); 1578 if (IS_ERR(rx_chn->desc_pool)) { 1579 ret = PTR_ERR(rx_chn->desc_pool); 1580 dev_err(dev, "Failed to create rx poll %d\n", ret); 1581 goto err; 1582 } 1583 1584 rx_chn->rx_chn = k3_udma_glue_request_rx_chn(dev, "rx", &rx_cfg); 1585 if (IS_ERR(rx_chn->rx_chn)) { 1586 ret = PTR_ERR(rx_chn->rx_chn); 1587 dev_err(dev, "Failed to request rx dma channel %d\n", ret); 1588 goto err; 1589 } 1590 1591 common->rx_flow_id_base = 1592 k3_udma_glue_rx_get_flow_id_base(rx_chn->rx_chn); 1593 dev_info(dev, "set new flow-id-base %u\n", common->rx_flow_id_base); 1594 1595 fdqring_id = K3_RINGACC_RING_ID_ANY; 1596 for (i = 0; i < rx_cfg.flow_id_num; i++) { 1597 struct k3_ring_cfg rxring_cfg = { 1598 .elm_size = K3_RINGACC_RING_ELSIZE_8, 1599 .mode = K3_RINGACC_RING_MODE_RING, 1600 .flags = 0, 1601 }; 1602 struct k3_ring_cfg fdqring_cfg = { 1603 .elm_size = K3_RINGACC_RING_ELSIZE_8, 1604 .mode = K3_RINGACC_RING_MODE_MESSAGE, 1605 .flags = K3_RINGACC_RING_SHARED, 1606 }; 1607 struct k3_udma_glue_rx_flow_cfg rx_flow_cfg = { 1608 .rx_cfg = rxring_cfg, 1609 .rxfdq_cfg = fdqring_cfg, 1610 .ring_rxq_id = K3_RINGACC_RING_ID_ANY, 1611 .src_tag_lo_sel = 1612 K3_UDMA_GLUE_SRC_TAG_LO_USE_REMOTE_SRC_TAG, 1613 }; 1614 1615 rx_flow_cfg.ring_rxfdq0_id = fdqring_id; 1616 rx_flow_cfg.rx_cfg.size = max_desc_num; 1617 rx_flow_cfg.rxfdq_cfg.size = max_desc_num; 1618 1619 ret = k3_udma_glue_rx_flow_init(rx_chn->rx_chn, 1620 i, &rx_flow_cfg); 1621 if (ret) { 1622 dev_err(dev, "Failed to init rx flow%d %d\n", i, ret); 1623 goto err; 1624 } 1625 if (!i) 1626 fdqring_id = 1627 k3_udma_glue_rx_flow_get_fdq_id(rx_chn->rx_chn, 1628 i); 1629 1630 rx_chn->irq = k3_udma_glue_rx_get_irq(rx_chn->rx_chn, i); 1631 1632 if (rx_chn->irq <= 0) { 1633 dev_err(dev, "Failed to get rx dma irq %d\n", 1634 rx_chn->irq); 1635 ret = -ENXIO; 1636 goto err; 1637 } 1638 } 1639 1640 err: 1641 i = devm_add_action(dev, am65_cpsw_nuss_free_rx_chns, common); 1642 if (i) { 1643 dev_err(dev, "Failed to add free_rx_chns action %d\n", i); 1644 return i; 1645 } 1646 1647 return ret; 1648 } 1649 1650 static int am65_cpsw_nuss_init_host_p(struct am65_cpsw_common *common) 1651 { 1652 struct am65_cpsw_host *host_p = am65_common_get_host(common); 1653 1654 host_p->common = common; 1655 host_p->port_base = common->cpsw_base + AM65_CPSW_NU_PORTS_BASE; 1656 host_p->stat_base = common->cpsw_base + AM65_CPSW_NU_STATS_BASE; 1657 1658 return 0; 1659 } 1660 1661 static int am65_cpsw_am654_get_efuse_macid(struct device_node *of_node, 1662 int slave, u8 *mac_addr) 1663 { 1664 u32 mac_lo, mac_hi, offset; 1665 struct regmap *syscon; 1666 int ret; 1667 1668 syscon = syscon_regmap_lookup_by_phandle(of_node, "ti,syscon-efuse"); 1669 if (IS_ERR(syscon)) { 1670 if (PTR_ERR(syscon) == -ENODEV) 1671 return 0; 1672 return PTR_ERR(syscon); 1673 } 1674 1675 ret = of_property_read_u32_index(of_node, "ti,syscon-efuse", 1, 1676 &offset); 1677 if (ret) 1678 return ret; 1679 1680 regmap_read(syscon, offset, &mac_lo); 1681 regmap_read(syscon, offset + 4, &mac_hi); 1682 1683 mac_addr[0] = (mac_hi >> 8) & 0xff; 1684 mac_addr[1] = mac_hi & 0xff; 1685 mac_addr[2] = (mac_lo >> 24) & 0xff; 1686 mac_addr[3] = (mac_lo >> 16) & 0xff; 1687 mac_addr[4] = (mac_lo >> 8) & 0xff; 1688 mac_addr[5] = mac_lo & 0xff; 1689 1690 return 0; 1691 } 1692 1693 static int am65_cpsw_init_cpts(struct am65_cpsw_common *common) 1694 { 1695 struct device *dev = common->dev; 1696 struct device_node *node; 1697 struct am65_cpts *cpts; 1698 void __iomem *reg_base; 1699 1700 if (!IS_ENABLED(CONFIG_TI_K3_AM65_CPTS)) 1701 return 0; 1702 1703 node = of_get_child_by_name(dev->of_node, "cpts"); 1704 if (!node) { 1705 dev_err(dev, "%s cpts not found\n", __func__); 1706 return -ENOENT; 1707 } 1708 1709 reg_base = common->cpsw_base + AM65_CPSW_NU_CPTS_BASE; 1710 cpts = am65_cpts_create(dev, reg_base, node); 1711 if (IS_ERR(cpts)) { 1712 int ret = PTR_ERR(cpts); 1713 1714 if (ret == -EOPNOTSUPP) { 1715 dev_info(dev, "cpts disabled\n"); 1716 return 0; 1717 } 1718 1719 dev_err(dev, "cpts create err %d\n", ret); 1720 return ret; 1721 } 1722 common->cpts = cpts; 1723 1724 return 0; 1725 } 1726 1727 static int am65_cpsw_nuss_init_slave_ports(struct am65_cpsw_common *common) 1728 { 1729 struct device_node *node, *port_np; 1730 struct device *dev = common->dev; 1731 int ret; 1732 1733 node = of_get_child_by_name(dev->of_node, "ethernet-ports"); 1734 if (!node) 1735 return -ENOENT; 1736 1737 for_each_child_of_node(node, port_np) { 1738 struct am65_cpsw_port *port; 1739 const void *mac_addr; 1740 u32 port_id; 1741 1742 /* it is not a slave port node, continue */ 1743 if (strcmp(port_np->name, "port")) 1744 continue; 1745 1746 ret = of_property_read_u32(port_np, "reg", &port_id); 1747 if (ret < 0) { 1748 dev_err(dev, "%pOF error reading port_id %d\n", 1749 port_np, ret); 1750 return ret; 1751 } 1752 1753 if (!port_id || port_id > common->port_num) { 1754 dev_err(dev, "%pOF has invalid port_id %u %s\n", 1755 port_np, port_id, port_np->name); 1756 return -EINVAL; 1757 } 1758 1759 port = am65_common_get_port(common, port_id); 1760 port->port_id = port_id; 1761 port->common = common; 1762 port->port_base = common->cpsw_base + AM65_CPSW_NU_PORTS_BASE + 1763 AM65_CPSW_NU_PORTS_OFFSET * (port_id); 1764 port->stat_base = common->cpsw_base + AM65_CPSW_NU_STATS_BASE + 1765 (AM65_CPSW_NU_STATS_PORT_OFFSET * port_id); 1766 port->name = of_get_property(port_np, "label", NULL); 1767 port->fetch_ram_base = 1768 common->cpsw_base + AM65_CPSW_NU_FRAM_BASE + 1769 (AM65_CPSW_NU_FRAM_PORT_OFFSET * (port_id - 1)); 1770 1771 port->slave.mac_sl = cpsw_sl_get("am65", dev, port->port_base); 1772 if (IS_ERR(port->slave.mac_sl)) 1773 return PTR_ERR(port->slave.mac_sl); 1774 1775 port->disabled = !of_device_is_available(port_np); 1776 if (port->disabled) 1777 continue; 1778 1779 port->slave.ifphy = devm_of_phy_get(dev, port_np, NULL); 1780 if (IS_ERR(port->slave.ifphy)) { 1781 ret = PTR_ERR(port->slave.ifphy); 1782 dev_err(dev, "%pOF error retrieving port phy: %d\n", 1783 port_np, ret); 1784 return ret; 1785 } 1786 1787 port->slave.mac_only = 1788 of_property_read_bool(port_np, "ti,mac-only"); 1789 1790 /* get phy/link info */ 1791 if (of_phy_is_fixed_link(port_np)) { 1792 ret = of_phy_register_fixed_link(port_np); 1793 if (ret) { 1794 if (ret != -EPROBE_DEFER) 1795 dev_err(dev, "%pOF failed to register fixed-link phy: %d\n", 1796 port_np, ret); 1797 return ret; 1798 } 1799 port->slave.phy_node = of_node_get(port_np); 1800 } else { 1801 port->slave.phy_node = 1802 of_parse_phandle(port_np, "phy-handle", 0); 1803 } 1804 1805 if (!port->slave.phy_node) { 1806 dev_err(dev, 1807 "slave[%d] no phy found\n", port_id); 1808 return -ENODEV; 1809 } 1810 1811 ret = of_get_phy_mode(port_np, &port->slave.phy_if); 1812 if (ret) { 1813 dev_err(dev, "%pOF read phy-mode err %d\n", 1814 port_np, ret); 1815 return ret; 1816 } 1817 1818 mac_addr = of_get_mac_address(port_np); 1819 if (!IS_ERR(mac_addr)) { 1820 ether_addr_copy(port->slave.mac_addr, mac_addr); 1821 } else if (am65_cpsw_am654_get_efuse_macid(port_np, 1822 port->port_id, 1823 port->slave.mac_addr) || 1824 !is_valid_ether_addr(port->slave.mac_addr)) { 1825 random_ether_addr(port->slave.mac_addr); 1826 dev_err(dev, "Use random MAC address\n"); 1827 } 1828 } 1829 of_node_put(node); 1830 1831 return 0; 1832 } 1833 1834 static void am65_cpsw_pcpu_stats_free(void *data) 1835 { 1836 struct am65_cpsw_ndev_stats __percpu *stats = data; 1837 1838 free_percpu(stats); 1839 } 1840 1841 static int am65_cpsw_nuss_init_ndev_2g(struct am65_cpsw_common *common) 1842 { 1843 struct am65_cpsw_ndev_priv *ndev_priv; 1844 struct device *dev = common->dev; 1845 struct am65_cpsw_port *port; 1846 int ret; 1847 1848 port = am65_common_get_port(common, 1); 1849 1850 /* alloc netdev */ 1851 port->ndev = devm_alloc_etherdev_mqs(common->dev, 1852 sizeof(struct am65_cpsw_ndev_priv), 1853 AM65_CPSW_MAX_TX_QUEUES, 1854 AM65_CPSW_MAX_RX_QUEUES); 1855 if (!port->ndev) { 1856 dev_err(dev, "error allocating slave net_device %u\n", 1857 port->port_id); 1858 return -ENOMEM; 1859 } 1860 1861 ndev_priv = netdev_priv(port->ndev); 1862 ndev_priv->port = port; 1863 ndev_priv->msg_enable = AM65_CPSW_DEBUG; 1864 SET_NETDEV_DEV(port->ndev, dev); 1865 1866 ether_addr_copy(port->ndev->dev_addr, port->slave.mac_addr); 1867 1868 port->ndev->min_mtu = AM65_CPSW_MIN_PACKET_SIZE; 1869 port->ndev->max_mtu = AM65_CPSW_MAX_PACKET_SIZE; 1870 port->ndev->hw_features = NETIF_F_SG | 1871 NETIF_F_RXCSUM | 1872 NETIF_F_HW_CSUM; 1873 port->ndev->features = port->ndev->hw_features | 1874 NETIF_F_HW_VLAN_CTAG_FILTER; 1875 port->ndev->vlan_features |= NETIF_F_SG; 1876 port->ndev->netdev_ops = &am65_cpsw_nuss_netdev_ops_2g; 1877 port->ndev->ethtool_ops = &am65_cpsw_ethtool_ops_slave; 1878 1879 /* Disable TX checksum offload by default due to HW bug */ 1880 if (common->pdata->quirks & AM65_CPSW_QUIRK_I2027_NO_TX_CSUM) 1881 port->ndev->features &= ~NETIF_F_HW_CSUM; 1882 1883 ndev_priv->stats = netdev_alloc_pcpu_stats(struct am65_cpsw_ndev_stats); 1884 if (!ndev_priv->stats) 1885 return -ENOMEM; 1886 1887 ret = devm_add_action_or_reset(dev, am65_cpsw_pcpu_stats_free, 1888 ndev_priv->stats); 1889 if (ret) { 1890 dev_err(dev, "Failed to add percpu stat free action %d\n", ret); 1891 return ret; 1892 } 1893 1894 netif_napi_add(port->ndev, &common->napi_rx, 1895 am65_cpsw_nuss_rx_poll, NAPI_POLL_WEIGHT); 1896 1897 return ret; 1898 } 1899 1900 static int am65_cpsw_nuss_ndev_add_napi_2g(struct am65_cpsw_common *common) 1901 { 1902 struct device *dev = common->dev; 1903 struct am65_cpsw_port *port; 1904 int i, ret = 0; 1905 1906 port = am65_common_get_port(common, 1); 1907 1908 for (i = 0; i < common->tx_ch_num; i++) { 1909 struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[i]; 1910 1911 netif_tx_napi_add(port->ndev, &tx_chn->napi_tx, 1912 am65_cpsw_nuss_tx_poll, NAPI_POLL_WEIGHT); 1913 1914 ret = devm_request_irq(dev, tx_chn->irq, 1915 am65_cpsw_nuss_tx_irq, 1916 IRQF_TRIGGER_HIGH, 1917 tx_chn->tx_chn_name, tx_chn); 1918 if (ret) { 1919 dev_err(dev, "failure requesting tx%u irq %u, %d\n", 1920 tx_chn->id, tx_chn->irq, ret); 1921 goto err; 1922 } 1923 } 1924 1925 err: 1926 return ret; 1927 } 1928 1929 static int am65_cpsw_nuss_ndev_reg_2g(struct am65_cpsw_common *common) 1930 { 1931 struct device *dev = common->dev; 1932 struct am65_cpsw_port *port; 1933 int ret = 0; 1934 1935 port = am65_common_get_port(common, 1); 1936 ret = am65_cpsw_nuss_ndev_add_napi_2g(common); 1937 if (ret) 1938 goto err; 1939 1940 ret = devm_request_irq(dev, common->rx_chns.irq, 1941 am65_cpsw_nuss_rx_irq, 1942 IRQF_TRIGGER_HIGH, dev_name(dev), common); 1943 if (ret) { 1944 dev_err(dev, "failure requesting rx irq %u, %d\n", 1945 common->rx_chns.irq, ret); 1946 goto err; 1947 } 1948 1949 ret = register_netdev(port->ndev); 1950 if (ret) 1951 dev_err(dev, "error registering slave net device %d\n", ret); 1952 1953 /* can't auto unregister ndev using devm_add_action() due to 1954 * devres release sequence in DD core for DMA 1955 */ 1956 err: 1957 return ret; 1958 } 1959 1960 int am65_cpsw_nuss_update_tx_chns(struct am65_cpsw_common *common, int num_tx) 1961 { 1962 int ret; 1963 1964 common->tx_ch_num = num_tx; 1965 ret = am65_cpsw_nuss_init_tx_chns(common); 1966 if (ret) 1967 return ret; 1968 1969 return am65_cpsw_nuss_ndev_add_napi_2g(common); 1970 } 1971 1972 static void am65_cpsw_nuss_cleanup_ndev(struct am65_cpsw_common *common) 1973 { 1974 struct am65_cpsw_port *port; 1975 int i; 1976 1977 for (i = 0; i < common->port_num; i++) { 1978 port = &common->ports[i]; 1979 if (port->ndev) 1980 unregister_netdev(port->ndev); 1981 } 1982 } 1983 1984 static const struct am65_cpsw_pdata am65x_sr1_0 = { 1985 .quirks = AM65_CPSW_QUIRK_I2027_NO_TX_CSUM, 1986 }; 1987 1988 static const struct am65_cpsw_pdata j721e_sr1_0 = { 1989 .quirks = 0, 1990 }; 1991 1992 static const struct of_device_id am65_cpsw_nuss_of_mtable[] = { 1993 { .compatible = "ti,am654-cpsw-nuss", .data = &am65x_sr1_0 }, 1994 { .compatible = "ti,j721e-cpsw-nuss", .data = &j721e_sr1_0 }, 1995 { /* sentinel */ }, 1996 }; 1997 MODULE_DEVICE_TABLE(of, am65_cpsw_nuss_of_mtable); 1998 1999 static int am65_cpsw_nuss_probe(struct platform_device *pdev) 2000 { 2001 struct cpsw_ale_params ale_params = { 0 }; 2002 const struct of_device_id *of_id; 2003 struct device *dev = &pdev->dev; 2004 struct am65_cpsw_common *common; 2005 struct device_node *node; 2006 struct resource *res; 2007 int ret, i; 2008 2009 common = devm_kzalloc(dev, sizeof(struct am65_cpsw_common), GFP_KERNEL); 2010 if (!common) 2011 return -ENOMEM; 2012 common->dev = dev; 2013 2014 of_id = of_match_device(am65_cpsw_nuss_of_mtable, dev); 2015 if (!of_id) 2016 return -EINVAL; 2017 common->pdata = of_id->data; 2018 2019 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cpsw_nuss"); 2020 common->ss_base = devm_ioremap_resource(&pdev->dev, res); 2021 if (IS_ERR(common->ss_base)) 2022 return PTR_ERR(common->ss_base); 2023 common->cpsw_base = common->ss_base + AM65_CPSW_CPSW_NU_BASE; 2024 2025 node = of_get_child_by_name(dev->of_node, "ethernet-ports"); 2026 if (!node) 2027 return -ENOENT; 2028 common->port_num = of_get_child_count(node); 2029 if (common->port_num < 1 || common->port_num > AM65_CPSW_MAX_PORTS) 2030 return -ENOENT; 2031 of_node_put(node); 2032 2033 if (common->port_num != 1) 2034 return -EOPNOTSUPP; 2035 2036 common->rx_flow_id_base = -1; 2037 init_completion(&common->tdown_complete); 2038 common->tx_ch_num = 1; 2039 common->pf_p0_rx_ptype_rrobin = false; 2040 2041 ret = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(48)); 2042 if (ret) { 2043 dev_err(dev, "error setting dma mask: %d\n", ret); 2044 return ret; 2045 } 2046 2047 common->ports = devm_kcalloc(dev, common->port_num, 2048 sizeof(*common->ports), 2049 GFP_KERNEL); 2050 if (!common->ports) 2051 return -ENOMEM; 2052 2053 pm_runtime_enable(dev); 2054 ret = pm_runtime_get_sync(dev); 2055 if (ret < 0) { 2056 pm_runtime_put_noidle(dev); 2057 pm_runtime_disable(dev); 2058 return ret; 2059 } 2060 2061 node = of_get_child_by_name(dev->of_node, "mdio"); 2062 if (!node) { 2063 dev_warn(dev, "MDIO node not found\n"); 2064 } else if (of_device_is_available(node)) { 2065 struct platform_device *mdio_pdev; 2066 2067 mdio_pdev = of_platform_device_create(node, NULL, dev); 2068 if (!mdio_pdev) { 2069 ret = -ENODEV; 2070 goto err_pm_clear; 2071 } 2072 2073 common->mdio_dev = &mdio_pdev->dev; 2074 } 2075 of_node_put(node); 2076 2077 am65_cpsw_nuss_get_ver(common); 2078 2079 /* init tx channels */ 2080 ret = am65_cpsw_nuss_init_tx_chns(common); 2081 if (ret) 2082 goto err_of_clear; 2083 ret = am65_cpsw_nuss_init_rx_chns(common); 2084 if (ret) 2085 goto err_of_clear; 2086 2087 ret = am65_cpsw_nuss_init_host_p(common); 2088 if (ret) 2089 goto err_of_clear; 2090 2091 ret = am65_cpsw_nuss_init_slave_ports(common); 2092 if (ret) 2093 goto err_of_clear; 2094 2095 /* init common data */ 2096 ale_params.dev = dev; 2097 ale_params.ale_ageout = AM65_CPSW_ALE_AGEOUT_DEFAULT; 2098 ale_params.ale_entries = 0; 2099 ale_params.ale_ports = common->port_num + 1; 2100 ale_params.ale_regs = common->cpsw_base + AM65_CPSW_NU_ALE_BASE; 2101 ale_params.nu_switch_ale = true; 2102 2103 common->ale = cpsw_ale_create(&ale_params); 2104 if (IS_ERR(common->ale)) { 2105 dev_err(dev, "error initializing ale engine\n"); 2106 ret = PTR_ERR(common->ale); 2107 goto err_of_clear; 2108 } 2109 2110 ret = am65_cpsw_init_cpts(common); 2111 if (ret) 2112 goto err_of_clear; 2113 2114 /* init ports */ 2115 for (i = 0; i < common->port_num; i++) 2116 am65_cpsw_nuss_slave_disable_unused(&common->ports[i]); 2117 2118 dev_set_drvdata(dev, common); 2119 2120 ret = am65_cpsw_nuss_init_ndev_2g(common); 2121 if (ret) 2122 goto err_of_clear; 2123 2124 ret = am65_cpsw_nuss_ndev_reg_2g(common); 2125 if (ret) 2126 goto err_of_clear; 2127 2128 pm_runtime_put(dev); 2129 return 0; 2130 2131 err_of_clear: 2132 of_platform_device_destroy(common->mdio_dev, NULL); 2133 err_pm_clear: 2134 pm_runtime_put_sync(dev); 2135 pm_runtime_disable(dev); 2136 return ret; 2137 } 2138 2139 static int am65_cpsw_nuss_remove(struct platform_device *pdev) 2140 { 2141 struct device *dev = &pdev->dev; 2142 struct am65_cpsw_common *common; 2143 int ret; 2144 2145 common = dev_get_drvdata(dev); 2146 2147 ret = pm_runtime_get_sync(&pdev->dev); 2148 if (ret < 0) { 2149 pm_runtime_put_noidle(&pdev->dev); 2150 return ret; 2151 } 2152 2153 /* must unregister ndevs here because DD release_driver routine calls 2154 * dma_deconfigure(dev) before devres_release_all(dev) 2155 */ 2156 am65_cpsw_nuss_cleanup_ndev(common); 2157 2158 of_platform_device_destroy(common->mdio_dev, NULL); 2159 2160 pm_runtime_put_sync(&pdev->dev); 2161 pm_runtime_disable(&pdev->dev); 2162 return 0; 2163 } 2164 2165 static struct platform_driver am65_cpsw_nuss_driver = { 2166 .driver = { 2167 .name = AM65_CPSW_DRV_NAME, 2168 .of_match_table = am65_cpsw_nuss_of_mtable, 2169 }, 2170 .probe = am65_cpsw_nuss_probe, 2171 .remove = am65_cpsw_nuss_remove, 2172 }; 2173 2174 module_platform_driver(am65_cpsw_nuss_driver); 2175 2176 MODULE_LICENSE("GPL v2"); 2177 MODULE_AUTHOR("Grygorii Strashko <grygorii.strashko@ti.com>"); 2178 MODULE_DESCRIPTION("TI AM65 CPSW Ethernet driver"); 2179