1 // SPDX-License-Identifier: GPL-2.0 2 /* Texas Instruments K3 AM65 Ethernet Switch SubSystem Driver 3 * 4 * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ 5 * 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/etherdevice.h> 10 #include <linux/if_vlan.h> 11 #include <linux/interrupt.h> 12 #include <linux/irqdomain.h> 13 #include <linux/kernel.h> 14 #include <linux/kmemleak.h> 15 #include <linux/module.h> 16 #include <linux/netdevice.h> 17 #include <linux/net_tstamp.h> 18 #include <linux/of.h> 19 #include <linux/of_mdio.h> 20 #include <linux/of_net.h> 21 #include <linux/of_device.h> 22 #include <linux/of_platform.h> 23 #include <linux/phylink.h> 24 #include <linux/phy/phy.h> 25 #include <linux/platform_device.h> 26 #include <linux/pm_runtime.h> 27 #include <linux/regmap.h> 28 #include <linux/rtnetlink.h> 29 #include <linux/mfd/syscon.h> 30 #include <linux/sys_soc.h> 31 #include <linux/dma/ti-cppi5.h> 32 #include <linux/dma/k3-udma-glue.h> 33 #include <net/switchdev.h> 34 35 #include "cpsw_ale.h" 36 #include "cpsw_sl.h" 37 #include "am65-cpsw-nuss.h" 38 #include "am65-cpsw-switchdev.h" 39 #include "k3-cppi-desc-pool.h" 40 #include "am65-cpts.h" 41 42 #define AM65_CPSW_SS_BASE 0x0 43 #define AM65_CPSW_SGMII_BASE 0x100 44 #define AM65_CPSW_XGMII_BASE 0x2100 45 #define AM65_CPSW_CPSW_NU_BASE 0x20000 46 #define AM65_CPSW_NU_PORTS_BASE 0x1000 47 #define AM65_CPSW_NU_FRAM_BASE 0x12000 48 #define AM65_CPSW_NU_STATS_BASE 0x1a000 49 #define AM65_CPSW_NU_ALE_BASE 0x1e000 50 #define AM65_CPSW_NU_CPTS_BASE 0x1d000 51 52 #define AM65_CPSW_NU_PORTS_OFFSET 0x1000 53 #define AM65_CPSW_NU_STATS_PORT_OFFSET 0x200 54 #define AM65_CPSW_NU_FRAM_PORT_OFFSET 0x200 55 56 #define AM65_CPSW_MAX_PORTS 8 57 58 #define AM65_CPSW_MIN_PACKET_SIZE VLAN_ETH_ZLEN 59 #define AM65_CPSW_MAX_PACKET_SIZE (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN) 60 61 #define AM65_CPSW_REG_CTL 0x004 62 #define AM65_CPSW_REG_STAT_PORT_EN 0x014 63 #define AM65_CPSW_REG_PTYPE 0x018 64 65 #define AM65_CPSW_P0_REG_CTL 0x004 66 #define AM65_CPSW_PORT0_REG_FLOW_ID_OFFSET 0x008 67 68 #define AM65_CPSW_PORT_REG_PRI_CTL 0x01c 69 #define AM65_CPSW_PORT_REG_RX_PRI_MAP 0x020 70 #define AM65_CPSW_PORT_REG_RX_MAXLEN 0x024 71 72 #define AM65_CPSW_PORTN_REG_SA_L 0x308 73 #define AM65_CPSW_PORTN_REG_SA_H 0x30c 74 #define AM65_CPSW_PORTN_REG_TS_CTL 0x310 75 #define AM65_CPSW_PORTN_REG_TS_SEQ_LTYPE_REG 0x314 76 #define AM65_CPSW_PORTN_REG_TS_VLAN_LTYPE_REG 0x318 77 #define AM65_CPSW_PORTN_REG_TS_CTL_LTYPE2 0x31C 78 79 #define AM65_CPSW_SGMII_CONTROL_REG 0x010 80 #define AM65_CPSW_SGMII_MR_ADV_ABILITY_REG 0x018 81 #define AM65_CPSW_SGMII_CONTROL_MR_AN_ENABLE BIT(0) 82 83 #define AM65_CPSW_CTL_VLAN_AWARE BIT(1) 84 #define AM65_CPSW_CTL_P0_ENABLE BIT(2) 85 #define AM65_CPSW_CTL_P0_TX_CRC_REMOVE BIT(13) 86 #define AM65_CPSW_CTL_P0_RX_PAD BIT(14) 87 88 /* AM65_CPSW_P0_REG_CTL */ 89 #define AM65_CPSW_P0_REG_CTL_RX_CHECKSUM_EN BIT(0) 90 #define AM65_CPSW_P0_REG_CTL_RX_REMAP_VLAN BIT(16) 91 92 /* AM65_CPSW_PORT_REG_PRI_CTL */ 93 #define AM65_CPSW_PORT_REG_PRI_CTL_RX_PTYPE_RROBIN BIT(8) 94 95 /* AM65_CPSW_PN_TS_CTL register fields */ 96 #define AM65_CPSW_PN_TS_CTL_TX_ANX_F_EN BIT(4) 97 #define AM65_CPSW_PN_TS_CTL_TX_VLAN_LT1_EN BIT(5) 98 #define AM65_CPSW_PN_TS_CTL_TX_VLAN_LT2_EN BIT(6) 99 #define AM65_CPSW_PN_TS_CTL_TX_ANX_D_EN BIT(7) 100 #define AM65_CPSW_PN_TS_CTL_TX_ANX_E_EN BIT(10) 101 #define AM65_CPSW_PN_TS_CTL_TX_HOST_TS_EN BIT(11) 102 #define AM65_CPSW_PN_TS_CTL_MSG_TYPE_EN_SHIFT 16 103 104 /* AM65_CPSW_PORTN_REG_TS_SEQ_LTYPE_REG register fields */ 105 #define AM65_CPSW_PN_TS_SEQ_ID_OFFSET_SHIFT 16 106 107 /* AM65_CPSW_PORTN_REG_TS_CTL_LTYPE2 */ 108 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_107 BIT(16) 109 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_129 BIT(17) 110 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_130 BIT(18) 111 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_131 BIT(19) 112 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_132 BIT(20) 113 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_319 BIT(21) 114 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_320 BIT(22) 115 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_TTL_NONZERO BIT(23) 116 117 /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */ 118 #define AM65_CPSW_TS_EVENT_MSG_TYPE_BITS (BIT(0) | BIT(1) | BIT(2) | BIT(3)) 119 120 #define AM65_CPSW_TS_SEQ_ID_OFFSET (0x1e) 121 122 #define AM65_CPSW_TS_TX_ANX_ALL_EN \ 123 (AM65_CPSW_PN_TS_CTL_TX_ANX_D_EN | \ 124 AM65_CPSW_PN_TS_CTL_TX_ANX_E_EN | \ 125 AM65_CPSW_PN_TS_CTL_TX_ANX_F_EN) 126 127 #define AM65_CPSW_ALE_AGEOUT_DEFAULT 30 128 /* Number of TX/RX descriptors */ 129 #define AM65_CPSW_MAX_TX_DESC 500 130 #define AM65_CPSW_MAX_RX_DESC 500 131 132 #define AM65_CPSW_NAV_PS_DATA_SIZE 16 133 #define AM65_CPSW_NAV_SW_DATA_SIZE 16 134 135 #define AM65_CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_DRV | NETIF_MSG_LINK | \ 136 NETIF_MSG_IFUP | NETIF_MSG_PROBE | NETIF_MSG_IFDOWN | \ 137 NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR) 138 139 static void am65_cpsw_port_set_sl_mac(struct am65_cpsw_port *slave, 140 const u8 *dev_addr) 141 { 142 u32 mac_hi = (dev_addr[0] << 0) | (dev_addr[1] << 8) | 143 (dev_addr[2] << 16) | (dev_addr[3] << 24); 144 u32 mac_lo = (dev_addr[4] << 0) | (dev_addr[5] << 8); 145 146 writel(mac_hi, slave->port_base + AM65_CPSW_PORTN_REG_SA_H); 147 writel(mac_lo, slave->port_base + AM65_CPSW_PORTN_REG_SA_L); 148 } 149 150 static void am65_cpsw_sl_ctl_reset(struct am65_cpsw_port *port) 151 { 152 cpsw_sl_reset(port->slave.mac_sl, 100); 153 /* Max length register has to be restored after MAC SL reset */ 154 writel(AM65_CPSW_MAX_PACKET_SIZE, 155 port->port_base + AM65_CPSW_PORT_REG_RX_MAXLEN); 156 } 157 158 static void am65_cpsw_nuss_get_ver(struct am65_cpsw_common *common) 159 { 160 common->nuss_ver = readl(common->ss_base); 161 common->cpsw_ver = readl(common->cpsw_base); 162 dev_info(common->dev, 163 "initializing am65 cpsw nuss version 0x%08X, cpsw version 0x%08X Ports: %u quirks:%08x\n", 164 common->nuss_ver, 165 common->cpsw_ver, 166 common->port_num + 1, 167 common->pdata.quirks); 168 } 169 170 static int am65_cpsw_nuss_ndo_slave_add_vid(struct net_device *ndev, 171 __be16 proto, u16 vid) 172 { 173 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 174 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 175 u32 port_mask, unreg_mcast = 0; 176 int ret; 177 178 if (!common->is_emac_mode) 179 return 0; 180 181 if (!netif_running(ndev) || !vid) 182 return 0; 183 184 ret = pm_runtime_resume_and_get(common->dev); 185 if (ret < 0) 186 return ret; 187 188 port_mask = BIT(port->port_id) | ALE_PORT_HOST; 189 if (!vid) 190 unreg_mcast = port_mask; 191 dev_info(common->dev, "Adding vlan %d to vlan filter\n", vid); 192 ret = cpsw_ale_vlan_add_modify(common->ale, vid, port_mask, 193 unreg_mcast, port_mask, 0); 194 195 pm_runtime_put(common->dev); 196 return ret; 197 } 198 199 static int am65_cpsw_nuss_ndo_slave_kill_vid(struct net_device *ndev, 200 __be16 proto, u16 vid) 201 { 202 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 203 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 204 int ret; 205 206 if (!common->is_emac_mode) 207 return 0; 208 209 if (!netif_running(ndev) || !vid) 210 return 0; 211 212 ret = pm_runtime_resume_and_get(common->dev); 213 if (ret < 0) 214 return ret; 215 216 dev_info(common->dev, "Removing vlan %d from vlan filter\n", vid); 217 ret = cpsw_ale_del_vlan(common->ale, vid, 218 BIT(port->port_id) | ALE_PORT_HOST); 219 220 pm_runtime_put(common->dev); 221 return ret; 222 } 223 224 static void am65_cpsw_slave_set_promisc(struct am65_cpsw_port *port, 225 bool promisc) 226 { 227 struct am65_cpsw_common *common = port->common; 228 229 if (promisc && !common->is_emac_mode) { 230 dev_dbg(common->dev, "promisc mode requested in switch mode"); 231 return; 232 } 233 234 if (promisc) { 235 /* Enable promiscuous mode */ 236 cpsw_ale_control_set(common->ale, port->port_id, 237 ALE_PORT_MACONLY_CAF, 1); 238 dev_dbg(common->dev, "promisc enabled\n"); 239 } else { 240 /* Disable promiscuous mode */ 241 cpsw_ale_control_set(common->ale, port->port_id, 242 ALE_PORT_MACONLY_CAF, 0); 243 dev_dbg(common->dev, "promisc disabled\n"); 244 } 245 } 246 247 static void am65_cpsw_nuss_ndo_slave_set_rx_mode(struct net_device *ndev) 248 { 249 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 250 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 251 u32 port_mask; 252 bool promisc; 253 254 promisc = !!(ndev->flags & IFF_PROMISC); 255 am65_cpsw_slave_set_promisc(port, promisc); 256 257 if (promisc) 258 return; 259 260 /* Restore allmulti on vlans if necessary */ 261 cpsw_ale_set_allmulti(common->ale, 262 ndev->flags & IFF_ALLMULTI, port->port_id); 263 264 port_mask = ALE_PORT_HOST; 265 /* Clear all mcast from ALE */ 266 cpsw_ale_flush_multicast(common->ale, port_mask, -1); 267 268 if (!netdev_mc_empty(ndev)) { 269 struct netdev_hw_addr *ha; 270 271 /* program multicast address list into ALE register */ 272 netdev_for_each_mc_addr(ha, ndev) { 273 cpsw_ale_add_mcast(common->ale, ha->addr, 274 port_mask, 0, 0, 0); 275 } 276 } 277 } 278 279 static void am65_cpsw_nuss_ndo_host_tx_timeout(struct net_device *ndev, 280 unsigned int txqueue) 281 { 282 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 283 struct am65_cpsw_tx_chn *tx_chn; 284 struct netdev_queue *netif_txq; 285 unsigned long trans_start; 286 287 netif_txq = netdev_get_tx_queue(ndev, txqueue); 288 tx_chn = &common->tx_chns[txqueue]; 289 trans_start = READ_ONCE(netif_txq->trans_start); 290 291 netdev_err(ndev, "txq:%d DRV_XOFF:%d tmo:%u dql_avail:%d free_desc:%zu\n", 292 txqueue, 293 netif_tx_queue_stopped(netif_txq), 294 jiffies_to_msecs(jiffies - trans_start), 295 dql_avail(&netif_txq->dql), 296 k3_cppi_desc_pool_avail(tx_chn->desc_pool)); 297 298 if (netif_tx_queue_stopped(netif_txq)) { 299 /* try recover if stopped by us */ 300 txq_trans_update(netif_txq); 301 netif_tx_wake_queue(netif_txq); 302 } 303 } 304 305 static int am65_cpsw_nuss_rx_push(struct am65_cpsw_common *common, 306 struct sk_buff *skb) 307 { 308 struct am65_cpsw_rx_chn *rx_chn = &common->rx_chns; 309 struct cppi5_host_desc_t *desc_rx; 310 struct device *dev = common->dev; 311 u32 pkt_len = skb_tailroom(skb); 312 dma_addr_t desc_dma; 313 dma_addr_t buf_dma; 314 void *swdata; 315 316 desc_rx = k3_cppi_desc_pool_alloc(rx_chn->desc_pool); 317 if (!desc_rx) { 318 dev_err(dev, "Failed to allocate RXFDQ descriptor\n"); 319 return -ENOMEM; 320 } 321 desc_dma = k3_cppi_desc_pool_virt2dma(rx_chn->desc_pool, desc_rx); 322 323 buf_dma = dma_map_single(rx_chn->dma_dev, skb->data, pkt_len, 324 DMA_FROM_DEVICE); 325 if (unlikely(dma_mapping_error(rx_chn->dma_dev, buf_dma))) { 326 k3_cppi_desc_pool_free(rx_chn->desc_pool, desc_rx); 327 dev_err(dev, "Failed to map rx skb buffer\n"); 328 return -EINVAL; 329 } 330 331 cppi5_hdesc_init(desc_rx, CPPI5_INFO0_HDESC_EPIB_PRESENT, 332 AM65_CPSW_NAV_PS_DATA_SIZE); 333 k3_udma_glue_rx_dma_to_cppi5_addr(rx_chn->rx_chn, &buf_dma); 334 cppi5_hdesc_attach_buf(desc_rx, buf_dma, skb_tailroom(skb), buf_dma, skb_tailroom(skb)); 335 swdata = cppi5_hdesc_get_swdata(desc_rx); 336 *((void **)swdata) = skb; 337 338 return k3_udma_glue_push_rx_chn(rx_chn->rx_chn, 0, desc_rx, desc_dma); 339 } 340 341 void am65_cpsw_nuss_set_p0_ptype(struct am65_cpsw_common *common) 342 { 343 struct am65_cpsw_host *host_p = am65_common_get_host(common); 344 u32 val, pri_map; 345 346 /* P0 set Receive Priority Type */ 347 val = readl(host_p->port_base + AM65_CPSW_PORT_REG_PRI_CTL); 348 349 if (common->pf_p0_rx_ptype_rrobin) { 350 val |= AM65_CPSW_PORT_REG_PRI_CTL_RX_PTYPE_RROBIN; 351 /* Enet Ports fifos works in fixed priority mode only, so 352 * reset P0_Rx_Pri_Map so all packet will go in Enet fifo 0 353 */ 354 pri_map = 0x0; 355 } else { 356 val &= ~AM65_CPSW_PORT_REG_PRI_CTL_RX_PTYPE_RROBIN; 357 /* restore P0_Rx_Pri_Map */ 358 pri_map = 0x76543210; 359 } 360 361 writel(pri_map, host_p->port_base + AM65_CPSW_PORT_REG_RX_PRI_MAP); 362 writel(val, host_p->port_base + AM65_CPSW_PORT_REG_PRI_CTL); 363 } 364 365 static void am65_cpsw_init_host_port_switch(struct am65_cpsw_common *common); 366 static void am65_cpsw_init_host_port_emac(struct am65_cpsw_common *common); 367 static void am65_cpsw_init_port_switch_ale(struct am65_cpsw_port *port); 368 static void am65_cpsw_init_port_emac_ale(struct am65_cpsw_port *port); 369 370 static int am65_cpsw_nuss_common_open(struct am65_cpsw_common *common) 371 { 372 struct am65_cpsw_host *host_p = am65_common_get_host(common); 373 int port_idx, i, ret; 374 struct sk_buff *skb; 375 u32 val, port_mask; 376 377 if (common->usage_count) 378 return 0; 379 380 /* Control register */ 381 writel(AM65_CPSW_CTL_P0_ENABLE | AM65_CPSW_CTL_P0_TX_CRC_REMOVE | 382 AM65_CPSW_CTL_VLAN_AWARE | AM65_CPSW_CTL_P0_RX_PAD, 383 common->cpsw_base + AM65_CPSW_REG_CTL); 384 /* Max length register */ 385 writel(AM65_CPSW_MAX_PACKET_SIZE, 386 host_p->port_base + AM65_CPSW_PORT_REG_RX_MAXLEN); 387 /* set base flow_id */ 388 writel(common->rx_flow_id_base, 389 host_p->port_base + AM65_CPSW_PORT0_REG_FLOW_ID_OFFSET); 390 writel(AM65_CPSW_P0_REG_CTL_RX_CHECKSUM_EN | AM65_CPSW_P0_REG_CTL_RX_REMAP_VLAN, 391 host_p->port_base + AM65_CPSW_P0_REG_CTL); 392 393 am65_cpsw_nuss_set_p0_ptype(common); 394 395 /* enable statistic */ 396 val = BIT(HOST_PORT_NUM); 397 for (port_idx = 0; port_idx < common->port_num; port_idx++) { 398 struct am65_cpsw_port *port = &common->ports[port_idx]; 399 400 if (!port->disabled) 401 val |= BIT(port->port_id); 402 } 403 writel(val, common->cpsw_base + AM65_CPSW_REG_STAT_PORT_EN); 404 405 /* disable priority elevation */ 406 writel(0, common->cpsw_base + AM65_CPSW_REG_PTYPE); 407 408 cpsw_ale_start(common->ale); 409 410 /* limit to one RX flow only */ 411 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, 412 ALE_DEFAULT_THREAD_ID, 0); 413 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, 414 ALE_DEFAULT_THREAD_ENABLE, 1); 415 /* switch to vlan unaware mode */ 416 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_VLAN_AWARE, 1); 417 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, 418 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); 419 420 /* default vlan cfg: create mask based on enabled ports */ 421 port_mask = GENMASK(common->port_num, 0) & 422 ~common->disabled_ports_mask; 423 424 cpsw_ale_add_vlan(common->ale, 0, port_mask, 425 port_mask, port_mask, 426 port_mask & ~ALE_PORT_HOST); 427 428 if (common->is_emac_mode) 429 am65_cpsw_init_host_port_emac(common); 430 else 431 am65_cpsw_init_host_port_switch(common); 432 433 am65_cpsw_qos_tx_p0_rate_init(common); 434 435 for (i = 0; i < common->rx_chns.descs_num; i++) { 436 skb = __netdev_alloc_skb_ip_align(NULL, 437 AM65_CPSW_MAX_PACKET_SIZE, 438 GFP_KERNEL); 439 if (!skb) { 440 dev_err(common->dev, "cannot allocate skb\n"); 441 return -ENOMEM; 442 } 443 444 ret = am65_cpsw_nuss_rx_push(common, skb); 445 if (ret < 0) { 446 dev_err(common->dev, 447 "cannot submit skb to channel rx, error %d\n", 448 ret); 449 kfree_skb(skb); 450 return ret; 451 } 452 kmemleak_not_leak(skb); 453 } 454 k3_udma_glue_enable_rx_chn(common->rx_chns.rx_chn); 455 456 for (i = 0; i < common->tx_ch_num; i++) { 457 ret = k3_udma_glue_enable_tx_chn(common->tx_chns[i].tx_chn); 458 if (ret) 459 return ret; 460 napi_enable(&common->tx_chns[i].napi_tx); 461 } 462 463 napi_enable(&common->napi_rx); 464 if (common->rx_irq_disabled) { 465 common->rx_irq_disabled = false; 466 enable_irq(common->rx_chns.irq); 467 } 468 469 dev_dbg(common->dev, "cpsw_nuss started\n"); 470 return 0; 471 } 472 473 static void am65_cpsw_nuss_tx_cleanup(void *data, dma_addr_t desc_dma); 474 static void am65_cpsw_nuss_rx_cleanup(void *data, dma_addr_t desc_dma); 475 476 static int am65_cpsw_nuss_common_stop(struct am65_cpsw_common *common) 477 { 478 int i; 479 480 if (common->usage_count != 1) 481 return 0; 482 483 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, 484 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 485 486 /* shutdown tx channels */ 487 atomic_set(&common->tdown_cnt, common->tx_ch_num); 488 /* ensure new tdown_cnt value is visible */ 489 smp_mb__after_atomic(); 490 reinit_completion(&common->tdown_complete); 491 492 for (i = 0; i < common->tx_ch_num; i++) 493 k3_udma_glue_tdown_tx_chn(common->tx_chns[i].tx_chn, false); 494 495 i = wait_for_completion_timeout(&common->tdown_complete, 496 msecs_to_jiffies(1000)); 497 if (!i) 498 dev_err(common->dev, "tx timeout\n"); 499 for (i = 0; i < common->tx_ch_num; i++) 500 napi_disable(&common->tx_chns[i].napi_tx); 501 502 for (i = 0; i < common->tx_ch_num; i++) { 503 k3_udma_glue_reset_tx_chn(common->tx_chns[i].tx_chn, 504 &common->tx_chns[i], 505 am65_cpsw_nuss_tx_cleanup); 506 k3_udma_glue_disable_tx_chn(common->tx_chns[i].tx_chn); 507 } 508 509 reinit_completion(&common->tdown_complete); 510 k3_udma_glue_tdown_rx_chn(common->rx_chns.rx_chn, true); 511 512 if (common->pdata.quirks & AM64_CPSW_QUIRK_DMA_RX_TDOWN_IRQ) { 513 i = wait_for_completion_timeout(&common->tdown_complete, msecs_to_jiffies(1000)); 514 if (!i) 515 dev_err(common->dev, "rx teardown timeout\n"); 516 } 517 518 napi_disable(&common->napi_rx); 519 520 for (i = 0; i < AM65_CPSW_MAX_RX_FLOWS; i++) 521 k3_udma_glue_reset_rx_chn(common->rx_chns.rx_chn, i, 522 &common->rx_chns, 523 am65_cpsw_nuss_rx_cleanup, !!i); 524 525 k3_udma_glue_disable_rx_chn(common->rx_chns.rx_chn); 526 527 cpsw_ale_stop(common->ale); 528 529 writel(0, common->cpsw_base + AM65_CPSW_REG_CTL); 530 writel(0, common->cpsw_base + AM65_CPSW_REG_STAT_PORT_EN); 531 532 dev_dbg(common->dev, "cpsw_nuss stopped\n"); 533 return 0; 534 } 535 536 static int am65_cpsw_nuss_ndo_slave_stop(struct net_device *ndev) 537 { 538 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 539 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 540 int ret; 541 542 phylink_stop(port->slave.phylink); 543 544 netif_tx_stop_all_queues(ndev); 545 546 phylink_disconnect_phy(port->slave.phylink); 547 548 ret = am65_cpsw_nuss_common_stop(common); 549 if (ret) 550 return ret; 551 552 common->usage_count--; 553 pm_runtime_put(common->dev); 554 return 0; 555 } 556 557 static int cpsw_restore_vlans(struct net_device *vdev, int vid, void *arg) 558 { 559 struct am65_cpsw_port *port = arg; 560 561 if (!vdev) 562 return 0; 563 564 return am65_cpsw_nuss_ndo_slave_add_vid(port->ndev, 0, vid); 565 } 566 567 static int am65_cpsw_nuss_ndo_slave_open(struct net_device *ndev) 568 { 569 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 570 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 571 int ret, i; 572 u32 reg; 573 574 ret = pm_runtime_resume_and_get(common->dev); 575 if (ret < 0) 576 return ret; 577 578 /* Idle MAC port */ 579 cpsw_sl_ctl_set(port->slave.mac_sl, CPSW_SL_CTL_CMD_IDLE); 580 cpsw_sl_wait_for_idle(port->slave.mac_sl, 100); 581 cpsw_sl_ctl_reset(port->slave.mac_sl); 582 583 /* soft reset MAC */ 584 cpsw_sl_reg_write(port->slave.mac_sl, CPSW_SL_SOFT_RESET, 1); 585 mdelay(1); 586 reg = cpsw_sl_reg_read(port->slave.mac_sl, CPSW_SL_SOFT_RESET); 587 if (reg) { 588 dev_err(common->dev, "soft RESET didn't complete\n"); 589 ret = -ETIMEDOUT; 590 goto runtime_put; 591 } 592 593 /* Notify the stack of the actual queue counts. */ 594 ret = netif_set_real_num_tx_queues(ndev, common->tx_ch_num); 595 if (ret) { 596 dev_err(common->dev, "cannot set real number of tx queues\n"); 597 goto runtime_put; 598 } 599 600 ret = netif_set_real_num_rx_queues(ndev, AM65_CPSW_MAX_RX_QUEUES); 601 if (ret) { 602 dev_err(common->dev, "cannot set real number of rx queues\n"); 603 goto runtime_put; 604 } 605 606 for (i = 0; i < common->tx_ch_num; i++) { 607 struct netdev_queue *txq = netdev_get_tx_queue(ndev, i); 608 609 netdev_tx_reset_queue(txq); 610 txq->tx_maxrate = common->tx_chns[i].rate_mbps; 611 } 612 613 ret = am65_cpsw_nuss_common_open(common); 614 if (ret) 615 goto runtime_put; 616 617 common->usage_count++; 618 619 am65_cpsw_port_set_sl_mac(port, ndev->dev_addr); 620 621 if (common->is_emac_mode) 622 am65_cpsw_init_port_emac_ale(port); 623 else 624 am65_cpsw_init_port_switch_ale(port); 625 626 /* mac_sl should be configured via phy-link interface */ 627 am65_cpsw_sl_ctl_reset(port); 628 629 ret = phylink_of_phy_connect(port->slave.phylink, port->slave.phy_node, 0); 630 if (ret) 631 goto error_cleanup; 632 633 /* restore vlan configurations */ 634 vlan_for_each(ndev, cpsw_restore_vlans, port); 635 636 /* Initialize QoS */ 637 am65_cpsw_qos_mqprio_init(port); 638 639 phylink_start(port->slave.phylink); 640 641 return 0; 642 643 error_cleanup: 644 am65_cpsw_nuss_ndo_slave_stop(ndev); 645 return ret; 646 647 runtime_put: 648 pm_runtime_put(common->dev); 649 return ret; 650 } 651 652 static void am65_cpsw_nuss_rx_cleanup(void *data, dma_addr_t desc_dma) 653 { 654 struct am65_cpsw_rx_chn *rx_chn = data; 655 struct cppi5_host_desc_t *desc_rx; 656 struct sk_buff *skb; 657 dma_addr_t buf_dma; 658 u32 buf_dma_len; 659 void **swdata; 660 661 desc_rx = k3_cppi_desc_pool_dma2virt(rx_chn->desc_pool, desc_dma); 662 swdata = cppi5_hdesc_get_swdata(desc_rx); 663 skb = *swdata; 664 cppi5_hdesc_get_obuf(desc_rx, &buf_dma, &buf_dma_len); 665 k3_udma_glue_rx_cppi5_to_dma_addr(rx_chn->rx_chn, &buf_dma); 666 667 dma_unmap_single(rx_chn->dma_dev, buf_dma, buf_dma_len, DMA_FROM_DEVICE); 668 k3_cppi_desc_pool_free(rx_chn->desc_pool, desc_rx); 669 670 dev_kfree_skb_any(skb); 671 } 672 673 static void am65_cpsw_nuss_rx_ts(struct sk_buff *skb, u32 *psdata) 674 { 675 struct skb_shared_hwtstamps *ssh; 676 u64 ns; 677 678 ns = ((u64)psdata[1] << 32) | psdata[0]; 679 680 ssh = skb_hwtstamps(skb); 681 memset(ssh, 0, sizeof(*ssh)); 682 ssh->hwtstamp = ns_to_ktime(ns); 683 } 684 685 /* RX psdata[2] word format - checksum information */ 686 #define AM65_CPSW_RX_PSD_CSUM_ADD GENMASK(15, 0) 687 #define AM65_CPSW_RX_PSD_CSUM_ERR BIT(16) 688 #define AM65_CPSW_RX_PSD_IS_FRAGMENT BIT(17) 689 #define AM65_CPSW_RX_PSD_IS_TCP BIT(18) 690 #define AM65_CPSW_RX_PSD_IPV6_VALID BIT(19) 691 #define AM65_CPSW_RX_PSD_IPV4_VALID BIT(20) 692 693 static void am65_cpsw_nuss_rx_csum(struct sk_buff *skb, u32 csum_info) 694 { 695 /* HW can verify IPv4/IPv6 TCP/UDP packets checksum 696 * csum information provides in psdata[2] word: 697 * AM65_CPSW_RX_PSD_CSUM_ERR bit - indicates csum error 698 * AM65_CPSW_RX_PSD_IPV6_VALID and AM65_CPSW_RX_PSD_IPV4_VALID 699 * bits - indicates IPv4/IPv6 packet 700 * AM65_CPSW_RX_PSD_IS_FRAGMENT bit - indicates fragmented packet 701 * AM65_CPSW_RX_PSD_CSUM_ADD has value 0xFFFF for non fragmented packets 702 * or csum value for fragmented packets if !AM65_CPSW_RX_PSD_CSUM_ERR 703 */ 704 skb_checksum_none_assert(skb); 705 706 if (unlikely(!(skb->dev->features & NETIF_F_RXCSUM))) 707 return; 708 709 if ((csum_info & (AM65_CPSW_RX_PSD_IPV6_VALID | 710 AM65_CPSW_RX_PSD_IPV4_VALID)) && 711 !(csum_info & AM65_CPSW_RX_PSD_CSUM_ERR)) { 712 /* csum for fragmented packets is unsupported */ 713 if (!(csum_info & AM65_CPSW_RX_PSD_IS_FRAGMENT)) 714 skb->ip_summed = CHECKSUM_UNNECESSARY; 715 } 716 } 717 718 static int am65_cpsw_nuss_rx_packets(struct am65_cpsw_common *common, 719 u32 flow_idx) 720 { 721 struct am65_cpsw_rx_chn *rx_chn = &common->rx_chns; 722 u32 buf_dma_len, pkt_len, port_id = 0, csum_info; 723 struct am65_cpsw_ndev_priv *ndev_priv; 724 struct am65_cpsw_ndev_stats *stats; 725 struct cppi5_host_desc_t *desc_rx; 726 struct device *dev = common->dev; 727 struct sk_buff *skb, *new_skb; 728 dma_addr_t desc_dma, buf_dma; 729 struct am65_cpsw_port *port; 730 struct net_device *ndev; 731 void **swdata; 732 u32 *psdata; 733 int ret = 0; 734 735 ret = k3_udma_glue_pop_rx_chn(rx_chn->rx_chn, flow_idx, &desc_dma); 736 if (ret) { 737 if (ret != -ENODATA) 738 dev_err(dev, "RX: pop chn fail %d\n", ret); 739 return ret; 740 } 741 742 if (cppi5_desc_is_tdcm(desc_dma)) { 743 dev_dbg(dev, "%s RX tdown flow: %u\n", __func__, flow_idx); 744 if (common->pdata.quirks & AM64_CPSW_QUIRK_DMA_RX_TDOWN_IRQ) 745 complete(&common->tdown_complete); 746 return 0; 747 } 748 749 desc_rx = k3_cppi_desc_pool_dma2virt(rx_chn->desc_pool, desc_dma); 750 dev_dbg(dev, "%s flow_idx: %u desc %pad\n", 751 __func__, flow_idx, &desc_dma); 752 753 swdata = cppi5_hdesc_get_swdata(desc_rx); 754 skb = *swdata; 755 cppi5_hdesc_get_obuf(desc_rx, &buf_dma, &buf_dma_len); 756 k3_udma_glue_rx_cppi5_to_dma_addr(rx_chn->rx_chn, &buf_dma); 757 pkt_len = cppi5_hdesc_get_pktlen(desc_rx); 758 cppi5_desc_get_tags_ids(&desc_rx->hdr, &port_id, NULL); 759 dev_dbg(dev, "%s rx port_id:%d\n", __func__, port_id); 760 port = am65_common_get_port(common, port_id); 761 ndev = port->ndev; 762 skb->dev = ndev; 763 764 psdata = cppi5_hdesc_get_psdata(desc_rx); 765 /* add RX timestamp */ 766 if (port->rx_ts_enabled) 767 am65_cpsw_nuss_rx_ts(skb, psdata); 768 csum_info = psdata[2]; 769 dev_dbg(dev, "%s rx csum_info:%#x\n", __func__, csum_info); 770 771 dma_unmap_single(rx_chn->dma_dev, buf_dma, buf_dma_len, DMA_FROM_DEVICE); 772 773 k3_cppi_desc_pool_free(rx_chn->desc_pool, desc_rx); 774 775 new_skb = netdev_alloc_skb_ip_align(ndev, AM65_CPSW_MAX_PACKET_SIZE); 776 if (new_skb) { 777 ndev_priv = netdev_priv(ndev); 778 am65_cpsw_nuss_set_offload_fwd_mark(skb, ndev_priv->offload_fwd_mark); 779 skb_put(skb, pkt_len); 780 skb->protocol = eth_type_trans(skb, ndev); 781 am65_cpsw_nuss_rx_csum(skb, csum_info); 782 napi_gro_receive(&common->napi_rx, skb); 783 784 stats = this_cpu_ptr(ndev_priv->stats); 785 786 u64_stats_update_begin(&stats->syncp); 787 stats->rx_packets++; 788 stats->rx_bytes += pkt_len; 789 u64_stats_update_end(&stats->syncp); 790 kmemleak_not_leak(new_skb); 791 } else { 792 ndev->stats.rx_dropped++; 793 new_skb = skb; 794 } 795 796 if (netif_dormant(ndev)) { 797 dev_kfree_skb_any(new_skb); 798 ndev->stats.rx_dropped++; 799 return 0; 800 } 801 802 ret = am65_cpsw_nuss_rx_push(common, new_skb); 803 if (WARN_ON(ret < 0)) { 804 dev_kfree_skb_any(new_skb); 805 ndev->stats.rx_errors++; 806 ndev->stats.rx_dropped++; 807 } 808 809 return ret; 810 } 811 812 static int am65_cpsw_nuss_rx_poll(struct napi_struct *napi_rx, int budget) 813 { 814 struct am65_cpsw_common *common = am65_cpsw_napi_to_common(napi_rx); 815 int flow = AM65_CPSW_MAX_RX_FLOWS; 816 int cur_budget, ret; 817 int num_rx = 0; 818 819 /* process every flow */ 820 while (flow--) { 821 cur_budget = budget - num_rx; 822 823 while (cur_budget--) { 824 ret = am65_cpsw_nuss_rx_packets(common, flow); 825 if (ret) 826 break; 827 num_rx++; 828 } 829 830 if (num_rx >= budget) 831 break; 832 } 833 834 dev_dbg(common->dev, "%s num_rx:%d %d\n", __func__, num_rx, budget); 835 836 if (num_rx < budget && napi_complete_done(napi_rx, num_rx)) { 837 if (common->rx_irq_disabled) { 838 common->rx_irq_disabled = false; 839 enable_irq(common->rx_chns.irq); 840 } 841 } 842 843 return num_rx; 844 } 845 846 static void am65_cpsw_nuss_xmit_free(struct am65_cpsw_tx_chn *tx_chn, 847 struct cppi5_host_desc_t *desc) 848 { 849 struct cppi5_host_desc_t *first_desc, *next_desc; 850 dma_addr_t buf_dma, next_desc_dma; 851 u32 buf_dma_len; 852 853 first_desc = desc; 854 next_desc = first_desc; 855 856 cppi5_hdesc_get_obuf(first_desc, &buf_dma, &buf_dma_len); 857 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &buf_dma); 858 859 dma_unmap_single(tx_chn->dma_dev, buf_dma, buf_dma_len, DMA_TO_DEVICE); 860 861 next_desc_dma = cppi5_hdesc_get_next_hbdesc(first_desc); 862 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &next_desc_dma); 863 while (next_desc_dma) { 864 next_desc = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool, 865 next_desc_dma); 866 cppi5_hdesc_get_obuf(next_desc, &buf_dma, &buf_dma_len); 867 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &buf_dma); 868 869 dma_unmap_page(tx_chn->dma_dev, buf_dma, buf_dma_len, 870 DMA_TO_DEVICE); 871 872 next_desc_dma = cppi5_hdesc_get_next_hbdesc(next_desc); 873 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &next_desc_dma); 874 875 k3_cppi_desc_pool_free(tx_chn->desc_pool, next_desc); 876 } 877 878 k3_cppi_desc_pool_free(tx_chn->desc_pool, first_desc); 879 } 880 881 static void am65_cpsw_nuss_tx_cleanup(void *data, dma_addr_t desc_dma) 882 { 883 struct am65_cpsw_tx_chn *tx_chn = data; 884 struct cppi5_host_desc_t *desc_tx; 885 struct sk_buff *skb; 886 void **swdata; 887 888 desc_tx = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool, desc_dma); 889 swdata = cppi5_hdesc_get_swdata(desc_tx); 890 skb = *(swdata); 891 am65_cpsw_nuss_xmit_free(tx_chn, desc_tx); 892 893 dev_kfree_skb_any(skb); 894 } 895 896 static struct sk_buff * 897 am65_cpsw_nuss_tx_compl_packet(struct am65_cpsw_tx_chn *tx_chn, 898 dma_addr_t desc_dma) 899 { 900 struct am65_cpsw_ndev_priv *ndev_priv; 901 struct am65_cpsw_ndev_stats *stats; 902 struct cppi5_host_desc_t *desc_tx; 903 struct net_device *ndev; 904 struct sk_buff *skb; 905 void **swdata; 906 907 desc_tx = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool, 908 desc_dma); 909 swdata = cppi5_hdesc_get_swdata(desc_tx); 910 skb = *(swdata); 911 am65_cpsw_nuss_xmit_free(tx_chn, desc_tx); 912 913 ndev = skb->dev; 914 915 am65_cpts_tx_timestamp(tx_chn->common->cpts, skb); 916 917 ndev_priv = netdev_priv(ndev); 918 stats = this_cpu_ptr(ndev_priv->stats); 919 u64_stats_update_begin(&stats->syncp); 920 stats->tx_packets++; 921 stats->tx_bytes += skb->len; 922 u64_stats_update_end(&stats->syncp); 923 924 return skb; 925 } 926 927 static void am65_cpsw_nuss_tx_wake(struct am65_cpsw_tx_chn *tx_chn, struct net_device *ndev, 928 struct netdev_queue *netif_txq) 929 { 930 if (netif_tx_queue_stopped(netif_txq)) { 931 /* Check whether the queue is stopped due to stalled 932 * tx dma, if the queue is stopped then wake the queue 933 * as we have free desc for tx 934 */ 935 __netif_tx_lock(netif_txq, smp_processor_id()); 936 if (netif_running(ndev) && 937 (k3_cppi_desc_pool_avail(tx_chn->desc_pool) >= MAX_SKB_FRAGS)) 938 netif_tx_wake_queue(netif_txq); 939 940 __netif_tx_unlock(netif_txq); 941 } 942 } 943 944 static int am65_cpsw_nuss_tx_compl_packets(struct am65_cpsw_common *common, 945 int chn, unsigned int budget) 946 { 947 struct device *dev = common->dev; 948 struct am65_cpsw_tx_chn *tx_chn; 949 struct netdev_queue *netif_txq; 950 unsigned int total_bytes = 0; 951 struct net_device *ndev; 952 struct sk_buff *skb; 953 dma_addr_t desc_dma; 954 int res, num_tx = 0; 955 956 tx_chn = &common->tx_chns[chn]; 957 958 while (true) { 959 spin_lock(&tx_chn->lock); 960 res = k3_udma_glue_pop_tx_chn(tx_chn->tx_chn, &desc_dma); 961 spin_unlock(&tx_chn->lock); 962 if (res == -ENODATA) 963 break; 964 965 if (cppi5_desc_is_tdcm(desc_dma)) { 966 if (atomic_dec_and_test(&common->tdown_cnt)) 967 complete(&common->tdown_complete); 968 break; 969 } 970 971 skb = am65_cpsw_nuss_tx_compl_packet(tx_chn, desc_dma); 972 total_bytes = skb->len; 973 ndev = skb->dev; 974 napi_consume_skb(skb, budget); 975 num_tx++; 976 977 netif_txq = netdev_get_tx_queue(ndev, chn); 978 979 netdev_tx_completed_queue(netif_txq, num_tx, total_bytes); 980 981 am65_cpsw_nuss_tx_wake(tx_chn, ndev, netif_txq); 982 } 983 984 dev_dbg(dev, "%s:%u pkt:%d\n", __func__, chn, num_tx); 985 986 return num_tx; 987 } 988 989 static int am65_cpsw_nuss_tx_compl_packets_2g(struct am65_cpsw_common *common, 990 int chn, unsigned int budget) 991 { 992 struct device *dev = common->dev; 993 struct am65_cpsw_tx_chn *tx_chn; 994 struct netdev_queue *netif_txq; 995 unsigned int total_bytes = 0; 996 struct net_device *ndev; 997 struct sk_buff *skb; 998 dma_addr_t desc_dma; 999 int res, num_tx = 0; 1000 1001 tx_chn = &common->tx_chns[chn]; 1002 1003 while (true) { 1004 res = k3_udma_glue_pop_tx_chn(tx_chn->tx_chn, &desc_dma); 1005 if (res == -ENODATA) 1006 break; 1007 1008 if (cppi5_desc_is_tdcm(desc_dma)) { 1009 if (atomic_dec_and_test(&common->tdown_cnt)) 1010 complete(&common->tdown_complete); 1011 break; 1012 } 1013 1014 skb = am65_cpsw_nuss_tx_compl_packet(tx_chn, desc_dma); 1015 1016 ndev = skb->dev; 1017 total_bytes += skb->len; 1018 napi_consume_skb(skb, budget); 1019 num_tx++; 1020 } 1021 1022 if (!num_tx) 1023 return 0; 1024 1025 netif_txq = netdev_get_tx_queue(ndev, chn); 1026 1027 netdev_tx_completed_queue(netif_txq, num_tx, total_bytes); 1028 1029 am65_cpsw_nuss_tx_wake(tx_chn, ndev, netif_txq); 1030 1031 dev_dbg(dev, "%s:%u pkt:%d\n", __func__, chn, num_tx); 1032 1033 return num_tx; 1034 } 1035 1036 static int am65_cpsw_nuss_tx_poll(struct napi_struct *napi_tx, int budget) 1037 { 1038 struct am65_cpsw_tx_chn *tx_chn = am65_cpsw_napi_to_tx_chn(napi_tx); 1039 int num_tx; 1040 1041 if (AM65_CPSW_IS_CPSW2G(tx_chn->common)) 1042 num_tx = am65_cpsw_nuss_tx_compl_packets_2g(tx_chn->common, tx_chn->id, budget); 1043 else 1044 num_tx = am65_cpsw_nuss_tx_compl_packets(tx_chn->common, tx_chn->id, budget); 1045 1046 if (num_tx >= budget) 1047 return budget; 1048 1049 if (napi_complete_done(napi_tx, num_tx)) 1050 enable_irq(tx_chn->irq); 1051 1052 return 0; 1053 } 1054 1055 static irqreturn_t am65_cpsw_nuss_rx_irq(int irq, void *dev_id) 1056 { 1057 struct am65_cpsw_common *common = dev_id; 1058 1059 common->rx_irq_disabled = true; 1060 disable_irq_nosync(irq); 1061 napi_schedule(&common->napi_rx); 1062 1063 return IRQ_HANDLED; 1064 } 1065 1066 static irqreturn_t am65_cpsw_nuss_tx_irq(int irq, void *dev_id) 1067 { 1068 struct am65_cpsw_tx_chn *tx_chn = dev_id; 1069 1070 disable_irq_nosync(irq); 1071 napi_schedule(&tx_chn->napi_tx); 1072 1073 return IRQ_HANDLED; 1074 } 1075 1076 static netdev_tx_t am65_cpsw_nuss_ndo_slave_xmit(struct sk_buff *skb, 1077 struct net_device *ndev) 1078 { 1079 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 1080 struct cppi5_host_desc_t *first_desc, *next_desc, *cur_desc; 1081 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1082 struct device *dev = common->dev; 1083 struct am65_cpsw_tx_chn *tx_chn; 1084 struct netdev_queue *netif_txq; 1085 dma_addr_t desc_dma, buf_dma; 1086 int ret, q_idx, i; 1087 void **swdata; 1088 u32 *psdata; 1089 u32 pkt_len; 1090 1091 /* padding enabled in hw */ 1092 pkt_len = skb_headlen(skb); 1093 1094 /* SKB TX timestamp */ 1095 if (port->tx_ts_enabled) 1096 am65_cpts_prep_tx_timestamp(common->cpts, skb); 1097 1098 q_idx = skb_get_queue_mapping(skb); 1099 dev_dbg(dev, "%s skb_queue:%d\n", __func__, q_idx); 1100 1101 tx_chn = &common->tx_chns[q_idx]; 1102 netif_txq = netdev_get_tx_queue(ndev, q_idx); 1103 1104 /* Map the linear buffer */ 1105 buf_dma = dma_map_single(tx_chn->dma_dev, skb->data, pkt_len, 1106 DMA_TO_DEVICE); 1107 if (unlikely(dma_mapping_error(tx_chn->dma_dev, buf_dma))) { 1108 dev_err(dev, "Failed to map tx skb buffer\n"); 1109 ndev->stats.tx_errors++; 1110 goto err_free_skb; 1111 } 1112 1113 first_desc = k3_cppi_desc_pool_alloc(tx_chn->desc_pool); 1114 if (!first_desc) { 1115 dev_dbg(dev, "Failed to allocate descriptor\n"); 1116 dma_unmap_single(tx_chn->dma_dev, buf_dma, pkt_len, 1117 DMA_TO_DEVICE); 1118 goto busy_stop_q; 1119 } 1120 1121 cppi5_hdesc_init(first_desc, CPPI5_INFO0_HDESC_EPIB_PRESENT, 1122 AM65_CPSW_NAV_PS_DATA_SIZE); 1123 cppi5_desc_set_pktids(&first_desc->hdr, 0, 0x3FFF); 1124 cppi5_hdesc_set_pkttype(first_desc, 0x7); 1125 cppi5_desc_set_tags_ids(&first_desc->hdr, 0, port->port_id); 1126 1127 k3_udma_glue_tx_dma_to_cppi5_addr(tx_chn->tx_chn, &buf_dma); 1128 cppi5_hdesc_attach_buf(first_desc, buf_dma, pkt_len, buf_dma, pkt_len); 1129 swdata = cppi5_hdesc_get_swdata(first_desc); 1130 *(swdata) = skb; 1131 psdata = cppi5_hdesc_get_psdata(first_desc); 1132 1133 /* HW csum offload if enabled */ 1134 psdata[2] = 0; 1135 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) { 1136 unsigned int cs_start, cs_offset; 1137 1138 cs_start = skb_transport_offset(skb); 1139 cs_offset = cs_start + skb->csum_offset; 1140 /* HW numerates bytes starting from 1 */ 1141 psdata[2] = ((cs_offset + 1) << 24) | 1142 ((cs_start + 1) << 16) | (skb->len - cs_start); 1143 dev_dbg(dev, "%s tx psdata:%#x\n", __func__, psdata[2]); 1144 } 1145 1146 if (!skb_is_nonlinear(skb)) 1147 goto done_tx; 1148 1149 dev_dbg(dev, "fragmented SKB\n"); 1150 1151 /* Handle the case where skb is fragmented in pages */ 1152 cur_desc = first_desc; 1153 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1154 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1155 u32 frag_size = skb_frag_size(frag); 1156 1157 next_desc = k3_cppi_desc_pool_alloc(tx_chn->desc_pool); 1158 if (!next_desc) { 1159 dev_err(dev, "Failed to allocate descriptor\n"); 1160 goto busy_free_descs; 1161 } 1162 1163 buf_dma = skb_frag_dma_map(tx_chn->dma_dev, frag, 0, frag_size, 1164 DMA_TO_DEVICE); 1165 if (unlikely(dma_mapping_error(tx_chn->dma_dev, buf_dma))) { 1166 dev_err(dev, "Failed to map tx skb page\n"); 1167 k3_cppi_desc_pool_free(tx_chn->desc_pool, next_desc); 1168 ndev->stats.tx_errors++; 1169 goto err_free_descs; 1170 } 1171 1172 cppi5_hdesc_reset_hbdesc(next_desc); 1173 k3_udma_glue_tx_dma_to_cppi5_addr(tx_chn->tx_chn, &buf_dma); 1174 cppi5_hdesc_attach_buf(next_desc, 1175 buf_dma, frag_size, buf_dma, frag_size); 1176 1177 desc_dma = k3_cppi_desc_pool_virt2dma(tx_chn->desc_pool, 1178 next_desc); 1179 k3_udma_glue_tx_dma_to_cppi5_addr(tx_chn->tx_chn, &desc_dma); 1180 cppi5_hdesc_link_hbdesc(cur_desc, desc_dma); 1181 1182 pkt_len += frag_size; 1183 cur_desc = next_desc; 1184 } 1185 WARN_ON(pkt_len != skb->len); 1186 1187 done_tx: 1188 skb_tx_timestamp(skb); 1189 1190 /* report bql before sending packet */ 1191 netdev_tx_sent_queue(netif_txq, pkt_len); 1192 1193 cppi5_hdesc_set_pktlen(first_desc, pkt_len); 1194 desc_dma = k3_cppi_desc_pool_virt2dma(tx_chn->desc_pool, first_desc); 1195 if (AM65_CPSW_IS_CPSW2G(common)) { 1196 ret = k3_udma_glue_push_tx_chn(tx_chn->tx_chn, first_desc, desc_dma); 1197 } else { 1198 spin_lock_bh(&tx_chn->lock); 1199 ret = k3_udma_glue_push_tx_chn(tx_chn->tx_chn, first_desc, desc_dma); 1200 spin_unlock_bh(&tx_chn->lock); 1201 } 1202 if (ret) { 1203 dev_err(dev, "can't push desc %d\n", ret); 1204 /* inform bql */ 1205 netdev_tx_completed_queue(netif_txq, 1, pkt_len); 1206 ndev->stats.tx_errors++; 1207 goto err_free_descs; 1208 } 1209 1210 if (k3_cppi_desc_pool_avail(tx_chn->desc_pool) < MAX_SKB_FRAGS) { 1211 netif_tx_stop_queue(netif_txq); 1212 /* Barrier, so that stop_queue visible to other cpus */ 1213 smp_mb__after_atomic(); 1214 dev_dbg(dev, "netif_tx_stop_queue %d\n", q_idx); 1215 1216 /* re-check for smp */ 1217 if (k3_cppi_desc_pool_avail(tx_chn->desc_pool) >= 1218 MAX_SKB_FRAGS) { 1219 netif_tx_wake_queue(netif_txq); 1220 dev_dbg(dev, "netif_tx_wake_queue %d\n", q_idx); 1221 } 1222 } 1223 1224 return NETDEV_TX_OK; 1225 1226 err_free_descs: 1227 am65_cpsw_nuss_xmit_free(tx_chn, first_desc); 1228 err_free_skb: 1229 ndev->stats.tx_dropped++; 1230 dev_kfree_skb_any(skb); 1231 return NETDEV_TX_OK; 1232 1233 busy_free_descs: 1234 am65_cpsw_nuss_xmit_free(tx_chn, first_desc); 1235 busy_stop_q: 1236 netif_tx_stop_queue(netif_txq); 1237 return NETDEV_TX_BUSY; 1238 } 1239 1240 static int am65_cpsw_nuss_ndo_slave_set_mac_address(struct net_device *ndev, 1241 void *addr) 1242 { 1243 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 1244 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1245 struct sockaddr *sockaddr = (struct sockaddr *)addr; 1246 int ret; 1247 1248 ret = eth_prepare_mac_addr_change(ndev, addr); 1249 if (ret < 0) 1250 return ret; 1251 1252 ret = pm_runtime_resume_and_get(common->dev); 1253 if (ret < 0) 1254 return ret; 1255 1256 cpsw_ale_del_ucast(common->ale, ndev->dev_addr, 1257 HOST_PORT_NUM, 0, 0); 1258 cpsw_ale_add_ucast(common->ale, sockaddr->sa_data, 1259 HOST_PORT_NUM, ALE_SECURE, 0); 1260 1261 am65_cpsw_port_set_sl_mac(port, addr); 1262 eth_commit_mac_addr_change(ndev, sockaddr); 1263 1264 pm_runtime_put(common->dev); 1265 1266 return 0; 1267 } 1268 1269 static int am65_cpsw_nuss_hwtstamp_set(struct net_device *ndev, 1270 struct ifreq *ifr) 1271 { 1272 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 1273 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1274 u32 ts_ctrl, seq_id, ts_ctrl_ltype2, ts_vlan_ltype; 1275 struct hwtstamp_config cfg; 1276 1277 if (!IS_ENABLED(CONFIG_TI_K3_AM65_CPTS)) 1278 return -EOPNOTSUPP; 1279 1280 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg))) 1281 return -EFAULT; 1282 1283 /* TX HW timestamp */ 1284 switch (cfg.tx_type) { 1285 case HWTSTAMP_TX_OFF: 1286 case HWTSTAMP_TX_ON: 1287 break; 1288 default: 1289 return -ERANGE; 1290 } 1291 1292 switch (cfg.rx_filter) { 1293 case HWTSTAMP_FILTER_NONE: 1294 port->rx_ts_enabled = false; 1295 break; 1296 case HWTSTAMP_FILTER_ALL: 1297 case HWTSTAMP_FILTER_SOME: 1298 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 1299 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 1300 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 1301 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 1302 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 1303 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 1304 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 1305 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 1306 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 1307 case HWTSTAMP_FILTER_PTP_V2_EVENT: 1308 case HWTSTAMP_FILTER_PTP_V2_SYNC: 1309 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 1310 case HWTSTAMP_FILTER_NTP_ALL: 1311 port->rx_ts_enabled = true; 1312 cfg.rx_filter = HWTSTAMP_FILTER_ALL; 1313 break; 1314 default: 1315 return -ERANGE; 1316 } 1317 1318 port->tx_ts_enabled = (cfg.tx_type == HWTSTAMP_TX_ON); 1319 1320 /* cfg TX timestamp */ 1321 seq_id = (AM65_CPSW_TS_SEQ_ID_OFFSET << 1322 AM65_CPSW_PN_TS_SEQ_ID_OFFSET_SHIFT) | ETH_P_1588; 1323 1324 ts_vlan_ltype = ETH_P_8021Q; 1325 1326 ts_ctrl_ltype2 = ETH_P_1588 | 1327 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_107 | 1328 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_129 | 1329 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_130 | 1330 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_131 | 1331 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_132 | 1332 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_319 | 1333 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_320 | 1334 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_TTL_NONZERO; 1335 1336 ts_ctrl = AM65_CPSW_TS_EVENT_MSG_TYPE_BITS << 1337 AM65_CPSW_PN_TS_CTL_MSG_TYPE_EN_SHIFT; 1338 1339 if (port->tx_ts_enabled) 1340 ts_ctrl |= AM65_CPSW_TS_TX_ANX_ALL_EN | 1341 AM65_CPSW_PN_TS_CTL_TX_VLAN_LT1_EN; 1342 1343 writel(seq_id, port->port_base + AM65_CPSW_PORTN_REG_TS_SEQ_LTYPE_REG); 1344 writel(ts_vlan_ltype, port->port_base + 1345 AM65_CPSW_PORTN_REG_TS_VLAN_LTYPE_REG); 1346 writel(ts_ctrl_ltype2, port->port_base + 1347 AM65_CPSW_PORTN_REG_TS_CTL_LTYPE2); 1348 writel(ts_ctrl, port->port_base + AM65_CPSW_PORTN_REG_TS_CTL); 1349 1350 /* en/dis RX timestamp */ 1351 am65_cpts_rx_enable(common->cpts, port->rx_ts_enabled); 1352 1353 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 1354 } 1355 1356 static int am65_cpsw_nuss_hwtstamp_get(struct net_device *ndev, 1357 struct ifreq *ifr) 1358 { 1359 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1360 struct hwtstamp_config cfg; 1361 1362 if (!IS_ENABLED(CONFIG_TI_K3_AM65_CPTS)) 1363 return -EOPNOTSUPP; 1364 1365 cfg.flags = 0; 1366 cfg.tx_type = port->tx_ts_enabled ? 1367 HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF; 1368 cfg.rx_filter = port->rx_ts_enabled ? 1369 HWTSTAMP_FILTER_ALL : HWTSTAMP_FILTER_NONE; 1370 1371 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 1372 } 1373 1374 static int am65_cpsw_nuss_ndo_slave_ioctl(struct net_device *ndev, 1375 struct ifreq *req, int cmd) 1376 { 1377 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1378 1379 if (!netif_running(ndev)) 1380 return -EINVAL; 1381 1382 switch (cmd) { 1383 case SIOCSHWTSTAMP: 1384 return am65_cpsw_nuss_hwtstamp_set(ndev, req); 1385 case SIOCGHWTSTAMP: 1386 return am65_cpsw_nuss_hwtstamp_get(ndev, req); 1387 } 1388 1389 return phylink_mii_ioctl(port->slave.phylink, req, cmd); 1390 } 1391 1392 static void am65_cpsw_nuss_ndo_get_stats(struct net_device *dev, 1393 struct rtnl_link_stats64 *stats) 1394 { 1395 struct am65_cpsw_ndev_priv *ndev_priv = netdev_priv(dev); 1396 unsigned int start; 1397 int cpu; 1398 1399 for_each_possible_cpu(cpu) { 1400 struct am65_cpsw_ndev_stats *cpu_stats; 1401 u64 rx_packets; 1402 u64 rx_bytes; 1403 u64 tx_packets; 1404 u64 tx_bytes; 1405 1406 cpu_stats = per_cpu_ptr(ndev_priv->stats, cpu); 1407 do { 1408 start = u64_stats_fetch_begin(&cpu_stats->syncp); 1409 rx_packets = cpu_stats->rx_packets; 1410 rx_bytes = cpu_stats->rx_bytes; 1411 tx_packets = cpu_stats->tx_packets; 1412 tx_bytes = cpu_stats->tx_bytes; 1413 } while (u64_stats_fetch_retry(&cpu_stats->syncp, start)); 1414 1415 stats->rx_packets += rx_packets; 1416 stats->rx_bytes += rx_bytes; 1417 stats->tx_packets += tx_packets; 1418 stats->tx_bytes += tx_bytes; 1419 } 1420 1421 stats->rx_errors = dev->stats.rx_errors; 1422 stats->rx_dropped = dev->stats.rx_dropped; 1423 stats->tx_dropped = dev->stats.tx_dropped; 1424 } 1425 1426 static const struct net_device_ops am65_cpsw_nuss_netdev_ops = { 1427 .ndo_open = am65_cpsw_nuss_ndo_slave_open, 1428 .ndo_stop = am65_cpsw_nuss_ndo_slave_stop, 1429 .ndo_start_xmit = am65_cpsw_nuss_ndo_slave_xmit, 1430 .ndo_set_rx_mode = am65_cpsw_nuss_ndo_slave_set_rx_mode, 1431 .ndo_get_stats64 = am65_cpsw_nuss_ndo_get_stats, 1432 .ndo_validate_addr = eth_validate_addr, 1433 .ndo_set_mac_address = am65_cpsw_nuss_ndo_slave_set_mac_address, 1434 .ndo_tx_timeout = am65_cpsw_nuss_ndo_host_tx_timeout, 1435 .ndo_vlan_rx_add_vid = am65_cpsw_nuss_ndo_slave_add_vid, 1436 .ndo_vlan_rx_kill_vid = am65_cpsw_nuss_ndo_slave_kill_vid, 1437 .ndo_eth_ioctl = am65_cpsw_nuss_ndo_slave_ioctl, 1438 .ndo_setup_tc = am65_cpsw_qos_ndo_setup_tc, 1439 .ndo_set_tx_maxrate = am65_cpsw_qos_ndo_tx_p0_set_maxrate, 1440 }; 1441 1442 static void am65_cpsw_disable_phy(struct phy *phy) 1443 { 1444 phy_power_off(phy); 1445 phy_exit(phy); 1446 } 1447 1448 static int am65_cpsw_enable_phy(struct phy *phy) 1449 { 1450 int ret; 1451 1452 ret = phy_init(phy); 1453 if (ret < 0) 1454 return ret; 1455 1456 ret = phy_power_on(phy); 1457 if (ret < 0) { 1458 phy_exit(phy); 1459 return ret; 1460 } 1461 1462 return 0; 1463 } 1464 1465 static void am65_cpsw_disable_serdes_phy(struct am65_cpsw_common *common) 1466 { 1467 struct am65_cpsw_port *port; 1468 struct phy *phy; 1469 int i; 1470 1471 for (i = 0; i < common->port_num; i++) { 1472 port = &common->ports[i]; 1473 phy = port->slave.serdes_phy; 1474 if (phy) 1475 am65_cpsw_disable_phy(phy); 1476 } 1477 } 1478 1479 static int am65_cpsw_init_serdes_phy(struct device *dev, struct device_node *port_np, 1480 struct am65_cpsw_port *port) 1481 { 1482 const char *name = "serdes"; 1483 struct phy *phy; 1484 int ret; 1485 1486 phy = devm_of_phy_optional_get(dev, port_np, name); 1487 if (IS_ERR_OR_NULL(phy)) 1488 return PTR_ERR_OR_ZERO(phy); 1489 1490 /* Serdes PHY exists. Store it. */ 1491 port->slave.serdes_phy = phy; 1492 1493 ret = am65_cpsw_enable_phy(phy); 1494 if (ret < 0) 1495 goto err_phy; 1496 1497 return 0; 1498 1499 err_phy: 1500 devm_phy_put(dev, phy); 1501 return ret; 1502 } 1503 1504 static void am65_cpsw_nuss_mac_config(struct phylink_config *config, unsigned int mode, 1505 const struct phylink_link_state *state) 1506 { 1507 struct am65_cpsw_slave_data *slave = container_of(config, struct am65_cpsw_slave_data, 1508 phylink_config); 1509 struct am65_cpsw_port *port = container_of(slave, struct am65_cpsw_port, slave); 1510 struct am65_cpsw_common *common = port->common; 1511 1512 if (common->pdata.extra_modes & BIT(state->interface)) { 1513 if (state->interface == PHY_INTERFACE_MODE_SGMII) { 1514 writel(ADVERTISE_SGMII, 1515 port->sgmii_base + AM65_CPSW_SGMII_MR_ADV_ABILITY_REG); 1516 cpsw_sl_ctl_set(port->slave.mac_sl, CPSW_SL_CTL_EXT_EN); 1517 } else { 1518 cpsw_sl_ctl_clr(port->slave.mac_sl, CPSW_SL_CTL_EXT_EN); 1519 } 1520 1521 if (state->interface == PHY_INTERFACE_MODE_USXGMII) { 1522 cpsw_sl_ctl_set(port->slave.mac_sl, 1523 CPSW_SL_CTL_XGIG | CPSW_SL_CTL_XGMII_EN); 1524 } else { 1525 cpsw_sl_ctl_clr(port->slave.mac_sl, 1526 CPSW_SL_CTL_XGIG | CPSW_SL_CTL_XGMII_EN); 1527 } 1528 1529 writel(AM65_CPSW_SGMII_CONTROL_MR_AN_ENABLE, 1530 port->sgmii_base + AM65_CPSW_SGMII_CONTROL_REG); 1531 } 1532 } 1533 1534 static void am65_cpsw_nuss_mac_link_down(struct phylink_config *config, unsigned int mode, 1535 phy_interface_t interface) 1536 { 1537 struct am65_cpsw_slave_data *slave = container_of(config, struct am65_cpsw_slave_data, 1538 phylink_config); 1539 struct am65_cpsw_port *port = container_of(slave, struct am65_cpsw_port, slave); 1540 struct am65_cpsw_common *common = port->common; 1541 struct net_device *ndev = port->ndev; 1542 u32 mac_control; 1543 int tmo; 1544 1545 /* disable forwarding */ 1546 cpsw_ale_control_set(common->ale, port->port_id, ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 1547 1548 cpsw_sl_ctl_set(port->slave.mac_sl, CPSW_SL_CTL_CMD_IDLE); 1549 1550 tmo = cpsw_sl_wait_for_idle(port->slave.mac_sl, 100); 1551 dev_dbg(common->dev, "down msc_sl %08x tmo %d\n", 1552 cpsw_sl_reg_read(port->slave.mac_sl, CPSW_SL_MACSTATUS), tmo); 1553 1554 /* All the bits that am65_cpsw_nuss_mac_link_up() can possibly set */ 1555 mac_control = CPSW_SL_CTL_GMII_EN | CPSW_SL_CTL_GIG | CPSW_SL_CTL_IFCTL_A | 1556 CPSW_SL_CTL_FULLDUPLEX | CPSW_SL_CTL_RX_FLOW_EN | CPSW_SL_CTL_TX_FLOW_EN; 1557 /* If interface mode is RGMII, CPSW_SL_CTL_EXT_EN might have been set for 10 Mbps */ 1558 if (phy_interface_mode_is_rgmii(interface)) 1559 mac_control |= CPSW_SL_CTL_EXT_EN; 1560 /* Only clear those bits that can be set by am65_cpsw_nuss_mac_link_up() */ 1561 cpsw_sl_ctl_clr(port->slave.mac_sl, mac_control); 1562 1563 am65_cpsw_qos_link_down(ndev); 1564 netif_tx_stop_all_queues(ndev); 1565 } 1566 1567 static void am65_cpsw_nuss_mac_link_up(struct phylink_config *config, struct phy_device *phy, 1568 unsigned int mode, phy_interface_t interface, int speed, 1569 int duplex, bool tx_pause, bool rx_pause) 1570 { 1571 struct am65_cpsw_slave_data *slave = container_of(config, struct am65_cpsw_slave_data, 1572 phylink_config); 1573 struct am65_cpsw_port *port = container_of(slave, struct am65_cpsw_port, slave); 1574 struct am65_cpsw_common *common = port->common; 1575 u32 mac_control = CPSW_SL_CTL_GMII_EN; 1576 struct net_device *ndev = port->ndev; 1577 1578 /* Bring the port out of idle state */ 1579 cpsw_sl_ctl_clr(port->slave.mac_sl, CPSW_SL_CTL_CMD_IDLE); 1580 1581 if (speed == SPEED_1000) 1582 mac_control |= CPSW_SL_CTL_GIG; 1583 /* TODO: Verify whether in-band is necessary for 10 Mbps RGMII */ 1584 if (speed == SPEED_10 && phy_interface_mode_is_rgmii(interface)) 1585 /* Can be used with in band mode only */ 1586 mac_control |= CPSW_SL_CTL_EXT_EN; 1587 if (speed == SPEED_100 && interface == PHY_INTERFACE_MODE_RMII) 1588 mac_control |= CPSW_SL_CTL_IFCTL_A; 1589 if (duplex) 1590 mac_control |= CPSW_SL_CTL_FULLDUPLEX; 1591 1592 /* rx_pause/tx_pause */ 1593 if (rx_pause) 1594 mac_control |= CPSW_SL_CTL_RX_FLOW_EN; 1595 1596 if (tx_pause) 1597 mac_control |= CPSW_SL_CTL_TX_FLOW_EN; 1598 1599 cpsw_sl_ctl_set(port->slave.mac_sl, mac_control); 1600 1601 /* enable forwarding */ 1602 cpsw_ale_control_set(common->ale, port->port_id, ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); 1603 1604 am65_cpsw_qos_link_up(ndev, speed); 1605 netif_tx_wake_all_queues(ndev); 1606 } 1607 1608 static const struct phylink_mac_ops am65_cpsw_phylink_mac_ops = { 1609 .mac_config = am65_cpsw_nuss_mac_config, 1610 .mac_link_down = am65_cpsw_nuss_mac_link_down, 1611 .mac_link_up = am65_cpsw_nuss_mac_link_up, 1612 }; 1613 1614 static void am65_cpsw_nuss_slave_disable_unused(struct am65_cpsw_port *port) 1615 { 1616 struct am65_cpsw_common *common = port->common; 1617 1618 if (!port->disabled) 1619 return; 1620 1621 cpsw_ale_control_set(common->ale, port->port_id, 1622 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 1623 1624 cpsw_sl_reset(port->slave.mac_sl, 100); 1625 cpsw_sl_ctl_reset(port->slave.mac_sl); 1626 } 1627 1628 static void am65_cpsw_nuss_free_tx_chns(void *data) 1629 { 1630 struct am65_cpsw_common *common = data; 1631 int i; 1632 1633 for (i = 0; i < common->tx_ch_num; i++) { 1634 struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[i]; 1635 1636 if (!IS_ERR_OR_NULL(tx_chn->desc_pool)) 1637 k3_cppi_desc_pool_destroy(tx_chn->desc_pool); 1638 1639 if (!IS_ERR_OR_NULL(tx_chn->tx_chn)) 1640 k3_udma_glue_release_tx_chn(tx_chn->tx_chn); 1641 1642 memset(tx_chn, 0, sizeof(*tx_chn)); 1643 } 1644 } 1645 1646 void am65_cpsw_nuss_remove_tx_chns(struct am65_cpsw_common *common) 1647 { 1648 struct device *dev = common->dev; 1649 int i; 1650 1651 devm_remove_action(dev, am65_cpsw_nuss_free_tx_chns, common); 1652 1653 common->tx_ch_rate_msk = 0; 1654 for (i = 0; i < common->tx_ch_num; i++) { 1655 struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[i]; 1656 1657 if (tx_chn->irq) 1658 devm_free_irq(dev, tx_chn->irq, tx_chn); 1659 1660 netif_napi_del(&tx_chn->napi_tx); 1661 1662 if (!IS_ERR_OR_NULL(tx_chn->desc_pool)) 1663 k3_cppi_desc_pool_destroy(tx_chn->desc_pool); 1664 1665 if (!IS_ERR_OR_NULL(tx_chn->tx_chn)) 1666 k3_udma_glue_release_tx_chn(tx_chn->tx_chn); 1667 1668 memset(tx_chn, 0, sizeof(*tx_chn)); 1669 } 1670 } 1671 1672 static int am65_cpsw_nuss_ndev_add_tx_napi(struct am65_cpsw_common *common) 1673 { 1674 struct device *dev = common->dev; 1675 int i, ret = 0; 1676 1677 for (i = 0; i < common->tx_ch_num; i++) { 1678 struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[i]; 1679 1680 netif_napi_add_tx(common->dma_ndev, &tx_chn->napi_tx, 1681 am65_cpsw_nuss_tx_poll); 1682 1683 ret = devm_request_irq(dev, tx_chn->irq, 1684 am65_cpsw_nuss_tx_irq, 1685 IRQF_TRIGGER_HIGH, 1686 tx_chn->tx_chn_name, tx_chn); 1687 if (ret) { 1688 dev_err(dev, "failure requesting tx%u irq %u, %d\n", 1689 tx_chn->id, tx_chn->irq, ret); 1690 goto err; 1691 } 1692 } 1693 1694 err: 1695 return ret; 1696 } 1697 1698 static int am65_cpsw_nuss_init_tx_chns(struct am65_cpsw_common *common) 1699 { 1700 u32 max_desc_num = ALIGN(AM65_CPSW_MAX_TX_DESC, MAX_SKB_FRAGS); 1701 struct k3_udma_glue_tx_channel_cfg tx_cfg = { 0 }; 1702 struct device *dev = common->dev; 1703 struct k3_ring_cfg ring_cfg = { 1704 .elm_size = K3_RINGACC_RING_ELSIZE_8, 1705 .mode = K3_RINGACC_RING_MODE_RING, 1706 .flags = 0 1707 }; 1708 u32 hdesc_size; 1709 int i, ret = 0; 1710 1711 hdesc_size = cppi5_hdesc_calc_size(true, AM65_CPSW_NAV_PS_DATA_SIZE, 1712 AM65_CPSW_NAV_SW_DATA_SIZE); 1713 1714 tx_cfg.swdata_size = AM65_CPSW_NAV_SW_DATA_SIZE; 1715 tx_cfg.tx_cfg = ring_cfg; 1716 tx_cfg.txcq_cfg = ring_cfg; 1717 tx_cfg.tx_cfg.size = max_desc_num; 1718 tx_cfg.txcq_cfg.size = max_desc_num; 1719 1720 for (i = 0; i < common->tx_ch_num; i++) { 1721 struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[i]; 1722 1723 snprintf(tx_chn->tx_chn_name, 1724 sizeof(tx_chn->tx_chn_name), "tx%d", i); 1725 1726 spin_lock_init(&tx_chn->lock); 1727 tx_chn->common = common; 1728 tx_chn->id = i; 1729 tx_chn->descs_num = max_desc_num; 1730 1731 tx_chn->tx_chn = 1732 k3_udma_glue_request_tx_chn(dev, 1733 tx_chn->tx_chn_name, 1734 &tx_cfg); 1735 if (IS_ERR(tx_chn->tx_chn)) { 1736 ret = dev_err_probe(dev, PTR_ERR(tx_chn->tx_chn), 1737 "Failed to request tx dma channel\n"); 1738 goto err; 1739 } 1740 tx_chn->dma_dev = k3_udma_glue_tx_get_dma_device(tx_chn->tx_chn); 1741 1742 tx_chn->desc_pool = k3_cppi_desc_pool_create_name(tx_chn->dma_dev, 1743 tx_chn->descs_num, 1744 hdesc_size, 1745 tx_chn->tx_chn_name); 1746 if (IS_ERR(tx_chn->desc_pool)) { 1747 ret = PTR_ERR(tx_chn->desc_pool); 1748 dev_err(dev, "Failed to create poll %d\n", ret); 1749 goto err; 1750 } 1751 1752 tx_chn->irq = k3_udma_glue_tx_get_irq(tx_chn->tx_chn); 1753 if (tx_chn->irq <= 0) { 1754 dev_err(dev, "Failed to get tx dma irq %d\n", 1755 tx_chn->irq); 1756 goto err; 1757 } 1758 1759 snprintf(tx_chn->tx_chn_name, 1760 sizeof(tx_chn->tx_chn_name), "%s-tx%d", 1761 dev_name(dev), tx_chn->id); 1762 } 1763 1764 ret = am65_cpsw_nuss_ndev_add_tx_napi(common); 1765 if (ret) { 1766 dev_err(dev, "Failed to add tx NAPI %d\n", ret); 1767 goto err; 1768 } 1769 1770 err: 1771 i = devm_add_action(dev, am65_cpsw_nuss_free_tx_chns, common); 1772 if (i) { 1773 dev_err(dev, "Failed to add free_tx_chns action %d\n", i); 1774 return i; 1775 } 1776 1777 return ret; 1778 } 1779 1780 static void am65_cpsw_nuss_free_rx_chns(void *data) 1781 { 1782 struct am65_cpsw_common *common = data; 1783 struct am65_cpsw_rx_chn *rx_chn; 1784 1785 rx_chn = &common->rx_chns; 1786 1787 if (!IS_ERR_OR_NULL(rx_chn->desc_pool)) 1788 k3_cppi_desc_pool_destroy(rx_chn->desc_pool); 1789 1790 if (!IS_ERR_OR_NULL(rx_chn->rx_chn)) 1791 k3_udma_glue_release_rx_chn(rx_chn->rx_chn); 1792 } 1793 1794 static void am65_cpsw_nuss_remove_rx_chns(void *data) 1795 { 1796 struct am65_cpsw_common *common = data; 1797 struct am65_cpsw_rx_chn *rx_chn; 1798 struct device *dev = common->dev; 1799 1800 rx_chn = &common->rx_chns; 1801 devm_remove_action(dev, am65_cpsw_nuss_free_rx_chns, common); 1802 1803 if (!(rx_chn->irq < 0)) 1804 devm_free_irq(dev, rx_chn->irq, common); 1805 1806 netif_napi_del(&common->napi_rx); 1807 1808 if (!IS_ERR_OR_NULL(rx_chn->desc_pool)) 1809 k3_cppi_desc_pool_destroy(rx_chn->desc_pool); 1810 1811 if (!IS_ERR_OR_NULL(rx_chn->rx_chn)) 1812 k3_udma_glue_release_rx_chn(rx_chn->rx_chn); 1813 1814 common->rx_flow_id_base = -1; 1815 } 1816 1817 static int am65_cpsw_nuss_init_rx_chns(struct am65_cpsw_common *common) 1818 { 1819 struct am65_cpsw_rx_chn *rx_chn = &common->rx_chns; 1820 struct k3_udma_glue_rx_channel_cfg rx_cfg = { 0 }; 1821 u32 max_desc_num = AM65_CPSW_MAX_RX_DESC; 1822 struct device *dev = common->dev; 1823 u32 hdesc_size; 1824 u32 fdqring_id; 1825 int i, ret = 0; 1826 1827 hdesc_size = cppi5_hdesc_calc_size(true, AM65_CPSW_NAV_PS_DATA_SIZE, 1828 AM65_CPSW_NAV_SW_DATA_SIZE); 1829 1830 rx_cfg.swdata_size = AM65_CPSW_NAV_SW_DATA_SIZE; 1831 rx_cfg.flow_id_num = AM65_CPSW_MAX_RX_FLOWS; 1832 rx_cfg.flow_id_base = common->rx_flow_id_base; 1833 1834 /* init all flows */ 1835 rx_chn->dev = dev; 1836 rx_chn->descs_num = max_desc_num; 1837 1838 rx_chn->rx_chn = k3_udma_glue_request_rx_chn(dev, "rx", &rx_cfg); 1839 if (IS_ERR(rx_chn->rx_chn)) { 1840 ret = dev_err_probe(dev, PTR_ERR(rx_chn->rx_chn), 1841 "Failed to request rx dma channel\n"); 1842 goto err; 1843 } 1844 rx_chn->dma_dev = k3_udma_glue_rx_get_dma_device(rx_chn->rx_chn); 1845 1846 rx_chn->desc_pool = k3_cppi_desc_pool_create_name(rx_chn->dma_dev, 1847 rx_chn->descs_num, 1848 hdesc_size, "rx"); 1849 if (IS_ERR(rx_chn->desc_pool)) { 1850 ret = PTR_ERR(rx_chn->desc_pool); 1851 dev_err(dev, "Failed to create rx poll %d\n", ret); 1852 goto err; 1853 } 1854 1855 common->rx_flow_id_base = 1856 k3_udma_glue_rx_get_flow_id_base(rx_chn->rx_chn); 1857 dev_info(dev, "set new flow-id-base %u\n", common->rx_flow_id_base); 1858 1859 fdqring_id = K3_RINGACC_RING_ID_ANY; 1860 for (i = 0; i < rx_cfg.flow_id_num; i++) { 1861 struct k3_ring_cfg rxring_cfg = { 1862 .elm_size = K3_RINGACC_RING_ELSIZE_8, 1863 .mode = K3_RINGACC_RING_MODE_RING, 1864 .flags = 0, 1865 }; 1866 struct k3_ring_cfg fdqring_cfg = { 1867 .elm_size = K3_RINGACC_RING_ELSIZE_8, 1868 .flags = K3_RINGACC_RING_SHARED, 1869 }; 1870 struct k3_udma_glue_rx_flow_cfg rx_flow_cfg = { 1871 .rx_cfg = rxring_cfg, 1872 .rxfdq_cfg = fdqring_cfg, 1873 .ring_rxq_id = K3_RINGACC_RING_ID_ANY, 1874 .src_tag_lo_sel = 1875 K3_UDMA_GLUE_SRC_TAG_LO_USE_REMOTE_SRC_TAG, 1876 }; 1877 1878 rx_flow_cfg.ring_rxfdq0_id = fdqring_id; 1879 rx_flow_cfg.rx_cfg.size = max_desc_num; 1880 rx_flow_cfg.rxfdq_cfg.size = max_desc_num; 1881 rx_flow_cfg.rxfdq_cfg.mode = common->pdata.fdqring_mode; 1882 1883 ret = k3_udma_glue_rx_flow_init(rx_chn->rx_chn, 1884 i, &rx_flow_cfg); 1885 if (ret) { 1886 dev_err(dev, "Failed to init rx flow%d %d\n", i, ret); 1887 goto err; 1888 } 1889 if (!i) 1890 fdqring_id = 1891 k3_udma_glue_rx_flow_get_fdq_id(rx_chn->rx_chn, 1892 i); 1893 1894 rx_chn->irq = k3_udma_glue_rx_get_irq(rx_chn->rx_chn, i); 1895 1896 if (rx_chn->irq <= 0) { 1897 dev_err(dev, "Failed to get rx dma irq %d\n", 1898 rx_chn->irq); 1899 ret = -ENXIO; 1900 goto err; 1901 } 1902 } 1903 1904 netif_napi_add(common->dma_ndev, &common->napi_rx, 1905 am65_cpsw_nuss_rx_poll); 1906 1907 ret = devm_request_irq(dev, rx_chn->irq, 1908 am65_cpsw_nuss_rx_irq, 1909 IRQF_TRIGGER_HIGH, dev_name(dev), common); 1910 if (ret) { 1911 dev_err(dev, "failure requesting rx irq %u, %d\n", 1912 rx_chn->irq, ret); 1913 goto err; 1914 } 1915 1916 err: 1917 i = devm_add_action(dev, am65_cpsw_nuss_free_rx_chns, common); 1918 if (i) { 1919 dev_err(dev, "Failed to add free_rx_chns action %d\n", i); 1920 return i; 1921 } 1922 1923 return ret; 1924 } 1925 1926 static int am65_cpsw_nuss_init_host_p(struct am65_cpsw_common *common) 1927 { 1928 struct am65_cpsw_host *host_p = am65_common_get_host(common); 1929 1930 host_p->common = common; 1931 host_p->port_base = common->cpsw_base + AM65_CPSW_NU_PORTS_BASE; 1932 host_p->stat_base = common->cpsw_base + AM65_CPSW_NU_STATS_BASE; 1933 1934 return 0; 1935 } 1936 1937 static int am65_cpsw_am654_get_efuse_macid(struct device_node *of_node, 1938 int slave, u8 *mac_addr) 1939 { 1940 u32 mac_lo, mac_hi, offset; 1941 struct regmap *syscon; 1942 int ret; 1943 1944 syscon = syscon_regmap_lookup_by_phandle(of_node, "ti,syscon-efuse"); 1945 if (IS_ERR(syscon)) { 1946 if (PTR_ERR(syscon) == -ENODEV) 1947 return 0; 1948 return PTR_ERR(syscon); 1949 } 1950 1951 ret = of_property_read_u32_index(of_node, "ti,syscon-efuse", 1, 1952 &offset); 1953 if (ret) 1954 return ret; 1955 1956 regmap_read(syscon, offset, &mac_lo); 1957 regmap_read(syscon, offset + 4, &mac_hi); 1958 1959 mac_addr[0] = (mac_hi >> 8) & 0xff; 1960 mac_addr[1] = mac_hi & 0xff; 1961 mac_addr[2] = (mac_lo >> 24) & 0xff; 1962 mac_addr[3] = (mac_lo >> 16) & 0xff; 1963 mac_addr[4] = (mac_lo >> 8) & 0xff; 1964 mac_addr[5] = mac_lo & 0xff; 1965 1966 return 0; 1967 } 1968 1969 static int am65_cpsw_init_cpts(struct am65_cpsw_common *common) 1970 { 1971 struct device *dev = common->dev; 1972 struct device_node *node; 1973 struct am65_cpts *cpts; 1974 void __iomem *reg_base; 1975 1976 if (!IS_ENABLED(CONFIG_TI_K3_AM65_CPTS)) 1977 return 0; 1978 1979 node = of_get_child_by_name(dev->of_node, "cpts"); 1980 if (!node) { 1981 dev_err(dev, "%s cpts not found\n", __func__); 1982 return -ENOENT; 1983 } 1984 1985 reg_base = common->cpsw_base + AM65_CPSW_NU_CPTS_BASE; 1986 cpts = am65_cpts_create(dev, reg_base, node); 1987 if (IS_ERR(cpts)) { 1988 int ret = PTR_ERR(cpts); 1989 1990 of_node_put(node); 1991 dev_err(dev, "cpts create err %d\n", ret); 1992 return ret; 1993 } 1994 common->cpts = cpts; 1995 /* Forbid PM runtime if CPTS is running. 1996 * K3 CPSWxG modules may completely lose context during ON->OFF 1997 * transitions depending on integration. 1998 * AM65x/J721E MCU CPSW2G: false 1999 * J721E MAIN_CPSW9G: true 2000 */ 2001 pm_runtime_forbid(dev); 2002 2003 return 0; 2004 } 2005 2006 static int am65_cpsw_nuss_init_slave_ports(struct am65_cpsw_common *common) 2007 { 2008 struct device_node *node, *port_np; 2009 struct device *dev = common->dev; 2010 int ret; 2011 2012 node = of_get_child_by_name(dev->of_node, "ethernet-ports"); 2013 if (!node) 2014 return -ENOENT; 2015 2016 for_each_child_of_node(node, port_np) { 2017 struct am65_cpsw_port *port; 2018 u32 port_id; 2019 2020 /* it is not a slave port node, continue */ 2021 if (strcmp(port_np->name, "port")) 2022 continue; 2023 2024 ret = of_property_read_u32(port_np, "reg", &port_id); 2025 if (ret < 0) { 2026 dev_err(dev, "%pOF error reading port_id %d\n", 2027 port_np, ret); 2028 goto of_node_put; 2029 } 2030 2031 if (!port_id || port_id > common->port_num) { 2032 dev_err(dev, "%pOF has invalid port_id %u %s\n", 2033 port_np, port_id, port_np->name); 2034 ret = -EINVAL; 2035 goto of_node_put; 2036 } 2037 2038 port = am65_common_get_port(common, port_id); 2039 port->port_id = port_id; 2040 port->common = common; 2041 port->port_base = common->cpsw_base + AM65_CPSW_NU_PORTS_BASE + 2042 AM65_CPSW_NU_PORTS_OFFSET * (port_id); 2043 if (common->pdata.extra_modes) 2044 port->sgmii_base = common->ss_base + AM65_CPSW_SGMII_BASE * (port_id); 2045 port->stat_base = common->cpsw_base + AM65_CPSW_NU_STATS_BASE + 2046 (AM65_CPSW_NU_STATS_PORT_OFFSET * port_id); 2047 port->name = of_get_property(port_np, "label", NULL); 2048 port->fetch_ram_base = 2049 common->cpsw_base + AM65_CPSW_NU_FRAM_BASE + 2050 (AM65_CPSW_NU_FRAM_PORT_OFFSET * (port_id - 1)); 2051 2052 port->slave.mac_sl = cpsw_sl_get("am65", dev, port->port_base); 2053 if (IS_ERR(port->slave.mac_sl)) { 2054 ret = PTR_ERR(port->slave.mac_sl); 2055 goto of_node_put; 2056 } 2057 2058 port->disabled = !of_device_is_available(port_np); 2059 if (port->disabled) { 2060 common->disabled_ports_mask |= BIT(port->port_id); 2061 continue; 2062 } 2063 2064 port->slave.ifphy = devm_of_phy_get(dev, port_np, NULL); 2065 if (IS_ERR(port->slave.ifphy)) { 2066 ret = PTR_ERR(port->slave.ifphy); 2067 dev_err(dev, "%pOF error retrieving port phy: %d\n", 2068 port_np, ret); 2069 goto of_node_put; 2070 } 2071 2072 /* Initialize the Serdes PHY for the port */ 2073 ret = am65_cpsw_init_serdes_phy(dev, port_np, port); 2074 if (ret) 2075 goto of_node_put; 2076 2077 port->slave.mac_only = 2078 of_property_read_bool(port_np, "ti,mac-only"); 2079 2080 /* get phy/link info */ 2081 port->slave.phy_node = port_np; 2082 ret = of_get_phy_mode(port_np, &port->slave.phy_if); 2083 if (ret) { 2084 dev_err(dev, "%pOF read phy-mode err %d\n", 2085 port_np, ret); 2086 goto of_node_put; 2087 } 2088 2089 ret = phy_set_mode_ext(port->slave.ifphy, PHY_MODE_ETHERNET, port->slave.phy_if); 2090 if (ret) 2091 goto of_node_put; 2092 2093 ret = of_get_mac_address(port_np, port->slave.mac_addr); 2094 if (ret) { 2095 am65_cpsw_am654_get_efuse_macid(port_np, 2096 port->port_id, 2097 port->slave.mac_addr); 2098 if (!is_valid_ether_addr(port->slave.mac_addr)) { 2099 eth_random_addr(port->slave.mac_addr); 2100 dev_err(dev, "Use random MAC address\n"); 2101 } 2102 } 2103 } 2104 of_node_put(node); 2105 2106 /* is there at least one ext.port */ 2107 if (!(~common->disabled_ports_mask & GENMASK(common->port_num, 1))) { 2108 dev_err(dev, "No Ext. port are available\n"); 2109 return -ENODEV; 2110 } 2111 2112 return 0; 2113 2114 of_node_put: 2115 of_node_put(port_np); 2116 of_node_put(node); 2117 return ret; 2118 } 2119 2120 static void am65_cpsw_pcpu_stats_free(void *data) 2121 { 2122 struct am65_cpsw_ndev_stats __percpu *stats = data; 2123 2124 free_percpu(stats); 2125 } 2126 2127 static void am65_cpsw_nuss_phylink_cleanup(struct am65_cpsw_common *common) 2128 { 2129 struct am65_cpsw_port *port; 2130 int i; 2131 2132 for (i = 0; i < common->port_num; i++) { 2133 port = &common->ports[i]; 2134 if (port->slave.phylink) 2135 phylink_destroy(port->slave.phylink); 2136 } 2137 } 2138 2139 static int 2140 am65_cpsw_nuss_init_port_ndev(struct am65_cpsw_common *common, u32 port_idx) 2141 { 2142 struct am65_cpsw_ndev_priv *ndev_priv; 2143 struct device *dev = common->dev; 2144 struct am65_cpsw_port *port; 2145 struct phylink *phylink; 2146 int ret; 2147 2148 port = &common->ports[port_idx]; 2149 2150 if (port->disabled) 2151 return 0; 2152 2153 /* alloc netdev */ 2154 port->ndev = devm_alloc_etherdev_mqs(common->dev, 2155 sizeof(struct am65_cpsw_ndev_priv), 2156 AM65_CPSW_MAX_TX_QUEUES, 2157 AM65_CPSW_MAX_RX_QUEUES); 2158 if (!port->ndev) { 2159 dev_err(dev, "error allocating slave net_device %u\n", 2160 port->port_id); 2161 return -ENOMEM; 2162 } 2163 2164 ndev_priv = netdev_priv(port->ndev); 2165 ndev_priv->port = port; 2166 ndev_priv->msg_enable = AM65_CPSW_DEBUG; 2167 SET_NETDEV_DEV(port->ndev, dev); 2168 2169 eth_hw_addr_set(port->ndev, port->slave.mac_addr); 2170 2171 port->ndev->min_mtu = AM65_CPSW_MIN_PACKET_SIZE; 2172 port->ndev->max_mtu = AM65_CPSW_MAX_PACKET_SIZE; 2173 port->ndev->hw_features = NETIF_F_SG | 2174 NETIF_F_RXCSUM | 2175 NETIF_F_HW_CSUM | 2176 NETIF_F_HW_TC; 2177 port->ndev->features = port->ndev->hw_features | 2178 NETIF_F_HW_VLAN_CTAG_FILTER; 2179 port->ndev->vlan_features |= NETIF_F_SG; 2180 port->ndev->netdev_ops = &am65_cpsw_nuss_netdev_ops; 2181 port->ndev->ethtool_ops = &am65_cpsw_ethtool_ops_slave; 2182 2183 /* Configuring Phylink */ 2184 port->slave.phylink_config.dev = &port->ndev->dev; 2185 port->slave.phylink_config.type = PHYLINK_NETDEV; 2186 port->slave.phylink_config.mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 2187 MAC_1000FD | MAC_5000FD; 2188 port->slave.phylink_config.mac_managed_pm = true; /* MAC does PM */ 2189 2190 switch (port->slave.phy_if) { 2191 case PHY_INTERFACE_MODE_RGMII: 2192 case PHY_INTERFACE_MODE_RGMII_ID: 2193 case PHY_INTERFACE_MODE_RGMII_RXID: 2194 case PHY_INTERFACE_MODE_RGMII_TXID: 2195 phy_interface_set_rgmii(port->slave.phylink_config.supported_interfaces); 2196 break; 2197 2198 case PHY_INTERFACE_MODE_RMII: 2199 __set_bit(PHY_INTERFACE_MODE_RMII, 2200 port->slave.phylink_config.supported_interfaces); 2201 break; 2202 2203 case PHY_INTERFACE_MODE_QSGMII: 2204 case PHY_INTERFACE_MODE_SGMII: 2205 case PHY_INTERFACE_MODE_USXGMII: 2206 if (common->pdata.extra_modes & BIT(port->slave.phy_if)) { 2207 __set_bit(port->slave.phy_if, 2208 port->slave.phylink_config.supported_interfaces); 2209 } else { 2210 dev_err(dev, "selected phy-mode is not supported\n"); 2211 return -EOPNOTSUPP; 2212 } 2213 break; 2214 2215 default: 2216 dev_err(dev, "selected phy-mode is not supported\n"); 2217 return -EOPNOTSUPP; 2218 } 2219 2220 phylink = phylink_create(&port->slave.phylink_config, 2221 of_node_to_fwnode(port->slave.phy_node), 2222 port->slave.phy_if, 2223 &am65_cpsw_phylink_mac_ops); 2224 if (IS_ERR(phylink)) 2225 return PTR_ERR(phylink); 2226 2227 port->slave.phylink = phylink; 2228 2229 /* Disable TX checksum offload by default due to HW bug */ 2230 if (common->pdata.quirks & AM65_CPSW_QUIRK_I2027_NO_TX_CSUM) 2231 port->ndev->features &= ~NETIF_F_HW_CSUM; 2232 2233 ndev_priv->stats = netdev_alloc_pcpu_stats(struct am65_cpsw_ndev_stats); 2234 if (!ndev_priv->stats) 2235 return -ENOMEM; 2236 2237 ret = devm_add_action_or_reset(dev, am65_cpsw_pcpu_stats_free, 2238 ndev_priv->stats); 2239 if (ret) 2240 dev_err(dev, "failed to add percpu stat free action %d\n", ret); 2241 2242 if (!common->dma_ndev) 2243 common->dma_ndev = port->ndev; 2244 2245 return ret; 2246 } 2247 2248 static int am65_cpsw_nuss_init_ndevs(struct am65_cpsw_common *common) 2249 { 2250 int ret; 2251 int i; 2252 2253 for (i = 0; i < common->port_num; i++) { 2254 ret = am65_cpsw_nuss_init_port_ndev(common, i); 2255 if (ret) 2256 return ret; 2257 } 2258 2259 return ret; 2260 } 2261 2262 static void am65_cpsw_nuss_cleanup_ndev(struct am65_cpsw_common *common) 2263 { 2264 struct am65_cpsw_port *port; 2265 int i; 2266 2267 for (i = 0; i < common->port_num; i++) { 2268 port = &common->ports[i]; 2269 if (port->ndev && port->ndev->reg_state == NETREG_REGISTERED) 2270 unregister_netdev(port->ndev); 2271 } 2272 } 2273 2274 static void am65_cpsw_port_offload_fwd_mark_update(struct am65_cpsw_common *common) 2275 { 2276 int set_val = 0; 2277 int i; 2278 2279 if (common->br_members == (GENMASK(common->port_num, 1) & ~common->disabled_ports_mask)) 2280 set_val = 1; 2281 2282 dev_dbg(common->dev, "set offload_fwd_mark %d\n", set_val); 2283 2284 for (i = 1; i <= common->port_num; i++) { 2285 struct am65_cpsw_port *port = am65_common_get_port(common, i); 2286 struct am65_cpsw_ndev_priv *priv; 2287 2288 if (!port->ndev) 2289 continue; 2290 2291 priv = am65_ndev_to_priv(port->ndev); 2292 priv->offload_fwd_mark = set_val; 2293 } 2294 } 2295 2296 bool am65_cpsw_port_dev_check(const struct net_device *ndev) 2297 { 2298 if (ndev->netdev_ops == &am65_cpsw_nuss_netdev_ops) { 2299 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 2300 2301 return !common->is_emac_mode; 2302 } 2303 2304 return false; 2305 } 2306 2307 static int am65_cpsw_netdevice_port_link(struct net_device *ndev, 2308 struct net_device *br_ndev, 2309 struct netlink_ext_ack *extack) 2310 { 2311 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 2312 struct am65_cpsw_ndev_priv *priv = am65_ndev_to_priv(ndev); 2313 int err; 2314 2315 if (!common->br_members) { 2316 common->hw_bridge_dev = br_ndev; 2317 } else { 2318 /* This is adding the port to a second bridge, this is 2319 * unsupported 2320 */ 2321 if (common->hw_bridge_dev != br_ndev) 2322 return -EOPNOTSUPP; 2323 } 2324 2325 err = switchdev_bridge_port_offload(ndev, ndev, NULL, NULL, NULL, 2326 false, extack); 2327 if (err) 2328 return err; 2329 2330 common->br_members |= BIT(priv->port->port_id); 2331 2332 am65_cpsw_port_offload_fwd_mark_update(common); 2333 2334 return NOTIFY_DONE; 2335 } 2336 2337 static void am65_cpsw_netdevice_port_unlink(struct net_device *ndev) 2338 { 2339 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 2340 struct am65_cpsw_ndev_priv *priv = am65_ndev_to_priv(ndev); 2341 2342 switchdev_bridge_port_unoffload(ndev, NULL, NULL, NULL); 2343 2344 common->br_members &= ~BIT(priv->port->port_id); 2345 2346 am65_cpsw_port_offload_fwd_mark_update(common); 2347 2348 if (!common->br_members) 2349 common->hw_bridge_dev = NULL; 2350 } 2351 2352 /* netdev notifier */ 2353 static int am65_cpsw_netdevice_event(struct notifier_block *unused, 2354 unsigned long event, void *ptr) 2355 { 2356 struct netlink_ext_ack *extack = netdev_notifier_info_to_extack(ptr); 2357 struct net_device *ndev = netdev_notifier_info_to_dev(ptr); 2358 struct netdev_notifier_changeupper_info *info; 2359 int ret = NOTIFY_DONE; 2360 2361 if (!am65_cpsw_port_dev_check(ndev)) 2362 return NOTIFY_DONE; 2363 2364 switch (event) { 2365 case NETDEV_CHANGEUPPER: 2366 info = ptr; 2367 2368 if (netif_is_bridge_master(info->upper_dev)) { 2369 if (info->linking) 2370 ret = am65_cpsw_netdevice_port_link(ndev, 2371 info->upper_dev, 2372 extack); 2373 else 2374 am65_cpsw_netdevice_port_unlink(ndev); 2375 } 2376 break; 2377 default: 2378 return NOTIFY_DONE; 2379 } 2380 2381 return notifier_from_errno(ret); 2382 } 2383 2384 static int am65_cpsw_register_notifiers(struct am65_cpsw_common *cpsw) 2385 { 2386 int ret = 0; 2387 2388 if (AM65_CPSW_IS_CPSW2G(cpsw) || 2389 !IS_REACHABLE(CONFIG_TI_K3_AM65_CPSW_SWITCHDEV)) 2390 return 0; 2391 2392 cpsw->am65_cpsw_netdevice_nb.notifier_call = &am65_cpsw_netdevice_event; 2393 ret = register_netdevice_notifier(&cpsw->am65_cpsw_netdevice_nb); 2394 if (ret) { 2395 dev_err(cpsw->dev, "can't register netdevice notifier\n"); 2396 return ret; 2397 } 2398 2399 ret = am65_cpsw_switchdev_register_notifiers(cpsw); 2400 if (ret) 2401 unregister_netdevice_notifier(&cpsw->am65_cpsw_netdevice_nb); 2402 2403 return ret; 2404 } 2405 2406 static void am65_cpsw_unregister_notifiers(struct am65_cpsw_common *cpsw) 2407 { 2408 if (AM65_CPSW_IS_CPSW2G(cpsw) || 2409 !IS_REACHABLE(CONFIG_TI_K3_AM65_CPSW_SWITCHDEV)) 2410 return; 2411 2412 am65_cpsw_switchdev_unregister_notifiers(cpsw); 2413 unregister_netdevice_notifier(&cpsw->am65_cpsw_netdevice_nb); 2414 } 2415 2416 static const struct devlink_ops am65_cpsw_devlink_ops = {}; 2417 2418 static void am65_cpsw_init_stp_ale_entry(struct am65_cpsw_common *cpsw) 2419 { 2420 cpsw_ale_add_mcast(cpsw->ale, eth_stp_addr, ALE_PORT_HOST, ALE_SUPER, 0, 2421 ALE_MCAST_BLOCK_LEARN_FWD); 2422 } 2423 2424 static void am65_cpsw_init_host_port_switch(struct am65_cpsw_common *common) 2425 { 2426 struct am65_cpsw_host *host = am65_common_get_host(common); 2427 2428 writel(common->default_vlan, host->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 2429 2430 am65_cpsw_init_stp_ale_entry(common); 2431 2432 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_P0_UNI_FLOOD, 1); 2433 dev_dbg(common->dev, "Set P0_UNI_FLOOD\n"); 2434 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_PORT_NOLEARN, 0); 2435 } 2436 2437 static void am65_cpsw_init_host_port_emac(struct am65_cpsw_common *common) 2438 { 2439 struct am65_cpsw_host *host = am65_common_get_host(common); 2440 2441 writel(0, host->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 2442 2443 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_P0_UNI_FLOOD, 0); 2444 dev_dbg(common->dev, "unset P0_UNI_FLOOD\n"); 2445 2446 /* learning make no sense in multi-mac mode */ 2447 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_PORT_NOLEARN, 1); 2448 } 2449 2450 static int am65_cpsw_dl_switch_mode_get(struct devlink *dl, u32 id, 2451 struct devlink_param_gset_ctx *ctx) 2452 { 2453 struct am65_cpsw_devlink *dl_priv = devlink_priv(dl); 2454 struct am65_cpsw_common *common = dl_priv->common; 2455 2456 dev_dbg(common->dev, "%s id:%u\n", __func__, id); 2457 2458 if (id != AM65_CPSW_DL_PARAM_SWITCH_MODE) 2459 return -EOPNOTSUPP; 2460 2461 ctx->val.vbool = !common->is_emac_mode; 2462 2463 return 0; 2464 } 2465 2466 static void am65_cpsw_init_port_emac_ale(struct am65_cpsw_port *port) 2467 { 2468 struct am65_cpsw_slave_data *slave = &port->slave; 2469 struct am65_cpsw_common *common = port->common; 2470 u32 port_mask; 2471 2472 writel(slave->port_vlan, port->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 2473 2474 if (slave->mac_only) 2475 /* enable mac-only mode on port */ 2476 cpsw_ale_control_set(common->ale, port->port_id, 2477 ALE_PORT_MACONLY, 1); 2478 2479 cpsw_ale_control_set(common->ale, port->port_id, ALE_PORT_NOLEARN, 1); 2480 2481 port_mask = BIT(port->port_id) | ALE_PORT_HOST; 2482 2483 cpsw_ale_add_ucast(common->ale, port->ndev->dev_addr, 2484 HOST_PORT_NUM, ALE_SECURE, slave->port_vlan); 2485 cpsw_ale_add_mcast(common->ale, port->ndev->broadcast, 2486 port_mask, ALE_VLAN, slave->port_vlan, ALE_MCAST_FWD_2); 2487 } 2488 2489 static void am65_cpsw_init_port_switch_ale(struct am65_cpsw_port *port) 2490 { 2491 struct am65_cpsw_slave_data *slave = &port->slave; 2492 struct am65_cpsw_common *cpsw = port->common; 2493 u32 port_mask; 2494 2495 cpsw_ale_control_set(cpsw->ale, port->port_id, 2496 ALE_PORT_NOLEARN, 0); 2497 2498 cpsw_ale_add_ucast(cpsw->ale, port->ndev->dev_addr, 2499 HOST_PORT_NUM, ALE_SECURE | ALE_BLOCKED | ALE_VLAN, 2500 slave->port_vlan); 2501 2502 port_mask = BIT(port->port_id) | ALE_PORT_HOST; 2503 2504 cpsw_ale_add_mcast(cpsw->ale, port->ndev->broadcast, 2505 port_mask, ALE_VLAN, slave->port_vlan, 2506 ALE_MCAST_FWD_2); 2507 2508 writel(slave->port_vlan, port->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 2509 2510 cpsw_ale_control_set(cpsw->ale, port->port_id, 2511 ALE_PORT_MACONLY, 0); 2512 } 2513 2514 static int am65_cpsw_dl_switch_mode_set(struct devlink *dl, u32 id, 2515 struct devlink_param_gset_ctx *ctx) 2516 { 2517 struct am65_cpsw_devlink *dl_priv = devlink_priv(dl); 2518 struct am65_cpsw_common *cpsw = dl_priv->common; 2519 bool switch_en = ctx->val.vbool; 2520 bool if_running = false; 2521 int i; 2522 2523 dev_dbg(cpsw->dev, "%s id:%u\n", __func__, id); 2524 2525 if (id != AM65_CPSW_DL_PARAM_SWITCH_MODE) 2526 return -EOPNOTSUPP; 2527 2528 if (switch_en == !cpsw->is_emac_mode) 2529 return 0; 2530 2531 if (!switch_en && cpsw->br_members) { 2532 dev_err(cpsw->dev, "Remove ports from bridge before disabling switch mode\n"); 2533 return -EINVAL; 2534 } 2535 2536 rtnl_lock(); 2537 2538 cpsw->is_emac_mode = !switch_en; 2539 2540 for (i = 0; i < cpsw->port_num; i++) { 2541 struct net_device *sl_ndev = cpsw->ports[i].ndev; 2542 2543 if (!sl_ndev || !netif_running(sl_ndev)) 2544 continue; 2545 2546 if_running = true; 2547 } 2548 2549 if (!if_running) { 2550 /* all ndevs are down */ 2551 for (i = 0; i < cpsw->port_num; i++) { 2552 struct net_device *sl_ndev = cpsw->ports[i].ndev; 2553 struct am65_cpsw_slave_data *slave; 2554 2555 if (!sl_ndev) 2556 continue; 2557 2558 slave = am65_ndev_to_slave(sl_ndev); 2559 if (switch_en) 2560 slave->port_vlan = cpsw->default_vlan; 2561 else 2562 slave->port_vlan = 0; 2563 } 2564 2565 goto exit; 2566 } 2567 2568 cpsw_ale_control_set(cpsw->ale, 0, ALE_BYPASS, 1); 2569 /* clean up ALE table */ 2570 cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM, ALE_CLEAR, 1); 2571 cpsw_ale_control_get(cpsw->ale, HOST_PORT_NUM, ALE_AGEOUT); 2572 2573 if (switch_en) { 2574 dev_info(cpsw->dev, "Enable switch mode\n"); 2575 2576 am65_cpsw_init_host_port_switch(cpsw); 2577 2578 for (i = 0; i < cpsw->port_num; i++) { 2579 struct net_device *sl_ndev = cpsw->ports[i].ndev; 2580 struct am65_cpsw_slave_data *slave; 2581 struct am65_cpsw_port *port; 2582 2583 if (!sl_ndev) 2584 continue; 2585 2586 port = am65_ndev_to_port(sl_ndev); 2587 slave = am65_ndev_to_slave(sl_ndev); 2588 slave->port_vlan = cpsw->default_vlan; 2589 2590 if (netif_running(sl_ndev)) 2591 am65_cpsw_init_port_switch_ale(port); 2592 } 2593 2594 } else { 2595 dev_info(cpsw->dev, "Disable switch mode\n"); 2596 2597 am65_cpsw_init_host_port_emac(cpsw); 2598 2599 for (i = 0; i < cpsw->port_num; i++) { 2600 struct net_device *sl_ndev = cpsw->ports[i].ndev; 2601 struct am65_cpsw_port *port; 2602 2603 if (!sl_ndev) 2604 continue; 2605 2606 port = am65_ndev_to_port(sl_ndev); 2607 port->slave.port_vlan = 0; 2608 if (netif_running(sl_ndev)) 2609 am65_cpsw_init_port_emac_ale(port); 2610 } 2611 } 2612 cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM, ALE_BYPASS, 0); 2613 exit: 2614 rtnl_unlock(); 2615 2616 return 0; 2617 } 2618 2619 static const struct devlink_param am65_cpsw_devlink_params[] = { 2620 DEVLINK_PARAM_DRIVER(AM65_CPSW_DL_PARAM_SWITCH_MODE, "switch_mode", 2621 DEVLINK_PARAM_TYPE_BOOL, 2622 BIT(DEVLINK_PARAM_CMODE_RUNTIME), 2623 am65_cpsw_dl_switch_mode_get, 2624 am65_cpsw_dl_switch_mode_set, NULL), 2625 }; 2626 2627 static int am65_cpsw_nuss_register_devlink(struct am65_cpsw_common *common) 2628 { 2629 struct devlink_port_attrs attrs = {}; 2630 struct am65_cpsw_devlink *dl_priv; 2631 struct device *dev = common->dev; 2632 struct devlink_port *dl_port; 2633 struct am65_cpsw_port *port; 2634 int ret = 0; 2635 int i; 2636 2637 common->devlink = 2638 devlink_alloc(&am65_cpsw_devlink_ops, sizeof(*dl_priv), dev); 2639 if (!common->devlink) 2640 return -ENOMEM; 2641 2642 dl_priv = devlink_priv(common->devlink); 2643 dl_priv->common = common; 2644 2645 /* Provide devlink hook to switch mode when multiple external ports 2646 * are present NUSS switchdev driver is enabled. 2647 */ 2648 if (!AM65_CPSW_IS_CPSW2G(common) && 2649 IS_ENABLED(CONFIG_TI_K3_AM65_CPSW_SWITCHDEV)) { 2650 ret = devlink_params_register(common->devlink, 2651 am65_cpsw_devlink_params, 2652 ARRAY_SIZE(am65_cpsw_devlink_params)); 2653 if (ret) { 2654 dev_err(dev, "devlink params reg fail ret:%d\n", ret); 2655 goto dl_unreg; 2656 } 2657 } 2658 2659 for (i = 1; i <= common->port_num; i++) { 2660 port = am65_common_get_port(common, i); 2661 dl_port = &port->devlink_port; 2662 2663 if (port->ndev) 2664 attrs.flavour = DEVLINK_PORT_FLAVOUR_PHYSICAL; 2665 else 2666 attrs.flavour = DEVLINK_PORT_FLAVOUR_UNUSED; 2667 attrs.phys.port_number = port->port_id; 2668 attrs.switch_id.id_len = sizeof(resource_size_t); 2669 memcpy(attrs.switch_id.id, common->switch_id, attrs.switch_id.id_len); 2670 devlink_port_attrs_set(dl_port, &attrs); 2671 2672 ret = devlink_port_register(common->devlink, dl_port, port->port_id); 2673 if (ret) { 2674 dev_err(dev, "devlink_port reg fail for port %d, ret:%d\n", 2675 port->port_id, ret); 2676 goto dl_port_unreg; 2677 } 2678 } 2679 devlink_register(common->devlink); 2680 return ret; 2681 2682 dl_port_unreg: 2683 for (i = i - 1; i >= 1; i--) { 2684 port = am65_common_get_port(common, i); 2685 dl_port = &port->devlink_port; 2686 2687 devlink_port_unregister(dl_port); 2688 } 2689 dl_unreg: 2690 devlink_free(common->devlink); 2691 return ret; 2692 } 2693 2694 static void am65_cpsw_unregister_devlink(struct am65_cpsw_common *common) 2695 { 2696 struct devlink_port *dl_port; 2697 struct am65_cpsw_port *port; 2698 int i; 2699 2700 devlink_unregister(common->devlink); 2701 2702 for (i = 1; i <= common->port_num; i++) { 2703 port = am65_common_get_port(common, i); 2704 dl_port = &port->devlink_port; 2705 2706 devlink_port_unregister(dl_port); 2707 } 2708 2709 if (!AM65_CPSW_IS_CPSW2G(common) && 2710 IS_ENABLED(CONFIG_TI_K3_AM65_CPSW_SWITCHDEV)) 2711 devlink_params_unregister(common->devlink, 2712 am65_cpsw_devlink_params, 2713 ARRAY_SIZE(am65_cpsw_devlink_params)); 2714 2715 devlink_free(common->devlink); 2716 } 2717 2718 static int am65_cpsw_nuss_register_ndevs(struct am65_cpsw_common *common) 2719 { 2720 struct device *dev = common->dev; 2721 struct am65_cpsw_port *port; 2722 int ret = 0, i; 2723 2724 /* init tx channels */ 2725 ret = am65_cpsw_nuss_init_tx_chns(common); 2726 if (ret) 2727 return ret; 2728 ret = am65_cpsw_nuss_init_rx_chns(common); 2729 if (ret) 2730 return ret; 2731 2732 ret = am65_cpsw_nuss_register_devlink(common); 2733 if (ret) 2734 return ret; 2735 2736 for (i = 0; i < common->port_num; i++) { 2737 port = &common->ports[i]; 2738 2739 if (!port->ndev) 2740 continue; 2741 2742 SET_NETDEV_DEVLINK_PORT(port->ndev, &port->devlink_port); 2743 2744 ret = register_netdev(port->ndev); 2745 if (ret) { 2746 dev_err(dev, "error registering slave net device%i %d\n", 2747 i, ret); 2748 goto err_cleanup_ndev; 2749 } 2750 } 2751 2752 ret = am65_cpsw_register_notifiers(common); 2753 if (ret) 2754 goto err_cleanup_ndev; 2755 2756 /* can't auto unregister ndev using devm_add_action() due to 2757 * devres release sequence in DD core for DMA 2758 */ 2759 2760 return 0; 2761 2762 err_cleanup_ndev: 2763 am65_cpsw_nuss_cleanup_ndev(common); 2764 am65_cpsw_unregister_devlink(common); 2765 2766 return ret; 2767 } 2768 2769 int am65_cpsw_nuss_update_tx_chns(struct am65_cpsw_common *common, int num_tx) 2770 { 2771 int ret; 2772 2773 common->tx_ch_num = num_tx; 2774 ret = am65_cpsw_nuss_init_tx_chns(common); 2775 2776 return ret; 2777 } 2778 2779 struct am65_cpsw_soc_pdata { 2780 u32 quirks_dis; 2781 }; 2782 2783 static const struct am65_cpsw_soc_pdata am65x_soc_sr2_0 = { 2784 .quirks_dis = AM65_CPSW_QUIRK_I2027_NO_TX_CSUM, 2785 }; 2786 2787 static const struct soc_device_attribute am65_cpsw_socinfo[] = { 2788 { .family = "AM65X", 2789 .revision = "SR2.0", 2790 .data = &am65x_soc_sr2_0 2791 }, 2792 {/* sentinel */} 2793 }; 2794 2795 static const struct am65_cpsw_pdata am65x_sr1_0 = { 2796 .quirks = AM65_CPSW_QUIRK_I2027_NO_TX_CSUM, 2797 .ale_dev_id = "am65x-cpsw2g", 2798 .fdqring_mode = K3_RINGACC_RING_MODE_MESSAGE, 2799 }; 2800 2801 static const struct am65_cpsw_pdata j721e_pdata = { 2802 .quirks = 0, 2803 .ale_dev_id = "am65x-cpsw2g", 2804 .fdqring_mode = K3_RINGACC_RING_MODE_MESSAGE, 2805 }; 2806 2807 static const struct am65_cpsw_pdata am64x_cpswxg_pdata = { 2808 .quirks = AM64_CPSW_QUIRK_DMA_RX_TDOWN_IRQ, 2809 .ale_dev_id = "am64-cpswxg", 2810 .fdqring_mode = K3_RINGACC_RING_MODE_RING, 2811 }; 2812 2813 static const struct am65_cpsw_pdata j7200_cpswxg_pdata = { 2814 .quirks = 0, 2815 .ale_dev_id = "am64-cpswxg", 2816 .fdqring_mode = K3_RINGACC_RING_MODE_RING, 2817 .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | BIT(PHY_INTERFACE_MODE_SGMII), 2818 }; 2819 2820 static const struct am65_cpsw_pdata j721e_cpswxg_pdata = { 2821 .quirks = 0, 2822 .ale_dev_id = "am64-cpswxg", 2823 .fdqring_mode = K3_RINGACC_RING_MODE_MESSAGE, 2824 .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | BIT(PHY_INTERFACE_MODE_SGMII), 2825 }; 2826 2827 static const struct am65_cpsw_pdata j784s4_cpswxg_pdata = { 2828 .quirks = 0, 2829 .ale_dev_id = "am64-cpswxg", 2830 .fdqring_mode = K3_RINGACC_RING_MODE_MESSAGE, 2831 .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | BIT(PHY_INTERFACE_MODE_USXGMII), 2832 }; 2833 2834 static const struct of_device_id am65_cpsw_nuss_of_mtable[] = { 2835 { .compatible = "ti,am654-cpsw-nuss", .data = &am65x_sr1_0}, 2836 { .compatible = "ti,j721e-cpsw-nuss", .data = &j721e_pdata}, 2837 { .compatible = "ti,am642-cpsw-nuss", .data = &am64x_cpswxg_pdata}, 2838 { .compatible = "ti,j7200-cpswxg-nuss", .data = &j7200_cpswxg_pdata}, 2839 { .compatible = "ti,j721e-cpswxg-nuss", .data = &j721e_cpswxg_pdata}, 2840 { .compatible = "ti,j784s4-cpswxg-nuss", .data = &j784s4_cpswxg_pdata}, 2841 { /* sentinel */ }, 2842 }; 2843 MODULE_DEVICE_TABLE(of, am65_cpsw_nuss_of_mtable); 2844 2845 static void am65_cpsw_nuss_apply_socinfo(struct am65_cpsw_common *common) 2846 { 2847 const struct soc_device_attribute *soc; 2848 2849 soc = soc_device_match(am65_cpsw_socinfo); 2850 if (soc && soc->data) { 2851 const struct am65_cpsw_soc_pdata *socdata = soc->data; 2852 2853 /* disable quirks */ 2854 common->pdata.quirks &= ~socdata->quirks_dis; 2855 } 2856 } 2857 2858 static int am65_cpsw_nuss_probe(struct platform_device *pdev) 2859 { 2860 struct cpsw_ale_params ale_params = { 0 }; 2861 const struct of_device_id *of_id; 2862 struct device *dev = &pdev->dev; 2863 struct am65_cpsw_common *common; 2864 struct device_node *node; 2865 struct resource *res; 2866 struct clk *clk; 2867 u64 id_temp; 2868 int ret, i; 2869 int ale_entries; 2870 2871 common = devm_kzalloc(dev, sizeof(struct am65_cpsw_common), GFP_KERNEL); 2872 if (!common) 2873 return -ENOMEM; 2874 common->dev = dev; 2875 2876 of_id = of_match_device(am65_cpsw_nuss_of_mtable, dev); 2877 if (!of_id) 2878 return -EINVAL; 2879 common->pdata = *(const struct am65_cpsw_pdata *)of_id->data; 2880 2881 am65_cpsw_nuss_apply_socinfo(common); 2882 2883 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cpsw_nuss"); 2884 common->ss_base = devm_ioremap_resource(&pdev->dev, res); 2885 if (IS_ERR(common->ss_base)) 2886 return PTR_ERR(common->ss_base); 2887 common->cpsw_base = common->ss_base + AM65_CPSW_CPSW_NU_BASE; 2888 /* Use device's physical base address as switch id */ 2889 id_temp = cpu_to_be64(res->start); 2890 memcpy(common->switch_id, &id_temp, sizeof(res->start)); 2891 2892 node = of_get_child_by_name(dev->of_node, "ethernet-ports"); 2893 if (!node) 2894 return -ENOENT; 2895 common->port_num = of_get_child_count(node); 2896 of_node_put(node); 2897 if (common->port_num < 1 || common->port_num > AM65_CPSW_MAX_PORTS) 2898 return -ENOENT; 2899 2900 common->rx_flow_id_base = -1; 2901 init_completion(&common->tdown_complete); 2902 common->tx_ch_num = 1; 2903 common->pf_p0_rx_ptype_rrobin = false; 2904 common->default_vlan = 1; 2905 2906 common->ports = devm_kcalloc(dev, common->port_num, 2907 sizeof(*common->ports), 2908 GFP_KERNEL); 2909 if (!common->ports) 2910 return -ENOMEM; 2911 2912 clk = devm_clk_get(dev, "fck"); 2913 if (IS_ERR(clk)) 2914 return dev_err_probe(dev, PTR_ERR(clk), "getting fck clock\n"); 2915 common->bus_freq = clk_get_rate(clk); 2916 2917 pm_runtime_enable(dev); 2918 ret = pm_runtime_resume_and_get(dev); 2919 if (ret < 0) { 2920 pm_runtime_disable(dev); 2921 return ret; 2922 } 2923 2924 node = of_get_child_by_name(dev->of_node, "mdio"); 2925 if (!node) { 2926 dev_warn(dev, "MDIO node not found\n"); 2927 } else if (of_device_is_available(node)) { 2928 struct platform_device *mdio_pdev; 2929 2930 mdio_pdev = of_platform_device_create(node, NULL, dev); 2931 if (!mdio_pdev) { 2932 ret = -ENODEV; 2933 goto err_pm_clear; 2934 } 2935 2936 common->mdio_dev = &mdio_pdev->dev; 2937 } 2938 of_node_put(node); 2939 2940 am65_cpsw_nuss_get_ver(common); 2941 2942 ret = am65_cpsw_nuss_init_host_p(common); 2943 if (ret) 2944 goto err_of_clear; 2945 2946 ret = am65_cpsw_nuss_init_slave_ports(common); 2947 if (ret) 2948 goto err_of_clear; 2949 2950 /* init common data */ 2951 ale_params.dev = dev; 2952 ale_params.ale_ageout = AM65_CPSW_ALE_AGEOUT_DEFAULT; 2953 ale_params.ale_ports = common->port_num + 1; 2954 ale_params.ale_regs = common->cpsw_base + AM65_CPSW_NU_ALE_BASE; 2955 ale_params.dev_id = common->pdata.ale_dev_id; 2956 ale_params.bus_freq = common->bus_freq; 2957 2958 common->ale = cpsw_ale_create(&ale_params); 2959 if (IS_ERR(common->ale)) { 2960 dev_err(dev, "error initializing ale engine\n"); 2961 ret = PTR_ERR(common->ale); 2962 goto err_of_clear; 2963 } 2964 2965 ale_entries = common->ale->params.ale_entries; 2966 common->ale_context = devm_kzalloc(dev, 2967 ale_entries * ALE_ENTRY_WORDS * sizeof(u32), 2968 GFP_KERNEL); 2969 ret = am65_cpsw_init_cpts(common); 2970 if (ret) 2971 goto err_of_clear; 2972 2973 /* init ports */ 2974 for (i = 0; i < common->port_num; i++) 2975 am65_cpsw_nuss_slave_disable_unused(&common->ports[i]); 2976 2977 dev_set_drvdata(dev, common); 2978 2979 common->is_emac_mode = true; 2980 2981 ret = am65_cpsw_nuss_init_ndevs(common); 2982 if (ret) 2983 goto err_free_phylink; 2984 2985 ret = am65_cpsw_nuss_register_ndevs(common); 2986 if (ret) 2987 goto err_free_phylink; 2988 2989 pm_runtime_put(dev); 2990 return 0; 2991 2992 err_free_phylink: 2993 am65_cpsw_nuss_phylink_cleanup(common); 2994 am65_cpts_release(common->cpts); 2995 err_of_clear: 2996 if (common->mdio_dev) 2997 of_platform_device_destroy(common->mdio_dev, NULL); 2998 err_pm_clear: 2999 pm_runtime_put_sync(dev); 3000 pm_runtime_disable(dev); 3001 return ret; 3002 } 3003 3004 static int am65_cpsw_nuss_remove(struct platform_device *pdev) 3005 { 3006 struct device *dev = &pdev->dev; 3007 struct am65_cpsw_common *common; 3008 int ret; 3009 3010 common = dev_get_drvdata(dev); 3011 3012 ret = pm_runtime_resume_and_get(&pdev->dev); 3013 if (ret < 0) 3014 return ret; 3015 3016 am65_cpsw_unregister_devlink(common); 3017 am65_cpsw_unregister_notifiers(common); 3018 3019 /* must unregister ndevs here because DD release_driver routine calls 3020 * dma_deconfigure(dev) before devres_release_all(dev) 3021 */ 3022 am65_cpsw_nuss_cleanup_ndev(common); 3023 am65_cpsw_nuss_phylink_cleanup(common); 3024 am65_cpts_release(common->cpts); 3025 am65_cpsw_disable_serdes_phy(common); 3026 3027 if (common->mdio_dev) 3028 of_platform_device_destroy(common->mdio_dev, NULL); 3029 3030 pm_runtime_put_sync(&pdev->dev); 3031 pm_runtime_disable(&pdev->dev); 3032 return 0; 3033 } 3034 3035 static int am65_cpsw_nuss_suspend(struct device *dev) 3036 { 3037 struct am65_cpsw_common *common = dev_get_drvdata(dev); 3038 struct am65_cpsw_host *host_p = am65_common_get_host(common); 3039 struct am65_cpsw_port *port; 3040 struct net_device *ndev; 3041 int i, ret; 3042 3043 cpsw_ale_dump(common->ale, common->ale_context); 3044 host_p->vid_context = readl(host_p->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 3045 for (i = 0; i < common->port_num; i++) { 3046 port = &common->ports[i]; 3047 ndev = port->ndev; 3048 3049 if (!ndev) 3050 continue; 3051 3052 port->vid_context = readl(port->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 3053 netif_device_detach(ndev); 3054 if (netif_running(ndev)) { 3055 rtnl_lock(); 3056 ret = am65_cpsw_nuss_ndo_slave_stop(ndev); 3057 rtnl_unlock(); 3058 if (ret < 0) { 3059 netdev_err(ndev, "failed to stop: %d", ret); 3060 return ret; 3061 } 3062 } 3063 } 3064 3065 am65_cpts_suspend(common->cpts); 3066 3067 am65_cpsw_nuss_remove_rx_chns(common); 3068 am65_cpsw_nuss_remove_tx_chns(common); 3069 3070 return 0; 3071 } 3072 3073 static int am65_cpsw_nuss_resume(struct device *dev) 3074 { 3075 struct am65_cpsw_common *common = dev_get_drvdata(dev); 3076 struct am65_cpsw_port *port; 3077 struct net_device *ndev; 3078 int i, ret; 3079 struct am65_cpsw_host *host_p = am65_common_get_host(common); 3080 3081 ret = am65_cpsw_nuss_init_tx_chns(common); 3082 if (ret) 3083 return ret; 3084 ret = am65_cpsw_nuss_init_rx_chns(common); 3085 if (ret) 3086 return ret; 3087 3088 /* If RX IRQ was disabled before suspend, keep it disabled */ 3089 if (common->rx_irq_disabled) 3090 disable_irq(common->rx_chns.irq); 3091 3092 am65_cpts_resume(common->cpts); 3093 3094 for (i = 0; i < common->port_num; i++) { 3095 port = &common->ports[i]; 3096 ndev = port->ndev; 3097 3098 if (!ndev) 3099 continue; 3100 3101 if (netif_running(ndev)) { 3102 rtnl_lock(); 3103 ret = am65_cpsw_nuss_ndo_slave_open(ndev); 3104 rtnl_unlock(); 3105 if (ret < 0) { 3106 netdev_err(ndev, "failed to start: %d", ret); 3107 return ret; 3108 } 3109 } 3110 3111 netif_device_attach(ndev); 3112 writel(port->vid_context, port->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 3113 } 3114 3115 writel(host_p->vid_context, host_p->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 3116 cpsw_ale_restore(common->ale, common->ale_context); 3117 3118 return 0; 3119 } 3120 3121 static const struct dev_pm_ops am65_cpsw_nuss_dev_pm_ops = { 3122 SYSTEM_SLEEP_PM_OPS(am65_cpsw_nuss_suspend, am65_cpsw_nuss_resume) 3123 }; 3124 3125 static struct platform_driver am65_cpsw_nuss_driver = { 3126 .driver = { 3127 .name = AM65_CPSW_DRV_NAME, 3128 .of_match_table = am65_cpsw_nuss_of_mtable, 3129 .pm = &am65_cpsw_nuss_dev_pm_ops, 3130 }, 3131 .probe = am65_cpsw_nuss_probe, 3132 .remove = am65_cpsw_nuss_remove, 3133 }; 3134 3135 module_platform_driver(am65_cpsw_nuss_driver); 3136 3137 MODULE_LICENSE("GPL v2"); 3138 MODULE_AUTHOR("Grygorii Strashko <grygorii.strashko@ti.com>"); 3139 MODULE_DESCRIPTION("TI AM65 CPSW Ethernet driver"); 3140