1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /**************************************************************************** 3 * Driver for Solarflare network controllers and boards 4 * Copyright 2005-2006 Fen Systems Ltd. 5 * Copyright 2006-2013 Solarflare Communications Inc. 6 * Copyright 2019-2020 Xilinx Inc. 7 */ 8 9 #ifndef EFX_NIC_COMMON_H 10 #define EFX_NIC_COMMON_H 11 12 #include "net_driver.h" 13 #include "efx_common.h" 14 #include "mcdi.h" 15 #include "ptp.h" 16 17 enum { 18 /* Revisions 0-3 were Falcon A0, A1, B0 and Siena respectively. 19 * They are not supported by this driver but these revision numbers 20 * form part of the ethtool API for register dumping. 21 */ 22 EFX_REV_HUNT_A0 = 4, 23 EFX_REV_EF100 = 5, 24 }; 25 26 static inline int efx_nic_rev(struct efx_nic *efx) 27 { 28 return efx->type->revision; 29 } 30 31 /* Read the current event from the event queue */ 32 static inline efx_qword_t *efx_event(struct efx_channel *channel, 33 unsigned int index) 34 { 35 return ((efx_qword_t *)(channel->eventq.addr)) + 36 (index & channel->eventq_mask); 37 } 38 39 /* See if an event is present 40 * 41 * We check both the high and low dword of the event for all ones. We 42 * wrote all ones when we cleared the event, and no valid event can 43 * have all ones in either its high or low dwords. This approach is 44 * robust against reordering. 45 * 46 * Note that using a single 64-bit comparison is incorrect; even 47 * though the CPU read will be atomic, the DMA write may not be. 48 */ 49 static inline int efx_event_present(efx_qword_t *event) 50 { 51 return !(EFX_DWORD_IS_ALL_ONES(event->dword[0]) | 52 EFX_DWORD_IS_ALL_ONES(event->dword[1])); 53 } 54 55 /* Returns a pointer to the specified transmit descriptor in the TX 56 * descriptor queue belonging to the specified channel. 57 */ 58 static inline efx_qword_t * 59 efx_tx_desc(struct efx_tx_queue *tx_queue, unsigned int index) 60 { 61 return ((efx_qword_t *)(tx_queue->txd.addr)) + index; 62 } 63 64 /* Report whether this TX queue would be empty for the given write_count. 65 * May return false negative. 66 */ 67 static inline bool efx_nic_tx_is_empty(struct efx_tx_queue *tx_queue, unsigned int write_count) 68 { 69 unsigned int empty_read_count = READ_ONCE(tx_queue->empty_read_count); 70 71 if (empty_read_count == 0) 72 return false; 73 74 return ((empty_read_count ^ write_count) & ~EFX_EMPTY_COUNT_VALID) == 0; 75 } 76 77 int efx_enqueue_skb_tso(struct efx_tx_queue *tx_queue, struct sk_buff *skb, 78 bool *data_mapped); 79 80 /* Decide whether to push a TX descriptor to the NIC vs merely writing 81 * the doorbell. This can reduce latency when we are adding a single 82 * descriptor to an empty queue, but is otherwise pointless. Further, 83 * Falcon and Siena have hardware bugs (SF bug 33851) that may be 84 * triggered if we don't check this. 85 * We use the write_count used for the last doorbell push, to get the 86 * NIC's view of the tx queue. 87 */ 88 static inline bool efx_nic_may_push_tx_desc(struct efx_tx_queue *tx_queue, 89 unsigned int write_count) 90 { 91 bool was_empty = efx_nic_tx_is_empty(tx_queue, write_count); 92 93 tx_queue->empty_read_count = 0; 94 return was_empty && tx_queue->write_count - write_count == 1; 95 } 96 97 /* Returns a pointer to the specified descriptor in the RX descriptor queue */ 98 static inline efx_qword_t * 99 efx_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index) 100 { 101 return ((efx_qword_t *)(rx_queue->rxd.addr)) + index; 102 } 103 104 /* Alignment of PCIe DMA boundaries (4KB) */ 105 #define EFX_PAGE_SIZE 4096 106 /* Size and alignment of buffer table entries (same) */ 107 #define EFX_BUF_SIZE EFX_PAGE_SIZE 108 109 /* NIC-generic software stats */ 110 enum { 111 GENERIC_STAT_rx_noskb_drops, 112 GENERIC_STAT_rx_nodesc_trunc, 113 GENERIC_STAT_COUNT 114 }; 115 116 #define EFX_GENERIC_SW_STAT(ext_name) \ 117 [GENERIC_STAT_ ## ext_name] = { #ext_name, 0, 0 } 118 119 /* TX data path */ 120 static inline int efx_nic_probe_tx(struct efx_tx_queue *tx_queue) 121 { 122 return tx_queue->efx->type->tx_probe(tx_queue); 123 } 124 static inline void efx_nic_init_tx(struct efx_tx_queue *tx_queue) 125 { 126 tx_queue->efx->type->tx_init(tx_queue); 127 } 128 static inline void efx_nic_remove_tx(struct efx_tx_queue *tx_queue) 129 { 130 if (tx_queue->efx->type->tx_remove) 131 tx_queue->efx->type->tx_remove(tx_queue); 132 } 133 static inline void efx_nic_push_buffers(struct efx_tx_queue *tx_queue) 134 { 135 tx_queue->efx->type->tx_write(tx_queue); 136 } 137 138 /* RX data path */ 139 static inline int efx_nic_probe_rx(struct efx_rx_queue *rx_queue) 140 { 141 return rx_queue->efx->type->rx_probe(rx_queue); 142 } 143 static inline void efx_nic_init_rx(struct efx_rx_queue *rx_queue) 144 { 145 rx_queue->efx->type->rx_init(rx_queue); 146 } 147 static inline void efx_nic_remove_rx(struct efx_rx_queue *rx_queue) 148 { 149 rx_queue->efx->type->rx_remove(rx_queue); 150 } 151 static inline void efx_nic_notify_rx_desc(struct efx_rx_queue *rx_queue) 152 { 153 rx_queue->efx->type->rx_write(rx_queue); 154 } 155 static inline void efx_nic_generate_fill_event(struct efx_rx_queue *rx_queue) 156 { 157 rx_queue->efx->type->rx_defer_refill(rx_queue); 158 } 159 160 /* Event data path */ 161 static inline int efx_nic_probe_eventq(struct efx_channel *channel) 162 { 163 return channel->efx->type->ev_probe(channel); 164 } 165 static inline int efx_nic_init_eventq(struct efx_channel *channel) 166 { 167 return channel->efx->type->ev_init(channel); 168 } 169 static inline void efx_nic_fini_eventq(struct efx_channel *channel) 170 { 171 channel->efx->type->ev_fini(channel); 172 } 173 static inline void efx_nic_remove_eventq(struct efx_channel *channel) 174 { 175 channel->efx->type->ev_remove(channel); 176 } 177 static inline int 178 efx_nic_process_eventq(struct efx_channel *channel, int quota) 179 { 180 return channel->efx->type->ev_process(channel, quota); 181 } 182 static inline void efx_nic_eventq_read_ack(struct efx_channel *channel) 183 { 184 channel->efx->type->ev_read_ack(channel); 185 } 186 187 void efx_nic_event_test_start(struct efx_channel *channel); 188 189 bool efx_nic_event_present(struct efx_channel *channel); 190 191 static inline void efx_sensor_event(struct efx_nic *efx, efx_qword_t *ev) 192 { 193 if (efx->type->sensor_event) 194 efx->type->sensor_event(efx, ev); 195 } 196 197 static inline unsigned int efx_rx_recycle_ring_size(const struct efx_nic *efx) 198 { 199 return efx->type->rx_recycle_ring_size(efx); 200 } 201 202 /* Some statistics are computed as A - B where A and B each increase 203 * linearly with some hardware counter(s) and the counters are read 204 * asynchronously. If the counters contributing to B are always read 205 * after those contributing to A, the computed value may be lower than 206 * the true value by some variable amount, and may decrease between 207 * subsequent computations. 208 * 209 * We should never allow statistics to decrease or to exceed the true 210 * value. Since the computed value will never be greater than the 211 * true value, we can achieve this by only storing the computed value 212 * when it increases. 213 */ 214 static inline void efx_update_diff_stat(u64 *stat, u64 diff) 215 { 216 if ((s64)(diff - *stat) > 0) 217 *stat = diff; 218 } 219 220 /* Interrupts */ 221 int efx_nic_init_interrupt(struct efx_nic *efx); 222 int efx_nic_irq_test_start(struct efx_nic *efx); 223 void efx_nic_fini_interrupt(struct efx_nic *efx); 224 225 static inline int efx_nic_event_test_irq_cpu(struct efx_channel *channel) 226 { 227 return READ_ONCE(channel->event_test_cpu); 228 } 229 static inline int efx_nic_irq_test_irq_cpu(struct efx_nic *efx) 230 { 231 return READ_ONCE(efx->last_irq_cpu); 232 } 233 234 /* Global Resources */ 235 int efx_nic_alloc_buffer(struct efx_nic *efx, struct efx_buffer *buffer, 236 unsigned int len, gfp_t gfp_flags); 237 void efx_nic_free_buffer(struct efx_nic *efx, struct efx_buffer *buffer); 238 239 size_t efx_nic_get_regs_len(struct efx_nic *efx); 240 void efx_nic_get_regs(struct efx_nic *efx, void *buf); 241 242 #define EFX_MC_STATS_GENERATION_INVALID ((__force __le64)(-1)) 243 244 size_t efx_nic_describe_stats(const struct efx_hw_stat_desc *desc, size_t count, 245 const unsigned long *mask, u8 *names); 246 int efx_nic_copy_stats(struct efx_nic *efx, __le64 *dest); 247 void efx_nic_update_stats(const struct efx_hw_stat_desc *desc, size_t count, 248 const unsigned long *mask, u64 *stats, 249 const void *dma_buf, bool accumulate); 250 void efx_nic_fix_nodesc_drop_stat(struct efx_nic *efx, u64 *stat); 251 static inline size_t efx_nic_update_stats_atomic(struct efx_nic *efx, u64 *full_stats, 252 struct rtnl_link_stats64 *core_stats) 253 { 254 if (efx->type->update_stats_atomic) 255 return efx->type->update_stats_atomic(efx, full_stats, core_stats); 256 return efx->type->update_stats(efx, full_stats, core_stats); 257 } 258 259 #define EFX_MAX_FLUSH_TIME 5000 260 261 #endif /* EFX_NIC_COMMON_H */ 262