1*d2912cb1SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 21edb9ca6SSiva Reddy /* 10G controller driver for Samsung SoCs 31edb9ca6SSiva Reddy * 41edb9ca6SSiva Reddy * Copyright (C) 2013 Samsung Electronics Co., Ltd. 51edb9ca6SSiva Reddy * http://www.samsung.com 61edb9ca6SSiva Reddy * 71edb9ca6SSiva Reddy * Author: Siva Reddy Kallam <siva.kallam@samsung.com> 81edb9ca6SSiva Reddy */ 91edb9ca6SSiva Reddy #ifndef __SXGBE_DMA_H__ 101edb9ca6SSiva Reddy #define __SXGBE_DMA_H__ 111edb9ca6SSiva Reddy 121edb9ca6SSiva Reddy /* forward declaration */ 131edb9ca6SSiva Reddy struct sxgbe_extra_stats; 141edb9ca6SSiva Reddy 151edb9ca6SSiva Reddy #define SXGBE_DMA_BLENMAP_LSHIFT 1 161edb9ca6SSiva Reddy #define SXGBE_DMA_TXPBL_LSHIFT 16 171edb9ca6SSiva Reddy #define SXGBE_DMA_RXPBL_LSHIFT 16 181edb9ca6SSiva Reddy #define DEFAULT_DMA_PBL 8 191edb9ca6SSiva Reddy 201edb9ca6SSiva Reddy struct sxgbe_dma_ops { 211edb9ca6SSiva Reddy /* DMA core initialization */ 221edb9ca6SSiva Reddy int (*init)(void __iomem *ioaddr, int fix_burst, int burst_map); 231edb9ca6SSiva Reddy void (*cha_init)(void __iomem *ioaddr, int cha_num, int fix_burst, 241edb9ca6SSiva Reddy int pbl, dma_addr_t dma_tx, dma_addr_t dma_rx, 251edb9ca6SSiva Reddy int t_rzie, int r_rsize); 261edb9ca6SSiva Reddy void (*enable_dma_transmission)(void __iomem *ioaddr, int dma_cnum); 271edb9ca6SSiva Reddy void (*enable_dma_irq)(void __iomem *ioaddr, int dma_cnum); 281edb9ca6SSiva Reddy void (*disable_dma_irq)(void __iomem *ioaddr, int dma_cnum); 291edb9ca6SSiva Reddy void (*start_tx)(void __iomem *ioaddr, int tchannels); 301edb9ca6SSiva Reddy void (*start_tx_queue)(void __iomem *ioaddr, int dma_cnum); 311edb9ca6SSiva Reddy void (*stop_tx)(void __iomem *ioaddr, int tchannels); 321edb9ca6SSiva Reddy void (*stop_tx_queue)(void __iomem *ioaddr, int dma_cnum); 331edb9ca6SSiva Reddy void (*start_rx)(void __iomem *ioaddr, int rchannels); 341edb9ca6SSiva Reddy void (*stop_rx)(void __iomem *ioaddr, int rchannels); 351edb9ca6SSiva Reddy int (*tx_dma_int_status)(void __iomem *ioaddr, int channel_no, 361edb9ca6SSiva Reddy struct sxgbe_extra_stats *x); 371edb9ca6SSiva Reddy int (*rx_dma_int_status)(void __iomem *ioaddr, int channel_no, 381edb9ca6SSiva Reddy struct sxgbe_extra_stats *x); 391edb9ca6SSiva Reddy /* Program the HW RX Watchdog */ 401edb9ca6SSiva Reddy void (*rx_watchdog)(void __iomem *ioaddr, u32 riwt); 411051125dSVipul Pandya /* Enable TSO for each DMA channel */ 421051125dSVipul Pandya void (*enable_tso)(void __iomem *ioaddr, u8 chan_num); 431edb9ca6SSiva Reddy }; 441edb9ca6SSiva Reddy 451edb9ca6SSiva Reddy const struct sxgbe_dma_ops *sxgbe_get_dma_ops(void); 461edb9ca6SSiva Reddy 471edb9ca6SSiva Reddy #endif /* __SXGBE_CORE_H__ */ 48