xref: /openbmc/linux/drivers/net/ethernet/qlogic/qede/qede.h (revision c900529f3d9161bfde5cca0754f83b4d3c3e0220)
17268f33eSAlexander Lobakin /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
2e712d52bSYuval Mintz /* QLogic qede NIC Driver
3e8f1cb50SMintz, Yuval  * Copyright (c) 2015-2017  QLogic Corporation
4c4fad2a5SAlexander Lobakin  * Copyright (c) 2019-2020 Marvell International Ltd.
5e712d52bSYuval Mintz  */
67268f33eSAlexander Lobakin 
7e712d52bSYuval Mintz #ifndef _QEDE_H_
8e712d52bSYuval Mintz #define _QEDE_H_
9e712d52bSYuval Mintz #include <linux/workqueue.h>
10e712d52bSYuval Mintz #include <linux/netdevice.h>
11e712d52bSYuval Mintz #include <linux/interrupt.h>
12e712d52bSYuval Mintz #include <linux/bitmap.h>
13e712d52bSYuval Mintz #include <linux/kernel.h>
14e712d52bSYuval Mintz #include <linux/mutex.h>
15496e0517SMintz, Yuval #include <linux/bpf.h>
16c0124f32SJesper Dangaard Brouer #include <net/xdp.h>
17b262a06eSMichal Kalderon #include <linux/qed/qede_rdma.h>
18e712d52bSYuval Mintz #include <linux/io.h>
19e4917d46SChopra, Manish #ifdef CONFIG_RFS_ACCEL
20e4917d46SChopra, Manish #include <linux/cpu_rmap.h>
21e4917d46SChopra, Manish #endif
22e712d52bSYuval Mintz #include <linux/qed/common_hsi.h>
23e712d52bSYuval Mintz #include <linux/qed/eth_common.h>
24e712d52bSYuval Mintz #include <linux/qed/qed_if.h>
25e712d52bSYuval Mintz #include <linux/qed/qed_chain.h>
26e712d52bSYuval Mintz #include <linux/qed/qed_eth_if.h>
27e712d52bSYuval Mintz 
282ce9c93eSManish Chopra #include <net/pkt_cls.h>
292ce9c93eSManish Chopra #include <net/tc_act/tc_gact.h>
302ce9c93eSManish Chopra 
31e712d52bSYuval Mintz #define DRV_MODULE_SYM		qede
32e712d52bSYuval Mintz 
339c79ddaaSMintz, Yuval struct qede_stats_common {
34133fac0eSSudarsana Kalluru 	u64 no_buff_discards;
351a5a366fSSudarsana Reddy Kalluru 	u64 packet_too_big_discard;
361a5a366fSSudarsana Reddy Kalluru 	u64 ttl0_discard;
37133fac0eSSudarsana Kalluru 	u64 rx_ucast_bytes;
38133fac0eSSudarsana Kalluru 	u64 rx_mcast_bytes;
39133fac0eSSudarsana Kalluru 	u64 rx_bcast_bytes;
40133fac0eSSudarsana Kalluru 	u64 rx_ucast_pkts;
41133fac0eSSudarsana Kalluru 	u64 rx_mcast_pkts;
42133fac0eSSudarsana Kalluru 	u64 rx_bcast_pkts;
43133fac0eSSudarsana Kalluru 	u64 mftag_filter_discards;
44133fac0eSSudarsana Kalluru 	u64 mac_filter_discards;
45608e00d0SManish Chopra 	u64 gft_filter_drop;
46133fac0eSSudarsana Kalluru 	u64 tx_ucast_bytes;
47133fac0eSSudarsana Kalluru 	u64 tx_mcast_bytes;
48133fac0eSSudarsana Kalluru 	u64 tx_bcast_bytes;
49133fac0eSSudarsana Kalluru 	u64 tx_ucast_pkts;
50133fac0eSSudarsana Kalluru 	u64 tx_mcast_pkts;
51133fac0eSSudarsana Kalluru 	u64 tx_bcast_pkts;
52133fac0eSSudarsana Kalluru 	u64 tx_err_drop_pkts;
53133fac0eSSudarsana Kalluru 	u64 coalesced_pkts;
54133fac0eSSudarsana Kalluru 	u64 coalesced_events;
55133fac0eSSudarsana Kalluru 	u64 coalesced_aborts_num;
56133fac0eSSudarsana Kalluru 	u64 non_coalesced_pkts;
57133fac0eSSudarsana Kalluru 	u64 coalesced_bytes;
5832d26a68SSudarsana Reddy Kalluru 	u64 link_change_count;
599adebac3SSudarsana Reddy Kalluru 	u64 ptp_skip_txts;
60133fac0eSSudarsana Kalluru 
61133fac0eSSudarsana Kalluru 	/* port */
62133fac0eSSudarsana Kalluru 	u64 rx_64_byte_packets;
63d4967cf3SYuval Mintz 	u64 rx_65_to_127_byte_packets;
64d4967cf3SYuval Mintz 	u64 rx_128_to_255_byte_packets;
65d4967cf3SYuval Mintz 	u64 rx_256_to_511_byte_packets;
66d4967cf3SYuval Mintz 	u64 rx_512_to_1023_byte_packets;
67d4967cf3SYuval Mintz 	u64 rx_1024_to_1518_byte_packets;
68133fac0eSSudarsana Kalluru 	u64 rx_crc_errors;
69133fac0eSSudarsana Kalluru 	u64 rx_mac_crtl_frames;
70133fac0eSSudarsana Kalluru 	u64 rx_pause_frames;
71133fac0eSSudarsana Kalluru 	u64 rx_pfc_frames;
72133fac0eSSudarsana Kalluru 	u64 rx_align_errors;
73133fac0eSSudarsana Kalluru 	u64 rx_carrier_errors;
74133fac0eSSudarsana Kalluru 	u64 rx_oversize_packets;
75133fac0eSSudarsana Kalluru 	u64 rx_jabbers;
76133fac0eSSudarsana Kalluru 	u64 rx_undersize_packets;
77133fac0eSSudarsana Kalluru 	u64 rx_fragments;
78133fac0eSSudarsana Kalluru 	u64 tx_64_byte_packets;
79133fac0eSSudarsana Kalluru 	u64 tx_65_to_127_byte_packets;
80133fac0eSSudarsana Kalluru 	u64 tx_128_to_255_byte_packets;
81133fac0eSSudarsana Kalluru 	u64 tx_256_to_511_byte_packets;
82133fac0eSSudarsana Kalluru 	u64 tx_512_to_1023_byte_packets;
83133fac0eSSudarsana Kalluru 	u64 tx_1024_to_1518_byte_packets;
849c79ddaaSMintz, Yuval 	u64 tx_pause_frames;
859c79ddaaSMintz, Yuval 	u64 tx_pfc_frames;
869c79ddaaSMintz, Yuval 	u64 brb_truncates;
879c79ddaaSMintz, Yuval 	u64 brb_discards;
889c79ddaaSMintz, Yuval 	u64 tx_mac_ctrl_frames;
899c79ddaaSMintz, Yuval };
909c79ddaaSMintz, Yuval 
919c79ddaaSMintz, Yuval struct qede_stats_bb {
929c79ddaaSMintz, Yuval 	u64 rx_1519_to_1522_byte_packets;
939c79ddaaSMintz, Yuval 	u64 rx_1519_to_2047_byte_packets;
949c79ddaaSMintz, Yuval 	u64 rx_2048_to_4095_byte_packets;
959c79ddaaSMintz, Yuval 	u64 rx_4096_to_9216_byte_packets;
969c79ddaaSMintz, Yuval 	u64 rx_9217_to_16383_byte_packets;
97133fac0eSSudarsana Kalluru 	u64 tx_1519_to_2047_byte_packets;
98133fac0eSSudarsana Kalluru 	u64 tx_2048_to_4095_byte_packets;
99133fac0eSSudarsana Kalluru 	u64 tx_4096_to_9216_byte_packets;
100133fac0eSSudarsana Kalluru 	u64 tx_9217_to_16383_byte_packets;
101133fac0eSSudarsana Kalluru 	u64 tx_lpi_entry_count;
102133fac0eSSudarsana Kalluru 	u64 tx_total_collisions;
1039c79ddaaSMintz, Yuval };
1049c79ddaaSMintz, Yuval 
1059c79ddaaSMintz, Yuval struct qede_stats_ah {
1069c79ddaaSMintz, Yuval 	u64 rx_1519_to_max_byte_packets;
1079c79ddaaSMintz, Yuval 	u64 tx_1519_to_max_byte_packets;
1089c79ddaaSMintz, Yuval };
1099c79ddaaSMintz, Yuval 
1109c79ddaaSMintz, Yuval struct qede_stats {
1119c79ddaaSMintz, Yuval 	struct qede_stats_common common;
1129c79ddaaSMintz, Yuval 
1139c79ddaaSMintz, Yuval 	union {
1149c79ddaaSMintz, Yuval 		struct qede_stats_bb bb;
1159c79ddaaSMintz, Yuval 		struct qede_stats_ah ah;
1169c79ddaaSMintz, Yuval 	};
117133fac0eSSudarsana Kalluru };
118133fac0eSSudarsana Kalluru 
1197c1bfcadSSudarsana Reddy Kalluru struct qede_vlan {
1207c1bfcadSSudarsana Reddy Kalluru 	struct list_head list;
1217c1bfcadSSudarsana Reddy Kalluru 	u16 vid;
1227c1bfcadSSudarsana Reddy Kalluru 	bool configured;
1237c1bfcadSSudarsana Reddy Kalluru };
1247c1bfcadSSudarsana Reddy Kalluru 
125cee9fbd8SRam Amrani struct qede_rdma_dev {
126cee9fbd8SRam Amrani 	struct qedr_dev *qedr_dev;
127cee9fbd8SRam Amrani 	struct list_head entry;
128bbfcd1e8SMichal Kalderon 	struct list_head rdma_event_list;
129bbfcd1e8SMichal Kalderon 	struct workqueue_struct *rdma_wq;
130af6565adSMichal Kalderon 	struct kref refcnt;
131af6565adSMichal Kalderon 	struct completion event_comp;
132ccc67ef5STomer Tayar 	bool exp_recovery;
133cee9fbd8SRam Amrani };
134cee9fbd8SRam Amrani 
1354c55215cSSudarsana Reddy Kalluru struct qede_ptp;
1364c55215cSSudarsana Reddy Kalluru 
137ec9b8dbdSChopra, Manish #define QEDE_RFS_MAX_FLTR	256
138ec9b8dbdSChopra, Manish 
139149d3775SSudarsana Reddy Kalluru enum qede_flags_bit {
140149d3775SSudarsana Reddy Kalluru 	QEDE_FLAGS_IS_VF = 0,
141f04e48dbSSudarsana Reddy Kalluru 	QEDE_FLAGS_LINK_REQUESTED,
142149d3775SSudarsana Reddy Kalluru 	QEDE_FLAGS_PTP_TX_IN_PRORGESS,
143149d3775SSudarsana Reddy Kalluru 	QEDE_FLAGS_TX_TIMESTAMPING_EN
144149d3775SSudarsana Reddy Kalluru };
145149d3775SSudarsana Reddy Kalluru 
146d44a3cedSSudarsana Reddy Kalluru #define QEDE_DUMP_MAX_ARGS 4
147d44a3cedSSudarsana Reddy Kalluru enum qede_dump_cmd {
148d44a3cedSSudarsana Reddy Kalluru 	QEDE_DUMP_CMD_NONE = 0,
149d44a3cedSSudarsana Reddy Kalluru 	QEDE_DUMP_CMD_NVM_CFG,
150849dbf09SSudarsana Reddy Kalluru 	QEDE_DUMP_CMD_GRCDUMP,
151d44a3cedSSudarsana Reddy Kalluru 	QEDE_DUMP_CMD_MAX
152d44a3cedSSudarsana Reddy Kalluru };
153d44a3cedSSudarsana Reddy Kalluru 
154d44a3cedSSudarsana Reddy Kalluru struct qede_dump_info {
155d44a3cedSSudarsana Reddy Kalluru 	enum qede_dump_cmd cmd;
156d44a3cedSSudarsana Reddy Kalluru 	u8 num_args;
157d44a3cedSSudarsana Reddy Kalluru 	u32 args[QEDE_DUMP_MAX_ARGS];
158d44a3cedSSudarsana Reddy Kalluru };
159d44a3cedSSudarsana Reddy Kalluru 
160b0ec5489SBhaskar Upadhaya struct qede_coalesce {
161b0ec5489SBhaskar Upadhaya 	bool isvalid;
162b0ec5489SBhaskar Upadhaya 	u16 rxc;
163b0ec5489SBhaskar Upadhaya 	u16 txc;
164b0ec5489SBhaskar Upadhaya };
165b0ec5489SBhaskar Upadhaya 
166e712d52bSYuval Mintz struct qede_dev {
167e712d52bSYuval Mintz 	struct qed_dev			*cdev;
168e712d52bSYuval Mintz 	struct net_device		*ndev;
169e712d52bSYuval Mintz 	struct pci_dev			*pdev;
170755f982bSIgor Russkikh 	struct devlink			*devlink;
171e712d52bSYuval Mintz 
172e712d52bSYuval Mintz 	u32				dp_module;
173e712d52bSYuval Mintz 	u8				dp_level;
174e712d52bSYuval Mintz 
175461eec12Ssudarsana.kalluru@cavium.com 	unsigned long			flags;
176f35535f7SAlexander Lobakin #define IS_VF(edev)			test_bit(QEDE_FLAGS_IS_VF, \
177f35535f7SAlexander Lobakin 						 &(edev)->flags)
178fefb0202SYuval Mintz 
179e712d52bSYuval Mintz 	const struct qed_eth_ops	*ops;
1804c55215cSSudarsana Reddy Kalluru 	struct qede_ptp			*ptp;
1819adebac3SSudarsana Reddy Kalluru 	u64				ptp_skip_txts;
182e712d52bSYuval Mintz 
183e712d52bSYuval Mintz 	struct qed_dev_eth_info		dev_info;
184e712d52bSYuval Mintz #define QEDE_MAX_RSS_CNT(edev)		((edev)->dev_info.num_queues)
18580439a17SMintz, Yuval #define QEDE_MAX_TSS_CNT(edev)		((edev)->dev_info.num_queues)
1869c79ddaaSMintz, Yuval #define QEDE_IS_BB(edev) \
1879c79ddaaSMintz, Yuval 	((edev)->dev_info.common.dev_type == QED_DEV_TYPE_BB)
1889c79ddaaSMintz, Yuval #define QEDE_IS_AH(edev) \
1899c79ddaaSMintz, Yuval 	((edev)->dev_info.common.dev_type == QED_DEV_TYPE_AH)
190e712d52bSYuval Mintz 
1912950219dSYuval Mintz 	struct qede_fastpath		*fp_array;
192b0ec5489SBhaskar Upadhaya 	struct qede_coalesce            *coal_entry;
1939a4d7e86SSudarsana Reddy Kalluru 	u8				req_num_tx;
1949a4d7e86SSudarsana Reddy Kalluru 	u8				fp_num_tx;
1959a4d7e86SSudarsana Reddy Kalluru 	u8				req_num_rx;
1969a4d7e86SSudarsana Reddy Kalluru 	u8				fp_num_rx;
1979a4d7e86SSudarsana Reddy Kalluru 	u16				req_queues;
1989a4d7e86SSudarsana Reddy Kalluru 	u16				num_queues;
199d1b25b79SAlexander Lobakin 	u16				total_xdp_queues;
200f35535f7SAlexander Lobakin 
2019a4d7e86SSudarsana Reddy Kalluru #define QEDE_QUEUE_CNT(edev)		((edev)->num_queues)
2029a4d7e86SSudarsana Reddy Kalluru #define QEDE_RSS_COUNT(edev)		((edev)->num_queues - (edev)->fp_num_tx)
203f29ffdb6SMintz, Yuval #define QEDE_RX_QUEUE_IDX(edev, i)	(i)
20480439a17SMintz, Yuval #define QEDE_TSS_COUNT(edev)		((edev)->num_queues - (edev)->fp_num_rx)
205e712d52bSYuval Mintz 
206e712d52bSYuval Mintz 	struct qed_int_info		int_info;
207e712d52bSYuval Mintz 
208f35535f7SAlexander Lobakin 	/* Smaller private variant of the RTNL lock */
209e712d52bSYuval Mintz 	struct mutex			qede_lock;
210e712d52bSYuval Mintz 	u32				state; /* Protected by qede_lock */
2112950219dSYuval Mintz 	u16				rx_buf_size;
2123d789994SManish Chopra 	u32				rx_copybreak;
2133d789994SManish Chopra 
2142950219dSYuval Mintz 	/* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
2152950219dSYuval Mintz #define ETH_OVERHEAD			(ETH_HLEN + 8 + 8)
2162950219dSYuval Mintz 	/* Max supported alignment is 256 (8 shift)
2172950219dSYuval Mintz 	 * minimal alignment shift 6 is optimal for 57xxx HW performance
2182950219dSYuval Mintz 	 */
2192950219dSYuval Mintz #define QEDE_RX_ALIGN_SHIFT		max(6, min(8, L1_CACHE_SHIFT))
2202950219dSYuval Mintz 	/* We assume skb_build() uses sizeof(struct skb_shared_info) bytes
2212950219dSYuval Mintz 	 * at the end of skb->data, to avoid wasting a full cache line.
2222950219dSYuval Mintz 	 * This reduces memory use (skb->truesize).
2232950219dSYuval Mintz 	 */
2242950219dSYuval Mintz #define QEDE_FW_RX_ALIGN_END					\
2252950219dSYuval Mintz 	max_t(u64, 1UL << QEDE_RX_ALIGN_SHIFT,			\
2262950219dSYuval Mintz 	      SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
2272950219dSYuval Mintz 
228133fac0eSSudarsana Kalluru 	struct qede_stats		stats;
229f35535f7SAlexander Lobakin 
230f35535f7SAlexander Lobakin 	/* Bitfield to track initialized RSS params */
231f35535f7SAlexander Lobakin 	u32				rss_params_inited;
232961acdeaSSudarsana Reddy Kalluru #define QEDE_RSS_INDIR_INITED		BIT(0)
233961acdeaSSudarsana Reddy Kalluru #define QEDE_RSS_KEY_INITED		BIT(1)
234961acdeaSSudarsana Reddy Kalluru #define QEDE_RSS_CAPS_INITED		BIT(2)
235f35535f7SAlexander Lobakin 
236f29ffdb6SMintz, Yuval 	u16				rss_ind_table[128];
237f29ffdb6SMintz, Yuval 	u32				rss_key[10];
238f29ffdb6SMintz, Yuval 	u8				rss_caps;
239f29ffdb6SMintz, Yuval 
240f35535f7SAlexander Lobakin 	/* Both must be a power of two */
241f35535f7SAlexander Lobakin 	u16				q_num_rx_buffers;
242f35535f7SAlexander Lobakin 	u16				q_num_tx_buffers;
2430d8e0aa0SSudarsana Kalluru 
24455482edcSManish Chopra 	bool				gro_disable;
245f35535f7SAlexander Lobakin 
2467c1bfcadSSudarsana Reddy Kalluru 	struct list_head		vlan_list;
2477c1bfcadSSudarsana Reddy Kalluru 	u16				configured_vlans;
2487c1bfcadSSudarsana Reddy Kalluru 	u16				non_configured_vlans;
2497c1bfcadSSudarsana Reddy Kalluru 	bool				accept_any_vlan;
250f35535f7SAlexander Lobakin 
2510d8e0aa0SSudarsana Kalluru 	struct delayed_work		sp_task;
2520d8e0aa0SSudarsana Kalluru 	unsigned long			sp_flags;
253b18e170cSManish Chopra 	u16				vxlan_dst_port;
2549a109dd0SManish Chopra 	u16				geneve_dst_port;
255cee9fbd8SRam Amrani 
256e4917d46SChopra, Manish 	struct qede_arfs		*arfs;
25714d39648SMintz, Yuval 	bool				wol_enabled;
25814d39648SMintz, Yuval 
259cee9fbd8SRam Amrani 	struct qede_rdma_dev		rdma_info;
260496e0517SMintz, Yuval 
261496e0517SMintz, Yuval 	struct bpf_prog			*xdp_prog;
262a8736ea8SIgor Russkikh 
2634f5a8db2SIgor Russkikh 	enum qed_hw_err_type		last_err_type;
264a8736ea8SIgor Russkikh 	unsigned long			err_flags;
265a8736ea8SIgor Russkikh #define QEDE_ERR_IS_HANDLED		31
266a8736ea8SIgor Russkikh #define QEDE_ERR_ATTN_CLR_EN		0
267a8736ea8SIgor Russkikh #define QEDE_ERR_GET_DBG_INFO		1
268a8736ea8SIgor Russkikh #define QEDE_ERR_IS_RECOVERABLE		2
269a8736ea8SIgor Russkikh #define QEDE_ERR_WARN			3
270a8736ea8SIgor Russkikh 
271d44a3cedSSudarsana Reddy Kalluru 	struct qede_dump_info		dump_info;
272*42510dffSManish Chopra 	struct delayed_work		periodic_task;
273*42510dffSManish Chopra 	unsigned long			stats_coal_ticks;
274*42510dffSManish Chopra 	u32				stats_coal_usecs;
275*42510dffSManish Chopra 	spinlock_t			stats_lock; /* lock for vport stats access */
2762950219dSYuval Mintz };
2772950219dSYuval Mintz 
2782950219dSYuval Mintz enum QEDE_STATE {
2792950219dSYuval Mintz 	QEDE_STATE_CLOSED,
2802950219dSYuval Mintz 	QEDE_STATE_OPEN,
281ccc67ef5STomer Tayar 	QEDE_STATE_RECOVERY,
2822950219dSYuval Mintz };
2832950219dSYuval Mintz 
2842950219dSYuval Mintz #define HILO_U64(hi, lo)		((((u64)(hi)) << 32) + (lo))
2852950219dSYuval Mintz 
2862950219dSYuval Mintz #define	MAX_NUM_TC	8
2872950219dSYuval Mintz #define	MAX_NUM_PRI	8
2882950219dSYuval Mintz 
2892950219dSYuval Mintz /* The driver supports the new build_skb() API:
2902950219dSYuval Mintz  * RX ring buffer contains pointer to kmalloc() data only,
2912950219dSYuval Mintz  * skb are built only after the frame was DMA-ed.
2922950219dSYuval Mintz  */
2932950219dSYuval Mintz struct sw_rx_data {
294fc48b7a6SYuval Mintz 	struct page *data;
295fc48b7a6SYuval Mintz 	dma_addr_t mapping;
296fc48b7a6SYuval Mintz 	unsigned int page_offset;
2972950219dSYuval Mintz };
2982950219dSYuval Mintz 
29955482edcSManish Chopra enum qede_agg_state {
30055482edcSManish Chopra 	QEDE_AGG_STATE_NONE  = 0,
30155482edcSManish Chopra 	QEDE_AGG_STATE_START = 1,
30255482edcSManish Chopra 	QEDE_AGG_STATE_ERROR = 2
30355482edcSManish Chopra };
30455482edcSManish Chopra 
30555482edcSManish Chopra struct qede_agg_info {
30601e23015SMintz, Yuval 	/* rx_buf is a data buffer that can be placed / consumed from rx bd
30701e23015SMintz, Yuval 	 * chain. It has two purposes: We will preallocate the data buffer
30801e23015SMintz, Yuval 	 * for each aggregation when we open the interface and will place this
30901e23015SMintz, Yuval 	 * buffer on the rx-bd-ring when we receive TPA_START. We don't want
31001e23015SMintz, Yuval 	 * to be in a state where allocation fails, as we can't reuse the
31101e23015SMintz, Yuval 	 * consumer buffer in the rx-chain since FW may still be writing to it
31201e23015SMintz, Yuval 	 * (since header needs to be modified for TPA).
31301e23015SMintz, Yuval 	 * The second purpose is to keep a pointer to the bd buffer during
31401e23015SMintz, Yuval 	 * aggregation.
31501e23015SMintz, Yuval 	 */
31601e23015SMintz, Yuval 	struct sw_rx_data buffer;
31755482edcSManish Chopra 	struct sk_buff *skb;
31801e23015SMintz, Yuval 
31901e23015SMintz, Yuval 	/* We need some structs from the start cookie until termination */
32055482edcSManish Chopra 	u16 vlan_tag;
32101e23015SMintz, Yuval 
3228a863397SManish Chopra 	bool tpa_start_fail;
32301e23015SMintz, Yuval 	u8 state;
32401e23015SMintz, Yuval 	u8 frag_id;
32501e23015SMintz, Yuval 
32601e23015SMintz, Yuval 	u8 tunnel_type;
32755482edcSManish Chopra };
32855482edcSManish Chopra 
3292950219dSYuval Mintz struct qede_rx_queue {
3302950219dSYuval Mintz 	__le16 *hw_cons_ptr;
3319eb22357SMintz, Yuval 	void __iomem *hw_rxq_prod_addr;
3329eb22357SMintz, Yuval 
3339eb22357SMintz, Yuval 	/* Required for the allocation of replacement buffers */
3349eb22357SMintz, Yuval 	struct device *dev;
3359eb22357SMintz, Yuval 
336496e0517SMintz, Yuval 	struct bpf_prog *xdp_prog;
337496e0517SMintz, Yuval 
3382950219dSYuval Mintz 	u16 sw_rx_cons;
3392950219dSYuval Mintz 	u16 sw_rx_prod;
3409eb22357SMintz, Yuval 
341e3eef7eeSMintz, Yuval 	u16 filled_buffers;
342cb6aeb07SMintz, Yuval 	u8 data_direction;
3439eb22357SMintz, Yuval 	u8 rxq_id;
3449eb22357SMintz, Yuval 
34515ed8a47SMintz, Yuval 	/* Used once per each NAPI run */
34615ed8a47SMintz, Yuval 	u16 num_rx_buffers;
34715ed8a47SMintz, Yuval 
34815ed8a47SMintz, Yuval 	u16 rx_headroom;
34915ed8a47SMintz, Yuval 
3509eb22357SMintz, Yuval 	u32 rx_buf_size;
3519eb22357SMintz, Yuval 	u32 rx_buf_seg_size;
3529eb22357SMintz, Yuval 
3539eb22357SMintz, Yuval 	struct sw_rx_data *sw_rx_ring;
3542950219dSYuval Mintz 	struct qed_chain rx_bd_ring;
3559eb22357SMintz, Yuval 	struct qed_chain rx_comp_ring ____cacheline_aligned;
3562950219dSYuval Mintz 
35755482edcSManish Chopra 	/* GRO */
35855482edcSManish Chopra 	struct qede_agg_info tpa_info[ETH_TPA_MAX_AGGS_NUM];
35955482edcSManish Chopra 
36015ed8a47SMintz, Yuval 	/* Used once per each NAPI run */
36115ed8a47SMintz, Yuval 	u64 rcv_pkts;
36215ed8a47SMintz, Yuval 
3632950219dSYuval Mintz 	u64 rx_hw_errors;
3642950219dSYuval Mintz 	u64 rx_alloc_errors;
365c72a6125SManish Chopra 	u64 rx_ip_frags;
3663da7a37aSMintz, Yuval 
367496e0517SMintz, Yuval 	u64 xdp_no_pass;
368496e0517SMintz, Yuval 
3693da7a37aSMintz, Yuval 	void *handle;
370c0124f32SJesper Dangaard Brouer 	struct xdp_rxq_info xdp_rxq;
3712950219dSYuval Mintz };
3722950219dSYuval Mintz 
3732950219dSYuval Mintz union db_prod {
3742950219dSYuval Mintz 	struct eth_db_data data;
3752950219dSYuval Mintz 	u32		raw;
3762950219dSYuval Mintz };
3772950219dSYuval Mintz 
3782950219dSYuval Mintz struct sw_tx_bd {
3792950219dSYuval Mintz 	struct sk_buff *skb;
3802950219dSYuval Mintz 	u8 flags;
3812950219dSYuval Mintz /* Set on the first BD descriptor when there is a split BD */
3822950219dSYuval Mintz #define QEDE_TSO_SPLIT_BD		BIT(0)
3832950219dSYuval Mintz };
3842950219dSYuval Mintz 
38589e1afc4SMintz, Yuval struct sw_tx_xdp {
38689e1afc4SMintz, Yuval 	struct page			*page;
387d1b25b79SAlexander Lobakin 	struct xdp_frame		*xdpf;
38889e1afc4SMintz, Yuval 	dma_addr_t			mapping;
38989e1afc4SMintz, Yuval };
39089e1afc4SMintz, Yuval 
3912950219dSYuval Mintz struct qede_tx_queue {
392cb6aeb07SMintz, Yuval 	u8				is_xdp;
3939eb22357SMintz, Yuval 	bool				is_legacy;
3942950219dSYuval Mintz 	u16				sw_tx_cons;
3952950219dSYuval Mintz 	u16				sw_tx_prod;
3969eb22357SMintz, Yuval 	u16				num_tx_buffers; /* Slowpath only */
3972950219dSYuval Mintz 
39868db9ec2SSudarsana Reddy Kalluru 	u64				xmit_pkts;
39968db9ec2SSudarsana Reddy Kalluru 	u64				stopped_cnt;
400dcc6abaeSMichael Shteinbok 	u64				tx_mem_alloc_err;
401d8c2c7e3SYuval Mintz 
4029eb22357SMintz, Yuval 	__le16				*hw_cons_ptr;
4033da7a37aSMintz, Yuval 
4049eb22357SMintz, Yuval 	/* Needed for the mapping of packets */
4059eb22357SMintz, Yuval 	struct device			*dev;
4069eb22357SMintz, Yuval 
4079eb22357SMintz, Yuval 	void __iomem			*doorbell_addr;
4089eb22357SMintz, Yuval 	union db_prod			tx_db;
409f35535f7SAlexander Lobakin 
410d1b25b79SAlexander Lobakin 	/* Spinlock for XDP queues in case of XDP_REDIRECT */
411d1b25b79SAlexander Lobakin 	spinlock_t			xdp_tx_lock;
412d1b25b79SAlexander Lobakin 
4139eb22357SMintz, Yuval 	int				index; /* Slowpath only */
414cb6aeb07SMintz, Yuval #define QEDE_TXQ_XDP_TO_IDX(edev, txq)	((txq)->index - \
415cb6aeb07SMintz, Yuval 					 QEDE_MAX_TSS_CNT(edev))
416cb6aeb07SMintz, Yuval #define QEDE_TXQ_IDX_TO_XDP(edev, idx)	((idx) + QEDE_MAX_TSS_CNT(edev))
4175e7baf0fSManish Chopra #define QEDE_NDEV_TXQ_ID_TO_FP_ID(edev, idx)	((edev)->fp_num_rx + \
4185e7baf0fSManish Chopra 						 ((idx) % QEDE_TSS_COUNT(edev)))
4195e7baf0fSManish Chopra #define QEDE_NDEV_TXQ_ID_TO_TXQ_COS(edev, idx)	((idx) / QEDE_TSS_COUNT(edev))
4205e7baf0fSManish Chopra #define QEDE_TXQ_TO_NDEV_TXQ_ID(edev, txq)	((QEDE_TSS_COUNT(edev) * \
4215e7baf0fSManish Chopra 						 (txq)->cos) + (txq)->index)
4225e7baf0fSManish Chopra #define QEDE_NDEV_TXQ_ID_TO_TXQ(edev, idx)	\
4235e7baf0fSManish Chopra 	(&((edev)->fp_array[QEDE_NDEV_TXQ_ID_TO_FP_ID(edev, idx)].txq \
4245e7baf0fSManish Chopra 	[QEDE_NDEV_TXQ_ID_TO_TXQ_COS(edev, idx)]))
4255e7baf0fSManish Chopra #define QEDE_FP_TC0_TXQ(fp)		(&((fp)->txq[0]))
4269eb22357SMintz, Yuval 
427cb6aeb07SMintz, Yuval 	/* Regular Tx requires skb + metadata for release purpose,
42889e1afc4SMintz, Yuval 	 * while XDP requires the pages and the mapped address.
429cb6aeb07SMintz, Yuval 	 */
430cb6aeb07SMintz, Yuval 	union {
431cb6aeb07SMintz, Yuval 		struct sw_tx_bd		*skbs;
43289e1afc4SMintz, Yuval 		struct sw_tx_xdp	*xdp;
433cb6aeb07SMintz, Yuval 	}				sw_tx_ring;
434cb6aeb07SMintz, Yuval 
4359eb22357SMintz, Yuval 	struct qed_chain		tx_pbl;
4369eb22357SMintz, Yuval 
4379eb22357SMintz, Yuval 	/* Slowpath; Should be kept in end [unless missing padding] */
4389eb22357SMintz, Yuval 	void				*handle;
4395e7baf0fSManish Chopra 	u16				cos;
4405e7baf0fSManish Chopra 	u16				ndev_txq_id;
4412950219dSYuval Mintz };
4422950219dSYuval Mintz 
4432950219dSYuval Mintz #define BD_UNMAP_ADDR(bd)		HILO_U64(le32_to_cpu((bd)->addr.hi), \
4442950219dSYuval Mintz 						 le32_to_cpu((bd)->addr.lo))
4452950219dSYuval Mintz #define BD_SET_UNMAP_ADDR_LEN(bd, maddr, len)				\
4462950219dSYuval Mintz 	do {								\
4472950219dSYuval Mintz 		(bd)->addr.hi = cpu_to_le32(upper_32_bits(maddr));	\
4482950219dSYuval Mintz 		(bd)->addr.lo = cpu_to_le32(lower_32_bits(maddr));	\
4492950219dSYuval Mintz 		(bd)->nbytes = cpu_to_le16(len);			\
4502950219dSYuval Mintz 	} while (0)
4512950219dSYuval Mintz #define BD_UNMAP_LEN(bd)		(le16_to_cpu((bd)->nbytes))
4522950219dSYuval Mintz 
4532950219dSYuval Mintz struct qede_fastpath {
4542950219dSYuval Mintz 	struct qede_dev			*edev;
455f35535f7SAlexander Lobakin 
456f35535f7SAlexander Lobakin 	u8				type;
4579a4d7e86SSudarsana Reddy Kalluru #define QEDE_FASTPATH_TX		BIT(0)
4589a4d7e86SSudarsana Reddy Kalluru #define QEDE_FASTPATH_RX		BIT(1)
459496e0517SMintz, Yuval #define QEDE_FASTPATH_XDP		BIT(2)
4609a4d7e86SSudarsana Reddy Kalluru #define QEDE_FASTPATH_COMBINED		(QEDE_FASTPATH_TX | QEDE_FASTPATH_RX)
461f35535f7SAlexander Lobakin 
4629a4d7e86SSudarsana Reddy Kalluru 	u8				id;
463f35535f7SAlexander Lobakin 
464cb6aeb07SMintz, Yuval 	u8				xdp_xmit;
4654c2bacbeSAlexander Lobakin #define QEDE_XDP_TX			BIT(0)
466d1b25b79SAlexander Lobakin #define QEDE_XDP_REDIRECT		BIT(1)
467f35535f7SAlexander Lobakin 
4682950219dSYuval Mintz 	struct napi_struct		napi;
4692950219dSYuval Mintz 	struct qed_sb_info		*sb_info;
4702950219dSYuval Mintz 	struct qede_rx_queue		*rxq;
47180439a17SMintz, Yuval 	struct qede_tx_queue		*txq;
472cb6aeb07SMintz, Yuval 	struct qede_tx_queue		*xdp_tx;
4732950219dSYuval Mintz 
474f35535f7SAlexander Lobakin 	char				name[IFNAMSIZ + 8];
475e712d52bSYuval Mintz };
476e712d52bSYuval Mintz 
477e712d52bSYuval Mintz /* Debug print definitions */
478f35535f7SAlexander Lobakin #define DP_NAME(edev)			netdev_name((edev)->ndev)
479e712d52bSYuval Mintz 
4802950219dSYuval Mintz #define XMIT_PLAIN			0
4812950219dSYuval Mintz #define XMIT_L4_CSUM			BIT(0)
4822950219dSYuval Mintz #define XMIT_LSO			BIT(1)
4832950219dSYuval Mintz #define XMIT_ENC			BIT(2)
484a150241cSManish Chopra #define XMIT_ENC_GSO_L4_CSUM		BIT(3)
4852950219dSYuval Mintz 
4862950219dSYuval Mintz #define QEDE_CSUM_ERROR			BIT(0)
4872950219dSYuval Mintz #define QEDE_CSUM_UNNECESSARY		BIT(1)
48814db81deSManish Chopra #define QEDE_TUNN_CSUM_UNNECESSARY	BIT(2)
4890d8e0aa0SSudarsana Kalluru 
490ccc67ef5STomer Tayar #define QEDE_SP_RECOVERY		0
4910d8e0aa0SSudarsana Kalluru #define QEDE_SP_RX_MODE			1
492a8736ea8SIgor Russkikh #define QEDE_SP_RSVD1                   2
493a8736ea8SIgor Russkikh #define QEDE_SP_RSVD2                   3
494a8736ea8SIgor Russkikh #define QEDE_SP_HW_ERR                  4
495a8736ea8SIgor Russkikh #define QEDE_SP_ARFS_CONFIG             5
496731815e7SSudarsana Reddy Kalluru #define QEDE_SP_AER			7
4971159e25cSPrabhakar Kushwaha #define QEDE_SP_DISABLE			8
4980d8e0aa0SSudarsana Kalluru 
499e4917d46SChopra, Manish #ifdef CONFIG_RFS_ACCEL
500e4917d46SChopra, Manish int qede_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
501e4917d46SChopra, Manish 		       u16 rxq_index, u32 flow_id);
5023f2a2b8bSChopra, Manish #define QEDE_SP_TASK_POLL_DELAY	(5 * HZ)
5033f2a2b8bSChopra, Manish #endif
5043f2a2b8bSChopra, Manish 
505e4917d46SChopra, Manish void qede_process_arfs_filters(struct qede_dev *edev, bool free_fltr);
506e4917d46SChopra, Manish void qede_poll_for_freeing_arfs_filters(struct qede_dev *edev);
507e4917d46SChopra, Manish void qede_arfs_filter_op(void *dev, void *filter, u8 fw_rc);
508e4917d46SChopra, Manish void qede_free_arfs(struct qede_dev *edev);
509e4917d46SChopra, Manish int qede_alloc_arfs(struct qede_dev *edev);
5103f2a2b8bSChopra, Manish int qede_add_cls_rule(struct qede_dev *edev, struct ethtool_rxnfc *info);
5112ce9c93eSManish Chopra int qede_delete_flow_filter(struct qede_dev *edev, u64 cookie);
512ec9b8dbdSChopra, Manish int qede_get_cls_rule_entry(struct qede_dev *edev, struct ethtool_rxnfc *cmd);
513ec9b8dbdSChopra, Manish int qede_get_cls_rule_all(struct qede_dev *edev, struct ethtool_rxnfc *info,
514ec9b8dbdSChopra, Manish 			  u32 *rule_locs);
515ec9b8dbdSChopra, Manish int qede_get_arfs_filter_count(struct qede_dev *edev);
516ec9b8dbdSChopra, Manish 
517567b3c12SMintz, Yuval struct qede_reload_args {
518567b3c12SMintz, Yuval 	void (*func)(struct qede_dev *edev, struct qede_reload_args *args);
519567b3c12SMintz, Yuval 	union {
520567b3c12SMintz, Yuval 		netdev_features_t features;
521496e0517SMintz, Yuval 		struct bpf_prog *new_prog;
5220d8e0aa0SSudarsana Kalluru 		u16 mtu;
523567b3c12SMintz, Yuval 	} u;
5240d8e0aa0SSudarsana Kalluru };
5250d8e0aa0SSudarsana Kalluru 
526cdda926dSMintz, Yuval /* Datapath functions definition */
527cdda926dSMintz, Yuval netdev_tx_t qede_start_xmit(struct sk_buff *skb, struct net_device *ndev);
528d1b25b79SAlexander Lobakin int qede_xdp_transmit(struct net_device *dev, int n_frames,
529d1b25b79SAlexander Lobakin 		      struct xdp_frame **frames, u32 flags);
5300aa4febbSSudarsana Reddy Kalluru u16 qede_select_queue(struct net_device *dev, struct sk_buff *skb,
531a350ecceSPaolo Abeni 		      struct net_device *sb_dev);
532cdda926dSMintz, Yuval netdev_features_t qede_features_check(struct sk_buff *skb,
533cdda926dSMintz, Yuval 				      struct net_device *dev,
534cdda926dSMintz, Yuval 				      netdev_features_t features);
535e3eef7eeSMintz, Yuval int qede_alloc_rx_buffer(struct qede_rx_queue *rxq, bool allow_lazy);
536cdda926dSMintz, Yuval int qede_free_tx_pkt(struct qede_dev *edev,
537cdda926dSMintz, Yuval 		     struct qede_tx_queue *txq, int *len);
538cdda926dSMintz, Yuval int qede_poll(struct napi_struct *napi, int budget);
539cdda926dSMintz, Yuval irqreturn_t qede_msix_fp_int(int irq, void *fp_cookie);
540aed284c7SMintz, Yuval 
541aed284c7SMintz, Yuval /* Filtering function definitions */
542aed284c7SMintz, Yuval void qede_force_mac(void *dev, u8 *mac, bool forced);
54397379f15SChopra, Manish void qede_udp_ports_update(void *dev, u16 vxlan_port, u16 geneve_port);
544aed284c7SMintz, Yuval int qede_set_mac_addr(struct net_device *ndev, void *p);
545aed284c7SMintz, Yuval 
546aed284c7SMintz, Yuval int qede_vlan_rx_add_vid(struct net_device *dev, __be16 proto, u16 vid);
547aed284c7SMintz, Yuval int qede_vlan_rx_kill_vid(struct net_device *dev, __be16 proto, u16 vid);
548aed284c7SMintz, Yuval void qede_vlan_mark_nonconfigured(struct qede_dev *edev);
549aed284c7SMintz, Yuval int qede_configure_vlan_filters(struct qede_dev *edev);
550aed284c7SMintz, Yuval 
55118c602deSMichael Chan netdev_features_t qede_fix_features(struct net_device *dev,
55218c602deSMichael Chan 				    netdev_features_t features);
553aed284c7SMintz, Yuval int qede_set_features(struct net_device *dev, netdev_features_t features);
554aed284c7SMintz, Yuval void qede_set_rx_mode(struct net_device *ndev);
555aed284c7SMintz, Yuval void qede_config_rx_mode(struct net_device *ndev);
556aed284c7SMintz, Yuval void qede_fill_rss_params(struct qede_dev *edev,
557aed284c7SMintz, Yuval 			  struct qed_update_vport_rss_params *rss, u8 *update);
558aed284c7SMintz, Yuval 
559f4e63525SJakub Kicinski int qede_xdp(struct net_device *dev, struct netdev_bpf *xdp);
560aed284c7SMintz, Yuval 
561489e45aeSSudarsana Reddy Kalluru #ifdef CONFIG_DCB
562489e45aeSSudarsana Reddy Kalluru void qede_set_dcbnl_ops(struct net_device *ndev);
563489e45aeSSudarsana Reddy Kalluru #endif
564aed284c7SMintz, Yuval 
565133fac0eSSudarsana Kalluru void qede_config_debug(uint debug, u32 *p_dp_module, u8 *p_dp_level);
566133fac0eSSudarsana Kalluru void qede_set_ethtool_ops(struct net_device *netdev);
5678cd160a2SJakub Kicinski void qede_set_udp_tunnels(struct qede_dev *edev);
568133fac0eSSudarsana Kalluru void qede_reload(struct qede_dev *edev,
569567b3c12SMintz, Yuval 		 struct qede_reload_args *args, bool is_locked);
570133fac0eSSudarsana Kalluru int qede_change_mtu(struct net_device *dev, int new_mtu);
571133fac0eSSudarsana Kalluru void qede_fill_by_demand_stats(struct qede_dev *edev);
572567b3c12SMintz, Yuval void __qede_lock(struct qede_dev *edev);
573567b3c12SMintz, Yuval void __qede_unlock(struct qede_dev *edev);
57416f46bf0SSudarsana Reddy Kalluru bool qede_has_rx_work(struct qede_rx_queue *rxq);
57516f46bf0SSudarsana Reddy Kalluru int qede_txq_has_work(struct qede_tx_queue *txq);
5769eb22357SMintz, Yuval void qede_recycle_rx_bd_ring(struct qede_rx_queue *rxq, u8 count);
577837d4eb6SSudarsana Reddy Kalluru void qede_update_rx_prod(struct qede_dev *edev, struct qede_rx_queue *rxq);
5782ce9c93eSManish Chopra int qede_add_tc_flower_fltr(struct qede_dev *edev, __be16 proto,
579f9e30088SPablo Neira Ayuso 			    struct flow_cls_offload *f);
580133fac0eSSudarsana Kalluru 
5811d4e4eccSAlexander Lobakin void qede_forced_speed_maps_init(void);
582f3ccfda1SYufeng Mo int qede_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal,
583f3ccfda1SYufeng Mo 		      struct kernel_ethtool_coalesce *kernel_coal,
584f3ccfda1SYufeng Mo 		      struct netlink_ext_ack *extack);
585b0ec5489SBhaskar Upadhaya int qede_set_per_coalesce(struct net_device *dev, u32 queue,
586b0ec5489SBhaskar Upadhaya 			  struct ethtool_coalesce *coal);
5871d4e4eccSAlexander Lobakin 
5882950219dSYuval Mintz #define RX_RING_SIZE_POW	13
58901ef7e05SSudarsana Kalluru #define RX_RING_SIZE		((u16)BIT(RX_RING_SIZE_POW))
5902950219dSYuval Mintz #define NUM_RX_BDS_MAX		(RX_RING_SIZE - 1)
5912950219dSYuval Mintz #define NUM_RX_BDS_MIN		128
59273e03097SBhupesh Sharma #define NUM_RX_BDS_KDUMP_MIN	63
5930e191827SSudarsana Reddy Kalluru #define NUM_RX_BDS_DEF		((u16)BIT(10) - 1)
5942950219dSYuval Mintz 
5952950219dSYuval Mintz #define TX_RING_SIZE_POW	13
59601ef7e05SSudarsana Kalluru #define TX_RING_SIZE		((u16)BIT(TX_RING_SIZE_POW))
5972950219dSYuval Mintz #define NUM_TX_BDS_MAX		(TX_RING_SIZE - 1)
5982950219dSYuval Mintz #define NUM_TX_BDS_MIN		128
59973e03097SBhupesh Sharma #define NUM_TX_BDS_KDUMP_MIN	63
6002950219dSYuval Mintz #define NUM_TX_BDS_DEF		NUM_TX_BDS_MAX
6012950219dSYuval Mintz 
6023d789994SManish Chopra #define QEDE_MIN_PKT_LEN		64
603fc48b7a6SYuval Mintz #define QEDE_RX_HDR_SIZE		256
604caff2a87SJarod Wilson #define QEDE_MAX_JUMBO_PACKET_SIZE	9600
6059a4d7e86SSudarsana Reddy Kalluru #define	for_each_queue(i) for (i = 0; i < edev->num_queues; i++)
6065e7baf0fSManish Chopra #define for_each_cos_in_txq(edev, var) \
6075e7baf0fSManish Chopra 	for ((var) = 0; (var) < (edev)->dev_info.num_tc; (var)++)
6082950219dSYuval Mintz 
609e712d52bSYuval Mintz #endif /* _QEDE_H_ */
610