1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* 3 * Hardware library for MAC Merge Layer and Frame Preemption on TSN-capable 4 * switches (VSC9959) 5 * 6 * Copyright 2022-2023 NXP 7 */ 8 #include <linux/ethtool.h> 9 #include <soc/mscc/ocelot.h> 10 #include <soc/mscc/ocelot_dev.h> 11 #include <soc/mscc/ocelot_qsys.h> 12 13 #include "ocelot.h" 14 15 static const char * 16 mm_verify_state_to_string(enum ethtool_mm_verify_status state) 17 { 18 switch (state) { 19 case ETHTOOL_MM_VERIFY_STATUS_INITIAL: 20 return "INITIAL"; 21 case ETHTOOL_MM_VERIFY_STATUS_VERIFYING: 22 return "VERIFYING"; 23 case ETHTOOL_MM_VERIFY_STATUS_SUCCEEDED: 24 return "SUCCEEDED"; 25 case ETHTOOL_MM_VERIFY_STATUS_FAILED: 26 return "FAILED"; 27 case ETHTOOL_MM_VERIFY_STATUS_DISABLED: 28 return "DISABLED"; 29 default: 30 return "UNKNOWN"; 31 } 32 } 33 34 static enum ethtool_mm_verify_status ocelot_mm_verify_status(u32 val) 35 { 36 switch (DEV_MM_STAT_MM_STATUS_PRMPT_VERIFY_STATE_X(val)) { 37 case 0: 38 return ETHTOOL_MM_VERIFY_STATUS_INITIAL; 39 case 1: 40 return ETHTOOL_MM_VERIFY_STATUS_VERIFYING; 41 case 2: 42 return ETHTOOL_MM_VERIFY_STATUS_SUCCEEDED; 43 case 3: 44 return ETHTOOL_MM_VERIFY_STATUS_FAILED; 45 case 4: 46 return ETHTOOL_MM_VERIFY_STATUS_DISABLED; 47 default: 48 return ETHTOOL_MM_VERIFY_STATUS_UNKNOWN; 49 } 50 } 51 52 void ocelot_port_update_active_preemptible_tcs(struct ocelot *ocelot, int port) 53 { 54 struct ocelot_port *ocelot_port = ocelot->ports[port]; 55 struct ocelot_mm_state *mm = &ocelot->mm[port]; 56 u32 val = 0; 57 58 lockdep_assert_held(&ocelot->fwd_domain_lock); 59 60 /* Only commit preemptible TCs when MAC Merge is active. 61 * On NXP LS1028A, when using QSGMII, the port hangs if transmitting 62 * preemptible frames at any other link speed than gigabit, so avoid 63 * preemption at lower speeds in this PHY mode. 64 */ 65 if ((ocelot_port->phy_mode != PHY_INTERFACE_MODE_QSGMII || 66 ocelot_port->speed == SPEED_1000) && mm->tx_active) 67 val = mm->preemptible_tcs; 68 69 /* Cut through switching doesn't work for preemptible priorities, 70 * so first make sure it is disabled. 71 */ 72 mm->active_preemptible_tcs = val; 73 ocelot->ops->cut_through_fwd(ocelot); 74 75 dev_dbg(ocelot->dev, 76 "port %d %s/%s, MM TX %s, preemptible TCs 0x%x, active 0x%x\n", 77 port, phy_modes(ocelot_port->phy_mode), 78 phy_speed_to_str(ocelot_port->speed), 79 mm->tx_active ? "active" : "inactive", mm->preemptible_tcs, 80 mm->active_preemptible_tcs); 81 82 ocelot_rmw_rix(ocelot, QSYS_PREEMPTION_CFG_P_QUEUES(val), 83 QSYS_PREEMPTION_CFG_P_QUEUES_M, 84 QSYS_PREEMPTION_CFG, port); 85 } 86 87 void ocelot_port_change_fp(struct ocelot *ocelot, int port, 88 unsigned long preemptible_tcs) 89 { 90 struct ocelot_mm_state *mm = &ocelot->mm[port]; 91 92 lockdep_assert_held(&ocelot->fwd_domain_lock); 93 94 if (mm->preemptible_tcs == preemptible_tcs) 95 return; 96 97 mm->preemptible_tcs = preemptible_tcs; 98 99 ocelot_port_update_active_preemptible_tcs(ocelot, port); 100 } 101 102 static void ocelot_mm_update_port_status(struct ocelot *ocelot, int port) 103 { 104 struct ocelot_port *ocelot_port = ocelot->ports[port]; 105 struct ocelot_mm_state *mm = &ocelot->mm[port]; 106 enum ethtool_mm_verify_status verify_status; 107 u32 val, ack = 0; 108 109 if (!mm->tx_enabled) 110 return; 111 112 val = ocelot_port_readl(ocelot_port, DEV_MM_STATUS); 113 114 verify_status = ocelot_mm_verify_status(val); 115 if (mm->verify_status != verify_status) { 116 dev_dbg(ocelot->dev, 117 "Port %d MAC Merge verification state %s\n", 118 port, mm_verify_state_to_string(verify_status)); 119 mm->verify_status = verify_status; 120 } 121 122 if (val & DEV_MM_STAT_MM_STATUS_PRMPT_ACTIVE_STICKY) { 123 mm->tx_active = !!(val & DEV_MM_STAT_MM_STATUS_PRMPT_ACTIVE_STATUS); 124 125 dev_dbg(ocelot->dev, "Port %d TX preemption %s\n", 126 port, mm->tx_active ? "active" : "inactive"); 127 ocelot_port_update_active_preemptible_tcs(ocelot, port); 128 129 ack |= DEV_MM_STAT_MM_STATUS_PRMPT_ACTIVE_STICKY; 130 } 131 132 if (val & DEV_MM_STAT_MM_STATUS_UNEXP_RX_PFRM_STICKY) { 133 dev_err(ocelot->dev, 134 "Unexpected P-frame received on port %d while verification was unsuccessful or not yet verified\n", 135 port); 136 137 ack |= DEV_MM_STAT_MM_STATUS_UNEXP_RX_PFRM_STICKY; 138 } 139 140 if (val & DEV_MM_STAT_MM_STATUS_UNEXP_TX_PFRM_STICKY) { 141 dev_err(ocelot->dev, 142 "Unexpected P-frame requested to be transmitted on port %d while verification was unsuccessful or not yet verified, or MM_TX_ENA=0\n", 143 port); 144 145 ack |= DEV_MM_STAT_MM_STATUS_UNEXP_TX_PFRM_STICKY; 146 } 147 148 if (ack) 149 ocelot_port_writel(ocelot_port, ack, DEV_MM_STATUS); 150 } 151 152 void ocelot_mm_irq(struct ocelot *ocelot) 153 { 154 int port; 155 156 mutex_lock(&ocelot->fwd_domain_lock); 157 158 for (port = 0; port < ocelot->num_phys_ports; port++) 159 ocelot_mm_update_port_status(ocelot, port); 160 161 mutex_unlock(&ocelot->fwd_domain_lock); 162 } 163 EXPORT_SYMBOL_GPL(ocelot_mm_irq); 164 165 int ocelot_port_set_mm(struct ocelot *ocelot, int port, 166 struct ethtool_mm_cfg *cfg, 167 struct netlink_ext_ack *extack) 168 { 169 struct ocelot_port *ocelot_port = ocelot->ports[port]; 170 u32 mm_enable = 0, verify_disable = 0, add_frag_size; 171 struct ocelot_mm_state *mm; 172 int err; 173 174 if (!ocelot->mm_supported) 175 return -EOPNOTSUPP; 176 177 mm = &ocelot->mm[port]; 178 179 err = ethtool_mm_frag_size_min_to_add(cfg->tx_min_frag_size, 180 &add_frag_size, extack); 181 if (err) 182 return err; 183 184 if (cfg->pmac_enabled) 185 mm_enable |= DEV_MM_CONFIG_ENABLE_CONFIG_MM_RX_ENA; 186 187 if (cfg->tx_enabled) 188 mm_enable |= DEV_MM_CONFIG_ENABLE_CONFIG_MM_TX_ENA; 189 190 if (!cfg->verify_enabled) 191 verify_disable = DEV_MM_CONFIG_VERIF_CONFIG_PRM_VERIFY_DIS; 192 193 mutex_lock(&ocelot->fwd_domain_lock); 194 195 ocelot_port_rmwl(ocelot_port, mm_enable, 196 DEV_MM_CONFIG_ENABLE_CONFIG_MM_TX_ENA | 197 DEV_MM_CONFIG_ENABLE_CONFIG_MM_RX_ENA, 198 DEV_MM_ENABLE_CONFIG); 199 200 ocelot_port_rmwl(ocelot_port, verify_disable | 201 DEV_MM_CONFIG_VERIF_CONFIG_PRM_VERIFY_TIME(cfg->verify_time), 202 DEV_MM_CONFIG_VERIF_CONFIG_PRM_VERIFY_DIS | 203 DEV_MM_CONFIG_VERIF_CONFIG_PRM_VERIFY_TIME_M, 204 DEV_MM_VERIF_CONFIG); 205 206 ocelot_rmw_rix(ocelot, 207 QSYS_PREEMPTION_CFG_MM_ADD_FRAG_SIZE(add_frag_size), 208 QSYS_PREEMPTION_CFG_MM_ADD_FRAG_SIZE_M, 209 QSYS_PREEMPTION_CFG, 210 port); 211 212 /* The switch will emit an IRQ when TX is disabled, to notify that it 213 * has become inactive. We optimize ocelot_mm_update_port_status() to 214 * not bother processing MM IRQs at all for ports with TX disabled, 215 * but we need to ACK this IRQ now, while mm->tx_enabled is still set, 216 * otherwise we get an IRQ storm. 217 */ 218 if (mm->tx_enabled && !cfg->tx_enabled) { 219 ocelot_mm_update_port_status(ocelot, port); 220 WARN_ON(mm->tx_active); 221 } 222 223 mm->tx_enabled = cfg->tx_enabled; 224 225 mutex_unlock(&ocelot->fwd_domain_lock); 226 227 return 0; 228 } 229 EXPORT_SYMBOL_GPL(ocelot_port_set_mm); 230 231 int ocelot_port_get_mm(struct ocelot *ocelot, int port, 232 struct ethtool_mm_state *state) 233 { 234 struct ocelot_port *ocelot_port = ocelot->ports[port]; 235 struct ocelot_mm_state *mm; 236 u32 val, add_frag_size; 237 238 if (!ocelot->mm_supported) 239 return -EOPNOTSUPP; 240 241 mm = &ocelot->mm[port]; 242 243 mutex_lock(&ocelot->fwd_domain_lock); 244 245 val = ocelot_port_readl(ocelot_port, DEV_MM_ENABLE_CONFIG); 246 state->pmac_enabled = !!(val & DEV_MM_CONFIG_ENABLE_CONFIG_MM_RX_ENA); 247 state->tx_enabled = !!(val & DEV_MM_CONFIG_ENABLE_CONFIG_MM_TX_ENA); 248 249 val = ocelot_port_readl(ocelot_port, DEV_MM_VERIF_CONFIG); 250 state->verify_enabled = !(val & DEV_MM_CONFIG_VERIF_CONFIG_PRM_VERIFY_DIS); 251 state->verify_time = DEV_MM_CONFIG_VERIF_CONFIG_PRM_VERIFY_TIME_X(val); 252 state->max_verify_time = 128; 253 254 val = ocelot_read_rix(ocelot, QSYS_PREEMPTION_CFG, port); 255 add_frag_size = QSYS_PREEMPTION_CFG_MM_ADD_FRAG_SIZE_X(val); 256 state->tx_min_frag_size = ethtool_mm_frag_size_add_to_min(add_frag_size); 257 state->rx_min_frag_size = ETH_ZLEN; 258 259 ocelot_mm_update_port_status(ocelot, port); 260 state->verify_status = mm->verify_status; 261 state->tx_active = mm->tx_active; 262 263 mutex_unlock(&ocelot->fwd_domain_lock); 264 265 return 0; 266 } 267 EXPORT_SYMBOL_GPL(ocelot_port_get_mm); 268 269 int ocelot_mm_init(struct ocelot *ocelot) 270 { 271 struct ocelot_port *ocelot_port; 272 struct ocelot_mm_state *mm; 273 int port; 274 275 if (!ocelot->mm_supported) 276 return 0; 277 278 ocelot->mm = devm_kcalloc(ocelot->dev, ocelot->num_phys_ports, 279 sizeof(*ocelot->mm), GFP_KERNEL); 280 if (!ocelot->mm) 281 return -ENOMEM; 282 283 for (port = 0; port < ocelot->num_phys_ports; port++) { 284 u32 val; 285 286 mm = &ocelot->mm[port]; 287 ocelot_port = ocelot->ports[port]; 288 289 /* Update initial status variable for the 290 * verification state machine 291 */ 292 val = ocelot_port_readl(ocelot_port, DEV_MM_STATUS); 293 mm->verify_status = ocelot_mm_verify_status(val); 294 } 295 296 return 0; 297 } 298