1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* 3 * Microsemi Ocelot Switch driver 4 * 5 * Copyright (c) 2017 Microsemi Corporation 6 */ 7 #include <linux/dsa/ocelot.h> 8 #include <linux/if_bridge.h> 9 #include <linux/iopoll.h> 10 #include <linux/phy/phy.h> 11 #include <net/pkt_sched.h> 12 #include <soc/mscc/ocelot_hsio.h> 13 #include <soc/mscc/ocelot_vcap.h> 14 #include "ocelot.h" 15 #include "ocelot_vcap.h" 16 17 #define TABLE_UPDATE_SLEEP_US 10 18 #define TABLE_UPDATE_TIMEOUT_US 100000 19 #define MEM_INIT_SLEEP_US 1000 20 #define MEM_INIT_TIMEOUT_US 100000 21 22 #define OCELOT_RSV_VLAN_RANGE_START 4000 23 24 struct ocelot_mact_entry { 25 u8 mac[ETH_ALEN]; 26 u16 vid; 27 enum macaccess_entry_type type; 28 }; 29 30 /* Caller must hold &ocelot->mact_lock */ 31 static inline u32 ocelot_mact_read_macaccess(struct ocelot *ocelot) 32 { 33 return ocelot_read(ocelot, ANA_TABLES_MACACCESS); 34 } 35 36 /* Caller must hold &ocelot->mact_lock */ 37 static inline int ocelot_mact_wait_for_completion(struct ocelot *ocelot) 38 { 39 u32 val; 40 41 return readx_poll_timeout(ocelot_mact_read_macaccess, 42 ocelot, val, 43 (val & ANA_TABLES_MACACCESS_MAC_TABLE_CMD_M) == 44 MACACCESS_CMD_IDLE, 45 TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US); 46 } 47 48 /* Caller must hold &ocelot->mact_lock */ 49 static void ocelot_mact_select(struct ocelot *ocelot, 50 const unsigned char mac[ETH_ALEN], 51 unsigned int vid) 52 { 53 u32 macl = 0, mach = 0; 54 55 /* Set the MAC address to handle and the vlan associated in a format 56 * understood by the hardware. 57 */ 58 mach |= vid << 16; 59 mach |= mac[0] << 8; 60 mach |= mac[1] << 0; 61 macl |= mac[2] << 24; 62 macl |= mac[3] << 16; 63 macl |= mac[4] << 8; 64 macl |= mac[5] << 0; 65 66 ocelot_write(ocelot, macl, ANA_TABLES_MACLDATA); 67 ocelot_write(ocelot, mach, ANA_TABLES_MACHDATA); 68 69 } 70 71 static int __ocelot_mact_learn(struct ocelot *ocelot, int port, 72 const unsigned char mac[ETH_ALEN], 73 unsigned int vid, enum macaccess_entry_type type) 74 { 75 u32 cmd = ANA_TABLES_MACACCESS_VALID | 76 ANA_TABLES_MACACCESS_DEST_IDX(port) | 77 ANA_TABLES_MACACCESS_ENTRYTYPE(type) | 78 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_LEARN); 79 unsigned int mc_ports; 80 int err; 81 82 /* Set MAC_CPU_COPY if the CPU port is used by a multicast entry */ 83 if (type == ENTRYTYPE_MACv4) 84 mc_ports = (mac[1] << 8) | mac[2]; 85 else if (type == ENTRYTYPE_MACv6) 86 mc_ports = (mac[0] << 8) | mac[1]; 87 else 88 mc_ports = 0; 89 90 if (mc_ports & BIT(ocelot->num_phys_ports)) 91 cmd |= ANA_TABLES_MACACCESS_MAC_CPU_COPY; 92 93 ocelot_mact_select(ocelot, mac, vid); 94 95 /* Issue a write command */ 96 ocelot_write(ocelot, cmd, ANA_TABLES_MACACCESS); 97 98 err = ocelot_mact_wait_for_completion(ocelot); 99 100 return err; 101 } 102 103 int ocelot_mact_learn(struct ocelot *ocelot, int port, 104 const unsigned char mac[ETH_ALEN], 105 unsigned int vid, enum macaccess_entry_type type) 106 { 107 int ret; 108 109 mutex_lock(&ocelot->mact_lock); 110 ret = __ocelot_mact_learn(ocelot, port, mac, vid, type); 111 mutex_unlock(&ocelot->mact_lock); 112 113 return ret; 114 } 115 EXPORT_SYMBOL(ocelot_mact_learn); 116 117 int ocelot_mact_forget(struct ocelot *ocelot, 118 const unsigned char mac[ETH_ALEN], unsigned int vid) 119 { 120 int err; 121 122 mutex_lock(&ocelot->mact_lock); 123 124 ocelot_mact_select(ocelot, mac, vid); 125 126 /* Issue a forget command */ 127 ocelot_write(ocelot, 128 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_FORGET), 129 ANA_TABLES_MACACCESS); 130 131 err = ocelot_mact_wait_for_completion(ocelot); 132 133 mutex_unlock(&ocelot->mact_lock); 134 135 return err; 136 } 137 EXPORT_SYMBOL(ocelot_mact_forget); 138 139 int ocelot_mact_lookup(struct ocelot *ocelot, int *dst_idx, 140 const unsigned char mac[ETH_ALEN], 141 unsigned int vid, enum macaccess_entry_type *type) 142 { 143 int val; 144 145 mutex_lock(&ocelot->mact_lock); 146 147 ocelot_mact_select(ocelot, mac, vid); 148 149 /* Issue a read command with MACACCESS_VALID=1. */ 150 ocelot_write(ocelot, ANA_TABLES_MACACCESS_VALID | 151 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_READ), 152 ANA_TABLES_MACACCESS); 153 154 if (ocelot_mact_wait_for_completion(ocelot)) { 155 mutex_unlock(&ocelot->mact_lock); 156 return -ETIMEDOUT; 157 } 158 159 /* Read back the entry flags */ 160 val = ocelot_read(ocelot, ANA_TABLES_MACACCESS); 161 162 mutex_unlock(&ocelot->mact_lock); 163 164 if (!(val & ANA_TABLES_MACACCESS_VALID)) 165 return -ENOENT; 166 167 *dst_idx = ANA_TABLES_MACACCESS_DEST_IDX_X(val); 168 *type = ANA_TABLES_MACACCESS_ENTRYTYPE_X(val); 169 170 return 0; 171 } 172 EXPORT_SYMBOL(ocelot_mact_lookup); 173 174 int ocelot_mact_learn_streamdata(struct ocelot *ocelot, int dst_idx, 175 const unsigned char mac[ETH_ALEN], 176 unsigned int vid, 177 enum macaccess_entry_type type, 178 int sfid, int ssid) 179 { 180 int ret; 181 182 mutex_lock(&ocelot->mact_lock); 183 184 ocelot_write(ocelot, 185 (sfid < 0 ? 0 : ANA_TABLES_STREAMDATA_SFID_VALID) | 186 ANA_TABLES_STREAMDATA_SFID(sfid) | 187 (ssid < 0 ? 0 : ANA_TABLES_STREAMDATA_SSID_VALID) | 188 ANA_TABLES_STREAMDATA_SSID(ssid), 189 ANA_TABLES_STREAMDATA); 190 191 ret = __ocelot_mact_learn(ocelot, dst_idx, mac, vid, type); 192 193 mutex_unlock(&ocelot->mact_lock); 194 195 return ret; 196 } 197 EXPORT_SYMBOL(ocelot_mact_learn_streamdata); 198 199 static void ocelot_mact_init(struct ocelot *ocelot) 200 { 201 /* Configure the learning mode entries attributes: 202 * - Do not copy the frame to the CPU extraction queues. 203 * - Use the vlan and mac_cpoy for dmac lookup. 204 */ 205 ocelot_rmw(ocelot, 0, 206 ANA_AGENCTRL_LEARN_CPU_COPY | ANA_AGENCTRL_IGNORE_DMAC_FLAGS 207 | ANA_AGENCTRL_LEARN_FWD_KILL 208 | ANA_AGENCTRL_LEARN_IGNORE_VLAN, 209 ANA_AGENCTRL); 210 211 /* Clear the MAC table. We are not concurrent with anyone, so 212 * holding &ocelot->mact_lock is pointless. 213 */ 214 ocelot_write(ocelot, MACACCESS_CMD_INIT, ANA_TABLES_MACACCESS); 215 } 216 217 void ocelot_pll5_init(struct ocelot *ocelot) 218 { 219 /* Configure PLL5. This will need a proper CCF driver 220 * The values are coming from the VTSS API for Ocelot 221 */ 222 regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG4, 223 HSIO_PLL5G_CFG4_IB_CTRL(0x7600) | 224 HSIO_PLL5G_CFG4_IB_BIAS_CTRL(0x8)); 225 regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG0, 226 HSIO_PLL5G_CFG0_CORE_CLK_DIV(0x11) | 227 HSIO_PLL5G_CFG0_CPU_CLK_DIV(2) | 228 HSIO_PLL5G_CFG0_ENA_BIAS | 229 HSIO_PLL5G_CFG0_ENA_VCO_BUF | 230 HSIO_PLL5G_CFG0_ENA_CP1 | 231 HSIO_PLL5G_CFG0_SELCPI(2) | 232 HSIO_PLL5G_CFG0_LOOP_BW_RES(0xe) | 233 HSIO_PLL5G_CFG0_SELBGV820(4) | 234 HSIO_PLL5G_CFG0_DIV4 | 235 HSIO_PLL5G_CFG0_ENA_CLKTREE | 236 HSIO_PLL5G_CFG0_ENA_LANE); 237 regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG2, 238 HSIO_PLL5G_CFG2_EN_RESET_FRQ_DET | 239 HSIO_PLL5G_CFG2_EN_RESET_OVERRUN | 240 HSIO_PLL5G_CFG2_GAIN_TEST(0x8) | 241 HSIO_PLL5G_CFG2_ENA_AMPCTRL | 242 HSIO_PLL5G_CFG2_PWD_AMPCTRL_N | 243 HSIO_PLL5G_CFG2_AMPC_SEL(0x10)); 244 } 245 EXPORT_SYMBOL(ocelot_pll5_init); 246 247 static void ocelot_vcap_enable(struct ocelot *ocelot, int port) 248 { 249 ocelot_write_gix(ocelot, ANA_PORT_VCAP_S2_CFG_S2_ENA | 250 ANA_PORT_VCAP_S2_CFG_S2_IP6_CFG(0xa), 251 ANA_PORT_VCAP_S2_CFG, port); 252 253 ocelot_write_gix(ocelot, ANA_PORT_VCAP_CFG_S1_ENA, 254 ANA_PORT_VCAP_CFG, port); 255 256 ocelot_rmw_gix(ocelot, REW_PORT_CFG_ES0_EN, 257 REW_PORT_CFG_ES0_EN, 258 REW_PORT_CFG, port); 259 } 260 261 static int ocelot_single_vlan_aware_bridge(struct ocelot *ocelot, 262 struct netlink_ext_ack *extack) 263 { 264 struct net_device *bridge = NULL; 265 int port; 266 267 for (port = 0; port < ocelot->num_phys_ports; port++) { 268 struct ocelot_port *ocelot_port = ocelot->ports[port]; 269 270 if (!ocelot_port || !ocelot_port->bridge || 271 !br_vlan_enabled(ocelot_port->bridge)) 272 continue; 273 274 if (!bridge) { 275 bridge = ocelot_port->bridge; 276 continue; 277 } 278 279 if (bridge == ocelot_port->bridge) 280 continue; 281 282 NL_SET_ERR_MSG_MOD(extack, 283 "Only one VLAN-aware bridge is supported"); 284 return -EBUSY; 285 } 286 287 return 0; 288 } 289 290 static inline u32 ocelot_vlant_read_vlanaccess(struct ocelot *ocelot) 291 { 292 return ocelot_read(ocelot, ANA_TABLES_VLANACCESS); 293 } 294 295 static inline int ocelot_vlant_wait_for_completion(struct ocelot *ocelot) 296 { 297 u32 val; 298 299 return readx_poll_timeout(ocelot_vlant_read_vlanaccess, 300 ocelot, 301 val, 302 (val & ANA_TABLES_VLANACCESS_VLAN_TBL_CMD_M) == 303 ANA_TABLES_VLANACCESS_CMD_IDLE, 304 TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US); 305 } 306 307 static int ocelot_vlant_set_mask(struct ocelot *ocelot, u16 vid, u32 mask) 308 { 309 /* Select the VID to configure */ 310 ocelot_write(ocelot, ANA_TABLES_VLANTIDX_V_INDEX(vid), 311 ANA_TABLES_VLANTIDX); 312 /* Set the vlan port members mask and issue a write command */ 313 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_VLAN_PORT_MASK(mask) | 314 ANA_TABLES_VLANACCESS_CMD_WRITE, 315 ANA_TABLES_VLANACCESS); 316 317 return ocelot_vlant_wait_for_completion(ocelot); 318 } 319 320 static int ocelot_port_num_untagged_vlans(struct ocelot *ocelot, int port) 321 { 322 struct ocelot_bridge_vlan *vlan; 323 int num_untagged = 0; 324 325 list_for_each_entry(vlan, &ocelot->vlans, list) { 326 if (!(vlan->portmask & BIT(port))) 327 continue; 328 329 /* Ignore the VLAN added by ocelot_add_vlan_unaware_pvid(), 330 * because this is never active in hardware at the same time as 331 * the bridge VLANs, which only matter in VLAN-aware mode. 332 */ 333 if (vlan->vid >= OCELOT_RSV_VLAN_RANGE_START) 334 continue; 335 336 if (vlan->untagged & BIT(port)) 337 num_untagged++; 338 } 339 340 return num_untagged; 341 } 342 343 static int ocelot_port_num_tagged_vlans(struct ocelot *ocelot, int port) 344 { 345 struct ocelot_bridge_vlan *vlan; 346 int num_tagged = 0; 347 348 list_for_each_entry(vlan, &ocelot->vlans, list) { 349 if (!(vlan->portmask & BIT(port))) 350 continue; 351 352 if (!(vlan->untagged & BIT(port))) 353 num_tagged++; 354 } 355 356 return num_tagged; 357 } 358 359 /* We use native VLAN when we have to mix egress-tagged VLANs with exactly 360 * _one_ egress-untagged VLAN (_the_ native VLAN) 361 */ 362 static bool ocelot_port_uses_native_vlan(struct ocelot *ocelot, int port) 363 { 364 return ocelot_port_num_tagged_vlans(ocelot, port) && 365 ocelot_port_num_untagged_vlans(ocelot, port) == 1; 366 } 367 368 static struct ocelot_bridge_vlan * 369 ocelot_port_find_native_vlan(struct ocelot *ocelot, int port) 370 { 371 struct ocelot_bridge_vlan *vlan; 372 373 list_for_each_entry(vlan, &ocelot->vlans, list) 374 if (vlan->portmask & BIT(port) && vlan->untagged & BIT(port)) 375 return vlan; 376 377 return NULL; 378 } 379 380 /* Keep in sync REW_TAG_CFG_TAG_CFG and, if applicable, 381 * REW_PORT_VLAN_CFG_PORT_VID, with the bridge VLAN table and VLAN awareness 382 * state of the port. 383 */ 384 static void ocelot_port_manage_port_tag(struct ocelot *ocelot, int port) 385 { 386 struct ocelot_port *ocelot_port = ocelot->ports[port]; 387 enum ocelot_port_tag_config tag_cfg; 388 bool uses_native_vlan = false; 389 390 if (ocelot_port->vlan_aware) { 391 uses_native_vlan = ocelot_port_uses_native_vlan(ocelot, port); 392 393 if (uses_native_vlan) 394 tag_cfg = OCELOT_PORT_TAG_NATIVE; 395 else if (ocelot_port_num_untagged_vlans(ocelot, port)) 396 tag_cfg = OCELOT_PORT_TAG_DISABLED; 397 else 398 tag_cfg = OCELOT_PORT_TAG_TRUNK; 399 } else { 400 tag_cfg = OCELOT_PORT_TAG_DISABLED; 401 } 402 403 ocelot_rmw_gix(ocelot, REW_TAG_CFG_TAG_CFG(tag_cfg), 404 REW_TAG_CFG_TAG_CFG_M, 405 REW_TAG_CFG, port); 406 407 if (uses_native_vlan) { 408 struct ocelot_bridge_vlan *native_vlan; 409 410 /* Not having a native VLAN is impossible, because 411 * ocelot_port_num_untagged_vlans has returned 1. 412 * So there is no use in checking for NULL here. 413 */ 414 native_vlan = ocelot_port_find_native_vlan(ocelot, port); 415 416 ocelot_rmw_gix(ocelot, 417 REW_PORT_VLAN_CFG_PORT_VID(native_vlan->vid), 418 REW_PORT_VLAN_CFG_PORT_VID_M, 419 REW_PORT_VLAN_CFG, port); 420 } 421 } 422 423 int ocelot_bridge_num_find(struct ocelot *ocelot, 424 const struct net_device *bridge) 425 { 426 int port; 427 428 for (port = 0; port < ocelot->num_phys_ports; port++) { 429 struct ocelot_port *ocelot_port = ocelot->ports[port]; 430 431 if (ocelot_port && ocelot_port->bridge == bridge) 432 return ocelot_port->bridge_num; 433 } 434 435 return -1; 436 } 437 EXPORT_SYMBOL_GPL(ocelot_bridge_num_find); 438 439 static u16 ocelot_vlan_unaware_pvid(struct ocelot *ocelot, 440 const struct net_device *bridge) 441 { 442 int bridge_num; 443 444 /* Standalone ports use VID 0 */ 445 if (!bridge) 446 return 0; 447 448 bridge_num = ocelot_bridge_num_find(ocelot, bridge); 449 if (WARN_ON(bridge_num < 0)) 450 return 0; 451 452 /* VLAN-unaware bridges use a reserved VID going from 4095 downwards */ 453 return VLAN_N_VID - bridge_num - 1; 454 } 455 456 /* Default vlan to clasify for untagged frames (may be zero) */ 457 static void ocelot_port_set_pvid(struct ocelot *ocelot, int port, 458 const struct ocelot_bridge_vlan *pvid_vlan) 459 { 460 struct ocelot_port *ocelot_port = ocelot->ports[port]; 461 u16 pvid = ocelot_vlan_unaware_pvid(ocelot, ocelot_port->bridge); 462 u32 val = 0; 463 464 ocelot_port->pvid_vlan = pvid_vlan; 465 466 if (ocelot_port->vlan_aware && pvid_vlan) 467 pvid = pvid_vlan->vid; 468 469 ocelot_rmw_gix(ocelot, 470 ANA_PORT_VLAN_CFG_VLAN_VID(pvid), 471 ANA_PORT_VLAN_CFG_VLAN_VID_M, 472 ANA_PORT_VLAN_CFG, port); 473 474 /* If there's no pvid, we should drop not only untagged traffic (which 475 * happens automatically), but also 802.1p traffic which gets 476 * classified to VLAN 0, but that is always in our RX filter, so it 477 * would get accepted were it not for this setting. 478 */ 479 if (!pvid_vlan && ocelot_port->vlan_aware) 480 val = ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA | 481 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA; 482 483 ocelot_rmw_gix(ocelot, val, 484 ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA | 485 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA, 486 ANA_PORT_DROP_CFG, port); 487 } 488 489 static struct ocelot_bridge_vlan *ocelot_bridge_vlan_find(struct ocelot *ocelot, 490 u16 vid) 491 { 492 struct ocelot_bridge_vlan *vlan; 493 494 list_for_each_entry(vlan, &ocelot->vlans, list) 495 if (vlan->vid == vid) 496 return vlan; 497 498 return NULL; 499 } 500 501 static int ocelot_vlan_member_add(struct ocelot *ocelot, int port, u16 vid, 502 bool untagged) 503 { 504 struct ocelot_bridge_vlan *vlan = ocelot_bridge_vlan_find(ocelot, vid); 505 unsigned long portmask; 506 int err; 507 508 if (vlan) { 509 portmask = vlan->portmask | BIT(port); 510 511 err = ocelot_vlant_set_mask(ocelot, vid, portmask); 512 if (err) 513 return err; 514 515 vlan->portmask = portmask; 516 /* Bridge VLANs can be overwritten with a different 517 * egress-tagging setting, so make sure to override an untagged 518 * with a tagged VID if that's going on. 519 */ 520 if (untagged) 521 vlan->untagged |= BIT(port); 522 else 523 vlan->untagged &= ~BIT(port); 524 525 return 0; 526 } 527 528 vlan = kzalloc(sizeof(*vlan), GFP_KERNEL); 529 if (!vlan) 530 return -ENOMEM; 531 532 portmask = BIT(port); 533 534 err = ocelot_vlant_set_mask(ocelot, vid, portmask); 535 if (err) { 536 kfree(vlan); 537 return err; 538 } 539 540 vlan->vid = vid; 541 vlan->portmask = portmask; 542 if (untagged) 543 vlan->untagged = BIT(port); 544 INIT_LIST_HEAD(&vlan->list); 545 list_add_tail(&vlan->list, &ocelot->vlans); 546 547 return 0; 548 } 549 550 static int ocelot_vlan_member_del(struct ocelot *ocelot, int port, u16 vid) 551 { 552 struct ocelot_bridge_vlan *vlan = ocelot_bridge_vlan_find(ocelot, vid); 553 unsigned long portmask; 554 int err; 555 556 if (!vlan) 557 return 0; 558 559 portmask = vlan->portmask & ~BIT(port); 560 561 err = ocelot_vlant_set_mask(ocelot, vid, portmask); 562 if (err) 563 return err; 564 565 vlan->portmask = portmask; 566 if (vlan->portmask) 567 return 0; 568 569 list_del(&vlan->list); 570 kfree(vlan); 571 572 return 0; 573 } 574 575 static int ocelot_add_vlan_unaware_pvid(struct ocelot *ocelot, int port, 576 const struct net_device *bridge) 577 { 578 u16 vid = ocelot_vlan_unaware_pvid(ocelot, bridge); 579 580 return ocelot_vlan_member_add(ocelot, port, vid, true); 581 } 582 583 static int ocelot_del_vlan_unaware_pvid(struct ocelot *ocelot, int port, 584 const struct net_device *bridge) 585 { 586 u16 vid = ocelot_vlan_unaware_pvid(ocelot, bridge); 587 588 return ocelot_vlan_member_del(ocelot, port, vid); 589 } 590 591 int ocelot_port_vlan_filtering(struct ocelot *ocelot, int port, 592 bool vlan_aware, struct netlink_ext_ack *extack) 593 { 594 struct ocelot_vcap_block *block = &ocelot->block[VCAP_IS1]; 595 struct ocelot_port *ocelot_port = ocelot->ports[port]; 596 struct ocelot_vcap_filter *filter; 597 int err = 0; 598 u32 val; 599 600 list_for_each_entry(filter, &block->rules, list) { 601 if (filter->ingress_port_mask & BIT(port) && 602 filter->action.vid_replace_ena) { 603 NL_SET_ERR_MSG_MOD(extack, 604 "Cannot change VLAN state with vlan modify rules active"); 605 return -EBUSY; 606 } 607 } 608 609 err = ocelot_single_vlan_aware_bridge(ocelot, extack); 610 if (err) 611 return err; 612 613 if (vlan_aware) 614 err = ocelot_del_vlan_unaware_pvid(ocelot, port, 615 ocelot_port->bridge); 616 else if (ocelot_port->bridge) 617 err = ocelot_add_vlan_unaware_pvid(ocelot, port, 618 ocelot_port->bridge); 619 if (err) 620 return err; 621 622 ocelot_port->vlan_aware = vlan_aware; 623 624 if (vlan_aware) 625 val = ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 626 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1); 627 else 628 val = 0; 629 ocelot_rmw_gix(ocelot, val, 630 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 631 ANA_PORT_VLAN_CFG_VLAN_POP_CNT_M, 632 ANA_PORT_VLAN_CFG, port); 633 634 ocelot_port_set_pvid(ocelot, port, ocelot_port->pvid_vlan); 635 ocelot_port_manage_port_tag(ocelot, port); 636 637 return 0; 638 } 639 EXPORT_SYMBOL(ocelot_port_vlan_filtering); 640 641 int ocelot_vlan_prepare(struct ocelot *ocelot, int port, u16 vid, bool pvid, 642 bool untagged, struct netlink_ext_ack *extack) 643 { 644 if (untagged) { 645 /* We are adding an egress-tagged VLAN */ 646 if (ocelot_port_uses_native_vlan(ocelot, port)) { 647 NL_SET_ERR_MSG_MOD(extack, 648 "Port with egress-tagged VLANs cannot have more than one egress-untagged (native) VLAN"); 649 return -EBUSY; 650 } 651 } else { 652 /* We are adding an egress-tagged VLAN */ 653 if (ocelot_port_num_untagged_vlans(ocelot, port) > 1) { 654 NL_SET_ERR_MSG_MOD(extack, 655 "Port with more than one egress-untagged VLAN cannot have egress-tagged VLANs"); 656 return -EBUSY; 657 } 658 } 659 660 if (vid > OCELOT_RSV_VLAN_RANGE_START) { 661 NL_SET_ERR_MSG_MOD(extack, 662 "VLAN range 4000-4095 reserved for VLAN-unaware bridging"); 663 return -EBUSY; 664 } 665 666 return 0; 667 } 668 EXPORT_SYMBOL(ocelot_vlan_prepare); 669 670 int ocelot_vlan_add(struct ocelot *ocelot, int port, u16 vid, bool pvid, 671 bool untagged) 672 { 673 int err; 674 675 /* Ignore VID 0 added to our RX filter by the 8021q module, since 676 * that collides with OCELOT_STANDALONE_PVID and changes it from 677 * egress-untagged to egress-tagged. 678 */ 679 if (!vid) 680 return 0; 681 682 err = ocelot_vlan_member_add(ocelot, port, vid, untagged); 683 if (err) 684 return err; 685 686 /* Default ingress vlan classification */ 687 if (pvid) 688 ocelot_port_set_pvid(ocelot, port, 689 ocelot_bridge_vlan_find(ocelot, vid)); 690 691 /* Untagged egress vlan clasification */ 692 ocelot_port_manage_port_tag(ocelot, port); 693 694 return 0; 695 } 696 EXPORT_SYMBOL(ocelot_vlan_add); 697 698 int ocelot_vlan_del(struct ocelot *ocelot, int port, u16 vid) 699 { 700 struct ocelot_port *ocelot_port = ocelot->ports[port]; 701 bool del_pvid = false; 702 int err; 703 704 if (!vid) 705 return 0; 706 707 if (ocelot_port->pvid_vlan && ocelot_port->pvid_vlan->vid == vid) 708 del_pvid = true; 709 710 err = ocelot_vlan_member_del(ocelot, port, vid); 711 if (err) 712 return err; 713 714 /* Ingress */ 715 if (del_pvid) 716 ocelot_port_set_pvid(ocelot, port, NULL); 717 718 /* Egress */ 719 ocelot_port_manage_port_tag(ocelot, port); 720 721 return 0; 722 } 723 EXPORT_SYMBOL(ocelot_vlan_del); 724 725 static void ocelot_vlan_init(struct ocelot *ocelot) 726 { 727 unsigned long all_ports = GENMASK(ocelot->num_phys_ports - 1, 0); 728 u16 port, vid; 729 730 /* Clear VLAN table, by default all ports are members of all VLANs */ 731 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_CMD_INIT, 732 ANA_TABLES_VLANACCESS); 733 ocelot_vlant_wait_for_completion(ocelot); 734 735 /* Configure the port VLAN memberships */ 736 for (vid = 1; vid < VLAN_N_VID; vid++) 737 ocelot_vlant_set_mask(ocelot, vid, 0); 738 739 /* We need VID 0 to get traffic on standalone ports. 740 * It is added automatically if the 8021q module is loaded, but we 741 * can't rely on that since it might not be. 742 */ 743 ocelot_vlant_set_mask(ocelot, OCELOT_STANDALONE_PVID, all_ports); 744 745 /* Set vlan ingress filter mask to all ports but the CPU port by 746 * default. 747 */ 748 ocelot_write(ocelot, all_ports, ANA_VLANMASK); 749 750 for (port = 0; port < ocelot->num_phys_ports; port++) { 751 ocelot_write_gix(ocelot, 0, REW_PORT_VLAN_CFG, port); 752 ocelot_write_gix(ocelot, 0, REW_TAG_CFG, port); 753 } 754 } 755 756 static u32 ocelot_read_eq_avail(struct ocelot *ocelot, int port) 757 { 758 return ocelot_read_rix(ocelot, QSYS_SW_STATUS, port); 759 } 760 761 static int ocelot_port_flush(struct ocelot *ocelot, int port) 762 { 763 unsigned int pause_ena; 764 int err, val; 765 766 /* Disable dequeuing from the egress queues */ 767 ocelot_rmw_rix(ocelot, QSYS_PORT_MODE_DEQUEUE_DIS, 768 QSYS_PORT_MODE_DEQUEUE_DIS, 769 QSYS_PORT_MODE, port); 770 771 /* Disable flow control */ 772 ocelot_fields_read(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, &pause_ena); 773 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, 0); 774 775 /* Disable priority flow control */ 776 ocelot_fields_write(ocelot, port, 777 QSYS_SWITCH_PORT_MODE_TX_PFC_ENA, 0); 778 779 /* Wait at least the time it takes to receive a frame of maximum length 780 * at the port. 781 * Worst-case delays for 10 kilobyte jumbo frames are: 782 * 8 ms on a 10M port 783 * 800 μs on a 100M port 784 * 80 μs on a 1G port 785 * 32 μs on a 2.5G port 786 */ 787 usleep_range(8000, 10000); 788 789 /* Disable half duplex backpressure. */ 790 ocelot_rmw_rix(ocelot, 0, SYS_FRONT_PORT_MODE_HDX_MODE, 791 SYS_FRONT_PORT_MODE, port); 792 793 /* Flush the queues associated with the port. */ 794 ocelot_rmw_gix(ocelot, REW_PORT_CFG_FLUSH_ENA, REW_PORT_CFG_FLUSH_ENA, 795 REW_PORT_CFG, port); 796 797 /* Enable dequeuing from the egress queues. */ 798 ocelot_rmw_rix(ocelot, 0, QSYS_PORT_MODE_DEQUEUE_DIS, QSYS_PORT_MODE, 799 port); 800 801 /* Wait until flushing is complete. */ 802 err = read_poll_timeout(ocelot_read_eq_avail, val, !val, 803 100, 2000000, false, ocelot, port); 804 805 /* Clear flushing again. */ 806 ocelot_rmw_gix(ocelot, 0, REW_PORT_CFG_FLUSH_ENA, REW_PORT_CFG, port); 807 808 /* Re-enable flow control */ 809 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, pause_ena); 810 811 return err; 812 } 813 814 int ocelot_port_configure_serdes(struct ocelot *ocelot, int port, 815 struct device_node *portnp) 816 { 817 struct ocelot_port *ocelot_port = ocelot->ports[port]; 818 struct device *dev = ocelot->dev; 819 int err; 820 821 /* Ensure clock signals and speed are set on all QSGMII links */ 822 if (ocelot_port->phy_mode == PHY_INTERFACE_MODE_QSGMII) 823 ocelot_port_rmwl(ocelot_port, 0, 824 DEV_CLOCK_CFG_MAC_TX_RST | 825 DEV_CLOCK_CFG_MAC_RX_RST, 826 DEV_CLOCK_CFG); 827 828 if (ocelot_port->phy_mode != PHY_INTERFACE_MODE_INTERNAL) { 829 struct phy *serdes = of_phy_get(portnp, NULL); 830 831 if (IS_ERR(serdes)) { 832 err = PTR_ERR(serdes); 833 dev_err_probe(dev, err, 834 "missing SerDes phys for port %d\n", 835 port); 836 return err; 837 } 838 839 err = phy_set_mode_ext(serdes, PHY_MODE_ETHERNET, 840 ocelot_port->phy_mode); 841 of_phy_put(serdes); 842 if (err) { 843 dev_err(dev, "Could not SerDes mode on port %d: %pe\n", 844 port, ERR_PTR(err)); 845 return err; 846 } 847 } 848 849 return 0; 850 } 851 EXPORT_SYMBOL_GPL(ocelot_port_configure_serdes); 852 853 void ocelot_phylink_mac_config(struct ocelot *ocelot, int port, 854 unsigned int link_an_mode, 855 const struct phylink_link_state *state) 856 { 857 struct ocelot_port *ocelot_port = ocelot->ports[port]; 858 859 /* Disable HDX fast control */ 860 ocelot_port_writel(ocelot_port, DEV_PORT_MISC_HDX_FAST_DIS, 861 DEV_PORT_MISC); 862 863 /* SGMII only for now */ 864 ocelot_port_writel(ocelot_port, PCS1G_MODE_CFG_SGMII_MODE_ENA, 865 PCS1G_MODE_CFG); 866 ocelot_port_writel(ocelot_port, PCS1G_SD_CFG_SD_SEL, PCS1G_SD_CFG); 867 868 /* Enable PCS */ 869 ocelot_port_writel(ocelot_port, PCS1G_CFG_PCS_ENA, PCS1G_CFG); 870 871 /* No aneg on SGMII */ 872 ocelot_port_writel(ocelot_port, 0, PCS1G_ANEG_CFG); 873 874 /* No loopback */ 875 ocelot_port_writel(ocelot_port, 0, PCS1G_LB_CFG); 876 } 877 EXPORT_SYMBOL_GPL(ocelot_phylink_mac_config); 878 879 void ocelot_phylink_mac_link_down(struct ocelot *ocelot, int port, 880 unsigned int link_an_mode, 881 phy_interface_t interface, 882 unsigned long quirks) 883 { 884 struct ocelot_port *ocelot_port = ocelot->ports[port]; 885 int err; 886 887 ocelot_port->speed = SPEED_UNKNOWN; 888 889 ocelot_port_rmwl(ocelot_port, 0, DEV_MAC_ENA_CFG_RX_ENA, 890 DEV_MAC_ENA_CFG); 891 892 if (ocelot->ops->cut_through_fwd) { 893 mutex_lock(&ocelot->fwd_domain_lock); 894 ocelot->ops->cut_through_fwd(ocelot); 895 mutex_unlock(&ocelot->fwd_domain_lock); 896 } 897 898 ocelot_fields_write(ocelot, port, QSYS_SWITCH_PORT_MODE_PORT_ENA, 0); 899 900 err = ocelot_port_flush(ocelot, port); 901 if (err) 902 dev_err(ocelot->dev, "failed to flush port %d: %d\n", 903 port, err); 904 905 /* Put the port in reset. */ 906 if (interface != PHY_INTERFACE_MODE_QSGMII || 907 !(quirks & OCELOT_QUIRK_QSGMII_PORTS_MUST_BE_UP)) 908 ocelot_port_rmwl(ocelot_port, 909 DEV_CLOCK_CFG_MAC_TX_RST | 910 DEV_CLOCK_CFG_MAC_RX_RST, 911 DEV_CLOCK_CFG_MAC_TX_RST | 912 DEV_CLOCK_CFG_MAC_RX_RST, 913 DEV_CLOCK_CFG); 914 } 915 EXPORT_SYMBOL_GPL(ocelot_phylink_mac_link_down); 916 917 void ocelot_phylink_mac_link_up(struct ocelot *ocelot, int port, 918 struct phy_device *phydev, 919 unsigned int link_an_mode, 920 phy_interface_t interface, 921 int speed, int duplex, 922 bool tx_pause, bool rx_pause, 923 unsigned long quirks) 924 { 925 struct ocelot_port *ocelot_port = ocelot->ports[port]; 926 int mac_speed, mode = 0; 927 u32 mac_fc_cfg; 928 929 ocelot_port->speed = speed; 930 931 /* The MAC might be integrated in systems where the MAC speed is fixed 932 * and it's the PCS who is performing the rate adaptation, so we have 933 * to write "1000Mbps" into the LINK_SPEED field of DEV_CLOCK_CFG 934 * (which is also its default value). 935 */ 936 if ((quirks & OCELOT_QUIRK_PCS_PERFORMS_RATE_ADAPTATION) || 937 speed == SPEED_1000) { 938 mac_speed = OCELOT_SPEED_1000; 939 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA; 940 } else if (speed == SPEED_2500) { 941 mac_speed = OCELOT_SPEED_2500; 942 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA; 943 } else if (speed == SPEED_100) { 944 mac_speed = OCELOT_SPEED_100; 945 } else { 946 mac_speed = OCELOT_SPEED_10; 947 } 948 949 if (duplex == DUPLEX_FULL) 950 mode |= DEV_MAC_MODE_CFG_FDX_ENA; 951 952 ocelot_port_writel(ocelot_port, mode, DEV_MAC_MODE_CFG); 953 954 /* Take port out of reset by clearing the MAC_TX_RST, MAC_RX_RST and 955 * PORT_RST bits in DEV_CLOCK_CFG. 956 */ 957 ocelot_port_writel(ocelot_port, DEV_CLOCK_CFG_LINK_SPEED(mac_speed), 958 DEV_CLOCK_CFG); 959 960 switch (speed) { 961 case SPEED_10: 962 mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(OCELOT_SPEED_10); 963 break; 964 case SPEED_100: 965 mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(OCELOT_SPEED_100); 966 break; 967 case SPEED_1000: 968 case SPEED_2500: 969 mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(OCELOT_SPEED_1000); 970 break; 971 default: 972 dev_err(ocelot->dev, "Unsupported speed on port %d: %d\n", 973 port, speed); 974 return; 975 } 976 977 if (rx_pause) 978 mac_fc_cfg |= SYS_MAC_FC_CFG_RX_FC_ENA; 979 980 if (tx_pause) 981 mac_fc_cfg |= SYS_MAC_FC_CFG_TX_FC_ENA | 982 SYS_MAC_FC_CFG_PAUSE_VAL_CFG(0xffff) | 983 SYS_MAC_FC_CFG_FC_LATENCY_CFG(0x7) | 984 SYS_MAC_FC_CFG_ZERO_PAUSE_ENA; 985 986 /* Flow control. Link speed is only used here to evaluate the time 987 * specification in incoming pause frames. 988 */ 989 ocelot_write_rix(ocelot, mac_fc_cfg, SYS_MAC_FC_CFG, port); 990 991 ocelot_write_rix(ocelot, 0, ANA_POL_FLOWC, port); 992 993 /* Don't attempt to send PAUSE frames on the NPI port, it's broken */ 994 if (port != ocelot->npi) 995 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, 996 tx_pause); 997 998 /* Undo the effects of ocelot_phylink_mac_link_down: 999 * enable MAC module 1000 */ 1001 ocelot_port_writel(ocelot_port, DEV_MAC_ENA_CFG_RX_ENA | 1002 DEV_MAC_ENA_CFG_TX_ENA, DEV_MAC_ENA_CFG); 1003 1004 /* If the port supports cut-through forwarding, update the masks before 1005 * enabling forwarding on the port. 1006 */ 1007 if (ocelot->ops->cut_through_fwd) { 1008 mutex_lock(&ocelot->fwd_domain_lock); 1009 /* Workaround for hardware bug - FP doesn't work 1010 * at all link speeds for all PHY modes. The function 1011 * below also calls ocelot->ops->cut_through_fwd(), 1012 * so we don't need to do it twice. 1013 */ 1014 ocelot_port_update_active_preemptible_tcs(ocelot, port); 1015 mutex_unlock(&ocelot->fwd_domain_lock); 1016 } 1017 1018 /* Core: Enable port for frame transfer */ 1019 ocelot_fields_write(ocelot, port, 1020 QSYS_SWITCH_PORT_MODE_PORT_ENA, 1); 1021 } 1022 EXPORT_SYMBOL_GPL(ocelot_phylink_mac_link_up); 1023 1024 static int ocelot_rx_frame_word(struct ocelot *ocelot, u8 grp, bool ifh, 1025 u32 *rval) 1026 { 1027 u32 bytes_valid, val; 1028 1029 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 1030 if (val == XTR_NOT_READY) { 1031 if (ifh) 1032 return -EIO; 1033 1034 do { 1035 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 1036 } while (val == XTR_NOT_READY); 1037 } 1038 1039 switch (val) { 1040 case XTR_ABORT: 1041 return -EIO; 1042 case XTR_EOF_0: 1043 case XTR_EOF_1: 1044 case XTR_EOF_2: 1045 case XTR_EOF_3: 1046 case XTR_PRUNED: 1047 bytes_valid = XTR_VALID_BYTES(val); 1048 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 1049 if (val == XTR_ESCAPE) 1050 *rval = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 1051 else 1052 *rval = val; 1053 1054 return bytes_valid; 1055 case XTR_ESCAPE: 1056 *rval = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 1057 1058 return 4; 1059 default: 1060 *rval = val; 1061 1062 return 4; 1063 } 1064 } 1065 1066 static int ocelot_xtr_poll_xfh(struct ocelot *ocelot, int grp, u32 *xfh) 1067 { 1068 int i, err = 0; 1069 1070 for (i = 0; i < OCELOT_TAG_LEN / 4; i++) { 1071 err = ocelot_rx_frame_word(ocelot, grp, true, &xfh[i]); 1072 if (err != 4) 1073 return (err < 0) ? err : -EIO; 1074 } 1075 1076 return 0; 1077 } 1078 1079 void ocelot_ptp_rx_timestamp(struct ocelot *ocelot, struct sk_buff *skb, 1080 u64 timestamp) 1081 { 1082 struct skb_shared_hwtstamps *shhwtstamps; 1083 u64 tod_in_ns, full_ts_in_ns; 1084 struct timespec64 ts; 1085 1086 ocelot_ptp_gettime64(&ocelot->ptp_info, &ts); 1087 1088 tod_in_ns = ktime_set(ts.tv_sec, ts.tv_nsec); 1089 if ((tod_in_ns & 0xffffffff) < timestamp) 1090 full_ts_in_ns = (((tod_in_ns >> 32) - 1) << 32) | 1091 timestamp; 1092 else 1093 full_ts_in_ns = (tod_in_ns & GENMASK_ULL(63, 32)) | 1094 timestamp; 1095 1096 shhwtstamps = skb_hwtstamps(skb); 1097 memset(shhwtstamps, 0, sizeof(struct skb_shared_hwtstamps)); 1098 shhwtstamps->hwtstamp = full_ts_in_ns; 1099 } 1100 EXPORT_SYMBOL(ocelot_ptp_rx_timestamp); 1101 1102 int ocelot_xtr_poll_frame(struct ocelot *ocelot, int grp, struct sk_buff **nskb) 1103 { 1104 u64 timestamp, src_port, len; 1105 u32 xfh[OCELOT_TAG_LEN / 4]; 1106 struct net_device *dev; 1107 struct sk_buff *skb; 1108 int sz, buf_len; 1109 u32 val, *buf; 1110 int err; 1111 1112 err = ocelot_xtr_poll_xfh(ocelot, grp, xfh); 1113 if (err) 1114 return err; 1115 1116 ocelot_xfh_get_src_port(xfh, &src_port); 1117 ocelot_xfh_get_len(xfh, &len); 1118 ocelot_xfh_get_rew_val(xfh, ×tamp); 1119 1120 if (WARN_ON(src_port >= ocelot->num_phys_ports)) 1121 return -EINVAL; 1122 1123 dev = ocelot->ops->port_to_netdev(ocelot, src_port); 1124 if (!dev) 1125 return -EINVAL; 1126 1127 skb = netdev_alloc_skb(dev, len); 1128 if (unlikely(!skb)) { 1129 netdev_err(dev, "Unable to allocate sk_buff\n"); 1130 return -ENOMEM; 1131 } 1132 1133 buf_len = len - ETH_FCS_LEN; 1134 buf = (u32 *)skb_put(skb, buf_len); 1135 1136 len = 0; 1137 do { 1138 sz = ocelot_rx_frame_word(ocelot, grp, false, &val); 1139 if (sz < 0) { 1140 err = sz; 1141 goto out_free_skb; 1142 } 1143 *buf++ = val; 1144 len += sz; 1145 } while (len < buf_len); 1146 1147 /* Read the FCS */ 1148 sz = ocelot_rx_frame_word(ocelot, grp, false, &val); 1149 if (sz < 0) { 1150 err = sz; 1151 goto out_free_skb; 1152 } 1153 1154 /* Update the statistics if part of the FCS was read before */ 1155 len -= ETH_FCS_LEN - sz; 1156 1157 if (unlikely(dev->features & NETIF_F_RXFCS)) { 1158 buf = (u32 *)skb_put(skb, ETH_FCS_LEN); 1159 *buf = val; 1160 } 1161 1162 if (ocelot->ptp) 1163 ocelot_ptp_rx_timestamp(ocelot, skb, timestamp); 1164 1165 /* Everything we see on an interface that is in the HW bridge 1166 * has already been forwarded. 1167 */ 1168 if (ocelot->ports[src_port]->bridge) 1169 skb->offload_fwd_mark = 1; 1170 1171 skb->protocol = eth_type_trans(skb, dev); 1172 1173 *nskb = skb; 1174 1175 return 0; 1176 1177 out_free_skb: 1178 kfree_skb(skb); 1179 return err; 1180 } 1181 EXPORT_SYMBOL(ocelot_xtr_poll_frame); 1182 1183 bool ocelot_can_inject(struct ocelot *ocelot, int grp) 1184 { 1185 u32 val = ocelot_read(ocelot, QS_INJ_STATUS); 1186 1187 if (!(val & QS_INJ_STATUS_FIFO_RDY(BIT(grp)))) 1188 return false; 1189 if (val & QS_INJ_STATUS_WMARK_REACHED(BIT(grp))) 1190 return false; 1191 1192 return true; 1193 } 1194 EXPORT_SYMBOL(ocelot_can_inject); 1195 1196 /** 1197 * ocelot_ifh_set_basic - Set basic information in Injection Frame Header 1198 * @ifh: Pointer to Injection Frame Header memory 1199 * @ocelot: Switch private data structure 1200 * @port: Egress port number 1201 * @rew_op: Egress rewriter operation for PTP 1202 * @skb: Pointer to socket buffer (packet) 1203 * 1204 * Populate the Injection Frame Header with basic information for this skb: the 1205 * analyzer bypass bit, destination port, VLAN info, egress rewriter info. 1206 */ 1207 void ocelot_ifh_set_basic(void *ifh, struct ocelot *ocelot, int port, 1208 u32 rew_op, struct sk_buff *skb) 1209 { 1210 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1211 struct net_device *dev = skb->dev; 1212 u64 vlan_tci, tag_type; 1213 int qos_class; 1214 1215 ocelot_xmit_get_vlan_info(skb, ocelot_port->bridge, &vlan_tci, 1216 &tag_type); 1217 1218 qos_class = netdev_get_num_tc(dev) ? 1219 netdev_get_prio_tc_map(dev, skb->priority) : skb->priority; 1220 1221 memset(ifh, 0, OCELOT_TAG_LEN); 1222 ocelot_ifh_set_bypass(ifh, 1); 1223 ocelot_ifh_set_src(ifh, BIT_ULL(ocelot->num_phys_ports)); 1224 ocelot_ifh_set_dest(ifh, BIT_ULL(port)); 1225 ocelot_ifh_set_qos_class(ifh, qos_class); 1226 ocelot_ifh_set_tag_type(ifh, tag_type); 1227 ocelot_ifh_set_vlan_tci(ifh, vlan_tci); 1228 if (rew_op) 1229 ocelot_ifh_set_rew_op(ifh, rew_op); 1230 } 1231 EXPORT_SYMBOL(ocelot_ifh_set_basic); 1232 1233 void ocelot_port_inject_frame(struct ocelot *ocelot, int port, int grp, 1234 u32 rew_op, struct sk_buff *skb) 1235 { 1236 u32 ifh[OCELOT_TAG_LEN / 4]; 1237 unsigned int i, count, last; 1238 1239 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) | 1240 QS_INJ_CTRL_SOF, QS_INJ_CTRL, grp); 1241 1242 ocelot_ifh_set_basic(ifh, ocelot, port, rew_op, skb); 1243 1244 for (i = 0; i < OCELOT_TAG_LEN / 4; i++) 1245 ocelot_write_rix(ocelot, ifh[i], QS_INJ_WR, grp); 1246 1247 count = DIV_ROUND_UP(skb->len, 4); 1248 last = skb->len % 4; 1249 for (i = 0; i < count; i++) 1250 ocelot_write_rix(ocelot, ((u32 *)skb->data)[i], QS_INJ_WR, grp); 1251 1252 /* Add padding */ 1253 while (i < (OCELOT_BUFFER_CELL_SZ / 4)) { 1254 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp); 1255 i++; 1256 } 1257 1258 /* Indicate EOF and valid bytes in last word */ 1259 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) | 1260 QS_INJ_CTRL_VLD_BYTES(skb->len < OCELOT_BUFFER_CELL_SZ ? 0 : last) | 1261 QS_INJ_CTRL_EOF, 1262 QS_INJ_CTRL, grp); 1263 1264 /* Add dummy CRC */ 1265 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp); 1266 skb_tx_timestamp(skb); 1267 1268 skb->dev->stats.tx_packets++; 1269 skb->dev->stats.tx_bytes += skb->len; 1270 } 1271 EXPORT_SYMBOL(ocelot_port_inject_frame); 1272 1273 void ocelot_drain_cpu_queue(struct ocelot *ocelot, int grp) 1274 { 1275 while (ocelot_read(ocelot, QS_XTR_DATA_PRESENT) & BIT(grp)) 1276 ocelot_read_rix(ocelot, QS_XTR_RD, grp); 1277 } 1278 EXPORT_SYMBOL(ocelot_drain_cpu_queue); 1279 1280 int ocelot_fdb_add(struct ocelot *ocelot, int port, const unsigned char *addr, 1281 u16 vid, const struct net_device *bridge) 1282 { 1283 if (!vid) 1284 vid = ocelot_vlan_unaware_pvid(ocelot, bridge); 1285 1286 return ocelot_mact_learn(ocelot, port, addr, vid, ENTRYTYPE_LOCKED); 1287 } 1288 EXPORT_SYMBOL(ocelot_fdb_add); 1289 1290 int ocelot_fdb_del(struct ocelot *ocelot, int port, const unsigned char *addr, 1291 u16 vid, const struct net_device *bridge) 1292 { 1293 if (!vid) 1294 vid = ocelot_vlan_unaware_pvid(ocelot, bridge); 1295 1296 return ocelot_mact_forget(ocelot, addr, vid); 1297 } 1298 EXPORT_SYMBOL(ocelot_fdb_del); 1299 1300 /* Caller must hold &ocelot->mact_lock */ 1301 static int ocelot_mact_read(struct ocelot *ocelot, int port, int row, int col, 1302 struct ocelot_mact_entry *entry) 1303 { 1304 u32 val, dst, macl, mach; 1305 char mac[ETH_ALEN]; 1306 1307 /* Set row and column to read from */ 1308 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_M_INDEX, row); 1309 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_BUCKET, col); 1310 1311 /* Issue a read command */ 1312 ocelot_write(ocelot, 1313 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_READ), 1314 ANA_TABLES_MACACCESS); 1315 1316 if (ocelot_mact_wait_for_completion(ocelot)) 1317 return -ETIMEDOUT; 1318 1319 /* Read the entry flags */ 1320 val = ocelot_read(ocelot, ANA_TABLES_MACACCESS); 1321 if (!(val & ANA_TABLES_MACACCESS_VALID)) 1322 return -EINVAL; 1323 1324 /* If the entry read has another port configured as its destination, 1325 * do not report it. 1326 */ 1327 dst = (val & ANA_TABLES_MACACCESS_DEST_IDX_M) >> 3; 1328 if (dst != port) 1329 return -EINVAL; 1330 1331 /* Get the entry's MAC address and VLAN id */ 1332 macl = ocelot_read(ocelot, ANA_TABLES_MACLDATA); 1333 mach = ocelot_read(ocelot, ANA_TABLES_MACHDATA); 1334 1335 mac[0] = (mach >> 8) & 0xff; 1336 mac[1] = (mach >> 0) & 0xff; 1337 mac[2] = (macl >> 24) & 0xff; 1338 mac[3] = (macl >> 16) & 0xff; 1339 mac[4] = (macl >> 8) & 0xff; 1340 mac[5] = (macl >> 0) & 0xff; 1341 1342 entry->vid = (mach >> 16) & 0xfff; 1343 ether_addr_copy(entry->mac, mac); 1344 1345 return 0; 1346 } 1347 1348 int ocelot_mact_flush(struct ocelot *ocelot, int port) 1349 { 1350 int err; 1351 1352 mutex_lock(&ocelot->mact_lock); 1353 1354 /* Program ageing filter for a single port */ 1355 ocelot_write(ocelot, ANA_ANAGEFIL_PID_EN | ANA_ANAGEFIL_PID_VAL(port), 1356 ANA_ANAGEFIL); 1357 1358 /* Flushing dynamic FDB entries requires two successive age scans */ 1359 ocelot_write(ocelot, 1360 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_AGE), 1361 ANA_TABLES_MACACCESS); 1362 1363 err = ocelot_mact_wait_for_completion(ocelot); 1364 if (err) { 1365 mutex_unlock(&ocelot->mact_lock); 1366 return err; 1367 } 1368 1369 /* And second... */ 1370 ocelot_write(ocelot, 1371 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_AGE), 1372 ANA_TABLES_MACACCESS); 1373 1374 err = ocelot_mact_wait_for_completion(ocelot); 1375 1376 /* Restore ageing filter */ 1377 ocelot_write(ocelot, 0, ANA_ANAGEFIL); 1378 1379 mutex_unlock(&ocelot->mact_lock); 1380 1381 return err; 1382 } 1383 EXPORT_SYMBOL_GPL(ocelot_mact_flush); 1384 1385 int ocelot_fdb_dump(struct ocelot *ocelot, int port, 1386 dsa_fdb_dump_cb_t *cb, void *data) 1387 { 1388 int err = 0; 1389 int i, j; 1390 1391 /* We could take the lock just around ocelot_mact_read, but doing so 1392 * thousands of times in a row seems rather pointless and inefficient. 1393 */ 1394 mutex_lock(&ocelot->mact_lock); 1395 1396 /* Loop through all the mac tables entries. */ 1397 for (i = 0; i < ocelot->num_mact_rows; i++) { 1398 for (j = 0; j < 4; j++) { 1399 struct ocelot_mact_entry entry; 1400 bool is_static; 1401 1402 err = ocelot_mact_read(ocelot, port, i, j, &entry); 1403 /* If the entry is invalid (wrong port, invalid...), 1404 * skip it. 1405 */ 1406 if (err == -EINVAL) 1407 continue; 1408 else if (err) 1409 break; 1410 1411 is_static = (entry.type == ENTRYTYPE_LOCKED); 1412 1413 /* Hide the reserved VLANs used for 1414 * VLAN-unaware bridging. 1415 */ 1416 if (entry.vid > OCELOT_RSV_VLAN_RANGE_START) 1417 entry.vid = 0; 1418 1419 err = cb(entry.mac, entry.vid, is_static, data); 1420 if (err) 1421 break; 1422 } 1423 } 1424 1425 mutex_unlock(&ocelot->mact_lock); 1426 1427 return err; 1428 } 1429 EXPORT_SYMBOL(ocelot_fdb_dump); 1430 1431 int ocelot_trap_add(struct ocelot *ocelot, int port, 1432 unsigned long cookie, bool take_ts, 1433 void (*populate)(struct ocelot_vcap_filter *f)) 1434 { 1435 struct ocelot_vcap_block *block_vcap_is2; 1436 struct ocelot_vcap_filter *trap; 1437 bool new = false; 1438 int err; 1439 1440 block_vcap_is2 = &ocelot->block[VCAP_IS2]; 1441 1442 trap = ocelot_vcap_block_find_filter_by_id(block_vcap_is2, cookie, 1443 false); 1444 if (!trap) { 1445 trap = kzalloc(sizeof(*trap), GFP_KERNEL); 1446 if (!trap) 1447 return -ENOMEM; 1448 1449 populate(trap); 1450 trap->prio = 1; 1451 trap->id.cookie = cookie; 1452 trap->id.tc_offload = false; 1453 trap->block_id = VCAP_IS2; 1454 trap->type = OCELOT_VCAP_FILTER_OFFLOAD; 1455 trap->lookup = 0; 1456 trap->action.cpu_copy_ena = true; 1457 trap->action.mask_mode = OCELOT_MASK_MODE_PERMIT_DENY; 1458 trap->action.port_mask = 0; 1459 trap->take_ts = take_ts; 1460 trap->is_trap = true; 1461 new = true; 1462 } 1463 1464 trap->ingress_port_mask |= BIT(port); 1465 1466 if (new) 1467 err = ocelot_vcap_filter_add(ocelot, trap, NULL); 1468 else 1469 err = ocelot_vcap_filter_replace(ocelot, trap); 1470 if (err) { 1471 trap->ingress_port_mask &= ~BIT(port); 1472 if (!trap->ingress_port_mask) 1473 kfree(trap); 1474 return err; 1475 } 1476 1477 return 0; 1478 } 1479 1480 int ocelot_trap_del(struct ocelot *ocelot, int port, unsigned long cookie) 1481 { 1482 struct ocelot_vcap_block *block_vcap_is2; 1483 struct ocelot_vcap_filter *trap; 1484 1485 block_vcap_is2 = &ocelot->block[VCAP_IS2]; 1486 1487 trap = ocelot_vcap_block_find_filter_by_id(block_vcap_is2, cookie, 1488 false); 1489 if (!trap) 1490 return 0; 1491 1492 trap->ingress_port_mask &= ~BIT(port); 1493 if (!trap->ingress_port_mask) 1494 return ocelot_vcap_filter_del(ocelot, trap); 1495 1496 return ocelot_vcap_filter_replace(ocelot, trap); 1497 } 1498 1499 static u32 ocelot_get_bond_mask(struct ocelot *ocelot, struct net_device *bond) 1500 { 1501 u32 mask = 0; 1502 int port; 1503 1504 lockdep_assert_held(&ocelot->fwd_domain_lock); 1505 1506 for (port = 0; port < ocelot->num_phys_ports; port++) { 1507 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1508 1509 if (!ocelot_port) 1510 continue; 1511 1512 if (ocelot_port->bond == bond) 1513 mask |= BIT(port); 1514 } 1515 1516 return mask; 1517 } 1518 1519 /* The logical port number of a LAG is equal to the lowest numbered physical 1520 * port ID present in that LAG. It may change if that port ever leaves the LAG. 1521 */ 1522 int ocelot_bond_get_id(struct ocelot *ocelot, struct net_device *bond) 1523 { 1524 int bond_mask = ocelot_get_bond_mask(ocelot, bond); 1525 1526 if (!bond_mask) 1527 return -ENOENT; 1528 1529 return __ffs(bond_mask); 1530 } 1531 EXPORT_SYMBOL_GPL(ocelot_bond_get_id); 1532 1533 /* Returns the mask of user ports assigned to this DSA tag_8021q CPU port. 1534 * Note that when CPU ports are in a LAG, the user ports are assigned to the 1535 * 'primary' CPU port, the one whose physical port number gives the logical 1536 * port number of the LAG. 1537 * 1538 * We leave PGID_SRC poorly configured for the 'secondary' CPU port in the LAG 1539 * (to which no user port is assigned), but it appears that forwarding from 1540 * this secondary CPU port looks at the PGID_SRC associated with the logical 1541 * port ID that it's assigned to, which *is* configured properly. 1542 */ 1543 static u32 ocelot_dsa_8021q_cpu_assigned_ports(struct ocelot *ocelot, 1544 struct ocelot_port *cpu) 1545 { 1546 u32 mask = 0; 1547 int port; 1548 1549 for (port = 0; port < ocelot->num_phys_ports; port++) { 1550 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1551 1552 if (!ocelot_port) 1553 continue; 1554 1555 if (ocelot_port->dsa_8021q_cpu == cpu) 1556 mask |= BIT(port); 1557 } 1558 1559 if (cpu->bond) 1560 mask &= ~ocelot_get_bond_mask(ocelot, cpu->bond); 1561 1562 return mask; 1563 } 1564 1565 /* Returns the DSA tag_8021q CPU port that the given port is assigned to, 1566 * or the bit mask of CPU ports if said CPU port is in a LAG. 1567 */ 1568 u32 ocelot_port_assigned_dsa_8021q_cpu_mask(struct ocelot *ocelot, int port) 1569 { 1570 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1571 struct ocelot_port *cpu_port = ocelot_port->dsa_8021q_cpu; 1572 1573 if (!cpu_port) 1574 return 0; 1575 1576 if (cpu_port->bond) 1577 return ocelot_get_bond_mask(ocelot, cpu_port->bond); 1578 1579 return BIT(cpu_port->index); 1580 } 1581 EXPORT_SYMBOL_GPL(ocelot_port_assigned_dsa_8021q_cpu_mask); 1582 1583 u32 ocelot_get_bridge_fwd_mask(struct ocelot *ocelot, int src_port) 1584 { 1585 struct ocelot_port *ocelot_port = ocelot->ports[src_port]; 1586 const struct net_device *bridge; 1587 u32 mask = 0; 1588 int port; 1589 1590 if (!ocelot_port || ocelot_port->stp_state != BR_STATE_FORWARDING) 1591 return 0; 1592 1593 bridge = ocelot_port->bridge; 1594 if (!bridge) 1595 return 0; 1596 1597 for (port = 0; port < ocelot->num_phys_ports; port++) { 1598 ocelot_port = ocelot->ports[port]; 1599 1600 if (!ocelot_port) 1601 continue; 1602 1603 if (ocelot_port->stp_state == BR_STATE_FORWARDING && 1604 ocelot_port->bridge == bridge) 1605 mask |= BIT(port); 1606 } 1607 1608 return mask; 1609 } 1610 EXPORT_SYMBOL_GPL(ocelot_get_bridge_fwd_mask); 1611 1612 static void ocelot_apply_bridge_fwd_mask(struct ocelot *ocelot, bool joining) 1613 { 1614 int port; 1615 1616 lockdep_assert_held(&ocelot->fwd_domain_lock); 1617 1618 /* If cut-through forwarding is supported, update the masks before a 1619 * port joins the forwarding domain, to avoid potential underruns if it 1620 * has the highest speed from the new domain. 1621 */ 1622 if (joining && ocelot->ops->cut_through_fwd) 1623 ocelot->ops->cut_through_fwd(ocelot); 1624 1625 /* Apply FWD mask. The loop is needed to add/remove the current port as 1626 * a source for the other ports. 1627 */ 1628 for (port = 0; port < ocelot->num_phys_ports; port++) { 1629 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1630 unsigned long mask; 1631 1632 if (!ocelot_port) { 1633 /* Unused ports can't send anywhere */ 1634 mask = 0; 1635 } else if (ocelot_port->is_dsa_8021q_cpu) { 1636 /* The DSA tag_8021q CPU ports need to be able to 1637 * forward packets to all ports assigned to them. 1638 */ 1639 mask = ocelot_dsa_8021q_cpu_assigned_ports(ocelot, 1640 ocelot_port); 1641 } else if (ocelot_port->bridge) { 1642 struct net_device *bond = ocelot_port->bond; 1643 1644 mask = ocelot_get_bridge_fwd_mask(ocelot, port); 1645 mask &= ~BIT(port); 1646 1647 mask |= ocelot_port_assigned_dsa_8021q_cpu_mask(ocelot, 1648 port); 1649 1650 if (bond) 1651 mask &= ~ocelot_get_bond_mask(ocelot, bond); 1652 } else { 1653 /* Standalone ports forward only to DSA tag_8021q CPU 1654 * ports (if those exist), or to the hardware CPU port 1655 * module otherwise. 1656 */ 1657 mask = ocelot_port_assigned_dsa_8021q_cpu_mask(ocelot, 1658 port); 1659 } 1660 1661 ocelot_write_rix(ocelot, mask, ANA_PGID_PGID, PGID_SRC + port); 1662 } 1663 1664 /* If cut-through forwarding is supported and a port is leaving, there 1665 * is a chance that cut-through was disabled on the other ports due to 1666 * the port which is leaving (it has a higher link speed). We need to 1667 * update the cut-through masks of the remaining ports no earlier than 1668 * after the port has left, to prevent underruns from happening between 1669 * the cut-through update and the forwarding domain update. 1670 */ 1671 if (!joining && ocelot->ops->cut_through_fwd) 1672 ocelot->ops->cut_through_fwd(ocelot); 1673 } 1674 1675 /* Update PGID_CPU which is the destination port mask used for whitelisting 1676 * unicast addresses filtered towards the host. In the normal and NPI modes, 1677 * this points to the analyzer entry for the CPU port module, while in DSA 1678 * tag_8021q mode, it is a bit mask of all active CPU ports. 1679 * PGID_SRC will take care of forwarding a packet from one user port to 1680 * no more than a single CPU port. 1681 */ 1682 static void ocelot_update_pgid_cpu(struct ocelot *ocelot) 1683 { 1684 int pgid_cpu = 0; 1685 int port; 1686 1687 for (port = 0; port < ocelot->num_phys_ports; port++) { 1688 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1689 1690 if (!ocelot_port || !ocelot_port->is_dsa_8021q_cpu) 1691 continue; 1692 1693 pgid_cpu |= BIT(port); 1694 } 1695 1696 if (!pgid_cpu) 1697 pgid_cpu = BIT(ocelot->num_phys_ports); 1698 1699 ocelot_write_rix(ocelot, pgid_cpu, ANA_PGID_PGID, PGID_CPU); 1700 } 1701 1702 void ocelot_port_setup_dsa_8021q_cpu(struct ocelot *ocelot, int cpu) 1703 { 1704 struct ocelot_port *cpu_port = ocelot->ports[cpu]; 1705 u16 vid; 1706 1707 mutex_lock(&ocelot->fwd_domain_lock); 1708 1709 cpu_port->is_dsa_8021q_cpu = true; 1710 1711 for (vid = OCELOT_RSV_VLAN_RANGE_START; vid < VLAN_N_VID; vid++) 1712 ocelot_vlan_member_add(ocelot, cpu, vid, true); 1713 1714 ocelot_update_pgid_cpu(ocelot); 1715 1716 mutex_unlock(&ocelot->fwd_domain_lock); 1717 } 1718 EXPORT_SYMBOL_GPL(ocelot_port_setup_dsa_8021q_cpu); 1719 1720 void ocelot_port_teardown_dsa_8021q_cpu(struct ocelot *ocelot, int cpu) 1721 { 1722 struct ocelot_port *cpu_port = ocelot->ports[cpu]; 1723 u16 vid; 1724 1725 mutex_lock(&ocelot->fwd_domain_lock); 1726 1727 cpu_port->is_dsa_8021q_cpu = false; 1728 1729 for (vid = OCELOT_RSV_VLAN_RANGE_START; vid < VLAN_N_VID; vid++) 1730 ocelot_vlan_member_del(ocelot, cpu_port->index, vid); 1731 1732 ocelot_update_pgid_cpu(ocelot); 1733 1734 mutex_unlock(&ocelot->fwd_domain_lock); 1735 } 1736 EXPORT_SYMBOL_GPL(ocelot_port_teardown_dsa_8021q_cpu); 1737 1738 void ocelot_port_assign_dsa_8021q_cpu(struct ocelot *ocelot, int port, 1739 int cpu) 1740 { 1741 struct ocelot_port *cpu_port = ocelot->ports[cpu]; 1742 1743 mutex_lock(&ocelot->fwd_domain_lock); 1744 1745 ocelot->ports[port]->dsa_8021q_cpu = cpu_port; 1746 ocelot_apply_bridge_fwd_mask(ocelot, true); 1747 1748 mutex_unlock(&ocelot->fwd_domain_lock); 1749 } 1750 EXPORT_SYMBOL_GPL(ocelot_port_assign_dsa_8021q_cpu); 1751 1752 void ocelot_port_unassign_dsa_8021q_cpu(struct ocelot *ocelot, int port) 1753 { 1754 mutex_lock(&ocelot->fwd_domain_lock); 1755 1756 ocelot->ports[port]->dsa_8021q_cpu = NULL; 1757 ocelot_apply_bridge_fwd_mask(ocelot, true); 1758 1759 mutex_unlock(&ocelot->fwd_domain_lock); 1760 } 1761 EXPORT_SYMBOL_GPL(ocelot_port_unassign_dsa_8021q_cpu); 1762 1763 void ocelot_bridge_stp_state_set(struct ocelot *ocelot, int port, u8 state) 1764 { 1765 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1766 u32 learn_ena = 0; 1767 1768 mutex_lock(&ocelot->fwd_domain_lock); 1769 1770 ocelot_port->stp_state = state; 1771 1772 if ((state == BR_STATE_LEARNING || state == BR_STATE_FORWARDING) && 1773 ocelot_port->learn_ena) 1774 learn_ena = ANA_PORT_PORT_CFG_LEARN_ENA; 1775 1776 ocelot_rmw_gix(ocelot, learn_ena, ANA_PORT_PORT_CFG_LEARN_ENA, 1777 ANA_PORT_PORT_CFG, port); 1778 1779 ocelot_apply_bridge_fwd_mask(ocelot, state == BR_STATE_FORWARDING); 1780 1781 mutex_unlock(&ocelot->fwd_domain_lock); 1782 } 1783 EXPORT_SYMBOL(ocelot_bridge_stp_state_set); 1784 1785 void ocelot_set_ageing_time(struct ocelot *ocelot, unsigned int msecs) 1786 { 1787 unsigned int age_period = ANA_AUTOAGE_AGE_PERIOD(msecs / 2000); 1788 1789 /* Setting AGE_PERIOD to zero effectively disables automatic aging, 1790 * which is clearly not what our intention is. So avoid that. 1791 */ 1792 if (!age_period) 1793 age_period = 1; 1794 1795 ocelot_rmw(ocelot, age_period, ANA_AUTOAGE_AGE_PERIOD_M, ANA_AUTOAGE); 1796 } 1797 EXPORT_SYMBOL(ocelot_set_ageing_time); 1798 1799 static struct ocelot_multicast *ocelot_multicast_get(struct ocelot *ocelot, 1800 const unsigned char *addr, 1801 u16 vid) 1802 { 1803 struct ocelot_multicast *mc; 1804 1805 list_for_each_entry(mc, &ocelot->multicast, list) { 1806 if (ether_addr_equal(mc->addr, addr) && mc->vid == vid) 1807 return mc; 1808 } 1809 1810 return NULL; 1811 } 1812 1813 static enum macaccess_entry_type ocelot_classify_mdb(const unsigned char *addr) 1814 { 1815 if (addr[0] == 0x01 && addr[1] == 0x00 && addr[2] == 0x5e) 1816 return ENTRYTYPE_MACv4; 1817 if (addr[0] == 0x33 && addr[1] == 0x33) 1818 return ENTRYTYPE_MACv6; 1819 return ENTRYTYPE_LOCKED; 1820 } 1821 1822 static struct ocelot_pgid *ocelot_pgid_alloc(struct ocelot *ocelot, int index, 1823 unsigned long ports) 1824 { 1825 struct ocelot_pgid *pgid; 1826 1827 pgid = kzalloc(sizeof(*pgid), GFP_KERNEL); 1828 if (!pgid) 1829 return ERR_PTR(-ENOMEM); 1830 1831 pgid->ports = ports; 1832 pgid->index = index; 1833 refcount_set(&pgid->refcount, 1); 1834 list_add_tail(&pgid->list, &ocelot->pgids); 1835 1836 return pgid; 1837 } 1838 1839 static void ocelot_pgid_free(struct ocelot *ocelot, struct ocelot_pgid *pgid) 1840 { 1841 if (!refcount_dec_and_test(&pgid->refcount)) 1842 return; 1843 1844 list_del(&pgid->list); 1845 kfree(pgid); 1846 } 1847 1848 static struct ocelot_pgid *ocelot_mdb_get_pgid(struct ocelot *ocelot, 1849 const struct ocelot_multicast *mc) 1850 { 1851 struct ocelot_pgid *pgid; 1852 int index; 1853 1854 /* According to VSC7514 datasheet 3.9.1.5 IPv4 Multicast Entries and 1855 * 3.9.1.6 IPv6 Multicast Entries, "Instead of a lookup in the 1856 * destination mask table (PGID), the destination set is programmed as 1857 * part of the entry MAC address.", and the DEST_IDX is set to 0. 1858 */ 1859 if (mc->entry_type == ENTRYTYPE_MACv4 || 1860 mc->entry_type == ENTRYTYPE_MACv6) 1861 return ocelot_pgid_alloc(ocelot, 0, mc->ports); 1862 1863 list_for_each_entry(pgid, &ocelot->pgids, list) { 1864 /* When searching for a nonreserved multicast PGID, ignore the 1865 * dummy PGID of zero that we have for MACv4/MACv6 entries 1866 */ 1867 if (pgid->index && pgid->ports == mc->ports) { 1868 refcount_inc(&pgid->refcount); 1869 return pgid; 1870 } 1871 } 1872 1873 /* Search for a free index in the nonreserved multicast PGID area */ 1874 for_each_nonreserved_multicast_dest_pgid(ocelot, index) { 1875 bool used = false; 1876 1877 list_for_each_entry(pgid, &ocelot->pgids, list) { 1878 if (pgid->index == index) { 1879 used = true; 1880 break; 1881 } 1882 } 1883 1884 if (!used) 1885 return ocelot_pgid_alloc(ocelot, index, mc->ports); 1886 } 1887 1888 return ERR_PTR(-ENOSPC); 1889 } 1890 1891 static void ocelot_encode_ports_to_mdb(unsigned char *addr, 1892 struct ocelot_multicast *mc) 1893 { 1894 ether_addr_copy(addr, mc->addr); 1895 1896 if (mc->entry_type == ENTRYTYPE_MACv4) { 1897 addr[0] = 0; 1898 addr[1] = mc->ports >> 8; 1899 addr[2] = mc->ports & 0xff; 1900 } else if (mc->entry_type == ENTRYTYPE_MACv6) { 1901 addr[0] = mc->ports >> 8; 1902 addr[1] = mc->ports & 0xff; 1903 } 1904 } 1905 1906 int ocelot_port_mdb_add(struct ocelot *ocelot, int port, 1907 const struct switchdev_obj_port_mdb *mdb, 1908 const struct net_device *bridge) 1909 { 1910 unsigned char addr[ETH_ALEN]; 1911 struct ocelot_multicast *mc; 1912 struct ocelot_pgid *pgid; 1913 u16 vid = mdb->vid; 1914 1915 if (!vid) 1916 vid = ocelot_vlan_unaware_pvid(ocelot, bridge); 1917 1918 mc = ocelot_multicast_get(ocelot, mdb->addr, vid); 1919 if (!mc) { 1920 /* New entry */ 1921 mc = devm_kzalloc(ocelot->dev, sizeof(*mc), GFP_KERNEL); 1922 if (!mc) 1923 return -ENOMEM; 1924 1925 mc->entry_type = ocelot_classify_mdb(mdb->addr); 1926 ether_addr_copy(mc->addr, mdb->addr); 1927 mc->vid = vid; 1928 1929 list_add_tail(&mc->list, &ocelot->multicast); 1930 } else { 1931 /* Existing entry. Clean up the current port mask from 1932 * hardware now, because we'll be modifying it. 1933 */ 1934 ocelot_pgid_free(ocelot, mc->pgid); 1935 ocelot_encode_ports_to_mdb(addr, mc); 1936 ocelot_mact_forget(ocelot, addr, vid); 1937 } 1938 1939 mc->ports |= BIT(port); 1940 1941 pgid = ocelot_mdb_get_pgid(ocelot, mc); 1942 if (IS_ERR(pgid)) { 1943 dev_err(ocelot->dev, 1944 "Cannot allocate PGID for mdb %pM vid %d\n", 1945 mc->addr, mc->vid); 1946 devm_kfree(ocelot->dev, mc); 1947 return PTR_ERR(pgid); 1948 } 1949 mc->pgid = pgid; 1950 1951 ocelot_encode_ports_to_mdb(addr, mc); 1952 1953 if (mc->entry_type != ENTRYTYPE_MACv4 && 1954 mc->entry_type != ENTRYTYPE_MACv6) 1955 ocelot_write_rix(ocelot, pgid->ports, ANA_PGID_PGID, 1956 pgid->index); 1957 1958 return ocelot_mact_learn(ocelot, pgid->index, addr, vid, 1959 mc->entry_type); 1960 } 1961 EXPORT_SYMBOL(ocelot_port_mdb_add); 1962 1963 int ocelot_port_mdb_del(struct ocelot *ocelot, int port, 1964 const struct switchdev_obj_port_mdb *mdb, 1965 const struct net_device *bridge) 1966 { 1967 unsigned char addr[ETH_ALEN]; 1968 struct ocelot_multicast *mc; 1969 struct ocelot_pgid *pgid; 1970 u16 vid = mdb->vid; 1971 1972 if (!vid) 1973 vid = ocelot_vlan_unaware_pvid(ocelot, bridge); 1974 1975 mc = ocelot_multicast_get(ocelot, mdb->addr, vid); 1976 if (!mc) 1977 return -ENOENT; 1978 1979 ocelot_encode_ports_to_mdb(addr, mc); 1980 ocelot_mact_forget(ocelot, addr, vid); 1981 1982 ocelot_pgid_free(ocelot, mc->pgid); 1983 mc->ports &= ~BIT(port); 1984 if (!mc->ports) { 1985 list_del(&mc->list); 1986 devm_kfree(ocelot->dev, mc); 1987 return 0; 1988 } 1989 1990 /* We have a PGID with fewer ports now */ 1991 pgid = ocelot_mdb_get_pgid(ocelot, mc); 1992 if (IS_ERR(pgid)) 1993 return PTR_ERR(pgid); 1994 mc->pgid = pgid; 1995 1996 ocelot_encode_ports_to_mdb(addr, mc); 1997 1998 if (mc->entry_type != ENTRYTYPE_MACv4 && 1999 mc->entry_type != ENTRYTYPE_MACv6) 2000 ocelot_write_rix(ocelot, pgid->ports, ANA_PGID_PGID, 2001 pgid->index); 2002 2003 return ocelot_mact_learn(ocelot, pgid->index, addr, vid, 2004 mc->entry_type); 2005 } 2006 EXPORT_SYMBOL(ocelot_port_mdb_del); 2007 2008 int ocelot_port_bridge_join(struct ocelot *ocelot, int port, 2009 struct net_device *bridge, int bridge_num, 2010 struct netlink_ext_ack *extack) 2011 { 2012 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2013 int err; 2014 2015 err = ocelot_single_vlan_aware_bridge(ocelot, extack); 2016 if (err) 2017 return err; 2018 2019 mutex_lock(&ocelot->fwd_domain_lock); 2020 2021 ocelot_port->bridge = bridge; 2022 ocelot_port->bridge_num = bridge_num; 2023 2024 ocelot_apply_bridge_fwd_mask(ocelot, true); 2025 2026 mutex_unlock(&ocelot->fwd_domain_lock); 2027 2028 if (br_vlan_enabled(bridge)) 2029 return 0; 2030 2031 return ocelot_add_vlan_unaware_pvid(ocelot, port, bridge); 2032 } 2033 EXPORT_SYMBOL(ocelot_port_bridge_join); 2034 2035 void ocelot_port_bridge_leave(struct ocelot *ocelot, int port, 2036 struct net_device *bridge) 2037 { 2038 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2039 2040 mutex_lock(&ocelot->fwd_domain_lock); 2041 2042 if (!br_vlan_enabled(bridge)) 2043 ocelot_del_vlan_unaware_pvid(ocelot, port, bridge); 2044 2045 ocelot_port->bridge = NULL; 2046 ocelot_port->bridge_num = -1; 2047 2048 ocelot_port_set_pvid(ocelot, port, NULL); 2049 ocelot_port_manage_port_tag(ocelot, port); 2050 ocelot_apply_bridge_fwd_mask(ocelot, false); 2051 2052 mutex_unlock(&ocelot->fwd_domain_lock); 2053 } 2054 EXPORT_SYMBOL(ocelot_port_bridge_leave); 2055 2056 static void ocelot_set_aggr_pgids(struct ocelot *ocelot) 2057 { 2058 unsigned long visited = GENMASK(ocelot->num_phys_ports - 1, 0); 2059 int i, port, lag; 2060 2061 /* Reset destination and aggregation PGIDS */ 2062 for_each_unicast_dest_pgid(ocelot, port) 2063 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port); 2064 2065 for_each_aggr_pgid(ocelot, i) 2066 ocelot_write_rix(ocelot, GENMASK(ocelot->num_phys_ports - 1, 0), 2067 ANA_PGID_PGID, i); 2068 2069 /* The visited ports bitmask holds the list of ports offloading any 2070 * bonding interface. Initially we mark all these ports as unvisited, 2071 * then every time we visit a port in this bitmask, we know that it is 2072 * the lowest numbered port, i.e. the one whose logical ID == physical 2073 * port ID == LAG ID. So we mark as visited all further ports in the 2074 * bitmask that are offloading the same bonding interface. This way, 2075 * we set up the aggregation PGIDs only once per bonding interface. 2076 */ 2077 for (port = 0; port < ocelot->num_phys_ports; port++) { 2078 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2079 2080 if (!ocelot_port || !ocelot_port->bond) 2081 continue; 2082 2083 visited &= ~BIT(port); 2084 } 2085 2086 /* Now, set PGIDs for each active LAG */ 2087 for (lag = 0; lag < ocelot->num_phys_ports; lag++) { 2088 struct net_device *bond = ocelot->ports[lag]->bond; 2089 int num_active_ports = 0; 2090 unsigned long bond_mask; 2091 u8 aggr_idx[16]; 2092 2093 if (!bond || (visited & BIT(lag))) 2094 continue; 2095 2096 bond_mask = ocelot_get_bond_mask(ocelot, bond); 2097 2098 for_each_set_bit(port, &bond_mask, ocelot->num_phys_ports) { 2099 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2100 2101 // Destination mask 2102 ocelot_write_rix(ocelot, bond_mask, 2103 ANA_PGID_PGID, port); 2104 2105 if (ocelot_port->lag_tx_active) 2106 aggr_idx[num_active_ports++] = port; 2107 } 2108 2109 for_each_aggr_pgid(ocelot, i) { 2110 u32 ac; 2111 2112 ac = ocelot_read_rix(ocelot, ANA_PGID_PGID, i); 2113 ac &= ~bond_mask; 2114 /* Don't do division by zero if there was no active 2115 * port. Just make all aggregation codes zero. 2116 */ 2117 if (num_active_ports) 2118 ac |= BIT(aggr_idx[i % num_active_ports]); 2119 ocelot_write_rix(ocelot, ac, ANA_PGID_PGID, i); 2120 } 2121 2122 /* Mark all ports in the same LAG as visited to avoid applying 2123 * the same config again. 2124 */ 2125 for (port = lag; port < ocelot->num_phys_ports; port++) { 2126 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2127 2128 if (!ocelot_port) 2129 continue; 2130 2131 if (ocelot_port->bond == bond) 2132 visited |= BIT(port); 2133 } 2134 } 2135 } 2136 2137 /* When offloading a bonding interface, the switch ports configured under the 2138 * same bond must have the same logical port ID, equal to the physical port ID 2139 * of the lowest numbered physical port in that bond. Otherwise, in standalone/ 2140 * bridged mode, each port has a logical port ID equal to its physical port ID. 2141 */ 2142 static void ocelot_setup_logical_port_ids(struct ocelot *ocelot) 2143 { 2144 int port; 2145 2146 for (port = 0; port < ocelot->num_phys_ports; port++) { 2147 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2148 struct net_device *bond; 2149 2150 if (!ocelot_port) 2151 continue; 2152 2153 bond = ocelot_port->bond; 2154 if (bond) { 2155 int lag = ocelot_bond_get_id(ocelot, bond); 2156 2157 ocelot_rmw_gix(ocelot, 2158 ANA_PORT_PORT_CFG_PORTID_VAL(lag), 2159 ANA_PORT_PORT_CFG_PORTID_VAL_M, 2160 ANA_PORT_PORT_CFG, port); 2161 } else { 2162 ocelot_rmw_gix(ocelot, 2163 ANA_PORT_PORT_CFG_PORTID_VAL(port), 2164 ANA_PORT_PORT_CFG_PORTID_VAL_M, 2165 ANA_PORT_PORT_CFG, port); 2166 } 2167 } 2168 } 2169 2170 static int ocelot_migrate_mc(struct ocelot *ocelot, struct ocelot_multicast *mc, 2171 unsigned long from_mask, unsigned long to_mask) 2172 { 2173 unsigned char addr[ETH_ALEN]; 2174 struct ocelot_pgid *pgid; 2175 u16 vid = mc->vid; 2176 2177 dev_dbg(ocelot->dev, 2178 "Migrating multicast %pM vid %d from port mask 0x%lx to 0x%lx\n", 2179 mc->addr, mc->vid, from_mask, to_mask); 2180 2181 /* First clean up the current port mask from hardware, because 2182 * we'll be modifying it. 2183 */ 2184 ocelot_pgid_free(ocelot, mc->pgid); 2185 ocelot_encode_ports_to_mdb(addr, mc); 2186 ocelot_mact_forget(ocelot, addr, vid); 2187 2188 mc->ports &= ~from_mask; 2189 mc->ports |= to_mask; 2190 2191 pgid = ocelot_mdb_get_pgid(ocelot, mc); 2192 if (IS_ERR(pgid)) { 2193 dev_err(ocelot->dev, 2194 "Cannot allocate PGID for mdb %pM vid %d\n", 2195 mc->addr, mc->vid); 2196 devm_kfree(ocelot->dev, mc); 2197 return PTR_ERR(pgid); 2198 } 2199 mc->pgid = pgid; 2200 2201 ocelot_encode_ports_to_mdb(addr, mc); 2202 2203 if (mc->entry_type != ENTRYTYPE_MACv4 && 2204 mc->entry_type != ENTRYTYPE_MACv6) 2205 ocelot_write_rix(ocelot, pgid->ports, ANA_PGID_PGID, 2206 pgid->index); 2207 2208 return ocelot_mact_learn(ocelot, pgid->index, addr, vid, 2209 mc->entry_type); 2210 } 2211 2212 int ocelot_migrate_mdbs(struct ocelot *ocelot, unsigned long from_mask, 2213 unsigned long to_mask) 2214 { 2215 struct ocelot_multicast *mc; 2216 int err; 2217 2218 list_for_each_entry(mc, &ocelot->multicast, list) { 2219 if (!(mc->ports & from_mask)) 2220 continue; 2221 2222 err = ocelot_migrate_mc(ocelot, mc, from_mask, to_mask); 2223 if (err) 2224 return err; 2225 } 2226 2227 return 0; 2228 } 2229 EXPORT_SYMBOL_GPL(ocelot_migrate_mdbs); 2230 2231 /* Documentation for PORTID_VAL says: 2232 * Logical port number for front port. If port is not a member of a LLAG, 2233 * then PORTID must be set to the physical port number. 2234 * If port is a member of a LLAG, then PORTID must be set to the common 2235 * PORTID_VAL used for all member ports of the LLAG. 2236 * The value must not exceed the number of physical ports on the device. 2237 * 2238 * This means we have little choice but to migrate FDB entries pointing towards 2239 * a logical port when that changes. 2240 */ 2241 static void ocelot_migrate_lag_fdbs(struct ocelot *ocelot, 2242 struct net_device *bond, 2243 int lag) 2244 { 2245 struct ocelot_lag_fdb *fdb; 2246 int err; 2247 2248 lockdep_assert_held(&ocelot->fwd_domain_lock); 2249 2250 list_for_each_entry(fdb, &ocelot->lag_fdbs, list) { 2251 if (fdb->bond != bond) 2252 continue; 2253 2254 err = ocelot_mact_forget(ocelot, fdb->addr, fdb->vid); 2255 if (err) { 2256 dev_err(ocelot->dev, 2257 "failed to delete LAG %s FDB %pM vid %d: %pe\n", 2258 bond->name, fdb->addr, fdb->vid, ERR_PTR(err)); 2259 } 2260 2261 err = ocelot_mact_learn(ocelot, lag, fdb->addr, fdb->vid, 2262 ENTRYTYPE_LOCKED); 2263 if (err) { 2264 dev_err(ocelot->dev, 2265 "failed to migrate LAG %s FDB %pM vid %d: %pe\n", 2266 bond->name, fdb->addr, fdb->vid, ERR_PTR(err)); 2267 } 2268 } 2269 } 2270 2271 int ocelot_port_lag_join(struct ocelot *ocelot, int port, 2272 struct net_device *bond, 2273 struct netdev_lag_upper_info *info, 2274 struct netlink_ext_ack *extack) 2275 { 2276 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) { 2277 NL_SET_ERR_MSG_MOD(extack, 2278 "Can only offload LAG using hash TX type"); 2279 return -EOPNOTSUPP; 2280 } 2281 2282 mutex_lock(&ocelot->fwd_domain_lock); 2283 2284 ocelot->ports[port]->bond = bond; 2285 2286 ocelot_setup_logical_port_ids(ocelot); 2287 ocelot_apply_bridge_fwd_mask(ocelot, true); 2288 ocelot_set_aggr_pgids(ocelot); 2289 2290 mutex_unlock(&ocelot->fwd_domain_lock); 2291 2292 return 0; 2293 } 2294 EXPORT_SYMBOL(ocelot_port_lag_join); 2295 2296 void ocelot_port_lag_leave(struct ocelot *ocelot, int port, 2297 struct net_device *bond) 2298 { 2299 int old_lag_id, new_lag_id; 2300 2301 mutex_lock(&ocelot->fwd_domain_lock); 2302 2303 old_lag_id = ocelot_bond_get_id(ocelot, bond); 2304 2305 ocelot->ports[port]->bond = NULL; 2306 2307 ocelot_setup_logical_port_ids(ocelot); 2308 ocelot_apply_bridge_fwd_mask(ocelot, false); 2309 ocelot_set_aggr_pgids(ocelot); 2310 2311 new_lag_id = ocelot_bond_get_id(ocelot, bond); 2312 2313 if (new_lag_id >= 0 && old_lag_id != new_lag_id) 2314 ocelot_migrate_lag_fdbs(ocelot, bond, new_lag_id); 2315 2316 mutex_unlock(&ocelot->fwd_domain_lock); 2317 } 2318 EXPORT_SYMBOL(ocelot_port_lag_leave); 2319 2320 void ocelot_port_lag_change(struct ocelot *ocelot, int port, bool lag_tx_active) 2321 { 2322 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2323 2324 mutex_lock(&ocelot->fwd_domain_lock); 2325 2326 ocelot_port->lag_tx_active = lag_tx_active; 2327 2328 /* Rebalance the LAGs */ 2329 ocelot_set_aggr_pgids(ocelot); 2330 2331 mutex_unlock(&ocelot->fwd_domain_lock); 2332 } 2333 EXPORT_SYMBOL(ocelot_port_lag_change); 2334 2335 int ocelot_lag_fdb_add(struct ocelot *ocelot, struct net_device *bond, 2336 const unsigned char *addr, u16 vid, 2337 const struct net_device *bridge) 2338 { 2339 struct ocelot_lag_fdb *fdb; 2340 int lag, err; 2341 2342 fdb = kzalloc(sizeof(*fdb), GFP_KERNEL); 2343 if (!fdb) 2344 return -ENOMEM; 2345 2346 mutex_lock(&ocelot->fwd_domain_lock); 2347 2348 if (!vid) 2349 vid = ocelot_vlan_unaware_pvid(ocelot, bridge); 2350 2351 ether_addr_copy(fdb->addr, addr); 2352 fdb->vid = vid; 2353 fdb->bond = bond; 2354 2355 lag = ocelot_bond_get_id(ocelot, bond); 2356 2357 err = ocelot_mact_learn(ocelot, lag, addr, vid, ENTRYTYPE_LOCKED); 2358 if (err) { 2359 mutex_unlock(&ocelot->fwd_domain_lock); 2360 kfree(fdb); 2361 return err; 2362 } 2363 2364 list_add_tail(&fdb->list, &ocelot->lag_fdbs); 2365 mutex_unlock(&ocelot->fwd_domain_lock); 2366 2367 return 0; 2368 } 2369 EXPORT_SYMBOL_GPL(ocelot_lag_fdb_add); 2370 2371 int ocelot_lag_fdb_del(struct ocelot *ocelot, struct net_device *bond, 2372 const unsigned char *addr, u16 vid, 2373 const struct net_device *bridge) 2374 { 2375 struct ocelot_lag_fdb *fdb, *tmp; 2376 2377 mutex_lock(&ocelot->fwd_domain_lock); 2378 2379 if (!vid) 2380 vid = ocelot_vlan_unaware_pvid(ocelot, bridge); 2381 2382 list_for_each_entry_safe(fdb, tmp, &ocelot->lag_fdbs, list) { 2383 if (!ether_addr_equal(fdb->addr, addr) || fdb->vid != vid || 2384 fdb->bond != bond) 2385 continue; 2386 2387 ocelot_mact_forget(ocelot, addr, vid); 2388 list_del(&fdb->list); 2389 mutex_unlock(&ocelot->fwd_domain_lock); 2390 kfree(fdb); 2391 2392 return 0; 2393 } 2394 2395 mutex_unlock(&ocelot->fwd_domain_lock); 2396 2397 return -ENOENT; 2398 } 2399 EXPORT_SYMBOL_GPL(ocelot_lag_fdb_del); 2400 2401 /* Configure the maximum SDU (L2 payload) on RX to the value specified in @sdu. 2402 * The length of VLAN tags is accounted for automatically via DEV_MAC_TAGS_CFG. 2403 * In the special case that it's the NPI port that we're configuring, the 2404 * length of the tag and optional prefix needs to be accounted for privately, 2405 * in order to be able to sustain communication at the requested @sdu. 2406 */ 2407 void ocelot_port_set_maxlen(struct ocelot *ocelot, int port, size_t sdu) 2408 { 2409 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2410 int maxlen = sdu + ETH_HLEN + ETH_FCS_LEN; 2411 int pause_start, pause_stop; 2412 int atop, atop_tot; 2413 2414 if (port == ocelot->npi) { 2415 maxlen += OCELOT_TAG_LEN; 2416 2417 if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_SHORT) 2418 maxlen += OCELOT_SHORT_PREFIX_LEN; 2419 else if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_LONG) 2420 maxlen += OCELOT_LONG_PREFIX_LEN; 2421 } 2422 2423 ocelot_port_writel(ocelot_port, maxlen, DEV_MAC_MAXLEN_CFG); 2424 2425 /* Set Pause watermark hysteresis */ 2426 pause_start = 6 * maxlen / OCELOT_BUFFER_CELL_SZ; 2427 pause_stop = 4 * maxlen / OCELOT_BUFFER_CELL_SZ; 2428 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_START, 2429 pause_start); 2430 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_STOP, 2431 pause_stop); 2432 2433 /* Tail dropping watermarks */ 2434 atop_tot = (ocelot->packet_buffer_size - 9 * maxlen) / 2435 OCELOT_BUFFER_CELL_SZ; 2436 atop = (9 * maxlen) / OCELOT_BUFFER_CELL_SZ; 2437 ocelot_write_rix(ocelot, ocelot->ops->wm_enc(atop), SYS_ATOP, port); 2438 ocelot_write(ocelot, ocelot->ops->wm_enc(atop_tot), SYS_ATOP_TOT_CFG); 2439 } 2440 EXPORT_SYMBOL(ocelot_port_set_maxlen); 2441 2442 int ocelot_get_max_mtu(struct ocelot *ocelot, int port) 2443 { 2444 int max_mtu = 65535 - ETH_HLEN - ETH_FCS_LEN; 2445 2446 if (port == ocelot->npi) { 2447 max_mtu -= OCELOT_TAG_LEN; 2448 2449 if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_SHORT) 2450 max_mtu -= OCELOT_SHORT_PREFIX_LEN; 2451 else if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_LONG) 2452 max_mtu -= OCELOT_LONG_PREFIX_LEN; 2453 } 2454 2455 return max_mtu; 2456 } 2457 EXPORT_SYMBOL(ocelot_get_max_mtu); 2458 2459 static void ocelot_port_set_learning(struct ocelot *ocelot, int port, 2460 bool enabled) 2461 { 2462 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2463 u32 val = 0; 2464 2465 if (enabled) 2466 val = ANA_PORT_PORT_CFG_LEARN_ENA; 2467 2468 ocelot_rmw_gix(ocelot, val, ANA_PORT_PORT_CFG_LEARN_ENA, 2469 ANA_PORT_PORT_CFG, port); 2470 2471 ocelot_port->learn_ena = enabled; 2472 } 2473 2474 static void ocelot_port_set_ucast_flood(struct ocelot *ocelot, int port, 2475 bool enabled) 2476 { 2477 u32 val = 0; 2478 2479 if (enabled) 2480 val = BIT(port); 2481 2482 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_UC); 2483 } 2484 2485 static void ocelot_port_set_mcast_flood(struct ocelot *ocelot, int port, 2486 bool enabled) 2487 { 2488 u32 val = 0; 2489 2490 if (enabled) 2491 val = BIT(port); 2492 2493 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_MC); 2494 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_MCIPV4); 2495 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_MCIPV6); 2496 } 2497 2498 static void ocelot_port_set_bcast_flood(struct ocelot *ocelot, int port, 2499 bool enabled) 2500 { 2501 u32 val = 0; 2502 2503 if (enabled) 2504 val = BIT(port); 2505 2506 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_BC); 2507 } 2508 2509 int ocelot_port_pre_bridge_flags(struct ocelot *ocelot, int port, 2510 struct switchdev_brport_flags flags) 2511 { 2512 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | 2513 BR_BCAST_FLOOD)) 2514 return -EINVAL; 2515 2516 return 0; 2517 } 2518 EXPORT_SYMBOL(ocelot_port_pre_bridge_flags); 2519 2520 void ocelot_port_bridge_flags(struct ocelot *ocelot, int port, 2521 struct switchdev_brport_flags flags) 2522 { 2523 if (flags.mask & BR_LEARNING) 2524 ocelot_port_set_learning(ocelot, port, 2525 !!(flags.val & BR_LEARNING)); 2526 2527 if (flags.mask & BR_FLOOD) 2528 ocelot_port_set_ucast_flood(ocelot, port, 2529 !!(flags.val & BR_FLOOD)); 2530 2531 if (flags.mask & BR_MCAST_FLOOD) 2532 ocelot_port_set_mcast_flood(ocelot, port, 2533 !!(flags.val & BR_MCAST_FLOOD)); 2534 2535 if (flags.mask & BR_BCAST_FLOOD) 2536 ocelot_port_set_bcast_flood(ocelot, port, 2537 !!(flags.val & BR_BCAST_FLOOD)); 2538 } 2539 EXPORT_SYMBOL(ocelot_port_bridge_flags); 2540 2541 int ocelot_port_get_default_prio(struct ocelot *ocelot, int port) 2542 { 2543 int val = ocelot_read_gix(ocelot, ANA_PORT_QOS_CFG, port); 2544 2545 return ANA_PORT_QOS_CFG_QOS_DEFAULT_VAL_X(val); 2546 } 2547 EXPORT_SYMBOL_GPL(ocelot_port_get_default_prio); 2548 2549 int ocelot_port_set_default_prio(struct ocelot *ocelot, int port, u8 prio) 2550 { 2551 if (prio >= OCELOT_NUM_TC) 2552 return -ERANGE; 2553 2554 ocelot_rmw_gix(ocelot, 2555 ANA_PORT_QOS_CFG_QOS_DEFAULT_VAL(prio), 2556 ANA_PORT_QOS_CFG_QOS_DEFAULT_VAL_M, 2557 ANA_PORT_QOS_CFG, 2558 port); 2559 2560 return 0; 2561 } 2562 EXPORT_SYMBOL_GPL(ocelot_port_set_default_prio); 2563 2564 int ocelot_port_get_dscp_prio(struct ocelot *ocelot, int port, u8 dscp) 2565 { 2566 int qos_cfg = ocelot_read_gix(ocelot, ANA_PORT_QOS_CFG, port); 2567 int dscp_cfg = ocelot_read_rix(ocelot, ANA_DSCP_CFG, dscp); 2568 2569 /* Return error if DSCP prioritization isn't enabled */ 2570 if (!(qos_cfg & ANA_PORT_QOS_CFG_QOS_DSCP_ENA)) 2571 return -EOPNOTSUPP; 2572 2573 if (qos_cfg & ANA_PORT_QOS_CFG_DSCP_TRANSLATE_ENA) { 2574 dscp = ANA_DSCP_CFG_DSCP_TRANSLATE_VAL_X(dscp_cfg); 2575 /* Re-read ANA_DSCP_CFG for the translated DSCP */ 2576 dscp_cfg = ocelot_read_rix(ocelot, ANA_DSCP_CFG, dscp); 2577 } 2578 2579 /* If the DSCP value is not trusted, the QoS classification falls back 2580 * to VLAN PCP or port-based default. 2581 */ 2582 if (!(dscp_cfg & ANA_DSCP_CFG_DSCP_TRUST_ENA)) 2583 return -EOPNOTSUPP; 2584 2585 return ANA_DSCP_CFG_QOS_DSCP_VAL_X(dscp_cfg); 2586 } 2587 EXPORT_SYMBOL_GPL(ocelot_port_get_dscp_prio); 2588 2589 int ocelot_port_add_dscp_prio(struct ocelot *ocelot, int port, u8 dscp, u8 prio) 2590 { 2591 int mask, val; 2592 2593 if (prio >= OCELOT_NUM_TC) 2594 return -ERANGE; 2595 2596 /* There is at least one app table priority (this one), so we need to 2597 * make sure DSCP prioritization is enabled on the port. 2598 * Also make sure DSCP translation is disabled 2599 * (dcbnl doesn't support it). 2600 */ 2601 mask = ANA_PORT_QOS_CFG_QOS_DSCP_ENA | 2602 ANA_PORT_QOS_CFG_DSCP_TRANSLATE_ENA; 2603 2604 ocelot_rmw_gix(ocelot, ANA_PORT_QOS_CFG_QOS_DSCP_ENA, mask, 2605 ANA_PORT_QOS_CFG, port); 2606 2607 /* Trust this DSCP value and map it to the given QoS class */ 2608 val = ANA_DSCP_CFG_DSCP_TRUST_ENA | ANA_DSCP_CFG_QOS_DSCP_VAL(prio); 2609 2610 ocelot_write_rix(ocelot, val, ANA_DSCP_CFG, dscp); 2611 2612 return 0; 2613 } 2614 EXPORT_SYMBOL_GPL(ocelot_port_add_dscp_prio); 2615 2616 int ocelot_port_del_dscp_prio(struct ocelot *ocelot, int port, u8 dscp, u8 prio) 2617 { 2618 int dscp_cfg = ocelot_read_rix(ocelot, ANA_DSCP_CFG, dscp); 2619 int mask, i; 2620 2621 /* During a "dcb app replace" command, the new app table entry will be 2622 * added first, then the old one will be deleted. But the hardware only 2623 * supports one QoS class per DSCP value (duh), so if we blindly delete 2624 * the app table entry for this DSCP value, we end up deleting the 2625 * entry with the new priority. Avoid that by checking whether user 2626 * space wants to delete the priority which is currently configured, or 2627 * something else which is no longer current. 2628 */ 2629 if (ANA_DSCP_CFG_QOS_DSCP_VAL_X(dscp_cfg) != prio) 2630 return 0; 2631 2632 /* Untrust this DSCP value */ 2633 ocelot_write_rix(ocelot, 0, ANA_DSCP_CFG, dscp); 2634 2635 for (i = 0; i < 64; i++) { 2636 int dscp_cfg = ocelot_read_rix(ocelot, ANA_DSCP_CFG, i); 2637 2638 /* There are still app table entries on the port, so we need to 2639 * keep DSCP enabled, nothing to do. 2640 */ 2641 if (dscp_cfg & ANA_DSCP_CFG_DSCP_TRUST_ENA) 2642 return 0; 2643 } 2644 2645 /* Disable DSCP QoS classification if there isn't any trusted 2646 * DSCP value left. 2647 */ 2648 mask = ANA_PORT_QOS_CFG_QOS_DSCP_ENA | 2649 ANA_PORT_QOS_CFG_DSCP_TRANSLATE_ENA; 2650 2651 ocelot_rmw_gix(ocelot, 0, mask, ANA_PORT_QOS_CFG, port); 2652 2653 return 0; 2654 } 2655 EXPORT_SYMBOL_GPL(ocelot_port_del_dscp_prio); 2656 2657 struct ocelot_mirror *ocelot_mirror_get(struct ocelot *ocelot, int to, 2658 struct netlink_ext_ack *extack) 2659 { 2660 struct ocelot_mirror *m = ocelot->mirror; 2661 2662 if (m) { 2663 if (m->to != to) { 2664 NL_SET_ERR_MSG_MOD(extack, 2665 "Mirroring already configured towards different egress port"); 2666 return ERR_PTR(-EBUSY); 2667 } 2668 2669 refcount_inc(&m->refcount); 2670 return m; 2671 } 2672 2673 m = kzalloc(sizeof(*m), GFP_KERNEL); 2674 if (!m) 2675 return ERR_PTR(-ENOMEM); 2676 2677 m->to = to; 2678 refcount_set(&m->refcount, 1); 2679 ocelot->mirror = m; 2680 2681 /* Program the mirror port to hardware */ 2682 ocelot_write(ocelot, BIT(to), ANA_MIRRORPORTS); 2683 2684 return m; 2685 } 2686 2687 void ocelot_mirror_put(struct ocelot *ocelot) 2688 { 2689 struct ocelot_mirror *m = ocelot->mirror; 2690 2691 if (!refcount_dec_and_test(&m->refcount)) 2692 return; 2693 2694 ocelot_write(ocelot, 0, ANA_MIRRORPORTS); 2695 ocelot->mirror = NULL; 2696 kfree(m); 2697 } 2698 2699 int ocelot_port_mirror_add(struct ocelot *ocelot, int from, int to, 2700 bool ingress, struct netlink_ext_ack *extack) 2701 { 2702 struct ocelot_mirror *m = ocelot_mirror_get(ocelot, to, extack); 2703 2704 if (IS_ERR(m)) 2705 return PTR_ERR(m); 2706 2707 if (ingress) { 2708 ocelot_rmw_gix(ocelot, ANA_PORT_PORT_CFG_SRC_MIRROR_ENA, 2709 ANA_PORT_PORT_CFG_SRC_MIRROR_ENA, 2710 ANA_PORT_PORT_CFG, from); 2711 } else { 2712 ocelot_rmw(ocelot, BIT(from), BIT(from), 2713 ANA_EMIRRORPORTS); 2714 } 2715 2716 return 0; 2717 } 2718 EXPORT_SYMBOL_GPL(ocelot_port_mirror_add); 2719 2720 void ocelot_port_mirror_del(struct ocelot *ocelot, int from, bool ingress) 2721 { 2722 if (ingress) { 2723 ocelot_rmw_gix(ocelot, 0, ANA_PORT_PORT_CFG_SRC_MIRROR_ENA, 2724 ANA_PORT_PORT_CFG, from); 2725 } else { 2726 ocelot_rmw(ocelot, 0, BIT(from), ANA_EMIRRORPORTS); 2727 } 2728 2729 ocelot_mirror_put(ocelot); 2730 } 2731 EXPORT_SYMBOL_GPL(ocelot_port_mirror_del); 2732 2733 static void ocelot_port_reset_mqprio(struct ocelot *ocelot, int port) 2734 { 2735 struct net_device *dev = ocelot->ops->port_to_netdev(ocelot, port); 2736 2737 netdev_reset_tc(dev); 2738 ocelot_port_change_fp(ocelot, port, 0); 2739 } 2740 2741 int ocelot_port_mqprio(struct ocelot *ocelot, int port, 2742 struct tc_mqprio_qopt_offload *mqprio) 2743 { 2744 struct net_device *dev = ocelot->ops->port_to_netdev(ocelot, port); 2745 struct netlink_ext_ack *extack = mqprio->extack; 2746 struct tc_mqprio_qopt *qopt = &mqprio->qopt; 2747 int num_tc = qopt->num_tc; 2748 int tc, err; 2749 2750 if (!num_tc) { 2751 ocelot_port_reset_mqprio(ocelot, port); 2752 return 0; 2753 } 2754 2755 err = netdev_set_num_tc(dev, num_tc); 2756 if (err) 2757 return err; 2758 2759 for (tc = 0; tc < num_tc; tc++) { 2760 if (qopt->count[tc] != 1) { 2761 NL_SET_ERR_MSG_MOD(extack, 2762 "Only one TXQ per TC supported"); 2763 return -EINVAL; 2764 } 2765 2766 err = netdev_set_tc_queue(dev, tc, 1, qopt->offset[tc]); 2767 if (err) 2768 goto err_reset_tc; 2769 } 2770 2771 err = netif_set_real_num_tx_queues(dev, num_tc); 2772 if (err) 2773 goto err_reset_tc; 2774 2775 ocelot_port_change_fp(ocelot, port, mqprio->preemptible_tcs); 2776 2777 return 0; 2778 2779 err_reset_tc: 2780 ocelot_port_reset_mqprio(ocelot, port); 2781 return err; 2782 } 2783 EXPORT_SYMBOL_GPL(ocelot_port_mqprio); 2784 2785 void ocelot_init_port(struct ocelot *ocelot, int port) 2786 { 2787 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2788 2789 skb_queue_head_init(&ocelot_port->tx_skbs); 2790 2791 /* Basic L2 initialization */ 2792 2793 /* Set MAC IFG Gaps 2794 * FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 0 2795 * !FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 5 2796 */ 2797 ocelot_port_writel(ocelot_port, DEV_MAC_IFG_CFG_TX_IFG(5), 2798 DEV_MAC_IFG_CFG); 2799 2800 /* Load seed (0) and set MAC HDX late collision */ 2801 ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67) | 2802 DEV_MAC_HDX_CFG_SEED_LOAD, 2803 DEV_MAC_HDX_CFG); 2804 mdelay(1); 2805 ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67), 2806 DEV_MAC_HDX_CFG); 2807 2808 /* Set Max Length and maximum tags allowed */ 2809 ocelot_port_set_maxlen(ocelot, port, ETH_DATA_LEN); 2810 ocelot_port_writel(ocelot_port, DEV_MAC_TAGS_CFG_TAG_ID(ETH_P_8021AD) | 2811 DEV_MAC_TAGS_CFG_VLAN_AWR_ENA | 2812 DEV_MAC_TAGS_CFG_VLAN_DBL_AWR_ENA | 2813 DEV_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA, 2814 DEV_MAC_TAGS_CFG); 2815 2816 /* Set SMAC of Pause frame (00:00:00:00:00:00) */ 2817 ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_HIGH_CFG); 2818 ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_LOW_CFG); 2819 2820 /* Enable transmission of pause frames */ 2821 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, 1); 2822 2823 /* Drop frames with multicast source address */ 2824 ocelot_rmw_gix(ocelot, ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA, 2825 ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA, 2826 ANA_PORT_DROP_CFG, port); 2827 2828 /* Set default VLAN and tag type to 8021Q. */ 2829 ocelot_rmw_gix(ocelot, REW_PORT_VLAN_CFG_PORT_TPID(ETH_P_8021Q), 2830 REW_PORT_VLAN_CFG_PORT_TPID_M, 2831 REW_PORT_VLAN_CFG, port); 2832 2833 /* Disable source address learning for standalone mode */ 2834 ocelot_port_set_learning(ocelot, port, false); 2835 2836 /* Set the port's initial logical port ID value, enable receiving 2837 * frames on it, and configure the MAC address learning type to 2838 * automatic. 2839 */ 2840 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_LEARNAUTO | 2841 ANA_PORT_PORT_CFG_RECV_ENA | 2842 ANA_PORT_PORT_CFG_PORTID_VAL(port), 2843 ANA_PORT_PORT_CFG, port); 2844 2845 /* Enable vcap lookups */ 2846 ocelot_vcap_enable(ocelot, port); 2847 } 2848 EXPORT_SYMBOL(ocelot_init_port); 2849 2850 /* Configure and enable the CPU port module, which is a set of queues 2851 * accessible through register MMIO, frame DMA or Ethernet (in case 2852 * NPI mode is used). 2853 */ 2854 static void ocelot_cpu_port_init(struct ocelot *ocelot) 2855 { 2856 int cpu = ocelot->num_phys_ports; 2857 2858 /* The unicast destination PGID for the CPU port module is unused */ 2859 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, cpu); 2860 /* Instead set up a multicast destination PGID for traffic copied to 2861 * the CPU. Whitelisted MAC addresses like the port netdevice MAC 2862 * addresses will be copied to the CPU via this PGID. 2863 */ 2864 ocelot_write_rix(ocelot, BIT(cpu), ANA_PGID_PGID, PGID_CPU); 2865 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_RECV_ENA | 2866 ANA_PORT_PORT_CFG_PORTID_VAL(cpu), 2867 ANA_PORT_PORT_CFG, cpu); 2868 2869 /* Enable CPU port module */ 2870 ocelot_fields_write(ocelot, cpu, QSYS_SWITCH_PORT_MODE_PORT_ENA, 1); 2871 /* CPU port Injection/Extraction configuration */ 2872 ocelot_fields_write(ocelot, cpu, SYS_PORT_MODE_INCL_XTR_HDR, 2873 OCELOT_TAG_PREFIX_NONE); 2874 ocelot_fields_write(ocelot, cpu, SYS_PORT_MODE_INCL_INJ_HDR, 2875 OCELOT_TAG_PREFIX_NONE); 2876 2877 /* Configure the CPU port to be VLAN aware */ 2878 ocelot_write_gix(ocelot, 2879 ANA_PORT_VLAN_CFG_VLAN_VID(OCELOT_STANDALONE_PVID) | 2880 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 2881 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1), 2882 ANA_PORT_VLAN_CFG, cpu); 2883 } 2884 2885 static void ocelot_detect_features(struct ocelot *ocelot) 2886 { 2887 int mmgt, eq_ctrl; 2888 2889 /* For Ocelot, Felix, Seville, Serval etc, SYS:MMGT:MMGT:FREECNT holds 2890 * the number of 240-byte free memory words (aka 4-cell chunks) and not 2891 * 192 bytes as the documentation incorrectly says. 2892 */ 2893 mmgt = ocelot_read(ocelot, SYS_MMGT); 2894 ocelot->packet_buffer_size = 240 * SYS_MMGT_FREECNT(mmgt); 2895 2896 eq_ctrl = ocelot_read(ocelot, QSYS_EQ_CTRL); 2897 ocelot->num_frame_refs = QSYS_MMGT_EQ_CTRL_FP_FREE_CNT(eq_ctrl); 2898 } 2899 2900 static int ocelot_mem_init_status(struct ocelot *ocelot) 2901 { 2902 unsigned int val; 2903 int err; 2904 2905 err = regmap_field_read(ocelot->regfields[SYS_RESET_CFG_MEM_INIT], 2906 &val); 2907 2908 return err ?: val; 2909 } 2910 2911 int ocelot_reset(struct ocelot *ocelot) 2912 { 2913 int err; 2914 u32 val; 2915 2916 err = regmap_field_write(ocelot->regfields[SYS_RESET_CFG_MEM_INIT], 1); 2917 if (err) 2918 return err; 2919 2920 err = regmap_field_write(ocelot->regfields[SYS_RESET_CFG_MEM_ENA], 1); 2921 if (err) 2922 return err; 2923 2924 /* MEM_INIT is a self-clearing bit. Wait for it to be cleared (should be 2925 * 100us) before enabling the switch core. 2926 */ 2927 err = readx_poll_timeout(ocelot_mem_init_status, ocelot, val, !val, 2928 MEM_INIT_SLEEP_US, MEM_INIT_TIMEOUT_US); 2929 if (err) 2930 return err; 2931 2932 err = regmap_field_write(ocelot->regfields[SYS_RESET_CFG_MEM_ENA], 1); 2933 if (err) 2934 return err; 2935 2936 return regmap_field_write(ocelot->regfields[SYS_RESET_CFG_CORE_ENA], 1); 2937 } 2938 EXPORT_SYMBOL(ocelot_reset); 2939 2940 int ocelot_init(struct ocelot *ocelot) 2941 { 2942 int i, ret; 2943 u32 port; 2944 2945 if (ocelot->ops->reset) { 2946 ret = ocelot->ops->reset(ocelot); 2947 if (ret) { 2948 dev_err(ocelot->dev, "Switch reset failed\n"); 2949 return ret; 2950 } 2951 } 2952 2953 mutex_init(&ocelot->mact_lock); 2954 mutex_init(&ocelot->fwd_domain_lock); 2955 spin_lock_init(&ocelot->ptp_clock_lock); 2956 spin_lock_init(&ocelot->ts_id_lock); 2957 2958 ocelot->owq = alloc_ordered_workqueue("ocelot-owq", 0); 2959 if (!ocelot->owq) 2960 return -ENOMEM; 2961 2962 ret = ocelot_stats_init(ocelot); 2963 if (ret) 2964 goto err_stats_init; 2965 2966 INIT_LIST_HEAD(&ocelot->multicast); 2967 INIT_LIST_HEAD(&ocelot->pgids); 2968 INIT_LIST_HEAD(&ocelot->vlans); 2969 INIT_LIST_HEAD(&ocelot->lag_fdbs); 2970 ocelot_detect_features(ocelot); 2971 ocelot_mact_init(ocelot); 2972 ocelot_vlan_init(ocelot); 2973 ocelot_vcap_init(ocelot); 2974 ocelot_cpu_port_init(ocelot); 2975 2976 if (ocelot->ops->psfp_init) 2977 ocelot->ops->psfp_init(ocelot); 2978 2979 if (ocelot->mm_supported) { 2980 ret = ocelot_mm_init(ocelot); 2981 if (ret) 2982 goto err_mm_init; 2983 } 2984 2985 for (port = 0; port < ocelot->num_phys_ports; port++) { 2986 /* Clear all counters (5 groups) */ 2987 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(port) | 2988 SYS_STAT_CFG_STAT_CLEAR_SHOT(0x7f), 2989 SYS_STAT_CFG); 2990 } 2991 2992 /* Only use S-Tag */ 2993 ocelot_write(ocelot, ETH_P_8021AD, SYS_VLAN_ETYPE_CFG); 2994 2995 /* Aggregation mode */ 2996 ocelot_write(ocelot, ANA_AGGR_CFG_AC_SMAC_ENA | 2997 ANA_AGGR_CFG_AC_DMAC_ENA | 2998 ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA | 2999 ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA | 3000 ANA_AGGR_CFG_AC_IP6_FLOW_LBL_ENA | 3001 ANA_AGGR_CFG_AC_IP6_TCPUDP_ENA, 3002 ANA_AGGR_CFG); 3003 3004 /* Set MAC age time to default value. The entry is aged after 3005 * 2*AGE_PERIOD 3006 */ 3007 ocelot_write(ocelot, 3008 ANA_AUTOAGE_AGE_PERIOD(BR_DEFAULT_AGEING_TIME / 2 / HZ), 3009 ANA_AUTOAGE); 3010 3011 /* Disable learning for frames discarded by VLAN ingress filtering */ 3012 regmap_field_write(ocelot->regfields[ANA_ADVLEARN_VLAN_CHK], 1); 3013 3014 /* Setup frame ageing - fixed value "2 sec" - in 6.5 us units */ 3015 ocelot_write(ocelot, SYS_FRM_AGING_AGE_TX_ENA | 3016 SYS_FRM_AGING_MAX_AGE(307692), SYS_FRM_AGING); 3017 3018 /* Setup flooding PGIDs */ 3019 for (i = 0; i < ocelot->num_flooding_pgids; i++) 3020 ocelot_write_rix(ocelot, ANA_FLOODING_FLD_MULTICAST(PGID_MC) | 3021 ANA_FLOODING_FLD_BROADCAST(PGID_BC) | 3022 ANA_FLOODING_FLD_UNICAST(PGID_UC), 3023 ANA_FLOODING, i); 3024 ocelot_write(ocelot, ANA_FLOODING_IPMC_FLD_MC6_DATA(PGID_MCIPV6) | 3025 ANA_FLOODING_IPMC_FLD_MC6_CTRL(PGID_MC) | 3026 ANA_FLOODING_IPMC_FLD_MC4_DATA(PGID_MCIPV4) | 3027 ANA_FLOODING_IPMC_FLD_MC4_CTRL(PGID_MC), 3028 ANA_FLOODING_IPMC); 3029 3030 for (port = 0; port < ocelot->num_phys_ports; port++) { 3031 /* Transmit the frame to the local port. */ 3032 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port); 3033 /* Do not forward BPDU frames to the front ports. */ 3034 ocelot_write_gix(ocelot, 3035 ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA(0xffff), 3036 ANA_PORT_CPU_FWD_BPDU_CFG, 3037 port); 3038 /* Ensure bridging is disabled */ 3039 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_SRC + port); 3040 } 3041 3042 for_each_nonreserved_multicast_dest_pgid(ocelot, i) { 3043 u32 val = ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports - 1, 0)); 3044 3045 ocelot_write_rix(ocelot, val, ANA_PGID_PGID, i); 3046 } 3047 3048 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_BLACKHOLE); 3049 3050 /* Allow broadcast and unknown L2 multicast to the CPU. */ 3051 ocelot_rmw_rix(ocelot, ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)), 3052 ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)), 3053 ANA_PGID_PGID, PGID_MC); 3054 ocelot_rmw_rix(ocelot, ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)), 3055 ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)), 3056 ANA_PGID_PGID, PGID_BC); 3057 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV4); 3058 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV6); 3059 3060 /* Allow manual injection via DEVCPU_QS registers, and byte swap these 3061 * registers endianness. 3062 */ 3063 ocelot_write_rix(ocelot, QS_INJ_GRP_CFG_BYTE_SWAP | 3064 QS_INJ_GRP_CFG_MODE(1), QS_INJ_GRP_CFG, 0); 3065 ocelot_write_rix(ocelot, QS_XTR_GRP_CFG_BYTE_SWAP | 3066 QS_XTR_GRP_CFG_MODE(1), QS_XTR_GRP_CFG, 0); 3067 ocelot_write(ocelot, ANA_CPUQ_CFG_CPUQ_MIRROR(2) | 3068 ANA_CPUQ_CFG_CPUQ_LRN(2) | 3069 ANA_CPUQ_CFG_CPUQ_MAC_COPY(2) | 3070 ANA_CPUQ_CFG_CPUQ_SRC_COPY(2) | 3071 ANA_CPUQ_CFG_CPUQ_LOCKED_PORTMOVE(2) | 3072 ANA_CPUQ_CFG_CPUQ_ALLBRIDGE(6) | 3073 ANA_CPUQ_CFG_CPUQ_IPMC_CTRL(6) | 3074 ANA_CPUQ_CFG_CPUQ_IGMP(6) | 3075 ANA_CPUQ_CFG_CPUQ_MLD(6), ANA_CPUQ_CFG); 3076 for (i = 0; i < 16; i++) 3077 ocelot_write_rix(ocelot, ANA_CPUQ_8021_CFG_CPUQ_GARP_VAL(6) | 3078 ANA_CPUQ_8021_CFG_CPUQ_BPDU_VAL(6), 3079 ANA_CPUQ_8021_CFG, i); 3080 3081 return 0; 3082 3083 err_mm_init: 3084 ocelot_stats_deinit(ocelot); 3085 err_stats_init: 3086 destroy_workqueue(ocelot->owq); 3087 return ret; 3088 } 3089 EXPORT_SYMBOL(ocelot_init); 3090 3091 void ocelot_deinit(struct ocelot *ocelot) 3092 { 3093 ocelot_stats_deinit(ocelot); 3094 destroy_workqueue(ocelot->owq); 3095 } 3096 EXPORT_SYMBOL(ocelot_deinit); 3097 3098 void ocelot_deinit_port(struct ocelot *ocelot, int port) 3099 { 3100 struct ocelot_port *ocelot_port = ocelot->ports[port]; 3101 3102 skb_queue_purge(&ocelot_port->tx_skbs); 3103 } 3104 EXPORT_SYMBOL(ocelot_deinit_port); 3105 3106 MODULE_LICENSE("Dual MIT/GPL"); 3107