1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* 3 * Microsemi Ocelot Switch driver 4 * 5 * Copyright (c) 2017 Microsemi Corporation 6 */ 7 #include <linux/etherdevice.h> 8 #include <linux/ethtool.h> 9 #include <linux/if_bridge.h> 10 #include <linux/if_ether.h> 11 #include <linux/if_vlan.h> 12 #include <linux/interrupt.h> 13 #include <linux/kernel.h> 14 #include <linux/module.h> 15 #include <linux/netdevice.h> 16 #include <linux/phy.h> 17 #include <linux/skbuff.h> 18 #include <net/arp.h> 19 #include <net/netevent.h> 20 #include <net/rtnetlink.h> 21 #include <net/switchdev.h> 22 23 #include "ocelot.h" 24 25 /* MAC table entry types. 26 * ENTRYTYPE_NORMAL is subject to aging. 27 * ENTRYTYPE_LOCKED is not subject to aging. 28 * ENTRYTYPE_MACv4 is not subject to aging. For IPv4 multicast. 29 * ENTRYTYPE_MACv6 is not subject to aging. For IPv6 multicast. 30 */ 31 enum macaccess_entry_type { 32 ENTRYTYPE_NORMAL = 0, 33 ENTRYTYPE_LOCKED, 34 ENTRYTYPE_MACv4, 35 ENTRYTYPE_MACv6, 36 }; 37 38 struct ocelot_mact_entry { 39 u8 mac[ETH_ALEN]; 40 u16 vid; 41 enum macaccess_entry_type type; 42 }; 43 44 static inline int ocelot_mact_wait_for_completion(struct ocelot *ocelot) 45 { 46 unsigned int val, timeout = 10; 47 48 /* Wait for the issued mac table command to be completed, or timeout. 49 * When the command read from ANA_TABLES_MACACCESS is 50 * MACACCESS_CMD_IDLE, the issued command completed successfully. 51 */ 52 do { 53 val = ocelot_read(ocelot, ANA_TABLES_MACACCESS); 54 val &= ANA_TABLES_MACACCESS_MAC_TABLE_CMD_M; 55 } while (val != MACACCESS_CMD_IDLE && timeout--); 56 57 if (!timeout) 58 return -ETIMEDOUT; 59 60 return 0; 61 } 62 63 static void ocelot_mact_select(struct ocelot *ocelot, 64 const unsigned char mac[ETH_ALEN], 65 unsigned int vid) 66 { 67 u32 macl = 0, mach = 0; 68 69 /* Set the MAC address to handle and the vlan associated in a format 70 * understood by the hardware. 71 */ 72 mach |= vid << 16; 73 mach |= mac[0] << 8; 74 mach |= mac[1] << 0; 75 macl |= mac[2] << 24; 76 macl |= mac[3] << 16; 77 macl |= mac[4] << 8; 78 macl |= mac[5] << 0; 79 80 ocelot_write(ocelot, macl, ANA_TABLES_MACLDATA); 81 ocelot_write(ocelot, mach, ANA_TABLES_MACHDATA); 82 83 } 84 85 static int ocelot_mact_learn(struct ocelot *ocelot, int port, 86 const unsigned char mac[ETH_ALEN], 87 unsigned int vid, 88 enum macaccess_entry_type type) 89 { 90 ocelot_mact_select(ocelot, mac, vid); 91 92 /* Issue a write command */ 93 ocelot_write(ocelot, ANA_TABLES_MACACCESS_VALID | 94 ANA_TABLES_MACACCESS_DEST_IDX(port) | 95 ANA_TABLES_MACACCESS_ENTRYTYPE(type) | 96 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_LEARN), 97 ANA_TABLES_MACACCESS); 98 99 return ocelot_mact_wait_for_completion(ocelot); 100 } 101 102 static int ocelot_mact_forget(struct ocelot *ocelot, 103 const unsigned char mac[ETH_ALEN], 104 unsigned int vid) 105 { 106 ocelot_mact_select(ocelot, mac, vid); 107 108 /* Issue a forget command */ 109 ocelot_write(ocelot, 110 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_FORGET), 111 ANA_TABLES_MACACCESS); 112 113 return ocelot_mact_wait_for_completion(ocelot); 114 } 115 116 static void ocelot_mact_init(struct ocelot *ocelot) 117 { 118 /* Configure the learning mode entries attributes: 119 * - Do not copy the frame to the CPU extraction queues. 120 * - Use the vlan and mac_cpoy for dmac lookup. 121 */ 122 ocelot_rmw(ocelot, 0, 123 ANA_AGENCTRL_LEARN_CPU_COPY | ANA_AGENCTRL_IGNORE_DMAC_FLAGS 124 | ANA_AGENCTRL_LEARN_FWD_KILL 125 | ANA_AGENCTRL_LEARN_IGNORE_VLAN, 126 ANA_AGENCTRL); 127 128 /* Clear the MAC table */ 129 ocelot_write(ocelot, MACACCESS_CMD_INIT, ANA_TABLES_MACACCESS); 130 } 131 132 static inline int ocelot_vlant_wait_for_completion(struct ocelot *ocelot) 133 { 134 unsigned int val, timeout = 10; 135 136 /* Wait for the issued vlan table command to be completed, or timeout. 137 * When the command read from ANA_TABLES_VLANACCESS is 138 * VLANACCESS_CMD_IDLE, the issued command completed successfully. 139 */ 140 do { 141 val = ocelot_read(ocelot, ANA_TABLES_VLANACCESS); 142 val &= ANA_TABLES_VLANACCESS_VLAN_TBL_CMD_M; 143 } while (val != ANA_TABLES_VLANACCESS_CMD_IDLE && timeout--); 144 145 if (!timeout) 146 return -ETIMEDOUT; 147 148 return 0; 149 } 150 151 static int ocelot_vlant_set_mask(struct ocelot *ocelot, u16 vid, u32 mask) 152 { 153 /* Select the VID to configure */ 154 ocelot_write(ocelot, ANA_TABLES_VLANTIDX_V_INDEX(vid), 155 ANA_TABLES_VLANTIDX); 156 /* Set the vlan port members mask and issue a write command */ 157 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_VLAN_PORT_MASK(mask) | 158 ANA_TABLES_VLANACCESS_CMD_WRITE, 159 ANA_TABLES_VLANACCESS); 160 161 return ocelot_vlant_wait_for_completion(ocelot); 162 } 163 164 static void ocelot_vlan_mode(struct ocelot_port *port, 165 netdev_features_t features) 166 { 167 struct ocelot *ocelot = port->ocelot; 168 u8 p = port->chip_port; 169 u32 val; 170 171 /* Filtering */ 172 val = ocelot_read(ocelot, ANA_VLANMASK); 173 if (features & NETIF_F_HW_VLAN_CTAG_FILTER) 174 val |= BIT(p); 175 else 176 val &= ~BIT(p); 177 ocelot_write(ocelot, val, ANA_VLANMASK); 178 } 179 180 static void ocelot_vlan_port_apply(struct ocelot *ocelot, 181 struct ocelot_port *port) 182 { 183 u32 val; 184 185 /* Ingress clasification (ANA_PORT_VLAN_CFG) */ 186 /* Default vlan to clasify for untagged frames (may be zero) */ 187 val = ANA_PORT_VLAN_CFG_VLAN_VID(port->pvid); 188 if (port->vlan_aware) 189 val |= ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 190 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1); 191 192 ocelot_rmw_gix(ocelot, val, 193 ANA_PORT_VLAN_CFG_VLAN_VID_M | 194 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 195 ANA_PORT_VLAN_CFG_VLAN_POP_CNT_M, 196 ANA_PORT_VLAN_CFG, port->chip_port); 197 198 /* Drop frames with multicast source address */ 199 val = ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA; 200 if (port->vlan_aware && !port->vid) 201 /* If port is vlan-aware and tagged, drop untagged and priority 202 * tagged frames. 203 */ 204 val |= ANA_PORT_DROP_CFG_DROP_UNTAGGED_ENA | 205 ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA | 206 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA; 207 ocelot_write_gix(ocelot, val, ANA_PORT_DROP_CFG, port->chip_port); 208 209 /* Egress configuration (REW_TAG_CFG): VLAN tag type to 8021Q. */ 210 val = REW_TAG_CFG_TAG_TPID_CFG(0); 211 212 if (port->vlan_aware) { 213 if (port->vid) 214 /* Tag all frames except when VID == DEFAULT_VLAN */ 215 val |= REW_TAG_CFG_TAG_CFG(1); 216 else 217 /* Tag all frames */ 218 val |= REW_TAG_CFG_TAG_CFG(3); 219 } 220 ocelot_rmw_gix(ocelot, val, 221 REW_TAG_CFG_TAG_TPID_CFG_M | 222 REW_TAG_CFG_TAG_CFG_M, 223 REW_TAG_CFG, port->chip_port); 224 225 /* Set default VLAN and tag type to 8021Q. */ 226 val = REW_PORT_VLAN_CFG_PORT_TPID(ETH_P_8021Q) | 227 REW_PORT_VLAN_CFG_PORT_VID(port->vid); 228 ocelot_rmw_gix(ocelot, val, 229 REW_PORT_VLAN_CFG_PORT_TPID_M | 230 REW_PORT_VLAN_CFG_PORT_VID_M, 231 REW_PORT_VLAN_CFG, port->chip_port); 232 } 233 234 static int ocelot_vlan_vid_add(struct net_device *dev, u16 vid, bool pvid, 235 bool untagged) 236 { 237 struct ocelot_port *port = netdev_priv(dev); 238 struct ocelot *ocelot = port->ocelot; 239 int ret; 240 241 /* Add the port MAC address to with the right VLAN information */ 242 ocelot_mact_learn(ocelot, PGID_CPU, dev->dev_addr, vid, 243 ENTRYTYPE_LOCKED); 244 245 /* Make the port a member of the VLAN */ 246 ocelot->vlan_mask[vid] |= BIT(port->chip_port); 247 ret = ocelot_vlant_set_mask(ocelot, vid, ocelot->vlan_mask[vid]); 248 if (ret) 249 return ret; 250 251 /* Default ingress vlan classification */ 252 if (pvid) 253 port->pvid = vid; 254 255 /* Untagged egress vlan clasification */ 256 if (untagged) 257 port->vid = vid; 258 259 ocelot_vlan_port_apply(ocelot, port); 260 261 return 0; 262 } 263 264 static int ocelot_vlan_vid_del(struct net_device *dev, u16 vid) 265 { 266 struct ocelot_port *port = netdev_priv(dev); 267 struct ocelot *ocelot = port->ocelot; 268 int ret; 269 270 /* 8021q removes VID 0 on module unload for all interfaces 271 * with VLAN filtering feature. We need to keep it to receive 272 * untagged traffic. 273 */ 274 if (vid == 0) 275 return 0; 276 277 /* Del the port MAC address to with the right VLAN information */ 278 ocelot_mact_forget(ocelot, dev->dev_addr, vid); 279 280 /* Stop the port from being a member of the vlan */ 281 ocelot->vlan_mask[vid] &= ~BIT(port->chip_port); 282 ret = ocelot_vlant_set_mask(ocelot, vid, ocelot->vlan_mask[vid]); 283 if (ret) 284 return ret; 285 286 /* Ingress */ 287 if (port->pvid == vid) 288 port->pvid = 0; 289 290 /* Egress */ 291 if (port->vid == vid) 292 port->vid = 0; 293 294 ocelot_vlan_port_apply(ocelot, port); 295 296 return 0; 297 } 298 299 static void ocelot_vlan_init(struct ocelot *ocelot) 300 { 301 u16 port, vid; 302 303 /* Clear VLAN table, by default all ports are members of all VLANs */ 304 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_CMD_INIT, 305 ANA_TABLES_VLANACCESS); 306 ocelot_vlant_wait_for_completion(ocelot); 307 308 /* Configure the port VLAN memberships */ 309 for (vid = 1; vid < VLAN_N_VID; vid++) { 310 ocelot->vlan_mask[vid] = 0; 311 ocelot_vlant_set_mask(ocelot, vid, ocelot->vlan_mask[vid]); 312 } 313 314 /* Because VLAN filtering is enabled, we need VID 0 to get untagged 315 * traffic. It is added automatically if 8021q module is loaded, but 316 * we can't rely on it since module may be not loaded. 317 */ 318 ocelot->vlan_mask[0] = GENMASK(ocelot->num_phys_ports - 1, 0); 319 ocelot_vlant_set_mask(ocelot, 0, ocelot->vlan_mask[0]); 320 321 /* Configure the CPU port to be VLAN aware */ 322 ocelot_write_gix(ocelot, ANA_PORT_VLAN_CFG_VLAN_VID(0) | 323 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 324 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1), 325 ANA_PORT_VLAN_CFG, ocelot->num_phys_ports); 326 327 /* Set vlan ingress filter mask to all ports but the CPU port by 328 * default. 329 */ 330 ocelot_write(ocelot, GENMASK(9, 0), ANA_VLANMASK); 331 332 for (port = 0; port < ocelot->num_phys_ports; port++) { 333 ocelot_write_gix(ocelot, 0, REW_PORT_VLAN_CFG, port); 334 ocelot_write_gix(ocelot, 0, REW_TAG_CFG, port); 335 } 336 } 337 338 /* Watermark encode 339 * Bit 8: Unit; 0:1, 1:16 340 * Bit 7-0: Value to be multiplied with unit 341 */ 342 static u16 ocelot_wm_enc(u16 value) 343 { 344 if (value >= BIT(8)) 345 return BIT(8) | (value / 16); 346 347 return value; 348 } 349 350 static void ocelot_port_adjust_link(struct net_device *dev) 351 { 352 struct ocelot_port *port = netdev_priv(dev); 353 struct ocelot *ocelot = port->ocelot; 354 u8 p = port->chip_port; 355 int speed, atop_wm, mode = 0; 356 357 switch (dev->phydev->speed) { 358 case SPEED_10: 359 speed = OCELOT_SPEED_10; 360 break; 361 case SPEED_100: 362 speed = OCELOT_SPEED_100; 363 break; 364 case SPEED_1000: 365 speed = OCELOT_SPEED_1000; 366 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA; 367 break; 368 case SPEED_2500: 369 speed = OCELOT_SPEED_2500; 370 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA; 371 break; 372 default: 373 netdev_err(dev, "Unsupported PHY speed: %d\n", 374 dev->phydev->speed); 375 return; 376 } 377 378 phy_print_status(dev->phydev); 379 380 if (!dev->phydev->link) 381 return; 382 383 /* Only full duplex supported for now */ 384 ocelot_port_writel(port, DEV_MAC_MODE_CFG_FDX_ENA | 385 mode, DEV_MAC_MODE_CFG); 386 387 /* Set MAC IFG Gaps 388 * FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 0 389 * !FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 5 390 */ 391 ocelot_port_writel(port, DEV_MAC_IFG_CFG_TX_IFG(5), DEV_MAC_IFG_CFG); 392 393 /* Load seed (0) and set MAC HDX late collision */ 394 ocelot_port_writel(port, DEV_MAC_HDX_CFG_LATE_COL_POS(67) | 395 DEV_MAC_HDX_CFG_SEED_LOAD, 396 DEV_MAC_HDX_CFG); 397 mdelay(1); 398 ocelot_port_writel(port, DEV_MAC_HDX_CFG_LATE_COL_POS(67), 399 DEV_MAC_HDX_CFG); 400 401 /* Disable HDX fast control */ 402 ocelot_port_writel(port, DEV_PORT_MISC_HDX_FAST_DIS, DEV_PORT_MISC); 403 404 /* SGMII only for now */ 405 ocelot_port_writel(port, PCS1G_MODE_CFG_SGMII_MODE_ENA, PCS1G_MODE_CFG); 406 ocelot_port_writel(port, PCS1G_SD_CFG_SD_SEL, PCS1G_SD_CFG); 407 408 /* Enable PCS */ 409 ocelot_port_writel(port, PCS1G_CFG_PCS_ENA, PCS1G_CFG); 410 411 /* No aneg on SGMII */ 412 ocelot_port_writel(port, 0, PCS1G_ANEG_CFG); 413 414 /* No loopback */ 415 ocelot_port_writel(port, 0, PCS1G_LB_CFG); 416 417 /* Set Max Length and maximum tags allowed */ 418 ocelot_port_writel(port, VLAN_ETH_FRAME_LEN, DEV_MAC_MAXLEN_CFG); 419 ocelot_port_writel(port, DEV_MAC_TAGS_CFG_TAG_ID(ETH_P_8021AD) | 420 DEV_MAC_TAGS_CFG_VLAN_AWR_ENA | 421 DEV_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA, 422 DEV_MAC_TAGS_CFG); 423 424 /* Enable MAC module */ 425 ocelot_port_writel(port, DEV_MAC_ENA_CFG_RX_ENA | 426 DEV_MAC_ENA_CFG_TX_ENA, DEV_MAC_ENA_CFG); 427 428 /* Take MAC, Port, Phy (intern) and PCS (SGMII/Serdes) clock out of 429 * reset */ 430 ocelot_port_writel(port, DEV_CLOCK_CFG_LINK_SPEED(speed), 431 DEV_CLOCK_CFG); 432 433 /* Set SMAC of Pause frame (00:00:00:00:00:00) */ 434 ocelot_port_writel(port, 0, DEV_MAC_FC_MAC_HIGH_CFG); 435 ocelot_port_writel(port, 0, DEV_MAC_FC_MAC_LOW_CFG); 436 437 /* No PFC */ 438 ocelot_write_gix(ocelot, ANA_PFC_PFC_CFG_FC_LINK_SPEED(speed), 439 ANA_PFC_PFC_CFG, p); 440 441 /* Set Pause WM hysteresis 442 * 152 = 6 * VLAN_ETH_FRAME_LEN / OCELOT_BUFFER_CELL_SZ 443 * 101 = 4 * VLAN_ETH_FRAME_LEN / OCELOT_BUFFER_CELL_SZ 444 */ 445 ocelot_write_rix(ocelot, SYS_PAUSE_CFG_PAUSE_ENA | 446 SYS_PAUSE_CFG_PAUSE_STOP(101) | 447 SYS_PAUSE_CFG_PAUSE_START(152), SYS_PAUSE_CFG, p); 448 449 /* Core: Enable port for frame transfer */ 450 ocelot_write_rix(ocelot, QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE | 451 QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG(1) | 452 QSYS_SWITCH_PORT_MODE_PORT_ENA, 453 QSYS_SWITCH_PORT_MODE, p); 454 455 /* Flow control */ 456 ocelot_write_rix(ocelot, SYS_MAC_FC_CFG_PAUSE_VAL_CFG(0xffff) | 457 SYS_MAC_FC_CFG_RX_FC_ENA | SYS_MAC_FC_CFG_TX_FC_ENA | 458 SYS_MAC_FC_CFG_ZERO_PAUSE_ENA | 459 SYS_MAC_FC_CFG_FC_LATENCY_CFG(0x7) | 460 SYS_MAC_FC_CFG_FC_LINK_SPEED(speed), 461 SYS_MAC_FC_CFG, p); 462 ocelot_write_rix(ocelot, 0, ANA_POL_FLOWC, p); 463 464 /* Tail dropping watermark */ 465 atop_wm = (ocelot->shared_queue_sz - 9 * VLAN_ETH_FRAME_LEN) / OCELOT_BUFFER_CELL_SZ; 466 ocelot_write_rix(ocelot, ocelot_wm_enc(9 * VLAN_ETH_FRAME_LEN), 467 SYS_ATOP, p); 468 ocelot_write(ocelot, ocelot_wm_enc(atop_wm), SYS_ATOP_TOT_CFG); 469 } 470 471 static int ocelot_port_open(struct net_device *dev) 472 { 473 struct ocelot_port *port = netdev_priv(dev); 474 struct ocelot *ocelot = port->ocelot; 475 int err; 476 477 /* Enable receiving frames on the port, and activate auto-learning of 478 * MAC addresses. 479 */ 480 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_LEARNAUTO | 481 ANA_PORT_PORT_CFG_RECV_ENA | 482 ANA_PORT_PORT_CFG_PORTID_VAL(port->chip_port), 483 ANA_PORT_PORT_CFG, port->chip_port); 484 485 if (port->serdes) { 486 err = phy_set_mode_ext(port->serdes, PHY_MODE_ETHERNET, 487 port->phy_mode); 488 if (err) { 489 netdev_err(dev, "Could not set mode of SerDes\n"); 490 return err; 491 } 492 } 493 494 err = phy_connect_direct(dev, port->phy, &ocelot_port_adjust_link, 495 port->phy_mode); 496 if (err) { 497 netdev_err(dev, "Could not attach to PHY\n"); 498 return err; 499 } 500 501 dev->phydev = port->phy; 502 503 phy_attached_info(port->phy); 504 phy_start(port->phy); 505 return 0; 506 } 507 508 static int ocelot_port_stop(struct net_device *dev) 509 { 510 struct ocelot_port *port = netdev_priv(dev); 511 512 phy_disconnect(port->phy); 513 514 dev->phydev = NULL; 515 516 ocelot_port_writel(port, 0, DEV_MAC_ENA_CFG); 517 ocelot_rmw_rix(port->ocelot, 0, QSYS_SWITCH_PORT_MODE_PORT_ENA, 518 QSYS_SWITCH_PORT_MODE, port->chip_port); 519 return 0; 520 } 521 522 /* Generate the IFH for frame injection 523 * 524 * The IFH is a 128bit-value 525 * bit 127: bypass the analyzer processing 526 * bit 56-67: destination mask 527 * bit 28-29: pop_cnt: 3 disables all rewriting of the frame 528 * bit 20-27: cpu extraction queue mask 529 * bit 16: tag type 0: C-tag, 1: S-tag 530 * bit 0-11: VID 531 */ 532 static int ocelot_gen_ifh(u32 *ifh, struct frame_info *info) 533 { 534 ifh[0] = IFH_INJ_BYPASS; 535 ifh[1] = (0xf00 & info->port) >> 8; 536 ifh[2] = (0xff & info->port) << 24; 537 ifh[3] = (info->tag_type << 16) | info->vid; 538 539 return 0; 540 } 541 542 static int ocelot_port_xmit(struct sk_buff *skb, struct net_device *dev) 543 { 544 struct ocelot_port *port = netdev_priv(dev); 545 struct ocelot *ocelot = port->ocelot; 546 u32 val, ifh[IFH_LEN]; 547 struct frame_info info = {}; 548 u8 grp = 0; /* Send everything on CPU group 0 */ 549 unsigned int i, count, last; 550 551 val = ocelot_read(ocelot, QS_INJ_STATUS); 552 if (!(val & QS_INJ_STATUS_FIFO_RDY(BIT(grp))) || 553 (val & QS_INJ_STATUS_WMARK_REACHED(BIT(grp)))) 554 return NETDEV_TX_BUSY; 555 556 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) | 557 QS_INJ_CTRL_SOF, QS_INJ_CTRL, grp); 558 559 info.port = BIT(port->chip_port); 560 info.tag_type = IFH_TAG_TYPE_C; 561 info.vid = skb_vlan_tag_get(skb); 562 ocelot_gen_ifh(ifh, &info); 563 564 for (i = 0; i < IFH_LEN; i++) 565 ocelot_write_rix(ocelot, (__force u32)cpu_to_be32(ifh[i]), 566 QS_INJ_WR, grp); 567 568 count = (skb->len + 3) / 4; 569 last = skb->len % 4; 570 for (i = 0; i < count; i++) { 571 ocelot_write_rix(ocelot, ((u32 *)skb->data)[i], QS_INJ_WR, grp); 572 } 573 574 /* Add padding */ 575 while (i < (OCELOT_BUFFER_CELL_SZ / 4)) { 576 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp); 577 i++; 578 } 579 580 /* Indicate EOF and valid bytes in last word */ 581 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) | 582 QS_INJ_CTRL_VLD_BYTES(skb->len < OCELOT_BUFFER_CELL_SZ ? 0 : last) | 583 QS_INJ_CTRL_EOF, 584 QS_INJ_CTRL, grp); 585 586 /* Add dummy CRC */ 587 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp); 588 skb_tx_timestamp(skb); 589 590 dev->stats.tx_packets++; 591 dev->stats.tx_bytes += skb->len; 592 dev_kfree_skb_any(skb); 593 594 return NETDEV_TX_OK; 595 } 596 597 static void ocelot_mact_mc_reset(struct ocelot_port *port) 598 { 599 struct ocelot *ocelot = port->ocelot; 600 struct netdev_hw_addr *ha, *n; 601 602 /* Free and forget all the MAC addresses stored in the port private mc 603 * list. These are mc addresses that were previously added by calling 604 * ocelot_mact_mc_add(). 605 */ 606 list_for_each_entry_safe(ha, n, &port->mc, list) { 607 ocelot_mact_forget(ocelot, ha->addr, port->pvid); 608 list_del(&ha->list); 609 kfree(ha); 610 } 611 } 612 613 static int ocelot_mact_mc_add(struct ocelot_port *port, 614 struct netdev_hw_addr *hw_addr) 615 { 616 struct ocelot *ocelot = port->ocelot; 617 struct netdev_hw_addr *ha = kzalloc(sizeof(*ha), GFP_KERNEL); 618 619 if (!ha) 620 return -ENOMEM; 621 622 memcpy(ha, hw_addr, sizeof(*ha)); 623 list_add_tail(&ha->list, &port->mc); 624 625 ocelot_mact_learn(ocelot, PGID_CPU, ha->addr, port->pvid, 626 ENTRYTYPE_LOCKED); 627 628 return 0; 629 } 630 631 static void ocelot_set_rx_mode(struct net_device *dev) 632 { 633 struct ocelot_port *port = netdev_priv(dev); 634 struct ocelot *ocelot = port->ocelot; 635 struct netdev_hw_addr *ha; 636 int i; 637 u32 val; 638 639 /* This doesn't handle promiscuous mode because the bridge core is 640 * setting IFF_PROMISC on all slave interfaces and all frames would be 641 * forwarded to the CPU port. 642 */ 643 val = GENMASK(ocelot->num_phys_ports - 1, 0); 644 for (i = ocelot->num_phys_ports + 1; i < PGID_CPU; i++) 645 ocelot_write_rix(ocelot, val, ANA_PGID_PGID, i); 646 647 /* Handle the device multicast addresses. First remove all the 648 * previously installed addresses and then add the latest ones to the 649 * mac table. 650 */ 651 ocelot_mact_mc_reset(port); 652 netdev_for_each_mc_addr(ha, dev) 653 ocelot_mact_mc_add(port, ha); 654 } 655 656 static int ocelot_port_get_phys_port_name(struct net_device *dev, 657 char *buf, size_t len) 658 { 659 struct ocelot_port *port = netdev_priv(dev); 660 int ret; 661 662 ret = snprintf(buf, len, "p%d", port->chip_port); 663 if (ret >= len) 664 return -EINVAL; 665 666 return 0; 667 } 668 669 static int ocelot_port_set_mac_address(struct net_device *dev, void *p) 670 { 671 struct ocelot_port *port = netdev_priv(dev); 672 struct ocelot *ocelot = port->ocelot; 673 const struct sockaddr *addr = p; 674 675 /* Learn the new net device MAC address in the mac table. */ 676 ocelot_mact_learn(ocelot, PGID_CPU, addr->sa_data, port->pvid, 677 ENTRYTYPE_LOCKED); 678 /* Then forget the previous one. */ 679 ocelot_mact_forget(ocelot, dev->dev_addr, port->pvid); 680 681 ether_addr_copy(dev->dev_addr, addr->sa_data); 682 return 0; 683 } 684 685 static void ocelot_get_stats64(struct net_device *dev, 686 struct rtnl_link_stats64 *stats) 687 { 688 struct ocelot_port *port = netdev_priv(dev); 689 struct ocelot *ocelot = port->ocelot; 690 691 /* Configure the port to read the stats from */ 692 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(port->chip_port), 693 SYS_STAT_CFG); 694 695 /* Get Rx stats */ 696 stats->rx_bytes = ocelot_read(ocelot, SYS_COUNT_RX_OCTETS); 697 stats->rx_packets = ocelot_read(ocelot, SYS_COUNT_RX_SHORTS) + 698 ocelot_read(ocelot, SYS_COUNT_RX_FRAGMENTS) + 699 ocelot_read(ocelot, SYS_COUNT_RX_JABBERS) + 700 ocelot_read(ocelot, SYS_COUNT_RX_LONGS) + 701 ocelot_read(ocelot, SYS_COUNT_RX_64) + 702 ocelot_read(ocelot, SYS_COUNT_RX_65_127) + 703 ocelot_read(ocelot, SYS_COUNT_RX_128_255) + 704 ocelot_read(ocelot, SYS_COUNT_RX_256_1023) + 705 ocelot_read(ocelot, SYS_COUNT_RX_1024_1526) + 706 ocelot_read(ocelot, SYS_COUNT_RX_1527_MAX); 707 stats->multicast = ocelot_read(ocelot, SYS_COUNT_RX_MULTICAST); 708 stats->rx_dropped = dev->stats.rx_dropped; 709 710 /* Get Tx stats */ 711 stats->tx_bytes = ocelot_read(ocelot, SYS_COUNT_TX_OCTETS); 712 stats->tx_packets = ocelot_read(ocelot, SYS_COUNT_TX_64) + 713 ocelot_read(ocelot, SYS_COUNT_TX_65_127) + 714 ocelot_read(ocelot, SYS_COUNT_TX_128_511) + 715 ocelot_read(ocelot, SYS_COUNT_TX_512_1023) + 716 ocelot_read(ocelot, SYS_COUNT_TX_1024_1526) + 717 ocelot_read(ocelot, SYS_COUNT_TX_1527_MAX); 718 stats->tx_dropped = ocelot_read(ocelot, SYS_COUNT_TX_DROPS) + 719 ocelot_read(ocelot, SYS_COUNT_TX_AGING); 720 stats->collisions = ocelot_read(ocelot, SYS_COUNT_TX_COLLISION); 721 } 722 723 static int ocelot_fdb_add(struct ndmsg *ndm, struct nlattr *tb[], 724 struct net_device *dev, const unsigned char *addr, 725 u16 vid, u16 flags) 726 { 727 struct ocelot_port *port = netdev_priv(dev); 728 struct ocelot *ocelot = port->ocelot; 729 730 if (!vid) { 731 if (!port->vlan_aware) 732 /* If the bridge is not VLAN aware and no VID was 733 * provided, set it to pvid to ensure the MAC entry 734 * matches incoming untagged packets 735 */ 736 vid = port->pvid; 737 else 738 /* If the bridge is VLAN aware a VID must be provided as 739 * otherwise the learnt entry wouldn't match any frame. 740 */ 741 return -EINVAL; 742 } 743 744 return ocelot_mact_learn(ocelot, port->chip_port, addr, vid, 745 ENTRYTYPE_NORMAL); 746 } 747 748 static int ocelot_fdb_del(struct ndmsg *ndm, struct nlattr *tb[], 749 struct net_device *dev, 750 const unsigned char *addr, u16 vid) 751 { 752 struct ocelot_port *port = netdev_priv(dev); 753 struct ocelot *ocelot = port->ocelot; 754 755 return ocelot_mact_forget(ocelot, addr, vid); 756 } 757 758 struct ocelot_dump_ctx { 759 struct net_device *dev; 760 struct sk_buff *skb; 761 struct netlink_callback *cb; 762 int idx; 763 }; 764 765 static int ocelot_fdb_do_dump(struct ocelot_mact_entry *entry, 766 struct ocelot_dump_ctx *dump) 767 { 768 u32 portid = NETLINK_CB(dump->cb->skb).portid; 769 u32 seq = dump->cb->nlh->nlmsg_seq; 770 struct nlmsghdr *nlh; 771 struct ndmsg *ndm; 772 773 if (dump->idx < dump->cb->args[2]) 774 goto skip; 775 776 nlh = nlmsg_put(dump->skb, portid, seq, RTM_NEWNEIGH, 777 sizeof(*ndm), NLM_F_MULTI); 778 if (!nlh) 779 return -EMSGSIZE; 780 781 ndm = nlmsg_data(nlh); 782 ndm->ndm_family = AF_BRIDGE; 783 ndm->ndm_pad1 = 0; 784 ndm->ndm_pad2 = 0; 785 ndm->ndm_flags = NTF_SELF; 786 ndm->ndm_type = 0; 787 ndm->ndm_ifindex = dump->dev->ifindex; 788 ndm->ndm_state = NUD_REACHABLE; 789 790 if (nla_put(dump->skb, NDA_LLADDR, ETH_ALEN, entry->mac)) 791 goto nla_put_failure; 792 793 if (entry->vid && nla_put_u16(dump->skb, NDA_VLAN, entry->vid)) 794 goto nla_put_failure; 795 796 nlmsg_end(dump->skb, nlh); 797 798 skip: 799 dump->idx++; 800 return 0; 801 802 nla_put_failure: 803 nlmsg_cancel(dump->skb, nlh); 804 return -EMSGSIZE; 805 } 806 807 static inline int ocelot_mact_read(struct ocelot_port *port, int row, int col, 808 struct ocelot_mact_entry *entry) 809 { 810 struct ocelot *ocelot = port->ocelot; 811 char mac[ETH_ALEN]; 812 u32 val, dst, macl, mach; 813 814 /* Set row and column to read from */ 815 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_M_INDEX, row); 816 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_BUCKET, col); 817 818 /* Issue a read command */ 819 ocelot_write(ocelot, 820 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_READ), 821 ANA_TABLES_MACACCESS); 822 823 if (ocelot_mact_wait_for_completion(ocelot)) 824 return -ETIMEDOUT; 825 826 /* Read the entry flags */ 827 val = ocelot_read(ocelot, ANA_TABLES_MACACCESS); 828 if (!(val & ANA_TABLES_MACACCESS_VALID)) 829 return -EINVAL; 830 831 /* If the entry read has another port configured as its destination, 832 * do not report it. 833 */ 834 dst = (val & ANA_TABLES_MACACCESS_DEST_IDX_M) >> 3; 835 if (dst != port->chip_port) 836 return -EINVAL; 837 838 /* Get the entry's MAC address and VLAN id */ 839 macl = ocelot_read(ocelot, ANA_TABLES_MACLDATA); 840 mach = ocelot_read(ocelot, ANA_TABLES_MACHDATA); 841 842 mac[0] = (mach >> 8) & 0xff; 843 mac[1] = (mach >> 0) & 0xff; 844 mac[2] = (macl >> 24) & 0xff; 845 mac[3] = (macl >> 16) & 0xff; 846 mac[4] = (macl >> 8) & 0xff; 847 mac[5] = (macl >> 0) & 0xff; 848 849 entry->vid = (mach >> 16) & 0xfff; 850 ether_addr_copy(entry->mac, mac); 851 852 return 0; 853 } 854 855 static int ocelot_fdb_dump(struct sk_buff *skb, struct netlink_callback *cb, 856 struct net_device *dev, 857 struct net_device *filter_dev, int *idx) 858 { 859 struct ocelot_port *port = netdev_priv(dev); 860 int i, j, ret = 0; 861 struct ocelot_dump_ctx dump = { 862 .dev = dev, 863 .skb = skb, 864 .cb = cb, 865 .idx = *idx, 866 }; 867 868 struct ocelot_mact_entry entry; 869 870 /* Loop through all the mac tables entries. There are 1024 rows of 4 871 * entries. 872 */ 873 for (i = 0; i < 1024; i++) { 874 for (j = 0; j < 4; j++) { 875 ret = ocelot_mact_read(port, i, j, &entry); 876 /* If the entry is invalid (wrong port, invalid...), 877 * skip it. 878 */ 879 if (ret == -EINVAL) 880 continue; 881 else if (ret) 882 goto end; 883 884 ret = ocelot_fdb_do_dump(&entry, &dump); 885 if (ret) 886 goto end; 887 } 888 } 889 890 end: 891 *idx = dump.idx; 892 return ret; 893 } 894 895 static int ocelot_vlan_rx_add_vid(struct net_device *dev, __be16 proto, 896 u16 vid) 897 { 898 return ocelot_vlan_vid_add(dev, vid, false, true); 899 } 900 901 static int ocelot_vlan_rx_kill_vid(struct net_device *dev, __be16 proto, 902 u16 vid) 903 { 904 return ocelot_vlan_vid_del(dev, vid); 905 } 906 907 static int ocelot_set_features(struct net_device *dev, 908 netdev_features_t features) 909 { 910 struct ocelot_port *port = netdev_priv(dev); 911 netdev_features_t changed = dev->features ^ features; 912 913 if (changed & NETIF_F_HW_VLAN_CTAG_FILTER) 914 ocelot_vlan_mode(port, features); 915 916 return 0; 917 } 918 919 static const struct net_device_ops ocelot_port_netdev_ops = { 920 .ndo_open = ocelot_port_open, 921 .ndo_stop = ocelot_port_stop, 922 .ndo_start_xmit = ocelot_port_xmit, 923 .ndo_set_rx_mode = ocelot_set_rx_mode, 924 .ndo_get_phys_port_name = ocelot_port_get_phys_port_name, 925 .ndo_set_mac_address = ocelot_port_set_mac_address, 926 .ndo_get_stats64 = ocelot_get_stats64, 927 .ndo_fdb_add = ocelot_fdb_add, 928 .ndo_fdb_del = ocelot_fdb_del, 929 .ndo_fdb_dump = ocelot_fdb_dump, 930 .ndo_vlan_rx_add_vid = ocelot_vlan_rx_add_vid, 931 .ndo_vlan_rx_kill_vid = ocelot_vlan_rx_kill_vid, 932 .ndo_set_features = ocelot_set_features, 933 }; 934 935 static void ocelot_get_strings(struct net_device *netdev, u32 sset, u8 *data) 936 { 937 struct ocelot_port *port = netdev_priv(netdev); 938 struct ocelot *ocelot = port->ocelot; 939 int i; 940 941 if (sset != ETH_SS_STATS) 942 return; 943 944 for (i = 0; i < ocelot->num_stats; i++) 945 memcpy(data + i * ETH_GSTRING_LEN, ocelot->stats_layout[i].name, 946 ETH_GSTRING_LEN); 947 } 948 949 static void ocelot_check_stats(struct work_struct *work) 950 { 951 struct delayed_work *del_work = to_delayed_work(work); 952 struct ocelot *ocelot = container_of(del_work, struct ocelot, stats_work); 953 int i, j; 954 955 mutex_lock(&ocelot->stats_lock); 956 957 for (i = 0; i < ocelot->num_phys_ports; i++) { 958 /* Configure the port to read the stats from */ 959 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(i), SYS_STAT_CFG); 960 961 for (j = 0; j < ocelot->num_stats; j++) { 962 u32 val; 963 unsigned int idx = i * ocelot->num_stats + j; 964 965 val = ocelot_read_rix(ocelot, SYS_COUNT_RX_OCTETS, 966 ocelot->stats_layout[j].offset); 967 968 if (val < (ocelot->stats[idx] & U32_MAX)) 969 ocelot->stats[idx] += (u64)1 << 32; 970 971 ocelot->stats[idx] = (ocelot->stats[idx] & 972 ~(u64)U32_MAX) + val; 973 } 974 } 975 976 cancel_delayed_work(&ocelot->stats_work); 977 queue_delayed_work(ocelot->stats_queue, &ocelot->stats_work, 978 OCELOT_STATS_CHECK_DELAY); 979 980 mutex_unlock(&ocelot->stats_lock); 981 } 982 983 static void ocelot_get_ethtool_stats(struct net_device *dev, 984 struct ethtool_stats *stats, u64 *data) 985 { 986 struct ocelot_port *port = netdev_priv(dev); 987 struct ocelot *ocelot = port->ocelot; 988 int i; 989 990 /* check and update now */ 991 ocelot_check_stats(&ocelot->stats_work.work); 992 993 /* Copy all counters */ 994 for (i = 0; i < ocelot->num_stats; i++) 995 *data++ = ocelot->stats[port->chip_port * ocelot->num_stats + i]; 996 } 997 998 static int ocelot_get_sset_count(struct net_device *dev, int sset) 999 { 1000 struct ocelot_port *port = netdev_priv(dev); 1001 struct ocelot *ocelot = port->ocelot; 1002 1003 if (sset != ETH_SS_STATS) 1004 return -EOPNOTSUPP; 1005 return ocelot->num_stats; 1006 } 1007 1008 static const struct ethtool_ops ocelot_ethtool_ops = { 1009 .get_strings = ocelot_get_strings, 1010 .get_ethtool_stats = ocelot_get_ethtool_stats, 1011 .get_sset_count = ocelot_get_sset_count, 1012 .get_link_ksettings = phy_ethtool_get_link_ksettings, 1013 .set_link_ksettings = phy_ethtool_set_link_ksettings, 1014 }; 1015 1016 static int ocelot_port_attr_get(struct net_device *dev, 1017 struct switchdev_attr *attr) 1018 { 1019 struct ocelot_port *ocelot_port = netdev_priv(dev); 1020 struct ocelot *ocelot = ocelot_port->ocelot; 1021 1022 switch (attr->id) { 1023 case SWITCHDEV_ATTR_ID_PORT_PARENT_ID: 1024 attr->u.ppid.id_len = sizeof(ocelot->base_mac); 1025 memcpy(&attr->u.ppid.id, &ocelot->base_mac, 1026 attr->u.ppid.id_len); 1027 break; 1028 default: 1029 return -EOPNOTSUPP; 1030 } 1031 1032 return 0; 1033 } 1034 1035 static int ocelot_port_attr_stp_state_set(struct ocelot_port *ocelot_port, 1036 struct switchdev_trans *trans, 1037 u8 state) 1038 { 1039 struct ocelot *ocelot = ocelot_port->ocelot; 1040 u32 port_cfg; 1041 int port, i; 1042 1043 if (switchdev_trans_ph_prepare(trans)) 1044 return 0; 1045 1046 if (!(BIT(ocelot_port->chip_port) & ocelot->bridge_mask)) 1047 return 0; 1048 1049 port_cfg = ocelot_read_gix(ocelot, ANA_PORT_PORT_CFG, 1050 ocelot_port->chip_port); 1051 1052 switch (state) { 1053 case BR_STATE_FORWARDING: 1054 ocelot->bridge_fwd_mask |= BIT(ocelot_port->chip_port); 1055 /* Fallthrough */ 1056 case BR_STATE_LEARNING: 1057 port_cfg |= ANA_PORT_PORT_CFG_LEARN_ENA; 1058 break; 1059 1060 default: 1061 port_cfg &= ~ANA_PORT_PORT_CFG_LEARN_ENA; 1062 ocelot->bridge_fwd_mask &= ~BIT(ocelot_port->chip_port); 1063 break; 1064 } 1065 1066 ocelot_write_gix(ocelot, port_cfg, ANA_PORT_PORT_CFG, 1067 ocelot_port->chip_port); 1068 1069 /* Apply FWD mask. The loop is needed to add/remove the current port as 1070 * a source for the other ports. 1071 */ 1072 for (port = 0; port < ocelot->num_phys_ports; port++) { 1073 if (ocelot->bridge_fwd_mask & BIT(port)) { 1074 unsigned long mask = ocelot->bridge_fwd_mask & ~BIT(port); 1075 1076 for (i = 0; i < ocelot->num_phys_ports; i++) { 1077 unsigned long bond_mask = ocelot->lags[i]; 1078 1079 if (!bond_mask) 1080 continue; 1081 1082 if (bond_mask & BIT(port)) { 1083 mask &= ~bond_mask; 1084 break; 1085 } 1086 } 1087 1088 ocelot_write_rix(ocelot, 1089 BIT(ocelot->num_phys_ports) | mask, 1090 ANA_PGID_PGID, PGID_SRC + port); 1091 } else { 1092 /* Only the CPU port, this is compatible with link 1093 * aggregation. 1094 */ 1095 ocelot_write_rix(ocelot, 1096 BIT(ocelot->num_phys_ports), 1097 ANA_PGID_PGID, PGID_SRC + port); 1098 } 1099 } 1100 1101 return 0; 1102 } 1103 1104 static void ocelot_port_attr_ageing_set(struct ocelot_port *ocelot_port, 1105 unsigned long ageing_clock_t) 1106 { 1107 struct ocelot *ocelot = ocelot_port->ocelot; 1108 unsigned long ageing_jiffies = clock_t_to_jiffies(ageing_clock_t); 1109 u32 ageing_time = jiffies_to_msecs(ageing_jiffies) / 1000; 1110 1111 ocelot_write(ocelot, ANA_AUTOAGE_AGE_PERIOD(ageing_time / 2), 1112 ANA_AUTOAGE); 1113 } 1114 1115 static void ocelot_port_attr_mc_set(struct ocelot_port *port, bool mc) 1116 { 1117 struct ocelot *ocelot = port->ocelot; 1118 u32 val = ocelot_read_gix(ocelot, ANA_PORT_CPU_FWD_CFG, 1119 port->chip_port); 1120 1121 if (mc) 1122 val |= ANA_PORT_CPU_FWD_CFG_CPU_IGMP_REDIR_ENA | 1123 ANA_PORT_CPU_FWD_CFG_CPU_MLD_REDIR_ENA | 1124 ANA_PORT_CPU_FWD_CFG_CPU_IPMC_CTRL_COPY_ENA; 1125 else 1126 val &= ~(ANA_PORT_CPU_FWD_CFG_CPU_IGMP_REDIR_ENA | 1127 ANA_PORT_CPU_FWD_CFG_CPU_MLD_REDIR_ENA | 1128 ANA_PORT_CPU_FWD_CFG_CPU_IPMC_CTRL_COPY_ENA); 1129 1130 ocelot_write_gix(ocelot, val, ANA_PORT_CPU_FWD_CFG, port->chip_port); 1131 } 1132 1133 static int ocelot_port_attr_set(struct net_device *dev, 1134 const struct switchdev_attr *attr, 1135 struct switchdev_trans *trans) 1136 { 1137 struct ocelot_port *ocelot_port = netdev_priv(dev); 1138 int err = 0; 1139 1140 switch (attr->id) { 1141 case SWITCHDEV_ATTR_ID_PORT_STP_STATE: 1142 ocelot_port_attr_stp_state_set(ocelot_port, trans, 1143 attr->u.stp_state); 1144 break; 1145 case SWITCHDEV_ATTR_ID_BRIDGE_AGEING_TIME: 1146 ocelot_port_attr_ageing_set(ocelot_port, attr->u.ageing_time); 1147 break; 1148 case SWITCHDEV_ATTR_ID_BRIDGE_VLAN_FILTERING: 1149 ocelot_port->vlan_aware = attr->u.vlan_filtering; 1150 ocelot_vlan_port_apply(ocelot_port->ocelot, ocelot_port); 1151 break; 1152 case SWITCHDEV_ATTR_ID_BRIDGE_MC_DISABLED: 1153 ocelot_port_attr_mc_set(ocelot_port, !attr->u.mc_disabled); 1154 break; 1155 default: 1156 err = -EOPNOTSUPP; 1157 break; 1158 } 1159 1160 return err; 1161 } 1162 1163 static int ocelot_port_obj_add_vlan(struct net_device *dev, 1164 const struct switchdev_obj_port_vlan *vlan, 1165 struct switchdev_trans *trans) 1166 { 1167 int ret; 1168 u16 vid; 1169 1170 for (vid = vlan->vid_begin; vid <= vlan->vid_end; vid++) { 1171 ret = ocelot_vlan_vid_add(dev, vid, 1172 vlan->flags & BRIDGE_VLAN_INFO_PVID, 1173 vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED); 1174 if (ret) 1175 return ret; 1176 } 1177 1178 return 0; 1179 } 1180 1181 static int ocelot_port_vlan_del_vlan(struct net_device *dev, 1182 const struct switchdev_obj_port_vlan *vlan) 1183 { 1184 int ret; 1185 u16 vid; 1186 1187 for (vid = vlan->vid_begin; vid <= vlan->vid_end; vid++) { 1188 ret = ocelot_vlan_vid_del(dev, vid); 1189 1190 if (ret) 1191 return ret; 1192 } 1193 1194 return 0; 1195 } 1196 1197 static struct ocelot_multicast *ocelot_multicast_get(struct ocelot *ocelot, 1198 const unsigned char *addr, 1199 u16 vid) 1200 { 1201 struct ocelot_multicast *mc; 1202 1203 list_for_each_entry(mc, &ocelot->multicast, list) { 1204 if (ether_addr_equal(mc->addr, addr) && mc->vid == vid) 1205 return mc; 1206 } 1207 1208 return NULL; 1209 } 1210 1211 static int ocelot_port_obj_add_mdb(struct net_device *dev, 1212 const struct switchdev_obj_port_mdb *mdb, 1213 struct switchdev_trans *trans) 1214 { 1215 struct ocelot_port *port = netdev_priv(dev); 1216 struct ocelot *ocelot = port->ocelot; 1217 struct ocelot_multicast *mc; 1218 unsigned char addr[ETH_ALEN]; 1219 u16 vid = mdb->vid; 1220 bool new = false; 1221 1222 if (!vid) 1223 vid = port->pvid; 1224 1225 mc = ocelot_multicast_get(ocelot, mdb->addr, vid); 1226 if (!mc) { 1227 mc = devm_kzalloc(ocelot->dev, sizeof(*mc), GFP_KERNEL); 1228 if (!mc) 1229 return -ENOMEM; 1230 1231 memcpy(mc->addr, mdb->addr, ETH_ALEN); 1232 mc->vid = vid; 1233 1234 list_add_tail(&mc->list, &ocelot->multicast); 1235 new = true; 1236 } 1237 1238 memcpy(addr, mc->addr, ETH_ALEN); 1239 addr[0] = 0; 1240 1241 if (!new) { 1242 addr[2] = mc->ports << 0; 1243 addr[1] = mc->ports << 8; 1244 ocelot_mact_forget(ocelot, addr, vid); 1245 } 1246 1247 mc->ports |= BIT(port->chip_port); 1248 addr[2] = mc->ports << 0; 1249 addr[1] = mc->ports << 8; 1250 1251 return ocelot_mact_learn(ocelot, 0, addr, vid, ENTRYTYPE_MACv4); 1252 } 1253 1254 static int ocelot_port_obj_del_mdb(struct net_device *dev, 1255 const struct switchdev_obj_port_mdb *mdb) 1256 { 1257 struct ocelot_port *port = netdev_priv(dev); 1258 struct ocelot *ocelot = port->ocelot; 1259 struct ocelot_multicast *mc; 1260 unsigned char addr[ETH_ALEN]; 1261 u16 vid = mdb->vid; 1262 1263 if (!vid) 1264 vid = port->pvid; 1265 1266 mc = ocelot_multicast_get(ocelot, mdb->addr, vid); 1267 if (!mc) 1268 return -ENOENT; 1269 1270 memcpy(addr, mc->addr, ETH_ALEN); 1271 addr[2] = mc->ports << 0; 1272 addr[1] = mc->ports << 8; 1273 addr[0] = 0; 1274 ocelot_mact_forget(ocelot, addr, vid); 1275 1276 mc->ports &= ~BIT(port->chip_port); 1277 if (!mc->ports) { 1278 list_del(&mc->list); 1279 devm_kfree(ocelot->dev, mc); 1280 return 0; 1281 } 1282 1283 addr[2] = mc->ports << 0; 1284 addr[1] = mc->ports << 8; 1285 1286 return ocelot_mact_learn(ocelot, 0, addr, vid, ENTRYTYPE_MACv4); 1287 } 1288 1289 static int ocelot_port_obj_add(struct net_device *dev, 1290 const struct switchdev_obj *obj, 1291 struct switchdev_trans *trans) 1292 { 1293 int ret = 0; 1294 1295 switch (obj->id) { 1296 case SWITCHDEV_OBJ_ID_PORT_VLAN: 1297 ret = ocelot_port_obj_add_vlan(dev, 1298 SWITCHDEV_OBJ_PORT_VLAN(obj), 1299 trans); 1300 break; 1301 case SWITCHDEV_OBJ_ID_PORT_MDB: 1302 ret = ocelot_port_obj_add_mdb(dev, SWITCHDEV_OBJ_PORT_MDB(obj), 1303 trans); 1304 break; 1305 default: 1306 return -EOPNOTSUPP; 1307 } 1308 1309 return ret; 1310 } 1311 1312 static int ocelot_port_obj_del(struct net_device *dev, 1313 const struct switchdev_obj *obj) 1314 { 1315 int ret = 0; 1316 1317 switch (obj->id) { 1318 case SWITCHDEV_OBJ_ID_PORT_VLAN: 1319 ret = ocelot_port_vlan_del_vlan(dev, 1320 SWITCHDEV_OBJ_PORT_VLAN(obj)); 1321 break; 1322 case SWITCHDEV_OBJ_ID_PORT_MDB: 1323 ret = ocelot_port_obj_del_mdb(dev, SWITCHDEV_OBJ_PORT_MDB(obj)); 1324 break; 1325 default: 1326 return -EOPNOTSUPP; 1327 } 1328 1329 return ret; 1330 } 1331 1332 static const struct switchdev_ops ocelot_port_switchdev_ops = { 1333 .switchdev_port_attr_get = ocelot_port_attr_get, 1334 .switchdev_port_attr_set = ocelot_port_attr_set, 1335 .switchdev_port_obj_add = ocelot_port_obj_add, 1336 .switchdev_port_obj_del = ocelot_port_obj_del, 1337 }; 1338 1339 static int ocelot_port_bridge_join(struct ocelot_port *ocelot_port, 1340 struct net_device *bridge) 1341 { 1342 struct ocelot *ocelot = ocelot_port->ocelot; 1343 1344 if (!ocelot->bridge_mask) { 1345 ocelot->hw_bridge_dev = bridge; 1346 } else { 1347 if (ocelot->hw_bridge_dev != bridge) 1348 /* This is adding the port to a second bridge, this is 1349 * unsupported */ 1350 return -ENODEV; 1351 } 1352 1353 ocelot->bridge_mask |= BIT(ocelot_port->chip_port); 1354 1355 return 0; 1356 } 1357 1358 static void ocelot_port_bridge_leave(struct ocelot_port *ocelot_port, 1359 struct net_device *bridge) 1360 { 1361 struct ocelot *ocelot = ocelot_port->ocelot; 1362 1363 ocelot->bridge_mask &= ~BIT(ocelot_port->chip_port); 1364 1365 if (!ocelot->bridge_mask) 1366 ocelot->hw_bridge_dev = NULL; 1367 1368 /* Clear bridge vlan settings before calling ocelot_vlan_port_apply */ 1369 ocelot_port->vlan_aware = 0; 1370 ocelot_port->pvid = 0; 1371 ocelot_port->vid = 0; 1372 } 1373 1374 static void ocelot_set_aggr_pgids(struct ocelot *ocelot) 1375 { 1376 int i, port, lag; 1377 1378 /* Reset destination and aggregation PGIDS */ 1379 for (port = 0; port < ocelot->num_phys_ports; port++) 1380 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port); 1381 1382 for (i = PGID_AGGR; i < PGID_SRC; i++) 1383 ocelot_write_rix(ocelot, GENMASK(ocelot->num_phys_ports - 1, 0), 1384 ANA_PGID_PGID, i); 1385 1386 /* Now, set PGIDs for each LAG */ 1387 for (lag = 0; lag < ocelot->num_phys_ports; lag++) { 1388 unsigned long bond_mask; 1389 int aggr_count = 0; 1390 u8 aggr_idx[16]; 1391 1392 bond_mask = ocelot->lags[lag]; 1393 if (!bond_mask) 1394 continue; 1395 1396 for_each_set_bit(port, &bond_mask, ocelot->num_phys_ports) { 1397 // Destination mask 1398 ocelot_write_rix(ocelot, bond_mask, 1399 ANA_PGID_PGID, port); 1400 aggr_idx[aggr_count] = port; 1401 aggr_count++; 1402 } 1403 1404 for (i = PGID_AGGR; i < PGID_SRC; i++) { 1405 u32 ac; 1406 1407 ac = ocelot_read_rix(ocelot, ANA_PGID_PGID, i); 1408 ac &= ~bond_mask; 1409 ac |= BIT(aggr_idx[i % aggr_count]); 1410 ocelot_write_rix(ocelot, ac, ANA_PGID_PGID, i); 1411 } 1412 } 1413 } 1414 1415 static void ocelot_setup_lag(struct ocelot *ocelot, int lag) 1416 { 1417 unsigned long bond_mask = ocelot->lags[lag]; 1418 unsigned int p; 1419 1420 for_each_set_bit(p, &bond_mask, ocelot->num_phys_ports) { 1421 u32 port_cfg = ocelot_read_gix(ocelot, ANA_PORT_PORT_CFG, p); 1422 1423 port_cfg &= ~ANA_PORT_PORT_CFG_PORTID_VAL_M; 1424 1425 /* Use lag port as logical port for port i */ 1426 ocelot_write_gix(ocelot, port_cfg | 1427 ANA_PORT_PORT_CFG_PORTID_VAL(lag), 1428 ANA_PORT_PORT_CFG, p); 1429 } 1430 } 1431 1432 static int ocelot_port_lag_join(struct ocelot_port *ocelot_port, 1433 struct net_device *bond) 1434 { 1435 struct ocelot *ocelot = ocelot_port->ocelot; 1436 int p = ocelot_port->chip_port; 1437 int lag, lp; 1438 struct net_device *ndev; 1439 u32 bond_mask = 0; 1440 1441 rcu_read_lock(); 1442 for_each_netdev_in_bond_rcu(bond, ndev) { 1443 struct ocelot_port *port = netdev_priv(ndev); 1444 1445 bond_mask |= BIT(port->chip_port); 1446 } 1447 rcu_read_unlock(); 1448 1449 lp = __ffs(bond_mask); 1450 1451 /* If the new port is the lowest one, use it as the logical port from 1452 * now on 1453 */ 1454 if (p == lp) { 1455 lag = p; 1456 ocelot->lags[p] = bond_mask; 1457 bond_mask &= ~BIT(p); 1458 if (bond_mask) { 1459 lp = __ffs(bond_mask); 1460 ocelot->lags[lp] = 0; 1461 } 1462 } else { 1463 lag = lp; 1464 ocelot->lags[lp] |= BIT(p); 1465 } 1466 1467 ocelot_setup_lag(ocelot, lag); 1468 ocelot_set_aggr_pgids(ocelot); 1469 1470 return 0; 1471 } 1472 1473 static void ocelot_port_lag_leave(struct ocelot_port *ocelot_port, 1474 struct net_device *bond) 1475 { 1476 struct ocelot *ocelot = ocelot_port->ocelot; 1477 int p = ocelot_port->chip_port; 1478 u32 port_cfg; 1479 int i; 1480 1481 /* Remove port from any lag */ 1482 for (i = 0; i < ocelot->num_phys_ports; i++) 1483 ocelot->lags[i] &= ~BIT(ocelot_port->chip_port); 1484 1485 /* if it was the logical port of the lag, move the lag config to the 1486 * next port 1487 */ 1488 if (ocelot->lags[p]) { 1489 int n = __ffs(ocelot->lags[p]); 1490 1491 ocelot->lags[n] = ocelot->lags[p]; 1492 ocelot->lags[p] = 0; 1493 1494 ocelot_setup_lag(ocelot, n); 1495 } 1496 1497 port_cfg = ocelot_read_gix(ocelot, ANA_PORT_PORT_CFG, p); 1498 port_cfg &= ~ANA_PORT_PORT_CFG_PORTID_VAL_M; 1499 ocelot_write_gix(ocelot, port_cfg | ANA_PORT_PORT_CFG_PORTID_VAL(p), 1500 ANA_PORT_PORT_CFG, p); 1501 1502 ocelot_set_aggr_pgids(ocelot); 1503 } 1504 1505 /* Checks if the net_device instance given to us originate from our driver. */ 1506 static bool ocelot_netdevice_dev_check(const struct net_device *dev) 1507 { 1508 return dev->netdev_ops == &ocelot_port_netdev_ops; 1509 } 1510 1511 static int ocelot_netdevice_port_event(struct net_device *dev, 1512 unsigned long event, 1513 struct netdev_notifier_changeupper_info *info) 1514 { 1515 struct ocelot_port *ocelot_port = netdev_priv(dev); 1516 int err = 0; 1517 1518 if (!ocelot_netdevice_dev_check(dev)) 1519 return 0; 1520 1521 switch (event) { 1522 case NETDEV_CHANGEUPPER: 1523 if (netif_is_bridge_master(info->upper_dev)) { 1524 if (info->linking) 1525 err = ocelot_port_bridge_join(ocelot_port, 1526 info->upper_dev); 1527 else 1528 ocelot_port_bridge_leave(ocelot_port, 1529 info->upper_dev); 1530 1531 ocelot_vlan_port_apply(ocelot_port->ocelot, 1532 ocelot_port); 1533 } 1534 if (netif_is_lag_master(info->upper_dev)) { 1535 if (info->linking) 1536 err = ocelot_port_lag_join(ocelot_port, 1537 info->upper_dev); 1538 else 1539 ocelot_port_lag_leave(ocelot_port, 1540 info->upper_dev); 1541 } 1542 break; 1543 default: 1544 break; 1545 } 1546 1547 return err; 1548 } 1549 1550 static int ocelot_netdevice_event(struct notifier_block *unused, 1551 unsigned long event, void *ptr) 1552 { 1553 struct netdev_notifier_changeupper_info *info = ptr; 1554 struct net_device *dev = netdev_notifier_info_to_dev(ptr); 1555 int ret = 0; 1556 1557 if (event == NETDEV_PRECHANGEUPPER && 1558 netif_is_lag_master(info->upper_dev)) { 1559 struct netdev_lag_upper_info *lag_upper_info = info->upper_info; 1560 struct netlink_ext_ack *extack; 1561 1562 if (lag_upper_info->tx_type != NETDEV_LAG_TX_TYPE_HASH) { 1563 extack = netdev_notifier_info_to_extack(&info->info); 1564 NL_SET_ERR_MSG_MOD(extack, "LAG device using unsupported Tx type"); 1565 1566 ret = -EINVAL; 1567 goto notify; 1568 } 1569 } 1570 1571 if (netif_is_lag_master(dev)) { 1572 struct net_device *slave; 1573 struct list_head *iter; 1574 1575 netdev_for_each_lower_dev(dev, slave, iter) { 1576 ret = ocelot_netdevice_port_event(slave, event, info); 1577 if (ret) 1578 goto notify; 1579 } 1580 } else { 1581 ret = ocelot_netdevice_port_event(dev, event, info); 1582 } 1583 1584 notify: 1585 return notifier_from_errno(ret); 1586 } 1587 1588 struct notifier_block ocelot_netdevice_nb __read_mostly = { 1589 .notifier_call = ocelot_netdevice_event, 1590 }; 1591 EXPORT_SYMBOL(ocelot_netdevice_nb); 1592 1593 int ocelot_probe_port(struct ocelot *ocelot, u8 port, 1594 void __iomem *regs, 1595 struct phy_device *phy) 1596 { 1597 struct ocelot_port *ocelot_port; 1598 struct net_device *dev; 1599 int err; 1600 1601 dev = alloc_etherdev(sizeof(struct ocelot_port)); 1602 if (!dev) 1603 return -ENOMEM; 1604 SET_NETDEV_DEV(dev, ocelot->dev); 1605 ocelot_port = netdev_priv(dev); 1606 ocelot_port->dev = dev; 1607 ocelot_port->ocelot = ocelot; 1608 ocelot_port->regs = regs; 1609 ocelot_port->chip_port = port; 1610 ocelot_port->phy = phy; 1611 INIT_LIST_HEAD(&ocelot_port->mc); 1612 ocelot->ports[port] = ocelot_port; 1613 1614 dev->netdev_ops = &ocelot_port_netdev_ops; 1615 dev->ethtool_ops = &ocelot_ethtool_ops; 1616 dev->switchdev_ops = &ocelot_port_switchdev_ops; 1617 1618 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_RXFCS; 1619 dev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; 1620 1621 memcpy(dev->dev_addr, ocelot->base_mac, ETH_ALEN); 1622 dev->dev_addr[ETH_ALEN - 1] += port; 1623 ocelot_mact_learn(ocelot, PGID_CPU, dev->dev_addr, ocelot_port->pvid, 1624 ENTRYTYPE_LOCKED); 1625 1626 err = register_netdev(dev); 1627 if (err) { 1628 dev_err(ocelot->dev, "register_netdev failed\n"); 1629 goto err_register_netdev; 1630 } 1631 1632 /* Basic L2 initialization */ 1633 ocelot_vlan_port_apply(ocelot, ocelot_port); 1634 1635 return 0; 1636 1637 err_register_netdev: 1638 free_netdev(dev); 1639 return err; 1640 } 1641 EXPORT_SYMBOL(ocelot_probe_port); 1642 1643 int ocelot_init(struct ocelot *ocelot) 1644 { 1645 u32 port; 1646 int i, cpu = ocelot->num_phys_ports; 1647 char queue_name[32]; 1648 1649 ocelot->lags = devm_kcalloc(ocelot->dev, ocelot->num_phys_ports, 1650 sizeof(u32), GFP_KERNEL); 1651 if (!ocelot->lags) 1652 return -ENOMEM; 1653 1654 ocelot->stats = devm_kcalloc(ocelot->dev, 1655 ocelot->num_phys_ports * ocelot->num_stats, 1656 sizeof(u64), GFP_KERNEL); 1657 if (!ocelot->stats) 1658 return -ENOMEM; 1659 1660 mutex_init(&ocelot->stats_lock); 1661 snprintf(queue_name, sizeof(queue_name), "%s-stats", 1662 dev_name(ocelot->dev)); 1663 ocelot->stats_queue = create_singlethread_workqueue(queue_name); 1664 if (!ocelot->stats_queue) 1665 return -ENOMEM; 1666 1667 ocelot_mact_init(ocelot); 1668 ocelot_vlan_init(ocelot); 1669 1670 for (port = 0; port < ocelot->num_phys_ports; port++) { 1671 /* Clear all counters (5 groups) */ 1672 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(port) | 1673 SYS_STAT_CFG_STAT_CLEAR_SHOT(0x7f), 1674 SYS_STAT_CFG); 1675 } 1676 1677 /* Only use S-Tag */ 1678 ocelot_write(ocelot, ETH_P_8021AD, SYS_VLAN_ETYPE_CFG); 1679 1680 /* Aggregation mode */ 1681 ocelot_write(ocelot, ANA_AGGR_CFG_AC_SMAC_ENA | 1682 ANA_AGGR_CFG_AC_DMAC_ENA | 1683 ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA | 1684 ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA, ANA_AGGR_CFG); 1685 1686 /* Set MAC age time to default value. The entry is aged after 1687 * 2*AGE_PERIOD 1688 */ 1689 ocelot_write(ocelot, 1690 ANA_AUTOAGE_AGE_PERIOD(BR_DEFAULT_AGEING_TIME / 2 / HZ), 1691 ANA_AUTOAGE); 1692 1693 /* Disable learning for frames discarded by VLAN ingress filtering */ 1694 regmap_field_write(ocelot->regfields[ANA_ADVLEARN_VLAN_CHK], 1); 1695 1696 /* Setup frame ageing - fixed value "2 sec" - in 6.5 us units */ 1697 ocelot_write(ocelot, SYS_FRM_AGING_AGE_TX_ENA | 1698 SYS_FRM_AGING_MAX_AGE(307692), SYS_FRM_AGING); 1699 1700 /* Setup flooding PGIDs */ 1701 ocelot_write_rix(ocelot, ANA_FLOODING_FLD_MULTICAST(PGID_MC) | 1702 ANA_FLOODING_FLD_BROADCAST(PGID_MC) | 1703 ANA_FLOODING_FLD_UNICAST(PGID_UC), 1704 ANA_FLOODING, 0); 1705 ocelot_write(ocelot, ANA_FLOODING_IPMC_FLD_MC6_DATA(PGID_MCIPV6) | 1706 ANA_FLOODING_IPMC_FLD_MC6_CTRL(PGID_MC) | 1707 ANA_FLOODING_IPMC_FLD_MC4_DATA(PGID_MCIPV4) | 1708 ANA_FLOODING_IPMC_FLD_MC4_CTRL(PGID_MC), 1709 ANA_FLOODING_IPMC); 1710 1711 for (port = 0; port < ocelot->num_phys_ports; port++) { 1712 /* Transmit the frame to the local port. */ 1713 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port); 1714 /* Do not forward BPDU frames to the front ports. */ 1715 ocelot_write_gix(ocelot, 1716 ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA(0xffff), 1717 ANA_PORT_CPU_FWD_BPDU_CFG, 1718 port); 1719 /* Ensure bridging is disabled */ 1720 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_SRC + port); 1721 } 1722 1723 /* Configure and enable the CPU port. */ 1724 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, cpu); 1725 ocelot_write_rix(ocelot, BIT(cpu), ANA_PGID_PGID, PGID_CPU); 1726 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_RECV_ENA | 1727 ANA_PORT_PORT_CFG_PORTID_VAL(cpu), 1728 ANA_PORT_PORT_CFG, cpu); 1729 1730 /* Allow broadcast MAC frames. */ 1731 for (i = ocelot->num_phys_ports + 1; i < PGID_CPU; i++) { 1732 u32 val = ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports - 1, 0)); 1733 1734 ocelot_write_rix(ocelot, val, ANA_PGID_PGID, i); 1735 } 1736 ocelot_write_rix(ocelot, 1737 ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports, 0)), 1738 ANA_PGID_PGID, PGID_MC); 1739 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV4); 1740 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV6); 1741 1742 /* CPU port Injection/Extraction configuration */ 1743 ocelot_write_rix(ocelot, QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE | 1744 QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG(1) | 1745 QSYS_SWITCH_PORT_MODE_PORT_ENA, 1746 QSYS_SWITCH_PORT_MODE, cpu); 1747 ocelot_write_rix(ocelot, SYS_PORT_MODE_INCL_XTR_HDR(1) | 1748 SYS_PORT_MODE_INCL_INJ_HDR(1), SYS_PORT_MODE, cpu); 1749 /* Allow manual injection via DEVCPU_QS registers, and byte swap these 1750 * registers endianness. 1751 */ 1752 ocelot_write_rix(ocelot, QS_INJ_GRP_CFG_BYTE_SWAP | 1753 QS_INJ_GRP_CFG_MODE(1), QS_INJ_GRP_CFG, 0); 1754 ocelot_write_rix(ocelot, QS_XTR_GRP_CFG_BYTE_SWAP | 1755 QS_XTR_GRP_CFG_MODE(1), QS_XTR_GRP_CFG, 0); 1756 ocelot_write(ocelot, ANA_CPUQ_CFG_CPUQ_MIRROR(2) | 1757 ANA_CPUQ_CFG_CPUQ_LRN(2) | 1758 ANA_CPUQ_CFG_CPUQ_MAC_COPY(2) | 1759 ANA_CPUQ_CFG_CPUQ_SRC_COPY(2) | 1760 ANA_CPUQ_CFG_CPUQ_LOCKED_PORTMOVE(2) | 1761 ANA_CPUQ_CFG_CPUQ_ALLBRIDGE(6) | 1762 ANA_CPUQ_CFG_CPUQ_IPMC_CTRL(6) | 1763 ANA_CPUQ_CFG_CPUQ_IGMP(6) | 1764 ANA_CPUQ_CFG_CPUQ_MLD(6), ANA_CPUQ_CFG); 1765 for (i = 0; i < 16; i++) 1766 ocelot_write_rix(ocelot, ANA_CPUQ_8021_CFG_CPUQ_GARP_VAL(6) | 1767 ANA_CPUQ_8021_CFG_CPUQ_BPDU_VAL(6), 1768 ANA_CPUQ_8021_CFG, i); 1769 1770 INIT_DELAYED_WORK(&ocelot->stats_work, ocelot_check_stats); 1771 queue_delayed_work(ocelot->stats_queue, &ocelot->stats_work, 1772 OCELOT_STATS_CHECK_DELAY); 1773 return 0; 1774 } 1775 EXPORT_SYMBOL(ocelot_init); 1776 1777 void ocelot_deinit(struct ocelot *ocelot) 1778 { 1779 destroy_workqueue(ocelot->stats_queue); 1780 mutex_destroy(&ocelot->stats_lock); 1781 } 1782 EXPORT_SYMBOL(ocelot_deinit); 1783 1784 MODULE_LICENSE("Dual MIT/GPL"); 1785