1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* 3 * Microsemi Ocelot Switch driver 4 * 5 * Copyright (c) 2017 Microsemi Corporation 6 */ 7 #include <linux/dsa/ocelot.h> 8 #include <linux/if_bridge.h> 9 #include <linux/iopoll.h> 10 #include <linux/phy/phy.h> 11 #include <net/pkt_sched.h> 12 #include <soc/mscc/ocelot_hsio.h> 13 #include <soc/mscc/ocelot_vcap.h> 14 #include "ocelot.h" 15 #include "ocelot_vcap.h" 16 17 #define TABLE_UPDATE_SLEEP_US 10 18 #define TABLE_UPDATE_TIMEOUT_US 100000 19 #define MEM_INIT_SLEEP_US 1000 20 #define MEM_INIT_TIMEOUT_US 100000 21 22 #define OCELOT_RSV_VLAN_RANGE_START 4000 23 24 struct ocelot_mact_entry { 25 u8 mac[ETH_ALEN]; 26 u16 vid; 27 enum macaccess_entry_type type; 28 }; 29 30 /* Caller must hold &ocelot->mact_lock */ 31 static inline u32 ocelot_mact_read_macaccess(struct ocelot *ocelot) 32 { 33 return ocelot_read(ocelot, ANA_TABLES_MACACCESS); 34 } 35 36 /* Caller must hold &ocelot->mact_lock */ 37 static inline int ocelot_mact_wait_for_completion(struct ocelot *ocelot) 38 { 39 u32 val; 40 41 return readx_poll_timeout(ocelot_mact_read_macaccess, 42 ocelot, val, 43 (val & ANA_TABLES_MACACCESS_MAC_TABLE_CMD_M) == 44 MACACCESS_CMD_IDLE, 45 TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US); 46 } 47 48 /* Caller must hold &ocelot->mact_lock */ 49 static void ocelot_mact_select(struct ocelot *ocelot, 50 const unsigned char mac[ETH_ALEN], 51 unsigned int vid) 52 { 53 u32 macl = 0, mach = 0; 54 55 /* Set the MAC address to handle and the vlan associated in a format 56 * understood by the hardware. 57 */ 58 mach |= vid << 16; 59 mach |= mac[0] << 8; 60 mach |= mac[1] << 0; 61 macl |= mac[2] << 24; 62 macl |= mac[3] << 16; 63 macl |= mac[4] << 8; 64 macl |= mac[5] << 0; 65 66 ocelot_write(ocelot, macl, ANA_TABLES_MACLDATA); 67 ocelot_write(ocelot, mach, ANA_TABLES_MACHDATA); 68 69 } 70 71 static int __ocelot_mact_learn(struct ocelot *ocelot, int port, 72 const unsigned char mac[ETH_ALEN], 73 unsigned int vid, enum macaccess_entry_type type) 74 { 75 u32 cmd = ANA_TABLES_MACACCESS_VALID | 76 ANA_TABLES_MACACCESS_DEST_IDX(port) | 77 ANA_TABLES_MACACCESS_ENTRYTYPE(type) | 78 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_LEARN); 79 unsigned int mc_ports; 80 int err; 81 82 /* Set MAC_CPU_COPY if the CPU port is used by a multicast entry */ 83 if (type == ENTRYTYPE_MACv4) 84 mc_ports = (mac[1] << 8) | mac[2]; 85 else if (type == ENTRYTYPE_MACv6) 86 mc_ports = (mac[0] << 8) | mac[1]; 87 else 88 mc_ports = 0; 89 90 if (mc_ports & BIT(ocelot->num_phys_ports)) 91 cmd |= ANA_TABLES_MACACCESS_MAC_CPU_COPY; 92 93 ocelot_mact_select(ocelot, mac, vid); 94 95 /* Issue a write command */ 96 ocelot_write(ocelot, cmd, ANA_TABLES_MACACCESS); 97 98 err = ocelot_mact_wait_for_completion(ocelot); 99 100 return err; 101 } 102 103 int ocelot_mact_learn(struct ocelot *ocelot, int port, 104 const unsigned char mac[ETH_ALEN], 105 unsigned int vid, enum macaccess_entry_type type) 106 { 107 int ret; 108 109 mutex_lock(&ocelot->mact_lock); 110 ret = __ocelot_mact_learn(ocelot, port, mac, vid, type); 111 mutex_unlock(&ocelot->mact_lock); 112 113 return ret; 114 } 115 EXPORT_SYMBOL(ocelot_mact_learn); 116 117 int ocelot_mact_forget(struct ocelot *ocelot, 118 const unsigned char mac[ETH_ALEN], unsigned int vid) 119 { 120 int err; 121 122 mutex_lock(&ocelot->mact_lock); 123 124 ocelot_mact_select(ocelot, mac, vid); 125 126 /* Issue a forget command */ 127 ocelot_write(ocelot, 128 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_FORGET), 129 ANA_TABLES_MACACCESS); 130 131 err = ocelot_mact_wait_for_completion(ocelot); 132 133 mutex_unlock(&ocelot->mact_lock); 134 135 return err; 136 } 137 EXPORT_SYMBOL(ocelot_mact_forget); 138 139 int ocelot_mact_lookup(struct ocelot *ocelot, int *dst_idx, 140 const unsigned char mac[ETH_ALEN], 141 unsigned int vid, enum macaccess_entry_type *type) 142 { 143 int val; 144 145 mutex_lock(&ocelot->mact_lock); 146 147 ocelot_mact_select(ocelot, mac, vid); 148 149 /* Issue a read command with MACACCESS_VALID=1. */ 150 ocelot_write(ocelot, ANA_TABLES_MACACCESS_VALID | 151 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_READ), 152 ANA_TABLES_MACACCESS); 153 154 if (ocelot_mact_wait_for_completion(ocelot)) { 155 mutex_unlock(&ocelot->mact_lock); 156 return -ETIMEDOUT; 157 } 158 159 /* Read back the entry flags */ 160 val = ocelot_read(ocelot, ANA_TABLES_MACACCESS); 161 162 mutex_unlock(&ocelot->mact_lock); 163 164 if (!(val & ANA_TABLES_MACACCESS_VALID)) 165 return -ENOENT; 166 167 *dst_idx = ANA_TABLES_MACACCESS_DEST_IDX_X(val); 168 *type = ANA_TABLES_MACACCESS_ENTRYTYPE_X(val); 169 170 return 0; 171 } 172 EXPORT_SYMBOL(ocelot_mact_lookup); 173 174 int ocelot_mact_learn_streamdata(struct ocelot *ocelot, int dst_idx, 175 const unsigned char mac[ETH_ALEN], 176 unsigned int vid, 177 enum macaccess_entry_type type, 178 int sfid, int ssid) 179 { 180 int ret; 181 182 mutex_lock(&ocelot->mact_lock); 183 184 ocelot_write(ocelot, 185 (sfid < 0 ? 0 : ANA_TABLES_STREAMDATA_SFID_VALID) | 186 ANA_TABLES_STREAMDATA_SFID(sfid) | 187 (ssid < 0 ? 0 : ANA_TABLES_STREAMDATA_SSID_VALID) | 188 ANA_TABLES_STREAMDATA_SSID(ssid), 189 ANA_TABLES_STREAMDATA); 190 191 ret = __ocelot_mact_learn(ocelot, dst_idx, mac, vid, type); 192 193 mutex_unlock(&ocelot->mact_lock); 194 195 return ret; 196 } 197 EXPORT_SYMBOL(ocelot_mact_learn_streamdata); 198 199 static void ocelot_mact_init(struct ocelot *ocelot) 200 { 201 /* Configure the learning mode entries attributes: 202 * - Do not copy the frame to the CPU extraction queues. 203 * - Use the vlan and mac_cpoy for dmac lookup. 204 */ 205 ocelot_rmw(ocelot, 0, 206 ANA_AGENCTRL_LEARN_CPU_COPY | ANA_AGENCTRL_IGNORE_DMAC_FLAGS 207 | ANA_AGENCTRL_LEARN_FWD_KILL 208 | ANA_AGENCTRL_LEARN_IGNORE_VLAN, 209 ANA_AGENCTRL); 210 211 /* Clear the MAC table. We are not concurrent with anyone, so 212 * holding &ocelot->mact_lock is pointless. 213 */ 214 ocelot_write(ocelot, MACACCESS_CMD_INIT, ANA_TABLES_MACACCESS); 215 } 216 217 void ocelot_pll5_init(struct ocelot *ocelot) 218 { 219 /* Configure PLL5. This will need a proper CCF driver 220 * The values are coming from the VTSS API for Ocelot 221 */ 222 regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG4, 223 HSIO_PLL5G_CFG4_IB_CTRL(0x7600) | 224 HSIO_PLL5G_CFG4_IB_BIAS_CTRL(0x8)); 225 regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG0, 226 HSIO_PLL5G_CFG0_CORE_CLK_DIV(0x11) | 227 HSIO_PLL5G_CFG0_CPU_CLK_DIV(2) | 228 HSIO_PLL5G_CFG0_ENA_BIAS | 229 HSIO_PLL5G_CFG0_ENA_VCO_BUF | 230 HSIO_PLL5G_CFG0_ENA_CP1 | 231 HSIO_PLL5G_CFG0_SELCPI(2) | 232 HSIO_PLL5G_CFG0_LOOP_BW_RES(0xe) | 233 HSIO_PLL5G_CFG0_SELBGV820(4) | 234 HSIO_PLL5G_CFG0_DIV4 | 235 HSIO_PLL5G_CFG0_ENA_CLKTREE | 236 HSIO_PLL5G_CFG0_ENA_LANE); 237 regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG2, 238 HSIO_PLL5G_CFG2_EN_RESET_FRQ_DET | 239 HSIO_PLL5G_CFG2_EN_RESET_OVERRUN | 240 HSIO_PLL5G_CFG2_GAIN_TEST(0x8) | 241 HSIO_PLL5G_CFG2_ENA_AMPCTRL | 242 HSIO_PLL5G_CFG2_PWD_AMPCTRL_N | 243 HSIO_PLL5G_CFG2_AMPC_SEL(0x10)); 244 } 245 EXPORT_SYMBOL(ocelot_pll5_init); 246 247 static void ocelot_vcap_enable(struct ocelot *ocelot, int port) 248 { 249 ocelot_write_gix(ocelot, ANA_PORT_VCAP_S2_CFG_S2_ENA | 250 ANA_PORT_VCAP_S2_CFG_S2_IP6_CFG(0xa), 251 ANA_PORT_VCAP_S2_CFG, port); 252 253 ocelot_write_gix(ocelot, ANA_PORT_VCAP_CFG_S1_ENA, 254 ANA_PORT_VCAP_CFG, port); 255 256 ocelot_rmw_gix(ocelot, REW_PORT_CFG_ES0_EN, 257 REW_PORT_CFG_ES0_EN, 258 REW_PORT_CFG, port); 259 } 260 261 static int ocelot_single_vlan_aware_bridge(struct ocelot *ocelot, 262 struct netlink_ext_ack *extack) 263 { 264 struct net_device *bridge = NULL; 265 int port; 266 267 for (port = 0; port < ocelot->num_phys_ports; port++) { 268 struct ocelot_port *ocelot_port = ocelot->ports[port]; 269 270 if (!ocelot_port || !ocelot_port->bridge || 271 !br_vlan_enabled(ocelot_port->bridge)) 272 continue; 273 274 if (!bridge) { 275 bridge = ocelot_port->bridge; 276 continue; 277 } 278 279 if (bridge == ocelot_port->bridge) 280 continue; 281 282 NL_SET_ERR_MSG_MOD(extack, 283 "Only one VLAN-aware bridge is supported"); 284 return -EBUSY; 285 } 286 287 return 0; 288 } 289 290 static inline u32 ocelot_vlant_read_vlanaccess(struct ocelot *ocelot) 291 { 292 return ocelot_read(ocelot, ANA_TABLES_VLANACCESS); 293 } 294 295 static inline int ocelot_vlant_wait_for_completion(struct ocelot *ocelot) 296 { 297 u32 val; 298 299 return readx_poll_timeout(ocelot_vlant_read_vlanaccess, 300 ocelot, 301 val, 302 (val & ANA_TABLES_VLANACCESS_VLAN_TBL_CMD_M) == 303 ANA_TABLES_VLANACCESS_CMD_IDLE, 304 TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US); 305 } 306 307 static int ocelot_vlant_set_mask(struct ocelot *ocelot, u16 vid, u32 mask) 308 { 309 /* Select the VID to configure */ 310 ocelot_write(ocelot, ANA_TABLES_VLANTIDX_V_INDEX(vid), 311 ANA_TABLES_VLANTIDX); 312 /* Set the vlan port members mask and issue a write command */ 313 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_VLAN_PORT_MASK(mask) | 314 ANA_TABLES_VLANACCESS_CMD_WRITE, 315 ANA_TABLES_VLANACCESS); 316 317 return ocelot_vlant_wait_for_completion(ocelot); 318 } 319 320 static int ocelot_port_num_untagged_vlans(struct ocelot *ocelot, int port) 321 { 322 struct ocelot_bridge_vlan *vlan; 323 int num_untagged = 0; 324 325 list_for_each_entry(vlan, &ocelot->vlans, list) { 326 if (!(vlan->portmask & BIT(port))) 327 continue; 328 329 /* Ignore the VLAN added by ocelot_add_vlan_unaware_pvid(), 330 * because this is never active in hardware at the same time as 331 * the bridge VLANs, which only matter in VLAN-aware mode. 332 */ 333 if (vlan->vid >= OCELOT_RSV_VLAN_RANGE_START) 334 continue; 335 336 if (vlan->untagged & BIT(port)) 337 num_untagged++; 338 } 339 340 return num_untagged; 341 } 342 343 static int ocelot_port_num_tagged_vlans(struct ocelot *ocelot, int port) 344 { 345 struct ocelot_bridge_vlan *vlan; 346 int num_tagged = 0; 347 348 list_for_each_entry(vlan, &ocelot->vlans, list) { 349 if (!(vlan->portmask & BIT(port))) 350 continue; 351 352 if (!(vlan->untagged & BIT(port))) 353 num_tagged++; 354 } 355 356 return num_tagged; 357 } 358 359 /* We use native VLAN when we have to mix egress-tagged VLANs with exactly 360 * _one_ egress-untagged VLAN (_the_ native VLAN) 361 */ 362 static bool ocelot_port_uses_native_vlan(struct ocelot *ocelot, int port) 363 { 364 return ocelot_port_num_tagged_vlans(ocelot, port) && 365 ocelot_port_num_untagged_vlans(ocelot, port) == 1; 366 } 367 368 static struct ocelot_bridge_vlan * 369 ocelot_port_find_native_vlan(struct ocelot *ocelot, int port) 370 { 371 struct ocelot_bridge_vlan *vlan; 372 373 list_for_each_entry(vlan, &ocelot->vlans, list) 374 if (vlan->portmask & BIT(port) && vlan->untagged & BIT(port)) 375 return vlan; 376 377 return NULL; 378 } 379 380 /* Keep in sync REW_TAG_CFG_TAG_CFG and, if applicable, 381 * REW_PORT_VLAN_CFG_PORT_VID, with the bridge VLAN table and VLAN awareness 382 * state of the port. 383 */ 384 static void ocelot_port_manage_port_tag(struct ocelot *ocelot, int port) 385 { 386 struct ocelot_port *ocelot_port = ocelot->ports[port]; 387 enum ocelot_port_tag_config tag_cfg; 388 bool uses_native_vlan = false; 389 390 if (ocelot_port->vlan_aware) { 391 uses_native_vlan = ocelot_port_uses_native_vlan(ocelot, port); 392 393 if (uses_native_vlan) 394 tag_cfg = OCELOT_PORT_TAG_NATIVE; 395 else if (ocelot_port_num_untagged_vlans(ocelot, port)) 396 tag_cfg = OCELOT_PORT_TAG_DISABLED; 397 else 398 tag_cfg = OCELOT_PORT_TAG_TRUNK; 399 } else { 400 tag_cfg = OCELOT_PORT_TAG_DISABLED; 401 } 402 403 ocelot_rmw_gix(ocelot, REW_TAG_CFG_TAG_CFG(tag_cfg), 404 REW_TAG_CFG_TAG_CFG_M, 405 REW_TAG_CFG, port); 406 407 if (uses_native_vlan) { 408 struct ocelot_bridge_vlan *native_vlan; 409 410 /* Not having a native VLAN is impossible, because 411 * ocelot_port_num_untagged_vlans has returned 1. 412 * So there is no use in checking for NULL here. 413 */ 414 native_vlan = ocelot_port_find_native_vlan(ocelot, port); 415 416 ocelot_rmw_gix(ocelot, 417 REW_PORT_VLAN_CFG_PORT_VID(native_vlan->vid), 418 REW_PORT_VLAN_CFG_PORT_VID_M, 419 REW_PORT_VLAN_CFG, port); 420 } 421 } 422 423 int ocelot_bridge_num_find(struct ocelot *ocelot, 424 const struct net_device *bridge) 425 { 426 int port; 427 428 for (port = 0; port < ocelot->num_phys_ports; port++) { 429 struct ocelot_port *ocelot_port = ocelot->ports[port]; 430 431 if (ocelot_port && ocelot_port->bridge == bridge) 432 return ocelot_port->bridge_num; 433 } 434 435 return -1; 436 } 437 EXPORT_SYMBOL_GPL(ocelot_bridge_num_find); 438 439 static u16 ocelot_vlan_unaware_pvid(struct ocelot *ocelot, 440 const struct net_device *bridge) 441 { 442 int bridge_num; 443 444 /* Standalone ports use VID 0 */ 445 if (!bridge) 446 return 0; 447 448 bridge_num = ocelot_bridge_num_find(ocelot, bridge); 449 if (WARN_ON(bridge_num < 0)) 450 return 0; 451 452 /* VLAN-unaware bridges use a reserved VID going from 4095 downwards */ 453 return VLAN_N_VID - bridge_num - 1; 454 } 455 456 /* Default vlan to clasify for untagged frames (may be zero) */ 457 static void ocelot_port_set_pvid(struct ocelot *ocelot, int port, 458 const struct ocelot_bridge_vlan *pvid_vlan) 459 { 460 struct ocelot_port *ocelot_port = ocelot->ports[port]; 461 u16 pvid = ocelot_vlan_unaware_pvid(ocelot, ocelot_port->bridge); 462 u32 val = 0; 463 464 ocelot_port->pvid_vlan = pvid_vlan; 465 466 if (ocelot_port->vlan_aware && pvid_vlan) 467 pvid = pvid_vlan->vid; 468 469 ocelot_rmw_gix(ocelot, 470 ANA_PORT_VLAN_CFG_VLAN_VID(pvid), 471 ANA_PORT_VLAN_CFG_VLAN_VID_M, 472 ANA_PORT_VLAN_CFG, port); 473 474 /* If there's no pvid, we should drop not only untagged traffic (which 475 * happens automatically), but also 802.1p traffic which gets 476 * classified to VLAN 0, but that is always in our RX filter, so it 477 * would get accepted were it not for this setting. 478 */ 479 if (!pvid_vlan && ocelot_port->vlan_aware) 480 val = ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA | 481 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA; 482 483 ocelot_rmw_gix(ocelot, val, 484 ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA | 485 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA, 486 ANA_PORT_DROP_CFG, port); 487 } 488 489 static struct ocelot_bridge_vlan *ocelot_bridge_vlan_find(struct ocelot *ocelot, 490 u16 vid) 491 { 492 struct ocelot_bridge_vlan *vlan; 493 494 list_for_each_entry(vlan, &ocelot->vlans, list) 495 if (vlan->vid == vid) 496 return vlan; 497 498 return NULL; 499 } 500 501 static int ocelot_vlan_member_add(struct ocelot *ocelot, int port, u16 vid, 502 bool untagged) 503 { 504 struct ocelot_bridge_vlan *vlan = ocelot_bridge_vlan_find(ocelot, vid); 505 unsigned long portmask; 506 int err; 507 508 if (vlan) { 509 portmask = vlan->portmask | BIT(port); 510 511 err = ocelot_vlant_set_mask(ocelot, vid, portmask); 512 if (err) 513 return err; 514 515 vlan->portmask = portmask; 516 /* Bridge VLANs can be overwritten with a different 517 * egress-tagging setting, so make sure to override an untagged 518 * with a tagged VID if that's going on. 519 */ 520 if (untagged) 521 vlan->untagged |= BIT(port); 522 else 523 vlan->untagged &= ~BIT(port); 524 525 return 0; 526 } 527 528 vlan = kzalloc(sizeof(*vlan), GFP_KERNEL); 529 if (!vlan) 530 return -ENOMEM; 531 532 portmask = BIT(port); 533 534 err = ocelot_vlant_set_mask(ocelot, vid, portmask); 535 if (err) { 536 kfree(vlan); 537 return err; 538 } 539 540 vlan->vid = vid; 541 vlan->portmask = portmask; 542 if (untagged) 543 vlan->untagged = BIT(port); 544 INIT_LIST_HEAD(&vlan->list); 545 list_add_tail(&vlan->list, &ocelot->vlans); 546 547 return 0; 548 } 549 550 static int ocelot_vlan_member_del(struct ocelot *ocelot, int port, u16 vid) 551 { 552 struct ocelot_bridge_vlan *vlan = ocelot_bridge_vlan_find(ocelot, vid); 553 unsigned long portmask; 554 int err; 555 556 if (!vlan) 557 return 0; 558 559 portmask = vlan->portmask & ~BIT(port); 560 561 err = ocelot_vlant_set_mask(ocelot, vid, portmask); 562 if (err) 563 return err; 564 565 vlan->portmask = portmask; 566 if (vlan->portmask) 567 return 0; 568 569 list_del(&vlan->list); 570 kfree(vlan); 571 572 return 0; 573 } 574 575 static int ocelot_add_vlan_unaware_pvid(struct ocelot *ocelot, int port, 576 const struct net_device *bridge) 577 { 578 u16 vid = ocelot_vlan_unaware_pvid(ocelot, bridge); 579 580 return ocelot_vlan_member_add(ocelot, port, vid, true); 581 } 582 583 static int ocelot_del_vlan_unaware_pvid(struct ocelot *ocelot, int port, 584 const struct net_device *bridge) 585 { 586 u16 vid = ocelot_vlan_unaware_pvid(ocelot, bridge); 587 588 return ocelot_vlan_member_del(ocelot, port, vid); 589 } 590 591 int ocelot_port_vlan_filtering(struct ocelot *ocelot, int port, 592 bool vlan_aware, struct netlink_ext_ack *extack) 593 { 594 struct ocelot_vcap_block *block = &ocelot->block[VCAP_IS1]; 595 struct ocelot_port *ocelot_port = ocelot->ports[port]; 596 struct ocelot_vcap_filter *filter; 597 int err = 0; 598 u32 val; 599 600 list_for_each_entry(filter, &block->rules, list) { 601 if (filter->ingress_port_mask & BIT(port) && 602 filter->action.vid_replace_ena) { 603 NL_SET_ERR_MSG_MOD(extack, 604 "Cannot change VLAN state with vlan modify rules active"); 605 return -EBUSY; 606 } 607 } 608 609 err = ocelot_single_vlan_aware_bridge(ocelot, extack); 610 if (err) 611 return err; 612 613 if (vlan_aware) 614 err = ocelot_del_vlan_unaware_pvid(ocelot, port, 615 ocelot_port->bridge); 616 else if (ocelot_port->bridge) 617 err = ocelot_add_vlan_unaware_pvid(ocelot, port, 618 ocelot_port->bridge); 619 if (err) 620 return err; 621 622 ocelot_port->vlan_aware = vlan_aware; 623 624 if (vlan_aware) 625 val = ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 626 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1); 627 else 628 val = 0; 629 ocelot_rmw_gix(ocelot, val, 630 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 631 ANA_PORT_VLAN_CFG_VLAN_POP_CNT_M, 632 ANA_PORT_VLAN_CFG, port); 633 634 ocelot_port_set_pvid(ocelot, port, ocelot_port->pvid_vlan); 635 ocelot_port_manage_port_tag(ocelot, port); 636 637 return 0; 638 } 639 EXPORT_SYMBOL(ocelot_port_vlan_filtering); 640 641 int ocelot_vlan_prepare(struct ocelot *ocelot, int port, u16 vid, bool pvid, 642 bool untagged, struct netlink_ext_ack *extack) 643 { 644 if (untagged) { 645 /* We are adding an egress-tagged VLAN */ 646 if (ocelot_port_uses_native_vlan(ocelot, port)) { 647 NL_SET_ERR_MSG_MOD(extack, 648 "Port with egress-tagged VLANs cannot have more than one egress-untagged (native) VLAN"); 649 return -EBUSY; 650 } 651 } else { 652 /* We are adding an egress-tagged VLAN */ 653 if (ocelot_port_num_untagged_vlans(ocelot, port) > 1) { 654 NL_SET_ERR_MSG_MOD(extack, 655 "Port with more than one egress-untagged VLAN cannot have egress-tagged VLANs"); 656 return -EBUSY; 657 } 658 } 659 660 if (vid > OCELOT_RSV_VLAN_RANGE_START) { 661 NL_SET_ERR_MSG_MOD(extack, 662 "VLAN range 4000-4095 reserved for VLAN-unaware bridging"); 663 return -EBUSY; 664 } 665 666 return 0; 667 } 668 EXPORT_SYMBOL(ocelot_vlan_prepare); 669 670 int ocelot_vlan_add(struct ocelot *ocelot, int port, u16 vid, bool pvid, 671 bool untagged) 672 { 673 int err; 674 675 /* Ignore VID 0 added to our RX filter by the 8021q module, since 676 * that collides with OCELOT_STANDALONE_PVID and changes it from 677 * egress-untagged to egress-tagged. 678 */ 679 if (!vid) 680 return 0; 681 682 err = ocelot_vlan_member_add(ocelot, port, vid, untagged); 683 if (err) 684 return err; 685 686 /* Default ingress vlan classification */ 687 if (pvid) 688 ocelot_port_set_pvid(ocelot, port, 689 ocelot_bridge_vlan_find(ocelot, vid)); 690 691 /* Untagged egress vlan clasification */ 692 ocelot_port_manage_port_tag(ocelot, port); 693 694 return 0; 695 } 696 EXPORT_SYMBOL(ocelot_vlan_add); 697 698 int ocelot_vlan_del(struct ocelot *ocelot, int port, u16 vid) 699 { 700 struct ocelot_port *ocelot_port = ocelot->ports[port]; 701 bool del_pvid = false; 702 int err; 703 704 if (!vid) 705 return 0; 706 707 if (ocelot_port->pvid_vlan && ocelot_port->pvid_vlan->vid == vid) 708 del_pvid = true; 709 710 err = ocelot_vlan_member_del(ocelot, port, vid); 711 if (err) 712 return err; 713 714 /* Ingress */ 715 if (del_pvid) 716 ocelot_port_set_pvid(ocelot, port, NULL); 717 718 /* Egress */ 719 ocelot_port_manage_port_tag(ocelot, port); 720 721 return 0; 722 } 723 EXPORT_SYMBOL(ocelot_vlan_del); 724 725 static void ocelot_vlan_init(struct ocelot *ocelot) 726 { 727 unsigned long all_ports = GENMASK(ocelot->num_phys_ports - 1, 0); 728 u16 port, vid; 729 730 /* Clear VLAN table, by default all ports are members of all VLANs */ 731 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_CMD_INIT, 732 ANA_TABLES_VLANACCESS); 733 ocelot_vlant_wait_for_completion(ocelot); 734 735 /* Configure the port VLAN memberships */ 736 for (vid = 1; vid < VLAN_N_VID; vid++) 737 ocelot_vlant_set_mask(ocelot, vid, 0); 738 739 /* We need VID 0 to get traffic on standalone ports. 740 * It is added automatically if the 8021q module is loaded, but we 741 * can't rely on that since it might not be. 742 */ 743 ocelot_vlant_set_mask(ocelot, OCELOT_STANDALONE_PVID, all_ports); 744 745 /* Set vlan ingress filter mask to all ports but the CPU port by 746 * default. 747 */ 748 ocelot_write(ocelot, all_ports, ANA_VLANMASK); 749 750 for (port = 0; port < ocelot->num_phys_ports; port++) { 751 ocelot_write_gix(ocelot, 0, REW_PORT_VLAN_CFG, port); 752 ocelot_write_gix(ocelot, 0, REW_TAG_CFG, port); 753 } 754 } 755 756 static u32 ocelot_read_eq_avail(struct ocelot *ocelot, int port) 757 { 758 return ocelot_read_rix(ocelot, QSYS_SW_STATUS, port); 759 } 760 761 static int ocelot_port_flush(struct ocelot *ocelot, int port) 762 { 763 unsigned int pause_ena; 764 int err, val; 765 766 /* Disable dequeuing from the egress queues */ 767 ocelot_rmw_rix(ocelot, QSYS_PORT_MODE_DEQUEUE_DIS, 768 QSYS_PORT_MODE_DEQUEUE_DIS, 769 QSYS_PORT_MODE, port); 770 771 /* Disable flow control */ 772 ocelot_fields_read(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, &pause_ena); 773 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, 0); 774 775 /* Disable priority flow control */ 776 ocelot_fields_write(ocelot, port, 777 QSYS_SWITCH_PORT_MODE_TX_PFC_ENA, 0); 778 779 /* Wait at least the time it takes to receive a frame of maximum length 780 * at the port. 781 * Worst-case delays for 10 kilobyte jumbo frames are: 782 * 8 ms on a 10M port 783 * 800 μs on a 100M port 784 * 80 μs on a 1G port 785 * 32 μs on a 2.5G port 786 */ 787 usleep_range(8000, 10000); 788 789 /* Disable half duplex backpressure. */ 790 ocelot_rmw_rix(ocelot, 0, SYS_FRONT_PORT_MODE_HDX_MODE, 791 SYS_FRONT_PORT_MODE, port); 792 793 /* Flush the queues associated with the port. */ 794 ocelot_rmw_gix(ocelot, REW_PORT_CFG_FLUSH_ENA, REW_PORT_CFG_FLUSH_ENA, 795 REW_PORT_CFG, port); 796 797 /* Enable dequeuing from the egress queues. */ 798 ocelot_rmw_rix(ocelot, 0, QSYS_PORT_MODE_DEQUEUE_DIS, QSYS_PORT_MODE, 799 port); 800 801 /* Wait until flushing is complete. */ 802 err = read_poll_timeout(ocelot_read_eq_avail, val, !val, 803 100, 2000000, false, ocelot, port); 804 805 /* Clear flushing again. */ 806 ocelot_rmw_gix(ocelot, 0, REW_PORT_CFG_FLUSH_ENA, REW_PORT_CFG, port); 807 808 /* Re-enable flow control */ 809 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, pause_ena); 810 811 return err; 812 } 813 814 int ocelot_port_configure_serdes(struct ocelot *ocelot, int port, 815 struct device_node *portnp) 816 { 817 struct ocelot_port *ocelot_port = ocelot->ports[port]; 818 struct device *dev = ocelot->dev; 819 int err; 820 821 /* Ensure clock signals and speed are set on all QSGMII links */ 822 if (ocelot_port->phy_mode == PHY_INTERFACE_MODE_QSGMII) 823 ocelot_port_rmwl(ocelot_port, 0, 824 DEV_CLOCK_CFG_MAC_TX_RST | 825 DEV_CLOCK_CFG_MAC_RX_RST, 826 DEV_CLOCK_CFG); 827 828 if (ocelot_port->phy_mode != PHY_INTERFACE_MODE_INTERNAL) { 829 struct phy *serdes = of_phy_get(portnp, NULL); 830 831 if (IS_ERR(serdes)) { 832 err = PTR_ERR(serdes); 833 dev_err_probe(dev, err, 834 "missing SerDes phys for port %d\n", 835 port); 836 return err; 837 } 838 839 err = phy_set_mode_ext(serdes, PHY_MODE_ETHERNET, 840 ocelot_port->phy_mode); 841 of_phy_put(serdes); 842 if (err) { 843 dev_err(dev, "Could not SerDes mode on port %d: %pe\n", 844 port, ERR_PTR(err)); 845 return err; 846 } 847 } 848 849 return 0; 850 } 851 EXPORT_SYMBOL_GPL(ocelot_port_configure_serdes); 852 853 void ocelot_phylink_mac_config(struct ocelot *ocelot, int port, 854 unsigned int link_an_mode, 855 const struct phylink_link_state *state) 856 { 857 struct ocelot_port *ocelot_port = ocelot->ports[port]; 858 859 /* Disable HDX fast control */ 860 ocelot_port_writel(ocelot_port, DEV_PORT_MISC_HDX_FAST_DIS, 861 DEV_PORT_MISC); 862 863 /* SGMII only for now */ 864 ocelot_port_writel(ocelot_port, PCS1G_MODE_CFG_SGMII_MODE_ENA, 865 PCS1G_MODE_CFG); 866 ocelot_port_writel(ocelot_port, PCS1G_SD_CFG_SD_SEL, PCS1G_SD_CFG); 867 868 /* Enable PCS */ 869 ocelot_port_writel(ocelot_port, PCS1G_CFG_PCS_ENA, PCS1G_CFG); 870 871 /* No aneg on SGMII */ 872 ocelot_port_writel(ocelot_port, 0, PCS1G_ANEG_CFG); 873 874 /* No loopback */ 875 ocelot_port_writel(ocelot_port, 0, PCS1G_LB_CFG); 876 } 877 EXPORT_SYMBOL_GPL(ocelot_phylink_mac_config); 878 879 void ocelot_phylink_mac_link_down(struct ocelot *ocelot, int port, 880 unsigned int link_an_mode, 881 phy_interface_t interface, 882 unsigned long quirks) 883 { 884 struct ocelot_port *ocelot_port = ocelot->ports[port]; 885 int err; 886 887 ocelot_port->speed = SPEED_UNKNOWN; 888 889 ocelot_port_rmwl(ocelot_port, 0, DEV_MAC_ENA_CFG_RX_ENA, 890 DEV_MAC_ENA_CFG); 891 892 if (ocelot->ops->cut_through_fwd) { 893 mutex_lock(&ocelot->fwd_domain_lock); 894 ocelot->ops->cut_through_fwd(ocelot); 895 mutex_unlock(&ocelot->fwd_domain_lock); 896 } 897 898 ocelot_fields_write(ocelot, port, QSYS_SWITCH_PORT_MODE_PORT_ENA, 0); 899 900 err = ocelot_port_flush(ocelot, port); 901 if (err) 902 dev_err(ocelot->dev, "failed to flush port %d: %d\n", 903 port, err); 904 905 /* Put the port in reset. */ 906 if (interface != PHY_INTERFACE_MODE_QSGMII || 907 !(quirks & OCELOT_QUIRK_QSGMII_PORTS_MUST_BE_UP)) 908 ocelot_port_rmwl(ocelot_port, 909 DEV_CLOCK_CFG_MAC_TX_RST | 910 DEV_CLOCK_CFG_MAC_RX_RST, 911 DEV_CLOCK_CFG_MAC_TX_RST | 912 DEV_CLOCK_CFG_MAC_RX_RST, 913 DEV_CLOCK_CFG); 914 } 915 EXPORT_SYMBOL_GPL(ocelot_phylink_mac_link_down); 916 917 void ocelot_phylink_mac_link_up(struct ocelot *ocelot, int port, 918 struct phy_device *phydev, 919 unsigned int link_an_mode, 920 phy_interface_t interface, 921 int speed, int duplex, 922 bool tx_pause, bool rx_pause, 923 unsigned long quirks) 924 { 925 struct ocelot_port *ocelot_port = ocelot->ports[port]; 926 int mac_speed, mode = 0; 927 u32 mac_fc_cfg; 928 929 ocelot_port->speed = speed; 930 931 /* The MAC might be integrated in systems where the MAC speed is fixed 932 * and it's the PCS who is performing the rate adaptation, so we have 933 * to write "1000Mbps" into the LINK_SPEED field of DEV_CLOCK_CFG 934 * (which is also its default value). 935 */ 936 if ((quirks & OCELOT_QUIRK_PCS_PERFORMS_RATE_ADAPTATION) || 937 speed == SPEED_1000) { 938 mac_speed = OCELOT_SPEED_1000; 939 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA; 940 } else if (speed == SPEED_2500) { 941 mac_speed = OCELOT_SPEED_2500; 942 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA; 943 } else if (speed == SPEED_100) { 944 mac_speed = OCELOT_SPEED_100; 945 } else { 946 mac_speed = OCELOT_SPEED_10; 947 } 948 949 if (duplex == DUPLEX_FULL) 950 mode |= DEV_MAC_MODE_CFG_FDX_ENA; 951 952 ocelot_port_writel(ocelot_port, mode, DEV_MAC_MODE_CFG); 953 954 /* Take port out of reset by clearing the MAC_TX_RST, MAC_RX_RST and 955 * PORT_RST bits in DEV_CLOCK_CFG. 956 */ 957 ocelot_port_writel(ocelot_port, DEV_CLOCK_CFG_LINK_SPEED(mac_speed), 958 DEV_CLOCK_CFG); 959 960 switch (speed) { 961 case SPEED_10: 962 mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(OCELOT_SPEED_10); 963 break; 964 case SPEED_100: 965 mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(OCELOT_SPEED_100); 966 break; 967 case SPEED_1000: 968 case SPEED_2500: 969 mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(OCELOT_SPEED_1000); 970 break; 971 default: 972 dev_err(ocelot->dev, "Unsupported speed on port %d: %d\n", 973 port, speed); 974 return; 975 } 976 977 if (rx_pause) 978 mac_fc_cfg |= SYS_MAC_FC_CFG_RX_FC_ENA; 979 980 if (tx_pause) 981 mac_fc_cfg |= SYS_MAC_FC_CFG_TX_FC_ENA | 982 SYS_MAC_FC_CFG_PAUSE_VAL_CFG(0xffff) | 983 SYS_MAC_FC_CFG_FC_LATENCY_CFG(0x7) | 984 SYS_MAC_FC_CFG_ZERO_PAUSE_ENA; 985 986 /* Flow control. Link speed is only used here to evaluate the time 987 * specification in incoming pause frames. 988 */ 989 ocelot_write_rix(ocelot, mac_fc_cfg, SYS_MAC_FC_CFG, port); 990 991 ocelot_write_rix(ocelot, 0, ANA_POL_FLOWC, port); 992 993 /* Don't attempt to send PAUSE frames on the NPI port, it's broken */ 994 if (port != ocelot->npi) 995 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, 996 tx_pause); 997 998 /* Undo the effects of ocelot_phylink_mac_link_down: 999 * enable MAC module 1000 */ 1001 ocelot_port_writel(ocelot_port, DEV_MAC_ENA_CFG_RX_ENA | 1002 DEV_MAC_ENA_CFG_TX_ENA, DEV_MAC_ENA_CFG); 1003 1004 /* If the port supports cut-through forwarding, update the masks before 1005 * enabling forwarding on the port. 1006 */ 1007 if (ocelot->ops->cut_through_fwd) { 1008 mutex_lock(&ocelot->fwd_domain_lock); 1009 ocelot->ops->cut_through_fwd(ocelot); 1010 mutex_unlock(&ocelot->fwd_domain_lock); 1011 } 1012 1013 /* Core: Enable port for frame transfer */ 1014 ocelot_fields_write(ocelot, port, 1015 QSYS_SWITCH_PORT_MODE_PORT_ENA, 1); 1016 } 1017 EXPORT_SYMBOL_GPL(ocelot_phylink_mac_link_up); 1018 1019 static int ocelot_rx_frame_word(struct ocelot *ocelot, u8 grp, bool ifh, 1020 u32 *rval) 1021 { 1022 u32 bytes_valid, val; 1023 1024 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 1025 if (val == XTR_NOT_READY) { 1026 if (ifh) 1027 return -EIO; 1028 1029 do { 1030 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 1031 } while (val == XTR_NOT_READY); 1032 } 1033 1034 switch (val) { 1035 case XTR_ABORT: 1036 return -EIO; 1037 case XTR_EOF_0: 1038 case XTR_EOF_1: 1039 case XTR_EOF_2: 1040 case XTR_EOF_3: 1041 case XTR_PRUNED: 1042 bytes_valid = XTR_VALID_BYTES(val); 1043 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 1044 if (val == XTR_ESCAPE) 1045 *rval = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 1046 else 1047 *rval = val; 1048 1049 return bytes_valid; 1050 case XTR_ESCAPE: 1051 *rval = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 1052 1053 return 4; 1054 default: 1055 *rval = val; 1056 1057 return 4; 1058 } 1059 } 1060 1061 static int ocelot_xtr_poll_xfh(struct ocelot *ocelot, int grp, u32 *xfh) 1062 { 1063 int i, err = 0; 1064 1065 for (i = 0; i < OCELOT_TAG_LEN / 4; i++) { 1066 err = ocelot_rx_frame_word(ocelot, grp, true, &xfh[i]); 1067 if (err != 4) 1068 return (err < 0) ? err : -EIO; 1069 } 1070 1071 return 0; 1072 } 1073 1074 void ocelot_ptp_rx_timestamp(struct ocelot *ocelot, struct sk_buff *skb, 1075 u64 timestamp) 1076 { 1077 struct skb_shared_hwtstamps *shhwtstamps; 1078 u64 tod_in_ns, full_ts_in_ns; 1079 struct timespec64 ts; 1080 1081 ocelot_ptp_gettime64(&ocelot->ptp_info, &ts); 1082 1083 tod_in_ns = ktime_set(ts.tv_sec, ts.tv_nsec); 1084 if ((tod_in_ns & 0xffffffff) < timestamp) 1085 full_ts_in_ns = (((tod_in_ns >> 32) - 1) << 32) | 1086 timestamp; 1087 else 1088 full_ts_in_ns = (tod_in_ns & GENMASK_ULL(63, 32)) | 1089 timestamp; 1090 1091 shhwtstamps = skb_hwtstamps(skb); 1092 memset(shhwtstamps, 0, sizeof(struct skb_shared_hwtstamps)); 1093 shhwtstamps->hwtstamp = full_ts_in_ns; 1094 } 1095 EXPORT_SYMBOL(ocelot_ptp_rx_timestamp); 1096 1097 int ocelot_xtr_poll_frame(struct ocelot *ocelot, int grp, struct sk_buff **nskb) 1098 { 1099 u64 timestamp, src_port, len; 1100 u32 xfh[OCELOT_TAG_LEN / 4]; 1101 struct net_device *dev; 1102 struct sk_buff *skb; 1103 int sz, buf_len; 1104 u32 val, *buf; 1105 int err; 1106 1107 err = ocelot_xtr_poll_xfh(ocelot, grp, xfh); 1108 if (err) 1109 return err; 1110 1111 ocelot_xfh_get_src_port(xfh, &src_port); 1112 ocelot_xfh_get_len(xfh, &len); 1113 ocelot_xfh_get_rew_val(xfh, ×tamp); 1114 1115 if (WARN_ON(src_port >= ocelot->num_phys_ports)) 1116 return -EINVAL; 1117 1118 dev = ocelot->ops->port_to_netdev(ocelot, src_port); 1119 if (!dev) 1120 return -EINVAL; 1121 1122 skb = netdev_alloc_skb(dev, len); 1123 if (unlikely(!skb)) { 1124 netdev_err(dev, "Unable to allocate sk_buff\n"); 1125 return -ENOMEM; 1126 } 1127 1128 buf_len = len - ETH_FCS_LEN; 1129 buf = (u32 *)skb_put(skb, buf_len); 1130 1131 len = 0; 1132 do { 1133 sz = ocelot_rx_frame_word(ocelot, grp, false, &val); 1134 if (sz < 0) { 1135 err = sz; 1136 goto out_free_skb; 1137 } 1138 *buf++ = val; 1139 len += sz; 1140 } while (len < buf_len); 1141 1142 /* Read the FCS */ 1143 sz = ocelot_rx_frame_word(ocelot, grp, false, &val); 1144 if (sz < 0) { 1145 err = sz; 1146 goto out_free_skb; 1147 } 1148 1149 /* Update the statistics if part of the FCS was read before */ 1150 len -= ETH_FCS_LEN - sz; 1151 1152 if (unlikely(dev->features & NETIF_F_RXFCS)) { 1153 buf = (u32 *)skb_put(skb, ETH_FCS_LEN); 1154 *buf = val; 1155 } 1156 1157 if (ocelot->ptp) 1158 ocelot_ptp_rx_timestamp(ocelot, skb, timestamp); 1159 1160 /* Everything we see on an interface that is in the HW bridge 1161 * has already been forwarded. 1162 */ 1163 if (ocelot->ports[src_port]->bridge) 1164 skb->offload_fwd_mark = 1; 1165 1166 skb->protocol = eth_type_trans(skb, dev); 1167 1168 *nskb = skb; 1169 1170 return 0; 1171 1172 out_free_skb: 1173 kfree_skb(skb); 1174 return err; 1175 } 1176 EXPORT_SYMBOL(ocelot_xtr_poll_frame); 1177 1178 bool ocelot_can_inject(struct ocelot *ocelot, int grp) 1179 { 1180 u32 val = ocelot_read(ocelot, QS_INJ_STATUS); 1181 1182 if (!(val & QS_INJ_STATUS_FIFO_RDY(BIT(grp)))) 1183 return false; 1184 if (val & QS_INJ_STATUS_WMARK_REACHED(BIT(grp))) 1185 return false; 1186 1187 return true; 1188 } 1189 EXPORT_SYMBOL(ocelot_can_inject); 1190 1191 void ocelot_ifh_port_set(void *ifh, int port, u32 rew_op, u32 vlan_tag) 1192 { 1193 ocelot_ifh_set_bypass(ifh, 1); 1194 ocelot_ifh_set_dest(ifh, BIT_ULL(port)); 1195 ocelot_ifh_set_tag_type(ifh, IFH_TAG_TYPE_C); 1196 if (vlan_tag) 1197 ocelot_ifh_set_vlan_tci(ifh, vlan_tag); 1198 if (rew_op) 1199 ocelot_ifh_set_rew_op(ifh, rew_op); 1200 } 1201 EXPORT_SYMBOL(ocelot_ifh_port_set); 1202 1203 void ocelot_port_inject_frame(struct ocelot *ocelot, int port, int grp, 1204 u32 rew_op, struct sk_buff *skb) 1205 { 1206 u32 ifh[OCELOT_TAG_LEN / 4] = {0}; 1207 unsigned int i, count, last; 1208 1209 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) | 1210 QS_INJ_CTRL_SOF, QS_INJ_CTRL, grp); 1211 1212 ocelot_ifh_port_set(ifh, port, rew_op, skb_vlan_tag_get(skb)); 1213 1214 for (i = 0; i < OCELOT_TAG_LEN / 4; i++) 1215 ocelot_write_rix(ocelot, ifh[i], QS_INJ_WR, grp); 1216 1217 count = DIV_ROUND_UP(skb->len, 4); 1218 last = skb->len % 4; 1219 for (i = 0; i < count; i++) 1220 ocelot_write_rix(ocelot, ((u32 *)skb->data)[i], QS_INJ_WR, grp); 1221 1222 /* Add padding */ 1223 while (i < (OCELOT_BUFFER_CELL_SZ / 4)) { 1224 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp); 1225 i++; 1226 } 1227 1228 /* Indicate EOF and valid bytes in last word */ 1229 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) | 1230 QS_INJ_CTRL_VLD_BYTES(skb->len < OCELOT_BUFFER_CELL_SZ ? 0 : last) | 1231 QS_INJ_CTRL_EOF, 1232 QS_INJ_CTRL, grp); 1233 1234 /* Add dummy CRC */ 1235 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp); 1236 skb_tx_timestamp(skb); 1237 1238 skb->dev->stats.tx_packets++; 1239 skb->dev->stats.tx_bytes += skb->len; 1240 } 1241 EXPORT_SYMBOL(ocelot_port_inject_frame); 1242 1243 void ocelot_drain_cpu_queue(struct ocelot *ocelot, int grp) 1244 { 1245 while (ocelot_read(ocelot, QS_XTR_DATA_PRESENT) & BIT(grp)) 1246 ocelot_read_rix(ocelot, QS_XTR_RD, grp); 1247 } 1248 EXPORT_SYMBOL(ocelot_drain_cpu_queue); 1249 1250 int ocelot_fdb_add(struct ocelot *ocelot, int port, const unsigned char *addr, 1251 u16 vid, const struct net_device *bridge) 1252 { 1253 if (!vid) 1254 vid = ocelot_vlan_unaware_pvid(ocelot, bridge); 1255 1256 return ocelot_mact_learn(ocelot, port, addr, vid, ENTRYTYPE_LOCKED); 1257 } 1258 EXPORT_SYMBOL(ocelot_fdb_add); 1259 1260 int ocelot_fdb_del(struct ocelot *ocelot, int port, const unsigned char *addr, 1261 u16 vid, const struct net_device *bridge) 1262 { 1263 if (!vid) 1264 vid = ocelot_vlan_unaware_pvid(ocelot, bridge); 1265 1266 return ocelot_mact_forget(ocelot, addr, vid); 1267 } 1268 EXPORT_SYMBOL(ocelot_fdb_del); 1269 1270 /* Caller must hold &ocelot->mact_lock */ 1271 static int ocelot_mact_read(struct ocelot *ocelot, int port, int row, int col, 1272 struct ocelot_mact_entry *entry) 1273 { 1274 u32 val, dst, macl, mach; 1275 char mac[ETH_ALEN]; 1276 1277 /* Set row and column to read from */ 1278 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_M_INDEX, row); 1279 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_BUCKET, col); 1280 1281 /* Issue a read command */ 1282 ocelot_write(ocelot, 1283 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_READ), 1284 ANA_TABLES_MACACCESS); 1285 1286 if (ocelot_mact_wait_for_completion(ocelot)) 1287 return -ETIMEDOUT; 1288 1289 /* Read the entry flags */ 1290 val = ocelot_read(ocelot, ANA_TABLES_MACACCESS); 1291 if (!(val & ANA_TABLES_MACACCESS_VALID)) 1292 return -EINVAL; 1293 1294 /* If the entry read has another port configured as its destination, 1295 * do not report it. 1296 */ 1297 dst = (val & ANA_TABLES_MACACCESS_DEST_IDX_M) >> 3; 1298 if (dst != port) 1299 return -EINVAL; 1300 1301 /* Get the entry's MAC address and VLAN id */ 1302 macl = ocelot_read(ocelot, ANA_TABLES_MACLDATA); 1303 mach = ocelot_read(ocelot, ANA_TABLES_MACHDATA); 1304 1305 mac[0] = (mach >> 8) & 0xff; 1306 mac[1] = (mach >> 0) & 0xff; 1307 mac[2] = (macl >> 24) & 0xff; 1308 mac[3] = (macl >> 16) & 0xff; 1309 mac[4] = (macl >> 8) & 0xff; 1310 mac[5] = (macl >> 0) & 0xff; 1311 1312 entry->vid = (mach >> 16) & 0xfff; 1313 ether_addr_copy(entry->mac, mac); 1314 1315 return 0; 1316 } 1317 1318 int ocelot_mact_flush(struct ocelot *ocelot, int port) 1319 { 1320 int err; 1321 1322 mutex_lock(&ocelot->mact_lock); 1323 1324 /* Program ageing filter for a single port */ 1325 ocelot_write(ocelot, ANA_ANAGEFIL_PID_EN | ANA_ANAGEFIL_PID_VAL(port), 1326 ANA_ANAGEFIL); 1327 1328 /* Flushing dynamic FDB entries requires two successive age scans */ 1329 ocelot_write(ocelot, 1330 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_AGE), 1331 ANA_TABLES_MACACCESS); 1332 1333 err = ocelot_mact_wait_for_completion(ocelot); 1334 if (err) { 1335 mutex_unlock(&ocelot->mact_lock); 1336 return err; 1337 } 1338 1339 /* And second... */ 1340 ocelot_write(ocelot, 1341 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_AGE), 1342 ANA_TABLES_MACACCESS); 1343 1344 err = ocelot_mact_wait_for_completion(ocelot); 1345 1346 /* Restore ageing filter */ 1347 ocelot_write(ocelot, 0, ANA_ANAGEFIL); 1348 1349 mutex_unlock(&ocelot->mact_lock); 1350 1351 return err; 1352 } 1353 EXPORT_SYMBOL_GPL(ocelot_mact_flush); 1354 1355 int ocelot_fdb_dump(struct ocelot *ocelot, int port, 1356 dsa_fdb_dump_cb_t *cb, void *data) 1357 { 1358 int err = 0; 1359 int i, j; 1360 1361 /* We could take the lock just around ocelot_mact_read, but doing so 1362 * thousands of times in a row seems rather pointless and inefficient. 1363 */ 1364 mutex_lock(&ocelot->mact_lock); 1365 1366 /* Loop through all the mac tables entries. */ 1367 for (i = 0; i < ocelot->num_mact_rows; i++) { 1368 for (j = 0; j < 4; j++) { 1369 struct ocelot_mact_entry entry; 1370 bool is_static; 1371 1372 err = ocelot_mact_read(ocelot, port, i, j, &entry); 1373 /* If the entry is invalid (wrong port, invalid...), 1374 * skip it. 1375 */ 1376 if (err == -EINVAL) 1377 continue; 1378 else if (err) 1379 break; 1380 1381 is_static = (entry.type == ENTRYTYPE_LOCKED); 1382 1383 /* Hide the reserved VLANs used for 1384 * VLAN-unaware bridging. 1385 */ 1386 if (entry.vid > OCELOT_RSV_VLAN_RANGE_START) 1387 entry.vid = 0; 1388 1389 err = cb(entry.mac, entry.vid, is_static, data); 1390 if (err) 1391 break; 1392 } 1393 } 1394 1395 mutex_unlock(&ocelot->mact_lock); 1396 1397 return err; 1398 } 1399 EXPORT_SYMBOL(ocelot_fdb_dump); 1400 1401 int ocelot_trap_add(struct ocelot *ocelot, int port, 1402 unsigned long cookie, bool take_ts, 1403 void (*populate)(struct ocelot_vcap_filter *f)) 1404 { 1405 struct ocelot_vcap_block *block_vcap_is2; 1406 struct ocelot_vcap_filter *trap; 1407 bool new = false; 1408 int err; 1409 1410 block_vcap_is2 = &ocelot->block[VCAP_IS2]; 1411 1412 trap = ocelot_vcap_block_find_filter_by_id(block_vcap_is2, cookie, 1413 false); 1414 if (!trap) { 1415 trap = kzalloc(sizeof(*trap), GFP_KERNEL); 1416 if (!trap) 1417 return -ENOMEM; 1418 1419 populate(trap); 1420 trap->prio = 1; 1421 trap->id.cookie = cookie; 1422 trap->id.tc_offload = false; 1423 trap->block_id = VCAP_IS2; 1424 trap->type = OCELOT_VCAP_FILTER_OFFLOAD; 1425 trap->lookup = 0; 1426 trap->action.cpu_copy_ena = true; 1427 trap->action.mask_mode = OCELOT_MASK_MODE_PERMIT_DENY; 1428 trap->action.port_mask = 0; 1429 trap->take_ts = take_ts; 1430 trap->is_trap = true; 1431 new = true; 1432 } 1433 1434 trap->ingress_port_mask |= BIT(port); 1435 1436 if (new) 1437 err = ocelot_vcap_filter_add(ocelot, trap, NULL); 1438 else 1439 err = ocelot_vcap_filter_replace(ocelot, trap); 1440 if (err) { 1441 trap->ingress_port_mask &= ~BIT(port); 1442 if (!trap->ingress_port_mask) 1443 kfree(trap); 1444 return err; 1445 } 1446 1447 return 0; 1448 } 1449 1450 int ocelot_trap_del(struct ocelot *ocelot, int port, unsigned long cookie) 1451 { 1452 struct ocelot_vcap_block *block_vcap_is2; 1453 struct ocelot_vcap_filter *trap; 1454 1455 block_vcap_is2 = &ocelot->block[VCAP_IS2]; 1456 1457 trap = ocelot_vcap_block_find_filter_by_id(block_vcap_is2, cookie, 1458 false); 1459 if (!trap) 1460 return 0; 1461 1462 trap->ingress_port_mask &= ~BIT(port); 1463 if (!trap->ingress_port_mask) 1464 return ocelot_vcap_filter_del(ocelot, trap); 1465 1466 return ocelot_vcap_filter_replace(ocelot, trap); 1467 } 1468 1469 static u32 ocelot_get_bond_mask(struct ocelot *ocelot, struct net_device *bond) 1470 { 1471 u32 mask = 0; 1472 int port; 1473 1474 lockdep_assert_held(&ocelot->fwd_domain_lock); 1475 1476 for (port = 0; port < ocelot->num_phys_ports; port++) { 1477 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1478 1479 if (!ocelot_port) 1480 continue; 1481 1482 if (ocelot_port->bond == bond) 1483 mask |= BIT(port); 1484 } 1485 1486 return mask; 1487 } 1488 1489 /* The logical port number of a LAG is equal to the lowest numbered physical 1490 * port ID present in that LAG. It may change if that port ever leaves the LAG. 1491 */ 1492 int ocelot_bond_get_id(struct ocelot *ocelot, struct net_device *bond) 1493 { 1494 int bond_mask = ocelot_get_bond_mask(ocelot, bond); 1495 1496 if (!bond_mask) 1497 return -ENOENT; 1498 1499 return __ffs(bond_mask); 1500 } 1501 EXPORT_SYMBOL_GPL(ocelot_bond_get_id); 1502 1503 /* Returns the mask of user ports assigned to this DSA tag_8021q CPU port. 1504 * Note that when CPU ports are in a LAG, the user ports are assigned to the 1505 * 'primary' CPU port, the one whose physical port number gives the logical 1506 * port number of the LAG. 1507 * 1508 * We leave PGID_SRC poorly configured for the 'secondary' CPU port in the LAG 1509 * (to which no user port is assigned), but it appears that forwarding from 1510 * this secondary CPU port looks at the PGID_SRC associated with the logical 1511 * port ID that it's assigned to, which *is* configured properly. 1512 */ 1513 static u32 ocelot_dsa_8021q_cpu_assigned_ports(struct ocelot *ocelot, 1514 struct ocelot_port *cpu) 1515 { 1516 u32 mask = 0; 1517 int port; 1518 1519 for (port = 0; port < ocelot->num_phys_ports; port++) { 1520 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1521 1522 if (!ocelot_port) 1523 continue; 1524 1525 if (ocelot_port->dsa_8021q_cpu == cpu) 1526 mask |= BIT(port); 1527 } 1528 1529 if (cpu->bond) 1530 mask &= ~ocelot_get_bond_mask(ocelot, cpu->bond); 1531 1532 return mask; 1533 } 1534 1535 /* Returns the DSA tag_8021q CPU port that the given port is assigned to, 1536 * or the bit mask of CPU ports if said CPU port is in a LAG. 1537 */ 1538 u32 ocelot_port_assigned_dsa_8021q_cpu_mask(struct ocelot *ocelot, int port) 1539 { 1540 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1541 struct ocelot_port *cpu_port = ocelot_port->dsa_8021q_cpu; 1542 1543 if (!cpu_port) 1544 return 0; 1545 1546 if (cpu_port->bond) 1547 return ocelot_get_bond_mask(ocelot, cpu_port->bond); 1548 1549 return BIT(cpu_port->index); 1550 } 1551 EXPORT_SYMBOL_GPL(ocelot_port_assigned_dsa_8021q_cpu_mask); 1552 1553 u32 ocelot_get_bridge_fwd_mask(struct ocelot *ocelot, int src_port) 1554 { 1555 struct ocelot_port *ocelot_port = ocelot->ports[src_port]; 1556 const struct net_device *bridge; 1557 u32 mask = 0; 1558 int port; 1559 1560 if (!ocelot_port || ocelot_port->stp_state != BR_STATE_FORWARDING) 1561 return 0; 1562 1563 bridge = ocelot_port->bridge; 1564 if (!bridge) 1565 return 0; 1566 1567 for (port = 0; port < ocelot->num_phys_ports; port++) { 1568 ocelot_port = ocelot->ports[port]; 1569 1570 if (!ocelot_port) 1571 continue; 1572 1573 if (ocelot_port->stp_state == BR_STATE_FORWARDING && 1574 ocelot_port->bridge == bridge) 1575 mask |= BIT(port); 1576 } 1577 1578 return mask; 1579 } 1580 EXPORT_SYMBOL_GPL(ocelot_get_bridge_fwd_mask); 1581 1582 static void ocelot_apply_bridge_fwd_mask(struct ocelot *ocelot, bool joining) 1583 { 1584 int port; 1585 1586 lockdep_assert_held(&ocelot->fwd_domain_lock); 1587 1588 /* If cut-through forwarding is supported, update the masks before a 1589 * port joins the forwarding domain, to avoid potential underruns if it 1590 * has the highest speed from the new domain. 1591 */ 1592 if (joining && ocelot->ops->cut_through_fwd) 1593 ocelot->ops->cut_through_fwd(ocelot); 1594 1595 /* Apply FWD mask. The loop is needed to add/remove the current port as 1596 * a source for the other ports. 1597 */ 1598 for (port = 0; port < ocelot->num_phys_ports; port++) { 1599 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1600 unsigned long mask; 1601 1602 if (!ocelot_port) { 1603 /* Unused ports can't send anywhere */ 1604 mask = 0; 1605 } else if (ocelot_port->is_dsa_8021q_cpu) { 1606 /* The DSA tag_8021q CPU ports need to be able to 1607 * forward packets to all ports assigned to them. 1608 */ 1609 mask = ocelot_dsa_8021q_cpu_assigned_ports(ocelot, 1610 ocelot_port); 1611 } else if (ocelot_port->bridge) { 1612 struct net_device *bond = ocelot_port->bond; 1613 1614 mask = ocelot_get_bridge_fwd_mask(ocelot, port); 1615 mask &= ~BIT(port); 1616 1617 mask |= ocelot_port_assigned_dsa_8021q_cpu_mask(ocelot, 1618 port); 1619 1620 if (bond) 1621 mask &= ~ocelot_get_bond_mask(ocelot, bond); 1622 } else { 1623 /* Standalone ports forward only to DSA tag_8021q CPU 1624 * ports (if those exist), or to the hardware CPU port 1625 * module otherwise. 1626 */ 1627 mask = ocelot_port_assigned_dsa_8021q_cpu_mask(ocelot, 1628 port); 1629 } 1630 1631 ocelot_write_rix(ocelot, mask, ANA_PGID_PGID, PGID_SRC + port); 1632 } 1633 1634 /* If cut-through forwarding is supported and a port is leaving, there 1635 * is a chance that cut-through was disabled on the other ports due to 1636 * the port which is leaving (it has a higher link speed). We need to 1637 * update the cut-through masks of the remaining ports no earlier than 1638 * after the port has left, to prevent underruns from happening between 1639 * the cut-through update and the forwarding domain update. 1640 */ 1641 if (!joining && ocelot->ops->cut_through_fwd) 1642 ocelot->ops->cut_through_fwd(ocelot); 1643 } 1644 1645 /* Update PGID_CPU which is the destination port mask used for whitelisting 1646 * unicast addresses filtered towards the host. In the normal and NPI modes, 1647 * this points to the analyzer entry for the CPU port module, while in DSA 1648 * tag_8021q mode, it is a bit mask of all active CPU ports. 1649 * PGID_SRC will take care of forwarding a packet from one user port to 1650 * no more than a single CPU port. 1651 */ 1652 static void ocelot_update_pgid_cpu(struct ocelot *ocelot) 1653 { 1654 int pgid_cpu = 0; 1655 int port; 1656 1657 for (port = 0; port < ocelot->num_phys_ports; port++) { 1658 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1659 1660 if (!ocelot_port || !ocelot_port->is_dsa_8021q_cpu) 1661 continue; 1662 1663 pgid_cpu |= BIT(port); 1664 } 1665 1666 if (!pgid_cpu) 1667 pgid_cpu = BIT(ocelot->num_phys_ports); 1668 1669 ocelot_write_rix(ocelot, pgid_cpu, ANA_PGID_PGID, PGID_CPU); 1670 } 1671 1672 void ocelot_port_setup_dsa_8021q_cpu(struct ocelot *ocelot, int cpu) 1673 { 1674 struct ocelot_port *cpu_port = ocelot->ports[cpu]; 1675 u16 vid; 1676 1677 mutex_lock(&ocelot->fwd_domain_lock); 1678 1679 cpu_port->is_dsa_8021q_cpu = true; 1680 1681 for (vid = OCELOT_RSV_VLAN_RANGE_START; vid < VLAN_N_VID; vid++) 1682 ocelot_vlan_member_add(ocelot, cpu, vid, true); 1683 1684 ocelot_update_pgid_cpu(ocelot); 1685 1686 mutex_unlock(&ocelot->fwd_domain_lock); 1687 } 1688 EXPORT_SYMBOL_GPL(ocelot_port_setup_dsa_8021q_cpu); 1689 1690 void ocelot_port_teardown_dsa_8021q_cpu(struct ocelot *ocelot, int cpu) 1691 { 1692 struct ocelot_port *cpu_port = ocelot->ports[cpu]; 1693 u16 vid; 1694 1695 mutex_lock(&ocelot->fwd_domain_lock); 1696 1697 cpu_port->is_dsa_8021q_cpu = false; 1698 1699 for (vid = OCELOT_RSV_VLAN_RANGE_START; vid < VLAN_N_VID; vid++) 1700 ocelot_vlan_member_del(ocelot, cpu_port->index, vid); 1701 1702 ocelot_update_pgid_cpu(ocelot); 1703 1704 mutex_unlock(&ocelot->fwd_domain_lock); 1705 } 1706 EXPORT_SYMBOL_GPL(ocelot_port_teardown_dsa_8021q_cpu); 1707 1708 void ocelot_port_assign_dsa_8021q_cpu(struct ocelot *ocelot, int port, 1709 int cpu) 1710 { 1711 struct ocelot_port *cpu_port = ocelot->ports[cpu]; 1712 1713 mutex_lock(&ocelot->fwd_domain_lock); 1714 1715 ocelot->ports[port]->dsa_8021q_cpu = cpu_port; 1716 ocelot_apply_bridge_fwd_mask(ocelot, true); 1717 1718 mutex_unlock(&ocelot->fwd_domain_lock); 1719 } 1720 EXPORT_SYMBOL_GPL(ocelot_port_assign_dsa_8021q_cpu); 1721 1722 void ocelot_port_unassign_dsa_8021q_cpu(struct ocelot *ocelot, int port) 1723 { 1724 mutex_lock(&ocelot->fwd_domain_lock); 1725 1726 ocelot->ports[port]->dsa_8021q_cpu = NULL; 1727 ocelot_apply_bridge_fwd_mask(ocelot, true); 1728 1729 mutex_unlock(&ocelot->fwd_domain_lock); 1730 } 1731 EXPORT_SYMBOL_GPL(ocelot_port_unassign_dsa_8021q_cpu); 1732 1733 void ocelot_bridge_stp_state_set(struct ocelot *ocelot, int port, u8 state) 1734 { 1735 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1736 u32 learn_ena = 0; 1737 1738 mutex_lock(&ocelot->fwd_domain_lock); 1739 1740 ocelot_port->stp_state = state; 1741 1742 if ((state == BR_STATE_LEARNING || state == BR_STATE_FORWARDING) && 1743 ocelot_port->learn_ena) 1744 learn_ena = ANA_PORT_PORT_CFG_LEARN_ENA; 1745 1746 ocelot_rmw_gix(ocelot, learn_ena, ANA_PORT_PORT_CFG_LEARN_ENA, 1747 ANA_PORT_PORT_CFG, port); 1748 1749 ocelot_apply_bridge_fwd_mask(ocelot, state == BR_STATE_FORWARDING); 1750 1751 mutex_unlock(&ocelot->fwd_domain_lock); 1752 } 1753 EXPORT_SYMBOL(ocelot_bridge_stp_state_set); 1754 1755 void ocelot_set_ageing_time(struct ocelot *ocelot, unsigned int msecs) 1756 { 1757 unsigned int age_period = ANA_AUTOAGE_AGE_PERIOD(msecs / 2000); 1758 1759 /* Setting AGE_PERIOD to zero effectively disables automatic aging, 1760 * which is clearly not what our intention is. So avoid that. 1761 */ 1762 if (!age_period) 1763 age_period = 1; 1764 1765 ocelot_rmw(ocelot, age_period, ANA_AUTOAGE_AGE_PERIOD_M, ANA_AUTOAGE); 1766 } 1767 EXPORT_SYMBOL(ocelot_set_ageing_time); 1768 1769 static struct ocelot_multicast *ocelot_multicast_get(struct ocelot *ocelot, 1770 const unsigned char *addr, 1771 u16 vid) 1772 { 1773 struct ocelot_multicast *mc; 1774 1775 list_for_each_entry(mc, &ocelot->multicast, list) { 1776 if (ether_addr_equal(mc->addr, addr) && mc->vid == vid) 1777 return mc; 1778 } 1779 1780 return NULL; 1781 } 1782 1783 static enum macaccess_entry_type ocelot_classify_mdb(const unsigned char *addr) 1784 { 1785 if (addr[0] == 0x01 && addr[1] == 0x00 && addr[2] == 0x5e) 1786 return ENTRYTYPE_MACv4; 1787 if (addr[0] == 0x33 && addr[1] == 0x33) 1788 return ENTRYTYPE_MACv6; 1789 return ENTRYTYPE_LOCKED; 1790 } 1791 1792 static struct ocelot_pgid *ocelot_pgid_alloc(struct ocelot *ocelot, int index, 1793 unsigned long ports) 1794 { 1795 struct ocelot_pgid *pgid; 1796 1797 pgid = kzalloc(sizeof(*pgid), GFP_KERNEL); 1798 if (!pgid) 1799 return ERR_PTR(-ENOMEM); 1800 1801 pgid->ports = ports; 1802 pgid->index = index; 1803 refcount_set(&pgid->refcount, 1); 1804 list_add_tail(&pgid->list, &ocelot->pgids); 1805 1806 return pgid; 1807 } 1808 1809 static void ocelot_pgid_free(struct ocelot *ocelot, struct ocelot_pgid *pgid) 1810 { 1811 if (!refcount_dec_and_test(&pgid->refcount)) 1812 return; 1813 1814 list_del(&pgid->list); 1815 kfree(pgid); 1816 } 1817 1818 static struct ocelot_pgid *ocelot_mdb_get_pgid(struct ocelot *ocelot, 1819 const struct ocelot_multicast *mc) 1820 { 1821 struct ocelot_pgid *pgid; 1822 int index; 1823 1824 /* According to VSC7514 datasheet 3.9.1.5 IPv4 Multicast Entries and 1825 * 3.9.1.6 IPv6 Multicast Entries, "Instead of a lookup in the 1826 * destination mask table (PGID), the destination set is programmed as 1827 * part of the entry MAC address.", and the DEST_IDX is set to 0. 1828 */ 1829 if (mc->entry_type == ENTRYTYPE_MACv4 || 1830 mc->entry_type == ENTRYTYPE_MACv6) 1831 return ocelot_pgid_alloc(ocelot, 0, mc->ports); 1832 1833 list_for_each_entry(pgid, &ocelot->pgids, list) { 1834 /* When searching for a nonreserved multicast PGID, ignore the 1835 * dummy PGID of zero that we have for MACv4/MACv6 entries 1836 */ 1837 if (pgid->index && pgid->ports == mc->ports) { 1838 refcount_inc(&pgid->refcount); 1839 return pgid; 1840 } 1841 } 1842 1843 /* Search for a free index in the nonreserved multicast PGID area */ 1844 for_each_nonreserved_multicast_dest_pgid(ocelot, index) { 1845 bool used = false; 1846 1847 list_for_each_entry(pgid, &ocelot->pgids, list) { 1848 if (pgid->index == index) { 1849 used = true; 1850 break; 1851 } 1852 } 1853 1854 if (!used) 1855 return ocelot_pgid_alloc(ocelot, index, mc->ports); 1856 } 1857 1858 return ERR_PTR(-ENOSPC); 1859 } 1860 1861 static void ocelot_encode_ports_to_mdb(unsigned char *addr, 1862 struct ocelot_multicast *mc) 1863 { 1864 ether_addr_copy(addr, mc->addr); 1865 1866 if (mc->entry_type == ENTRYTYPE_MACv4) { 1867 addr[0] = 0; 1868 addr[1] = mc->ports >> 8; 1869 addr[2] = mc->ports & 0xff; 1870 } else if (mc->entry_type == ENTRYTYPE_MACv6) { 1871 addr[0] = mc->ports >> 8; 1872 addr[1] = mc->ports & 0xff; 1873 } 1874 } 1875 1876 int ocelot_port_mdb_add(struct ocelot *ocelot, int port, 1877 const struct switchdev_obj_port_mdb *mdb, 1878 const struct net_device *bridge) 1879 { 1880 unsigned char addr[ETH_ALEN]; 1881 struct ocelot_multicast *mc; 1882 struct ocelot_pgid *pgid; 1883 u16 vid = mdb->vid; 1884 1885 if (!vid) 1886 vid = ocelot_vlan_unaware_pvid(ocelot, bridge); 1887 1888 mc = ocelot_multicast_get(ocelot, mdb->addr, vid); 1889 if (!mc) { 1890 /* New entry */ 1891 mc = devm_kzalloc(ocelot->dev, sizeof(*mc), GFP_KERNEL); 1892 if (!mc) 1893 return -ENOMEM; 1894 1895 mc->entry_type = ocelot_classify_mdb(mdb->addr); 1896 ether_addr_copy(mc->addr, mdb->addr); 1897 mc->vid = vid; 1898 1899 list_add_tail(&mc->list, &ocelot->multicast); 1900 } else { 1901 /* Existing entry. Clean up the current port mask from 1902 * hardware now, because we'll be modifying it. 1903 */ 1904 ocelot_pgid_free(ocelot, mc->pgid); 1905 ocelot_encode_ports_to_mdb(addr, mc); 1906 ocelot_mact_forget(ocelot, addr, vid); 1907 } 1908 1909 mc->ports |= BIT(port); 1910 1911 pgid = ocelot_mdb_get_pgid(ocelot, mc); 1912 if (IS_ERR(pgid)) { 1913 dev_err(ocelot->dev, 1914 "Cannot allocate PGID for mdb %pM vid %d\n", 1915 mc->addr, mc->vid); 1916 devm_kfree(ocelot->dev, mc); 1917 return PTR_ERR(pgid); 1918 } 1919 mc->pgid = pgid; 1920 1921 ocelot_encode_ports_to_mdb(addr, mc); 1922 1923 if (mc->entry_type != ENTRYTYPE_MACv4 && 1924 mc->entry_type != ENTRYTYPE_MACv6) 1925 ocelot_write_rix(ocelot, pgid->ports, ANA_PGID_PGID, 1926 pgid->index); 1927 1928 return ocelot_mact_learn(ocelot, pgid->index, addr, vid, 1929 mc->entry_type); 1930 } 1931 EXPORT_SYMBOL(ocelot_port_mdb_add); 1932 1933 int ocelot_port_mdb_del(struct ocelot *ocelot, int port, 1934 const struct switchdev_obj_port_mdb *mdb, 1935 const struct net_device *bridge) 1936 { 1937 unsigned char addr[ETH_ALEN]; 1938 struct ocelot_multicast *mc; 1939 struct ocelot_pgid *pgid; 1940 u16 vid = mdb->vid; 1941 1942 if (!vid) 1943 vid = ocelot_vlan_unaware_pvid(ocelot, bridge); 1944 1945 mc = ocelot_multicast_get(ocelot, mdb->addr, vid); 1946 if (!mc) 1947 return -ENOENT; 1948 1949 ocelot_encode_ports_to_mdb(addr, mc); 1950 ocelot_mact_forget(ocelot, addr, vid); 1951 1952 ocelot_pgid_free(ocelot, mc->pgid); 1953 mc->ports &= ~BIT(port); 1954 if (!mc->ports) { 1955 list_del(&mc->list); 1956 devm_kfree(ocelot->dev, mc); 1957 return 0; 1958 } 1959 1960 /* We have a PGID with fewer ports now */ 1961 pgid = ocelot_mdb_get_pgid(ocelot, mc); 1962 if (IS_ERR(pgid)) 1963 return PTR_ERR(pgid); 1964 mc->pgid = pgid; 1965 1966 ocelot_encode_ports_to_mdb(addr, mc); 1967 1968 if (mc->entry_type != ENTRYTYPE_MACv4 && 1969 mc->entry_type != ENTRYTYPE_MACv6) 1970 ocelot_write_rix(ocelot, pgid->ports, ANA_PGID_PGID, 1971 pgid->index); 1972 1973 return ocelot_mact_learn(ocelot, pgid->index, addr, vid, 1974 mc->entry_type); 1975 } 1976 EXPORT_SYMBOL(ocelot_port_mdb_del); 1977 1978 int ocelot_port_bridge_join(struct ocelot *ocelot, int port, 1979 struct net_device *bridge, int bridge_num, 1980 struct netlink_ext_ack *extack) 1981 { 1982 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1983 int err; 1984 1985 err = ocelot_single_vlan_aware_bridge(ocelot, extack); 1986 if (err) 1987 return err; 1988 1989 mutex_lock(&ocelot->fwd_domain_lock); 1990 1991 ocelot_port->bridge = bridge; 1992 ocelot_port->bridge_num = bridge_num; 1993 1994 ocelot_apply_bridge_fwd_mask(ocelot, true); 1995 1996 mutex_unlock(&ocelot->fwd_domain_lock); 1997 1998 if (br_vlan_enabled(bridge)) 1999 return 0; 2000 2001 return ocelot_add_vlan_unaware_pvid(ocelot, port, bridge); 2002 } 2003 EXPORT_SYMBOL(ocelot_port_bridge_join); 2004 2005 void ocelot_port_bridge_leave(struct ocelot *ocelot, int port, 2006 struct net_device *bridge) 2007 { 2008 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2009 2010 mutex_lock(&ocelot->fwd_domain_lock); 2011 2012 if (!br_vlan_enabled(bridge)) 2013 ocelot_del_vlan_unaware_pvid(ocelot, port, bridge); 2014 2015 ocelot_port->bridge = NULL; 2016 ocelot_port->bridge_num = -1; 2017 2018 ocelot_port_set_pvid(ocelot, port, NULL); 2019 ocelot_port_manage_port_tag(ocelot, port); 2020 ocelot_apply_bridge_fwd_mask(ocelot, false); 2021 2022 mutex_unlock(&ocelot->fwd_domain_lock); 2023 } 2024 EXPORT_SYMBOL(ocelot_port_bridge_leave); 2025 2026 static void ocelot_set_aggr_pgids(struct ocelot *ocelot) 2027 { 2028 unsigned long visited = GENMASK(ocelot->num_phys_ports - 1, 0); 2029 int i, port, lag; 2030 2031 /* Reset destination and aggregation PGIDS */ 2032 for_each_unicast_dest_pgid(ocelot, port) 2033 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port); 2034 2035 for_each_aggr_pgid(ocelot, i) 2036 ocelot_write_rix(ocelot, GENMASK(ocelot->num_phys_ports - 1, 0), 2037 ANA_PGID_PGID, i); 2038 2039 /* The visited ports bitmask holds the list of ports offloading any 2040 * bonding interface. Initially we mark all these ports as unvisited, 2041 * then every time we visit a port in this bitmask, we know that it is 2042 * the lowest numbered port, i.e. the one whose logical ID == physical 2043 * port ID == LAG ID. So we mark as visited all further ports in the 2044 * bitmask that are offloading the same bonding interface. This way, 2045 * we set up the aggregation PGIDs only once per bonding interface. 2046 */ 2047 for (port = 0; port < ocelot->num_phys_ports; port++) { 2048 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2049 2050 if (!ocelot_port || !ocelot_port->bond) 2051 continue; 2052 2053 visited &= ~BIT(port); 2054 } 2055 2056 /* Now, set PGIDs for each active LAG */ 2057 for (lag = 0; lag < ocelot->num_phys_ports; lag++) { 2058 struct net_device *bond = ocelot->ports[lag]->bond; 2059 int num_active_ports = 0; 2060 unsigned long bond_mask; 2061 u8 aggr_idx[16]; 2062 2063 if (!bond || (visited & BIT(lag))) 2064 continue; 2065 2066 bond_mask = ocelot_get_bond_mask(ocelot, bond); 2067 2068 for_each_set_bit(port, &bond_mask, ocelot->num_phys_ports) { 2069 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2070 2071 // Destination mask 2072 ocelot_write_rix(ocelot, bond_mask, 2073 ANA_PGID_PGID, port); 2074 2075 if (ocelot_port->lag_tx_active) 2076 aggr_idx[num_active_ports++] = port; 2077 } 2078 2079 for_each_aggr_pgid(ocelot, i) { 2080 u32 ac; 2081 2082 ac = ocelot_read_rix(ocelot, ANA_PGID_PGID, i); 2083 ac &= ~bond_mask; 2084 /* Don't do division by zero if there was no active 2085 * port. Just make all aggregation codes zero. 2086 */ 2087 if (num_active_ports) 2088 ac |= BIT(aggr_idx[i % num_active_ports]); 2089 ocelot_write_rix(ocelot, ac, ANA_PGID_PGID, i); 2090 } 2091 2092 /* Mark all ports in the same LAG as visited to avoid applying 2093 * the same config again. 2094 */ 2095 for (port = lag; port < ocelot->num_phys_ports; port++) { 2096 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2097 2098 if (!ocelot_port) 2099 continue; 2100 2101 if (ocelot_port->bond == bond) 2102 visited |= BIT(port); 2103 } 2104 } 2105 } 2106 2107 /* When offloading a bonding interface, the switch ports configured under the 2108 * same bond must have the same logical port ID, equal to the physical port ID 2109 * of the lowest numbered physical port in that bond. Otherwise, in standalone/ 2110 * bridged mode, each port has a logical port ID equal to its physical port ID. 2111 */ 2112 static void ocelot_setup_logical_port_ids(struct ocelot *ocelot) 2113 { 2114 int port; 2115 2116 for (port = 0; port < ocelot->num_phys_ports; port++) { 2117 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2118 struct net_device *bond; 2119 2120 if (!ocelot_port) 2121 continue; 2122 2123 bond = ocelot_port->bond; 2124 if (bond) { 2125 int lag = ocelot_bond_get_id(ocelot, bond); 2126 2127 ocelot_rmw_gix(ocelot, 2128 ANA_PORT_PORT_CFG_PORTID_VAL(lag), 2129 ANA_PORT_PORT_CFG_PORTID_VAL_M, 2130 ANA_PORT_PORT_CFG, port); 2131 } else { 2132 ocelot_rmw_gix(ocelot, 2133 ANA_PORT_PORT_CFG_PORTID_VAL(port), 2134 ANA_PORT_PORT_CFG_PORTID_VAL_M, 2135 ANA_PORT_PORT_CFG, port); 2136 } 2137 } 2138 } 2139 2140 static int ocelot_migrate_mc(struct ocelot *ocelot, struct ocelot_multicast *mc, 2141 unsigned long from_mask, unsigned long to_mask) 2142 { 2143 unsigned char addr[ETH_ALEN]; 2144 struct ocelot_pgid *pgid; 2145 u16 vid = mc->vid; 2146 2147 dev_dbg(ocelot->dev, 2148 "Migrating multicast %pM vid %d from port mask 0x%lx to 0x%lx\n", 2149 mc->addr, mc->vid, from_mask, to_mask); 2150 2151 /* First clean up the current port mask from hardware, because 2152 * we'll be modifying it. 2153 */ 2154 ocelot_pgid_free(ocelot, mc->pgid); 2155 ocelot_encode_ports_to_mdb(addr, mc); 2156 ocelot_mact_forget(ocelot, addr, vid); 2157 2158 mc->ports &= ~from_mask; 2159 mc->ports |= to_mask; 2160 2161 pgid = ocelot_mdb_get_pgid(ocelot, mc); 2162 if (IS_ERR(pgid)) { 2163 dev_err(ocelot->dev, 2164 "Cannot allocate PGID for mdb %pM vid %d\n", 2165 mc->addr, mc->vid); 2166 devm_kfree(ocelot->dev, mc); 2167 return PTR_ERR(pgid); 2168 } 2169 mc->pgid = pgid; 2170 2171 ocelot_encode_ports_to_mdb(addr, mc); 2172 2173 if (mc->entry_type != ENTRYTYPE_MACv4 && 2174 mc->entry_type != ENTRYTYPE_MACv6) 2175 ocelot_write_rix(ocelot, pgid->ports, ANA_PGID_PGID, 2176 pgid->index); 2177 2178 return ocelot_mact_learn(ocelot, pgid->index, addr, vid, 2179 mc->entry_type); 2180 } 2181 2182 int ocelot_migrate_mdbs(struct ocelot *ocelot, unsigned long from_mask, 2183 unsigned long to_mask) 2184 { 2185 struct ocelot_multicast *mc; 2186 int err; 2187 2188 list_for_each_entry(mc, &ocelot->multicast, list) { 2189 if (!(mc->ports & from_mask)) 2190 continue; 2191 2192 err = ocelot_migrate_mc(ocelot, mc, from_mask, to_mask); 2193 if (err) 2194 return err; 2195 } 2196 2197 return 0; 2198 } 2199 EXPORT_SYMBOL_GPL(ocelot_migrate_mdbs); 2200 2201 /* Documentation for PORTID_VAL says: 2202 * Logical port number for front port. If port is not a member of a LLAG, 2203 * then PORTID must be set to the physical port number. 2204 * If port is a member of a LLAG, then PORTID must be set to the common 2205 * PORTID_VAL used for all member ports of the LLAG. 2206 * The value must not exceed the number of physical ports on the device. 2207 * 2208 * This means we have little choice but to migrate FDB entries pointing towards 2209 * a logical port when that changes. 2210 */ 2211 static void ocelot_migrate_lag_fdbs(struct ocelot *ocelot, 2212 struct net_device *bond, 2213 int lag) 2214 { 2215 struct ocelot_lag_fdb *fdb; 2216 int err; 2217 2218 lockdep_assert_held(&ocelot->fwd_domain_lock); 2219 2220 list_for_each_entry(fdb, &ocelot->lag_fdbs, list) { 2221 if (fdb->bond != bond) 2222 continue; 2223 2224 err = ocelot_mact_forget(ocelot, fdb->addr, fdb->vid); 2225 if (err) { 2226 dev_err(ocelot->dev, 2227 "failed to delete LAG %s FDB %pM vid %d: %pe\n", 2228 bond->name, fdb->addr, fdb->vid, ERR_PTR(err)); 2229 } 2230 2231 err = ocelot_mact_learn(ocelot, lag, fdb->addr, fdb->vid, 2232 ENTRYTYPE_LOCKED); 2233 if (err) { 2234 dev_err(ocelot->dev, 2235 "failed to migrate LAG %s FDB %pM vid %d: %pe\n", 2236 bond->name, fdb->addr, fdb->vid, ERR_PTR(err)); 2237 } 2238 } 2239 } 2240 2241 int ocelot_port_lag_join(struct ocelot *ocelot, int port, 2242 struct net_device *bond, 2243 struct netdev_lag_upper_info *info, 2244 struct netlink_ext_ack *extack) 2245 { 2246 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) { 2247 NL_SET_ERR_MSG_MOD(extack, 2248 "Can only offload LAG using hash TX type"); 2249 return -EOPNOTSUPP; 2250 } 2251 2252 mutex_lock(&ocelot->fwd_domain_lock); 2253 2254 ocelot->ports[port]->bond = bond; 2255 2256 ocelot_setup_logical_port_ids(ocelot); 2257 ocelot_apply_bridge_fwd_mask(ocelot, true); 2258 ocelot_set_aggr_pgids(ocelot); 2259 2260 mutex_unlock(&ocelot->fwd_domain_lock); 2261 2262 return 0; 2263 } 2264 EXPORT_SYMBOL(ocelot_port_lag_join); 2265 2266 void ocelot_port_lag_leave(struct ocelot *ocelot, int port, 2267 struct net_device *bond) 2268 { 2269 int old_lag_id, new_lag_id; 2270 2271 mutex_lock(&ocelot->fwd_domain_lock); 2272 2273 old_lag_id = ocelot_bond_get_id(ocelot, bond); 2274 2275 ocelot->ports[port]->bond = NULL; 2276 2277 ocelot_setup_logical_port_ids(ocelot); 2278 ocelot_apply_bridge_fwd_mask(ocelot, false); 2279 ocelot_set_aggr_pgids(ocelot); 2280 2281 new_lag_id = ocelot_bond_get_id(ocelot, bond); 2282 2283 if (new_lag_id >= 0 && old_lag_id != new_lag_id) 2284 ocelot_migrate_lag_fdbs(ocelot, bond, new_lag_id); 2285 2286 mutex_unlock(&ocelot->fwd_domain_lock); 2287 } 2288 EXPORT_SYMBOL(ocelot_port_lag_leave); 2289 2290 void ocelot_port_lag_change(struct ocelot *ocelot, int port, bool lag_tx_active) 2291 { 2292 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2293 2294 mutex_lock(&ocelot->fwd_domain_lock); 2295 2296 ocelot_port->lag_tx_active = lag_tx_active; 2297 2298 /* Rebalance the LAGs */ 2299 ocelot_set_aggr_pgids(ocelot); 2300 2301 mutex_unlock(&ocelot->fwd_domain_lock); 2302 } 2303 EXPORT_SYMBOL(ocelot_port_lag_change); 2304 2305 int ocelot_lag_fdb_add(struct ocelot *ocelot, struct net_device *bond, 2306 const unsigned char *addr, u16 vid, 2307 const struct net_device *bridge) 2308 { 2309 struct ocelot_lag_fdb *fdb; 2310 int lag, err; 2311 2312 fdb = kzalloc(sizeof(*fdb), GFP_KERNEL); 2313 if (!fdb) 2314 return -ENOMEM; 2315 2316 mutex_lock(&ocelot->fwd_domain_lock); 2317 2318 if (!vid) 2319 vid = ocelot_vlan_unaware_pvid(ocelot, bridge); 2320 2321 ether_addr_copy(fdb->addr, addr); 2322 fdb->vid = vid; 2323 fdb->bond = bond; 2324 2325 lag = ocelot_bond_get_id(ocelot, bond); 2326 2327 err = ocelot_mact_learn(ocelot, lag, addr, vid, ENTRYTYPE_LOCKED); 2328 if (err) { 2329 mutex_unlock(&ocelot->fwd_domain_lock); 2330 kfree(fdb); 2331 return err; 2332 } 2333 2334 list_add_tail(&fdb->list, &ocelot->lag_fdbs); 2335 mutex_unlock(&ocelot->fwd_domain_lock); 2336 2337 return 0; 2338 } 2339 EXPORT_SYMBOL_GPL(ocelot_lag_fdb_add); 2340 2341 int ocelot_lag_fdb_del(struct ocelot *ocelot, struct net_device *bond, 2342 const unsigned char *addr, u16 vid, 2343 const struct net_device *bridge) 2344 { 2345 struct ocelot_lag_fdb *fdb, *tmp; 2346 2347 mutex_lock(&ocelot->fwd_domain_lock); 2348 2349 if (!vid) 2350 vid = ocelot_vlan_unaware_pvid(ocelot, bridge); 2351 2352 list_for_each_entry_safe(fdb, tmp, &ocelot->lag_fdbs, list) { 2353 if (!ether_addr_equal(fdb->addr, addr) || fdb->vid != vid || 2354 fdb->bond != bond) 2355 continue; 2356 2357 ocelot_mact_forget(ocelot, addr, vid); 2358 list_del(&fdb->list); 2359 mutex_unlock(&ocelot->fwd_domain_lock); 2360 kfree(fdb); 2361 2362 return 0; 2363 } 2364 2365 mutex_unlock(&ocelot->fwd_domain_lock); 2366 2367 return -ENOENT; 2368 } 2369 EXPORT_SYMBOL_GPL(ocelot_lag_fdb_del); 2370 2371 /* Configure the maximum SDU (L2 payload) on RX to the value specified in @sdu. 2372 * The length of VLAN tags is accounted for automatically via DEV_MAC_TAGS_CFG. 2373 * In the special case that it's the NPI port that we're configuring, the 2374 * length of the tag and optional prefix needs to be accounted for privately, 2375 * in order to be able to sustain communication at the requested @sdu. 2376 */ 2377 void ocelot_port_set_maxlen(struct ocelot *ocelot, int port, size_t sdu) 2378 { 2379 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2380 int maxlen = sdu + ETH_HLEN + ETH_FCS_LEN; 2381 int pause_start, pause_stop; 2382 int atop, atop_tot; 2383 2384 if (port == ocelot->npi) { 2385 maxlen += OCELOT_TAG_LEN; 2386 2387 if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_SHORT) 2388 maxlen += OCELOT_SHORT_PREFIX_LEN; 2389 else if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_LONG) 2390 maxlen += OCELOT_LONG_PREFIX_LEN; 2391 } 2392 2393 ocelot_port_writel(ocelot_port, maxlen, DEV_MAC_MAXLEN_CFG); 2394 2395 /* Set Pause watermark hysteresis */ 2396 pause_start = 6 * maxlen / OCELOT_BUFFER_CELL_SZ; 2397 pause_stop = 4 * maxlen / OCELOT_BUFFER_CELL_SZ; 2398 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_START, 2399 pause_start); 2400 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_STOP, 2401 pause_stop); 2402 2403 /* Tail dropping watermarks */ 2404 atop_tot = (ocelot->packet_buffer_size - 9 * maxlen) / 2405 OCELOT_BUFFER_CELL_SZ; 2406 atop = (9 * maxlen) / OCELOT_BUFFER_CELL_SZ; 2407 ocelot_write_rix(ocelot, ocelot->ops->wm_enc(atop), SYS_ATOP, port); 2408 ocelot_write(ocelot, ocelot->ops->wm_enc(atop_tot), SYS_ATOP_TOT_CFG); 2409 } 2410 EXPORT_SYMBOL(ocelot_port_set_maxlen); 2411 2412 int ocelot_get_max_mtu(struct ocelot *ocelot, int port) 2413 { 2414 int max_mtu = 65535 - ETH_HLEN - ETH_FCS_LEN; 2415 2416 if (port == ocelot->npi) { 2417 max_mtu -= OCELOT_TAG_LEN; 2418 2419 if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_SHORT) 2420 max_mtu -= OCELOT_SHORT_PREFIX_LEN; 2421 else if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_LONG) 2422 max_mtu -= OCELOT_LONG_PREFIX_LEN; 2423 } 2424 2425 return max_mtu; 2426 } 2427 EXPORT_SYMBOL(ocelot_get_max_mtu); 2428 2429 static void ocelot_port_set_learning(struct ocelot *ocelot, int port, 2430 bool enabled) 2431 { 2432 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2433 u32 val = 0; 2434 2435 if (enabled) 2436 val = ANA_PORT_PORT_CFG_LEARN_ENA; 2437 2438 ocelot_rmw_gix(ocelot, val, ANA_PORT_PORT_CFG_LEARN_ENA, 2439 ANA_PORT_PORT_CFG, port); 2440 2441 ocelot_port->learn_ena = enabled; 2442 } 2443 2444 static void ocelot_port_set_ucast_flood(struct ocelot *ocelot, int port, 2445 bool enabled) 2446 { 2447 u32 val = 0; 2448 2449 if (enabled) 2450 val = BIT(port); 2451 2452 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_UC); 2453 } 2454 2455 static void ocelot_port_set_mcast_flood(struct ocelot *ocelot, int port, 2456 bool enabled) 2457 { 2458 u32 val = 0; 2459 2460 if (enabled) 2461 val = BIT(port); 2462 2463 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_MC); 2464 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_MCIPV4); 2465 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_MCIPV6); 2466 } 2467 2468 static void ocelot_port_set_bcast_flood(struct ocelot *ocelot, int port, 2469 bool enabled) 2470 { 2471 u32 val = 0; 2472 2473 if (enabled) 2474 val = BIT(port); 2475 2476 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_BC); 2477 } 2478 2479 int ocelot_port_pre_bridge_flags(struct ocelot *ocelot, int port, 2480 struct switchdev_brport_flags flags) 2481 { 2482 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | 2483 BR_BCAST_FLOOD)) 2484 return -EINVAL; 2485 2486 return 0; 2487 } 2488 EXPORT_SYMBOL(ocelot_port_pre_bridge_flags); 2489 2490 void ocelot_port_bridge_flags(struct ocelot *ocelot, int port, 2491 struct switchdev_brport_flags flags) 2492 { 2493 if (flags.mask & BR_LEARNING) 2494 ocelot_port_set_learning(ocelot, port, 2495 !!(flags.val & BR_LEARNING)); 2496 2497 if (flags.mask & BR_FLOOD) 2498 ocelot_port_set_ucast_flood(ocelot, port, 2499 !!(flags.val & BR_FLOOD)); 2500 2501 if (flags.mask & BR_MCAST_FLOOD) 2502 ocelot_port_set_mcast_flood(ocelot, port, 2503 !!(flags.val & BR_MCAST_FLOOD)); 2504 2505 if (flags.mask & BR_BCAST_FLOOD) 2506 ocelot_port_set_bcast_flood(ocelot, port, 2507 !!(flags.val & BR_BCAST_FLOOD)); 2508 } 2509 EXPORT_SYMBOL(ocelot_port_bridge_flags); 2510 2511 int ocelot_port_get_default_prio(struct ocelot *ocelot, int port) 2512 { 2513 int val = ocelot_read_gix(ocelot, ANA_PORT_QOS_CFG, port); 2514 2515 return ANA_PORT_QOS_CFG_QOS_DEFAULT_VAL_X(val); 2516 } 2517 EXPORT_SYMBOL_GPL(ocelot_port_get_default_prio); 2518 2519 int ocelot_port_set_default_prio(struct ocelot *ocelot, int port, u8 prio) 2520 { 2521 if (prio >= OCELOT_NUM_TC) 2522 return -ERANGE; 2523 2524 ocelot_rmw_gix(ocelot, 2525 ANA_PORT_QOS_CFG_QOS_DEFAULT_VAL(prio), 2526 ANA_PORT_QOS_CFG_QOS_DEFAULT_VAL_M, 2527 ANA_PORT_QOS_CFG, 2528 port); 2529 2530 return 0; 2531 } 2532 EXPORT_SYMBOL_GPL(ocelot_port_set_default_prio); 2533 2534 int ocelot_port_get_dscp_prio(struct ocelot *ocelot, int port, u8 dscp) 2535 { 2536 int qos_cfg = ocelot_read_gix(ocelot, ANA_PORT_QOS_CFG, port); 2537 int dscp_cfg = ocelot_read_rix(ocelot, ANA_DSCP_CFG, dscp); 2538 2539 /* Return error if DSCP prioritization isn't enabled */ 2540 if (!(qos_cfg & ANA_PORT_QOS_CFG_QOS_DSCP_ENA)) 2541 return -EOPNOTSUPP; 2542 2543 if (qos_cfg & ANA_PORT_QOS_CFG_DSCP_TRANSLATE_ENA) { 2544 dscp = ANA_DSCP_CFG_DSCP_TRANSLATE_VAL_X(dscp_cfg); 2545 /* Re-read ANA_DSCP_CFG for the translated DSCP */ 2546 dscp_cfg = ocelot_read_rix(ocelot, ANA_DSCP_CFG, dscp); 2547 } 2548 2549 /* If the DSCP value is not trusted, the QoS classification falls back 2550 * to VLAN PCP or port-based default. 2551 */ 2552 if (!(dscp_cfg & ANA_DSCP_CFG_DSCP_TRUST_ENA)) 2553 return -EOPNOTSUPP; 2554 2555 return ANA_DSCP_CFG_QOS_DSCP_VAL_X(dscp_cfg); 2556 } 2557 EXPORT_SYMBOL_GPL(ocelot_port_get_dscp_prio); 2558 2559 int ocelot_port_add_dscp_prio(struct ocelot *ocelot, int port, u8 dscp, u8 prio) 2560 { 2561 int mask, val; 2562 2563 if (prio >= OCELOT_NUM_TC) 2564 return -ERANGE; 2565 2566 /* There is at least one app table priority (this one), so we need to 2567 * make sure DSCP prioritization is enabled on the port. 2568 * Also make sure DSCP translation is disabled 2569 * (dcbnl doesn't support it). 2570 */ 2571 mask = ANA_PORT_QOS_CFG_QOS_DSCP_ENA | 2572 ANA_PORT_QOS_CFG_DSCP_TRANSLATE_ENA; 2573 2574 ocelot_rmw_gix(ocelot, ANA_PORT_QOS_CFG_QOS_DSCP_ENA, mask, 2575 ANA_PORT_QOS_CFG, port); 2576 2577 /* Trust this DSCP value and map it to the given QoS class */ 2578 val = ANA_DSCP_CFG_DSCP_TRUST_ENA | ANA_DSCP_CFG_QOS_DSCP_VAL(prio); 2579 2580 ocelot_write_rix(ocelot, val, ANA_DSCP_CFG, dscp); 2581 2582 return 0; 2583 } 2584 EXPORT_SYMBOL_GPL(ocelot_port_add_dscp_prio); 2585 2586 int ocelot_port_del_dscp_prio(struct ocelot *ocelot, int port, u8 dscp, u8 prio) 2587 { 2588 int dscp_cfg = ocelot_read_rix(ocelot, ANA_DSCP_CFG, dscp); 2589 int mask, i; 2590 2591 /* During a "dcb app replace" command, the new app table entry will be 2592 * added first, then the old one will be deleted. But the hardware only 2593 * supports one QoS class per DSCP value (duh), so if we blindly delete 2594 * the app table entry for this DSCP value, we end up deleting the 2595 * entry with the new priority. Avoid that by checking whether user 2596 * space wants to delete the priority which is currently configured, or 2597 * something else which is no longer current. 2598 */ 2599 if (ANA_DSCP_CFG_QOS_DSCP_VAL_X(dscp_cfg) != prio) 2600 return 0; 2601 2602 /* Untrust this DSCP value */ 2603 ocelot_write_rix(ocelot, 0, ANA_DSCP_CFG, dscp); 2604 2605 for (i = 0; i < 64; i++) { 2606 int dscp_cfg = ocelot_read_rix(ocelot, ANA_DSCP_CFG, i); 2607 2608 /* There are still app table entries on the port, so we need to 2609 * keep DSCP enabled, nothing to do. 2610 */ 2611 if (dscp_cfg & ANA_DSCP_CFG_DSCP_TRUST_ENA) 2612 return 0; 2613 } 2614 2615 /* Disable DSCP QoS classification if there isn't any trusted 2616 * DSCP value left. 2617 */ 2618 mask = ANA_PORT_QOS_CFG_QOS_DSCP_ENA | 2619 ANA_PORT_QOS_CFG_DSCP_TRANSLATE_ENA; 2620 2621 ocelot_rmw_gix(ocelot, 0, mask, ANA_PORT_QOS_CFG, port); 2622 2623 return 0; 2624 } 2625 EXPORT_SYMBOL_GPL(ocelot_port_del_dscp_prio); 2626 2627 struct ocelot_mirror *ocelot_mirror_get(struct ocelot *ocelot, int to, 2628 struct netlink_ext_ack *extack) 2629 { 2630 struct ocelot_mirror *m = ocelot->mirror; 2631 2632 if (m) { 2633 if (m->to != to) { 2634 NL_SET_ERR_MSG_MOD(extack, 2635 "Mirroring already configured towards different egress port"); 2636 return ERR_PTR(-EBUSY); 2637 } 2638 2639 refcount_inc(&m->refcount); 2640 return m; 2641 } 2642 2643 m = kzalloc(sizeof(*m), GFP_KERNEL); 2644 if (!m) 2645 return ERR_PTR(-ENOMEM); 2646 2647 m->to = to; 2648 refcount_set(&m->refcount, 1); 2649 ocelot->mirror = m; 2650 2651 /* Program the mirror port to hardware */ 2652 ocelot_write(ocelot, BIT(to), ANA_MIRRORPORTS); 2653 2654 return m; 2655 } 2656 2657 void ocelot_mirror_put(struct ocelot *ocelot) 2658 { 2659 struct ocelot_mirror *m = ocelot->mirror; 2660 2661 if (!refcount_dec_and_test(&m->refcount)) 2662 return; 2663 2664 ocelot_write(ocelot, 0, ANA_MIRRORPORTS); 2665 ocelot->mirror = NULL; 2666 kfree(m); 2667 } 2668 2669 int ocelot_port_mirror_add(struct ocelot *ocelot, int from, int to, 2670 bool ingress, struct netlink_ext_ack *extack) 2671 { 2672 struct ocelot_mirror *m = ocelot_mirror_get(ocelot, to, extack); 2673 2674 if (IS_ERR(m)) 2675 return PTR_ERR(m); 2676 2677 if (ingress) { 2678 ocelot_rmw_gix(ocelot, ANA_PORT_PORT_CFG_SRC_MIRROR_ENA, 2679 ANA_PORT_PORT_CFG_SRC_MIRROR_ENA, 2680 ANA_PORT_PORT_CFG, from); 2681 } else { 2682 ocelot_rmw(ocelot, BIT(from), BIT(from), 2683 ANA_EMIRRORPORTS); 2684 } 2685 2686 return 0; 2687 } 2688 EXPORT_SYMBOL_GPL(ocelot_port_mirror_add); 2689 2690 void ocelot_port_mirror_del(struct ocelot *ocelot, int from, bool ingress) 2691 { 2692 if (ingress) { 2693 ocelot_rmw_gix(ocelot, 0, ANA_PORT_PORT_CFG_SRC_MIRROR_ENA, 2694 ANA_PORT_PORT_CFG, from); 2695 } else { 2696 ocelot_rmw(ocelot, 0, BIT(from), ANA_EMIRRORPORTS); 2697 } 2698 2699 ocelot_mirror_put(ocelot); 2700 } 2701 EXPORT_SYMBOL_GPL(ocelot_port_mirror_del); 2702 2703 static void ocelot_port_reset_mqprio(struct ocelot *ocelot, int port) 2704 { 2705 struct net_device *dev = ocelot->ops->port_to_netdev(ocelot, port); 2706 2707 netdev_reset_tc(dev); 2708 } 2709 2710 int ocelot_port_mqprio(struct ocelot *ocelot, int port, 2711 struct tc_mqprio_qopt_offload *mqprio) 2712 { 2713 struct net_device *dev = ocelot->ops->port_to_netdev(ocelot, port); 2714 struct netlink_ext_ack *extack = mqprio->extack; 2715 struct tc_mqprio_qopt *qopt = &mqprio->qopt; 2716 int num_tc = qopt->num_tc; 2717 int tc, err; 2718 2719 if (!num_tc) { 2720 ocelot_port_reset_mqprio(ocelot, port); 2721 return 0; 2722 } 2723 2724 err = netdev_set_num_tc(dev, num_tc); 2725 if (err) 2726 return err; 2727 2728 for (tc = 0; tc < num_tc; tc++) { 2729 if (qopt->count[tc] != 1) { 2730 NL_SET_ERR_MSG_MOD(extack, 2731 "Only one TXQ per TC supported"); 2732 return -EINVAL; 2733 } 2734 2735 err = netdev_set_tc_queue(dev, tc, 1, qopt->offset[tc]); 2736 if (err) 2737 goto err_reset_tc; 2738 } 2739 2740 err = netif_set_real_num_tx_queues(dev, num_tc); 2741 if (err) 2742 goto err_reset_tc; 2743 2744 return 0; 2745 2746 err_reset_tc: 2747 ocelot_port_reset_mqprio(ocelot, port); 2748 return err; 2749 } 2750 EXPORT_SYMBOL_GPL(ocelot_port_mqprio); 2751 2752 void ocelot_init_port(struct ocelot *ocelot, int port) 2753 { 2754 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2755 2756 skb_queue_head_init(&ocelot_port->tx_skbs); 2757 2758 /* Basic L2 initialization */ 2759 2760 /* Set MAC IFG Gaps 2761 * FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 0 2762 * !FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 5 2763 */ 2764 ocelot_port_writel(ocelot_port, DEV_MAC_IFG_CFG_TX_IFG(5), 2765 DEV_MAC_IFG_CFG); 2766 2767 /* Load seed (0) and set MAC HDX late collision */ 2768 ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67) | 2769 DEV_MAC_HDX_CFG_SEED_LOAD, 2770 DEV_MAC_HDX_CFG); 2771 mdelay(1); 2772 ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67), 2773 DEV_MAC_HDX_CFG); 2774 2775 /* Set Max Length and maximum tags allowed */ 2776 ocelot_port_set_maxlen(ocelot, port, ETH_DATA_LEN); 2777 ocelot_port_writel(ocelot_port, DEV_MAC_TAGS_CFG_TAG_ID(ETH_P_8021AD) | 2778 DEV_MAC_TAGS_CFG_VLAN_AWR_ENA | 2779 DEV_MAC_TAGS_CFG_VLAN_DBL_AWR_ENA | 2780 DEV_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA, 2781 DEV_MAC_TAGS_CFG); 2782 2783 /* Set SMAC of Pause frame (00:00:00:00:00:00) */ 2784 ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_HIGH_CFG); 2785 ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_LOW_CFG); 2786 2787 /* Enable transmission of pause frames */ 2788 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, 1); 2789 2790 /* Drop frames with multicast source address */ 2791 ocelot_rmw_gix(ocelot, ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA, 2792 ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA, 2793 ANA_PORT_DROP_CFG, port); 2794 2795 /* Set default VLAN and tag type to 8021Q. */ 2796 ocelot_rmw_gix(ocelot, REW_PORT_VLAN_CFG_PORT_TPID(ETH_P_8021Q), 2797 REW_PORT_VLAN_CFG_PORT_TPID_M, 2798 REW_PORT_VLAN_CFG, port); 2799 2800 /* Disable source address learning for standalone mode */ 2801 ocelot_port_set_learning(ocelot, port, false); 2802 2803 /* Set the port's initial logical port ID value, enable receiving 2804 * frames on it, and configure the MAC address learning type to 2805 * automatic. 2806 */ 2807 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_LEARNAUTO | 2808 ANA_PORT_PORT_CFG_RECV_ENA | 2809 ANA_PORT_PORT_CFG_PORTID_VAL(port), 2810 ANA_PORT_PORT_CFG, port); 2811 2812 /* Enable vcap lookups */ 2813 ocelot_vcap_enable(ocelot, port); 2814 } 2815 EXPORT_SYMBOL(ocelot_init_port); 2816 2817 /* Configure and enable the CPU port module, which is a set of queues 2818 * accessible through register MMIO, frame DMA or Ethernet (in case 2819 * NPI mode is used). 2820 */ 2821 static void ocelot_cpu_port_init(struct ocelot *ocelot) 2822 { 2823 int cpu = ocelot->num_phys_ports; 2824 2825 /* The unicast destination PGID for the CPU port module is unused */ 2826 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, cpu); 2827 /* Instead set up a multicast destination PGID for traffic copied to 2828 * the CPU. Whitelisted MAC addresses like the port netdevice MAC 2829 * addresses will be copied to the CPU via this PGID. 2830 */ 2831 ocelot_write_rix(ocelot, BIT(cpu), ANA_PGID_PGID, PGID_CPU); 2832 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_RECV_ENA | 2833 ANA_PORT_PORT_CFG_PORTID_VAL(cpu), 2834 ANA_PORT_PORT_CFG, cpu); 2835 2836 /* Enable CPU port module */ 2837 ocelot_fields_write(ocelot, cpu, QSYS_SWITCH_PORT_MODE_PORT_ENA, 1); 2838 /* CPU port Injection/Extraction configuration */ 2839 ocelot_fields_write(ocelot, cpu, SYS_PORT_MODE_INCL_XTR_HDR, 2840 OCELOT_TAG_PREFIX_NONE); 2841 ocelot_fields_write(ocelot, cpu, SYS_PORT_MODE_INCL_INJ_HDR, 2842 OCELOT_TAG_PREFIX_NONE); 2843 2844 /* Configure the CPU port to be VLAN aware */ 2845 ocelot_write_gix(ocelot, 2846 ANA_PORT_VLAN_CFG_VLAN_VID(OCELOT_STANDALONE_PVID) | 2847 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 2848 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1), 2849 ANA_PORT_VLAN_CFG, cpu); 2850 } 2851 2852 static void ocelot_detect_features(struct ocelot *ocelot) 2853 { 2854 int mmgt, eq_ctrl; 2855 2856 /* For Ocelot, Felix, Seville, Serval etc, SYS:MMGT:MMGT:FREECNT holds 2857 * the number of 240-byte free memory words (aka 4-cell chunks) and not 2858 * 192 bytes as the documentation incorrectly says. 2859 */ 2860 mmgt = ocelot_read(ocelot, SYS_MMGT); 2861 ocelot->packet_buffer_size = 240 * SYS_MMGT_FREECNT(mmgt); 2862 2863 eq_ctrl = ocelot_read(ocelot, QSYS_EQ_CTRL); 2864 ocelot->num_frame_refs = QSYS_MMGT_EQ_CTRL_FP_FREE_CNT(eq_ctrl); 2865 } 2866 2867 static int ocelot_mem_init_status(struct ocelot *ocelot) 2868 { 2869 unsigned int val; 2870 int err; 2871 2872 err = regmap_field_read(ocelot->regfields[SYS_RESET_CFG_MEM_INIT], 2873 &val); 2874 2875 return err ?: val; 2876 } 2877 2878 int ocelot_reset(struct ocelot *ocelot) 2879 { 2880 int err; 2881 u32 val; 2882 2883 err = regmap_field_write(ocelot->regfields[SYS_RESET_CFG_MEM_INIT], 1); 2884 if (err) 2885 return err; 2886 2887 err = regmap_field_write(ocelot->regfields[SYS_RESET_CFG_MEM_ENA], 1); 2888 if (err) 2889 return err; 2890 2891 /* MEM_INIT is a self-clearing bit. Wait for it to be cleared (should be 2892 * 100us) before enabling the switch core. 2893 */ 2894 err = readx_poll_timeout(ocelot_mem_init_status, ocelot, val, !val, 2895 MEM_INIT_SLEEP_US, MEM_INIT_TIMEOUT_US); 2896 if (err) 2897 return err; 2898 2899 err = regmap_field_write(ocelot->regfields[SYS_RESET_CFG_MEM_ENA], 1); 2900 if (err) 2901 return err; 2902 2903 return regmap_field_write(ocelot->regfields[SYS_RESET_CFG_CORE_ENA], 1); 2904 } 2905 EXPORT_SYMBOL(ocelot_reset); 2906 2907 int ocelot_init(struct ocelot *ocelot) 2908 { 2909 int i, ret; 2910 u32 port; 2911 2912 if (ocelot->ops->reset) { 2913 ret = ocelot->ops->reset(ocelot); 2914 if (ret) { 2915 dev_err(ocelot->dev, "Switch reset failed\n"); 2916 return ret; 2917 } 2918 } 2919 2920 mutex_init(&ocelot->ptp_lock); 2921 mutex_init(&ocelot->mact_lock); 2922 mutex_init(&ocelot->fwd_domain_lock); 2923 mutex_init(&ocelot->tas_lock); 2924 spin_lock_init(&ocelot->ptp_clock_lock); 2925 spin_lock_init(&ocelot->ts_id_lock); 2926 2927 ocelot->owq = alloc_ordered_workqueue("ocelot-owq", 0); 2928 if (!ocelot->owq) 2929 return -ENOMEM; 2930 2931 ret = ocelot_stats_init(ocelot); 2932 if (ret) 2933 goto err_stats_init; 2934 2935 INIT_LIST_HEAD(&ocelot->multicast); 2936 INIT_LIST_HEAD(&ocelot->pgids); 2937 INIT_LIST_HEAD(&ocelot->vlans); 2938 INIT_LIST_HEAD(&ocelot->lag_fdbs); 2939 ocelot_detect_features(ocelot); 2940 ocelot_mact_init(ocelot); 2941 ocelot_vlan_init(ocelot); 2942 ocelot_vcap_init(ocelot); 2943 ocelot_cpu_port_init(ocelot); 2944 2945 if (ocelot->ops->psfp_init) 2946 ocelot->ops->psfp_init(ocelot); 2947 2948 if (ocelot->mm_supported) { 2949 ret = ocelot_mm_init(ocelot); 2950 if (ret) 2951 goto err_mm_init; 2952 } 2953 2954 for (port = 0; port < ocelot->num_phys_ports; port++) { 2955 /* Clear all counters (5 groups) */ 2956 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(port) | 2957 SYS_STAT_CFG_STAT_CLEAR_SHOT(0x7f), 2958 SYS_STAT_CFG); 2959 } 2960 2961 /* Only use S-Tag */ 2962 ocelot_write(ocelot, ETH_P_8021AD, SYS_VLAN_ETYPE_CFG); 2963 2964 /* Aggregation mode */ 2965 ocelot_write(ocelot, ANA_AGGR_CFG_AC_SMAC_ENA | 2966 ANA_AGGR_CFG_AC_DMAC_ENA | 2967 ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA | 2968 ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA | 2969 ANA_AGGR_CFG_AC_IP6_FLOW_LBL_ENA | 2970 ANA_AGGR_CFG_AC_IP6_TCPUDP_ENA, 2971 ANA_AGGR_CFG); 2972 2973 /* Set MAC age time to default value. The entry is aged after 2974 * 2*AGE_PERIOD 2975 */ 2976 ocelot_write(ocelot, 2977 ANA_AUTOAGE_AGE_PERIOD(BR_DEFAULT_AGEING_TIME / 2 / HZ), 2978 ANA_AUTOAGE); 2979 2980 /* Disable learning for frames discarded by VLAN ingress filtering */ 2981 regmap_field_write(ocelot->regfields[ANA_ADVLEARN_VLAN_CHK], 1); 2982 2983 /* Setup frame ageing - fixed value "2 sec" - in 6.5 us units */ 2984 ocelot_write(ocelot, SYS_FRM_AGING_AGE_TX_ENA | 2985 SYS_FRM_AGING_MAX_AGE(307692), SYS_FRM_AGING); 2986 2987 /* Setup flooding PGIDs */ 2988 for (i = 0; i < ocelot->num_flooding_pgids; i++) 2989 ocelot_write_rix(ocelot, ANA_FLOODING_FLD_MULTICAST(PGID_MC) | 2990 ANA_FLOODING_FLD_BROADCAST(PGID_BC) | 2991 ANA_FLOODING_FLD_UNICAST(PGID_UC), 2992 ANA_FLOODING, i); 2993 ocelot_write(ocelot, ANA_FLOODING_IPMC_FLD_MC6_DATA(PGID_MCIPV6) | 2994 ANA_FLOODING_IPMC_FLD_MC6_CTRL(PGID_MC) | 2995 ANA_FLOODING_IPMC_FLD_MC4_DATA(PGID_MCIPV4) | 2996 ANA_FLOODING_IPMC_FLD_MC4_CTRL(PGID_MC), 2997 ANA_FLOODING_IPMC); 2998 2999 for (port = 0; port < ocelot->num_phys_ports; port++) { 3000 /* Transmit the frame to the local port. */ 3001 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port); 3002 /* Do not forward BPDU frames to the front ports. */ 3003 ocelot_write_gix(ocelot, 3004 ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA(0xffff), 3005 ANA_PORT_CPU_FWD_BPDU_CFG, 3006 port); 3007 /* Ensure bridging is disabled */ 3008 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_SRC + port); 3009 } 3010 3011 for_each_nonreserved_multicast_dest_pgid(ocelot, i) { 3012 u32 val = ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports - 1, 0)); 3013 3014 ocelot_write_rix(ocelot, val, ANA_PGID_PGID, i); 3015 } 3016 3017 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_BLACKHOLE); 3018 3019 /* Allow broadcast and unknown L2 multicast to the CPU. */ 3020 ocelot_rmw_rix(ocelot, ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)), 3021 ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)), 3022 ANA_PGID_PGID, PGID_MC); 3023 ocelot_rmw_rix(ocelot, ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)), 3024 ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)), 3025 ANA_PGID_PGID, PGID_BC); 3026 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV4); 3027 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV6); 3028 3029 /* Allow manual injection via DEVCPU_QS registers, and byte swap these 3030 * registers endianness. 3031 */ 3032 ocelot_write_rix(ocelot, QS_INJ_GRP_CFG_BYTE_SWAP | 3033 QS_INJ_GRP_CFG_MODE(1), QS_INJ_GRP_CFG, 0); 3034 ocelot_write_rix(ocelot, QS_XTR_GRP_CFG_BYTE_SWAP | 3035 QS_XTR_GRP_CFG_MODE(1), QS_XTR_GRP_CFG, 0); 3036 ocelot_write(ocelot, ANA_CPUQ_CFG_CPUQ_MIRROR(2) | 3037 ANA_CPUQ_CFG_CPUQ_LRN(2) | 3038 ANA_CPUQ_CFG_CPUQ_MAC_COPY(2) | 3039 ANA_CPUQ_CFG_CPUQ_SRC_COPY(2) | 3040 ANA_CPUQ_CFG_CPUQ_LOCKED_PORTMOVE(2) | 3041 ANA_CPUQ_CFG_CPUQ_ALLBRIDGE(6) | 3042 ANA_CPUQ_CFG_CPUQ_IPMC_CTRL(6) | 3043 ANA_CPUQ_CFG_CPUQ_IGMP(6) | 3044 ANA_CPUQ_CFG_CPUQ_MLD(6), ANA_CPUQ_CFG); 3045 for (i = 0; i < 16; i++) 3046 ocelot_write_rix(ocelot, ANA_CPUQ_8021_CFG_CPUQ_GARP_VAL(6) | 3047 ANA_CPUQ_8021_CFG_CPUQ_BPDU_VAL(6), 3048 ANA_CPUQ_8021_CFG, i); 3049 3050 return 0; 3051 3052 err_mm_init: 3053 ocelot_stats_deinit(ocelot); 3054 err_stats_init: 3055 destroy_workqueue(ocelot->owq); 3056 return ret; 3057 } 3058 EXPORT_SYMBOL(ocelot_init); 3059 3060 void ocelot_deinit(struct ocelot *ocelot) 3061 { 3062 ocelot_stats_deinit(ocelot); 3063 destroy_workqueue(ocelot->owq); 3064 } 3065 EXPORT_SYMBOL(ocelot_deinit); 3066 3067 void ocelot_deinit_port(struct ocelot *ocelot, int port) 3068 { 3069 struct ocelot_port *ocelot_port = ocelot->ports[port]; 3070 3071 skb_queue_purge(&ocelot_port->tx_skbs); 3072 } 3073 EXPORT_SYMBOL(ocelot_deinit_port); 3074 3075 MODULE_LICENSE("Dual MIT/GPL"); 3076