1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* 3 * Microsemi Ocelot Switch driver 4 * 5 * Copyright (c) 2017 Microsemi Corporation 6 */ 7 #include <linux/dsa/ocelot.h> 8 #include <linux/if_bridge.h> 9 #include <linux/ptp_classify.h> 10 #include <soc/mscc/ocelot_vcap.h> 11 #include "ocelot.h" 12 #include "ocelot_vcap.h" 13 14 #define TABLE_UPDATE_SLEEP_US 10 15 #define TABLE_UPDATE_TIMEOUT_US 100000 16 17 struct ocelot_mact_entry { 18 u8 mac[ETH_ALEN]; 19 u16 vid; 20 enum macaccess_entry_type type; 21 }; 22 23 /* Caller must hold &ocelot->mact_lock */ 24 static inline u32 ocelot_mact_read_macaccess(struct ocelot *ocelot) 25 { 26 return ocelot_read(ocelot, ANA_TABLES_MACACCESS); 27 } 28 29 /* Caller must hold &ocelot->mact_lock */ 30 static inline int ocelot_mact_wait_for_completion(struct ocelot *ocelot) 31 { 32 u32 val; 33 34 return readx_poll_timeout(ocelot_mact_read_macaccess, 35 ocelot, val, 36 (val & ANA_TABLES_MACACCESS_MAC_TABLE_CMD_M) == 37 MACACCESS_CMD_IDLE, 38 TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US); 39 } 40 41 /* Caller must hold &ocelot->mact_lock */ 42 static void ocelot_mact_select(struct ocelot *ocelot, 43 const unsigned char mac[ETH_ALEN], 44 unsigned int vid) 45 { 46 u32 macl = 0, mach = 0; 47 48 /* Set the MAC address to handle and the vlan associated in a format 49 * understood by the hardware. 50 */ 51 mach |= vid << 16; 52 mach |= mac[0] << 8; 53 mach |= mac[1] << 0; 54 macl |= mac[2] << 24; 55 macl |= mac[3] << 16; 56 macl |= mac[4] << 8; 57 macl |= mac[5] << 0; 58 59 ocelot_write(ocelot, macl, ANA_TABLES_MACLDATA); 60 ocelot_write(ocelot, mach, ANA_TABLES_MACHDATA); 61 62 } 63 64 static int __ocelot_mact_learn(struct ocelot *ocelot, int port, 65 const unsigned char mac[ETH_ALEN], 66 unsigned int vid, enum macaccess_entry_type type) 67 { 68 u32 cmd = ANA_TABLES_MACACCESS_VALID | 69 ANA_TABLES_MACACCESS_DEST_IDX(port) | 70 ANA_TABLES_MACACCESS_ENTRYTYPE(type) | 71 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_LEARN); 72 unsigned int mc_ports; 73 int err; 74 75 /* Set MAC_CPU_COPY if the CPU port is used by a multicast entry */ 76 if (type == ENTRYTYPE_MACv4) 77 mc_ports = (mac[1] << 8) | mac[2]; 78 else if (type == ENTRYTYPE_MACv6) 79 mc_ports = (mac[0] << 8) | mac[1]; 80 else 81 mc_ports = 0; 82 83 if (mc_ports & BIT(ocelot->num_phys_ports)) 84 cmd |= ANA_TABLES_MACACCESS_MAC_CPU_COPY; 85 86 ocelot_mact_select(ocelot, mac, vid); 87 88 /* Issue a write command */ 89 ocelot_write(ocelot, cmd, ANA_TABLES_MACACCESS); 90 91 err = ocelot_mact_wait_for_completion(ocelot); 92 93 return err; 94 } 95 96 int ocelot_mact_learn(struct ocelot *ocelot, int port, 97 const unsigned char mac[ETH_ALEN], 98 unsigned int vid, enum macaccess_entry_type type) 99 { 100 int ret; 101 102 mutex_lock(&ocelot->mact_lock); 103 ret = __ocelot_mact_learn(ocelot, port, mac, vid, type); 104 mutex_unlock(&ocelot->mact_lock); 105 106 return ret; 107 } 108 EXPORT_SYMBOL(ocelot_mact_learn); 109 110 int ocelot_mact_forget(struct ocelot *ocelot, 111 const unsigned char mac[ETH_ALEN], unsigned int vid) 112 { 113 int err; 114 115 mutex_lock(&ocelot->mact_lock); 116 117 ocelot_mact_select(ocelot, mac, vid); 118 119 /* Issue a forget command */ 120 ocelot_write(ocelot, 121 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_FORGET), 122 ANA_TABLES_MACACCESS); 123 124 err = ocelot_mact_wait_for_completion(ocelot); 125 126 mutex_unlock(&ocelot->mact_lock); 127 128 return err; 129 } 130 EXPORT_SYMBOL(ocelot_mact_forget); 131 132 int ocelot_mact_lookup(struct ocelot *ocelot, int *dst_idx, 133 const unsigned char mac[ETH_ALEN], 134 unsigned int vid, enum macaccess_entry_type *type) 135 { 136 int val; 137 138 mutex_lock(&ocelot->mact_lock); 139 140 ocelot_mact_select(ocelot, mac, vid); 141 142 /* Issue a read command with MACACCESS_VALID=1. */ 143 ocelot_write(ocelot, ANA_TABLES_MACACCESS_VALID | 144 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_READ), 145 ANA_TABLES_MACACCESS); 146 147 if (ocelot_mact_wait_for_completion(ocelot)) { 148 mutex_unlock(&ocelot->mact_lock); 149 return -ETIMEDOUT; 150 } 151 152 /* Read back the entry flags */ 153 val = ocelot_read(ocelot, ANA_TABLES_MACACCESS); 154 155 mutex_unlock(&ocelot->mact_lock); 156 157 if (!(val & ANA_TABLES_MACACCESS_VALID)) 158 return -ENOENT; 159 160 *dst_idx = ANA_TABLES_MACACCESS_DEST_IDX_X(val); 161 *type = ANA_TABLES_MACACCESS_ENTRYTYPE_X(val); 162 163 return 0; 164 } 165 EXPORT_SYMBOL(ocelot_mact_lookup); 166 167 int ocelot_mact_learn_streamdata(struct ocelot *ocelot, int dst_idx, 168 const unsigned char mac[ETH_ALEN], 169 unsigned int vid, 170 enum macaccess_entry_type type, 171 int sfid, int ssid) 172 { 173 int ret; 174 175 mutex_lock(&ocelot->mact_lock); 176 177 ocelot_write(ocelot, 178 (sfid < 0 ? 0 : ANA_TABLES_STREAMDATA_SFID_VALID) | 179 ANA_TABLES_STREAMDATA_SFID(sfid) | 180 (ssid < 0 ? 0 : ANA_TABLES_STREAMDATA_SSID_VALID) | 181 ANA_TABLES_STREAMDATA_SSID(ssid), 182 ANA_TABLES_STREAMDATA); 183 184 ret = __ocelot_mact_learn(ocelot, dst_idx, mac, vid, type); 185 186 mutex_unlock(&ocelot->mact_lock); 187 188 return ret; 189 } 190 EXPORT_SYMBOL(ocelot_mact_learn_streamdata); 191 192 static void ocelot_mact_init(struct ocelot *ocelot) 193 { 194 /* Configure the learning mode entries attributes: 195 * - Do not copy the frame to the CPU extraction queues. 196 * - Use the vlan and mac_cpoy for dmac lookup. 197 */ 198 ocelot_rmw(ocelot, 0, 199 ANA_AGENCTRL_LEARN_CPU_COPY | ANA_AGENCTRL_IGNORE_DMAC_FLAGS 200 | ANA_AGENCTRL_LEARN_FWD_KILL 201 | ANA_AGENCTRL_LEARN_IGNORE_VLAN, 202 ANA_AGENCTRL); 203 204 /* Clear the MAC table. We are not concurrent with anyone, so 205 * holding &ocelot->mact_lock is pointless. 206 */ 207 ocelot_write(ocelot, MACACCESS_CMD_INIT, ANA_TABLES_MACACCESS); 208 } 209 210 static void ocelot_vcap_enable(struct ocelot *ocelot, int port) 211 { 212 ocelot_write_gix(ocelot, ANA_PORT_VCAP_S2_CFG_S2_ENA | 213 ANA_PORT_VCAP_S2_CFG_S2_IP6_CFG(0xa), 214 ANA_PORT_VCAP_S2_CFG, port); 215 216 ocelot_write_gix(ocelot, ANA_PORT_VCAP_CFG_S1_ENA, 217 ANA_PORT_VCAP_CFG, port); 218 219 ocelot_rmw_gix(ocelot, REW_PORT_CFG_ES0_EN, 220 REW_PORT_CFG_ES0_EN, 221 REW_PORT_CFG, port); 222 } 223 224 static inline u32 ocelot_vlant_read_vlanaccess(struct ocelot *ocelot) 225 { 226 return ocelot_read(ocelot, ANA_TABLES_VLANACCESS); 227 } 228 229 static inline int ocelot_vlant_wait_for_completion(struct ocelot *ocelot) 230 { 231 u32 val; 232 233 return readx_poll_timeout(ocelot_vlant_read_vlanaccess, 234 ocelot, 235 val, 236 (val & ANA_TABLES_VLANACCESS_VLAN_TBL_CMD_M) == 237 ANA_TABLES_VLANACCESS_CMD_IDLE, 238 TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US); 239 } 240 241 static int ocelot_vlant_set_mask(struct ocelot *ocelot, u16 vid, u32 mask) 242 { 243 /* Select the VID to configure */ 244 ocelot_write(ocelot, ANA_TABLES_VLANTIDX_V_INDEX(vid), 245 ANA_TABLES_VLANTIDX); 246 /* Set the vlan port members mask and issue a write command */ 247 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_VLAN_PORT_MASK(mask) | 248 ANA_TABLES_VLANACCESS_CMD_WRITE, 249 ANA_TABLES_VLANACCESS); 250 251 return ocelot_vlant_wait_for_completion(ocelot); 252 } 253 254 static int ocelot_port_num_untagged_vlans(struct ocelot *ocelot, int port) 255 { 256 struct ocelot_bridge_vlan *vlan; 257 int num_untagged = 0; 258 259 list_for_each_entry(vlan, &ocelot->vlans, list) { 260 if (!(vlan->portmask & BIT(port))) 261 continue; 262 263 if (vlan->untagged & BIT(port)) 264 num_untagged++; 265 } 266 267 return num_untagged; 268 } 269 270 static int ocelot_port_num_tagged_vlans(struct ocelot *ocelot, int port) 271 { 272 struct ocelot_bridge_vlan *vlan; 273 int num_tagged = 0; 274 275 list_for_each_entry(vlan, &ocelot->vlans, list) { 276 if (!(vlan->portmask & BIT(port))) 277 continue; 278 279 if (!(vlan->untagged & BIT(port))) 280 num_tagged++; 281 } 282 283 return num_tagged; 284 } 285 286 /* We use native VLAN when we have to mix egress-tagged VLANs with exactly 287 * _one_ egress-untagged VLAN (_the_ native VLAN) 288 */ 289 static bool ocelot_port_uses_native_vlan(struct ocelot *ocelot, int port) 290 { 291 return ocelot_port_num_tagged_vlans(ocelot, port) && 292 ocelot_port_num_untagged_vlans(ocelot, port) == 1; 293 } 294 295 static struct ocelot_bridge_vlan * 296 ocelot_port_find_native_vlan(struct ocelot *ocelot, int port) 297 { 298 struct ocelot_bridge_vlan *vlan; 299 300 list_for_each_entry(vlan, &ocelot->vlans, list) 301 if (vlan->portmask & BIT(port) && vlan->untagged & BIT(port)) 302 return vlan; 303 304 return NULL; 305 } 306 307 /* Keep in sync REW_TAG_CFG_TAG_CFG and, if applicable, 308 * REW_PORT_VLAN_CFG_PORT_VID, with the bridge VLAN table and VLAN awareness 309 * state of the port. 310 */ 311 static void ocelot_port_manage_port_tag(struct ocelot *ocelot, int port) 312 { 313 struct ocelot_port *ocelot_port = ocelot->ports[port]; 314 enum ocelot_port_tag_config tag_cfg; 315 bool uses_native_vlan = false; 316 317 if (ocelot_port->vlan_aware) { 318 uses_native_vlan = ocelot_port_uses_native_vlan(ocelot, port); 319 320 if (uses_native_vlan) 321 tag_cfg = OCELOT_PORT_TAG_NATIVE; 322 else if (ocelot_port_num_untagged_vlans(ocelot, port)) 323 tag_cfg = OCELOT_PORT_TAG_DISABLED; 324 else 325 tag_cfg = OCELOT_PORT_TAG_TRUNK; 326 } else { 327 tag_cfg = OCELOT_PORT_TAG_DISABLED; 328 } 329 330 ocelot_rmw_gix(ocelot, REW_TAG_CFG_TAG_CFG(tag_cfg), 331 REW_TAG_CFG_TAG_CFG_M, 332 REW_TAG_CFG, port); 333 334 if (uses_native_vlan) { 335 struct ocelot_bridge_vlan *native_vlan; 336 337 /* Not having a native VLAN is impossible, because 338 * ocelot_port_num_untagged_vlans has returned 1. 339 * So there is no use in checking for NULL here. 340 */ 341 native_vlan = ocelot_port_find_native_vlan(ocelot, port); 342 343 ocelot_rmw_gix(ocelot, 344 REW_PORT_VLAN_CFG_PORT_VID(native_vlan->vid), 345 REW_PORT_VLAN_CFG_PORT_VID_M, 346 REW_PORT_VLAN_CFG, port); 347 } 348 } 349 350 /* Default vlan to clasify for untagged frames (may be zero) */ 351 static void ocelot_port_set_pvid(struct ocelot *ocelot, int port, 352 const struct ocelot_bridge_vlan *pvid_vlan) 353 { 354 struct ocelot_port *ocelot_port = ocelot->ports[port]; 355 u16 pvid = OCELOT_VLAN_UNAWARE_PVID; 356 u32 val = 0; 357 358 ocelot_port->pvid_vlan = pvid_vlan; 359 360 if (ocelot_port->vlan_aware && pvid_vlan) 361 pvid = pvid_vlan->vid; 362 363 ocelot_rmw_gix(ocelot, 364 ANA_PORT_VLAN_CFG_VLAN_VID(pvid), 365 ANA_PORT_VLAN_CFG_VLAN_VID_M, 366 ANA_PORT_VLAN_CFG, port); 367 368 /* If there's no pvid, we should drop not only untagged traffic (which 369 * happens automatically), but also 802.1p traffic which gets 370 * classified to VLAN 0, but that is always in our RX filter, so it 371 * would get accepted were it not for this setting. 372 */ 373 if (!pvid_vlan && ocelot_port->vlan_aware) 374 val = ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA | 375 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA; 376 377 ocelot_rmw_gix(ocelot, val, 378 ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA | 379 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA, 380 ANA_PORT_DROP_CFG, port); 381 } 382 383 static struct ocelot_bridge_vlan *ocelot_bridge_vlan_find(struct ocelot *ocelot, 384 u16 vid) 385 { 386 struct ocelot_bridge_vlan *vlan; 387 388 list_for_each_entry(vlan, &ocelot->vlans, list) 389 if (vlan->vid == vid) 390 return vlan; 391 392 return NULL; 393 } 394 395 static int ocelot_vlan_member_add(struct ocelot *ocelot, int port, u16 vid, 396 bool untagged) 397 { 398 struct ocelot_bridge_vlan *vlan = ocelot_bridge_vlan_find(ocelot, vid); 399 unsigned long portmask; 400 int err; 401 402 if (vlan) { 403 portmask = vlan->portmask | BIT(port); 404 405 err = ocelot_vlant_set_mask(ocelot, vid, portmask); 406 if (err) 407 return err; 408 409 vlan->portmask = portmask; 410 /* Bridge VLANs can be overwritten with a different 411 * egress-tagging setting, so make sure to override an untagged 412 * with a tagged VID if that's going on. 413 */ 414 if (untagged) 415 vlan->untagged |= BIT(port); 416 else 417 vlan->untagged &= ~BIT(port); 418 419 return 0; 420 } 421 422 vlan = kzalloc(sizeof(*vlan), GFP_KERNEL); 423 if (!vlan) 424 return -ENOMEM; 425 426 portmask = BIT(port); 427 428 err = ocelot_vlant_set_mask(ocelot, vid, portmask); 429 if (err) { 430 kfree(vlan); 431 return err; 432 } 433 434 vlan->vid = vid; 435 vlan->portmask = portmask; 436 if (untagged) 437 vlan->untagged = BIT(port); 438 INIT_LIST_HEAD(&vlan->list); 439 list_add_tail(&vlan->list, &ocelot->vlans); 440 441 return 0; 442 } 443 444 static int ocelot_vlan_member_del(struct ocelot *ocelot, int port, u16 vid) 445 { 446 struct ocelot_bridge_vlan *vlan = ocelot_bridge_vlan_find(ocelot, vid); 447 unsigned long portmask; 448 int err; 449 450 if (!vlan) 451 return 0; 452 453 portmask = vlan->portmask & ~BIT(port); 454 455 err = ocelot_vlant_set_mask(ocelot, vid, portmask); 456 if (err) 457 return err; 458 459 vlan->portmask = portmask; 460 if (vlan->portmask) 461 return 0; 462 463 list_del(&vlan->list); 464 kfree(vlan); 465 466 return 0; 467 } 468 469 int ocelot_port_vlan_filtering(struct ocelot *ocelot, int port, 470 bool vlan_aware, struct netlink_ext_ack *extack) 471 { 472 struct ocelot_vcap_block *block = &ocelot->block[VCAP_IS1]; 473 struct ocelot_port *ocelot_port = ocelot->ports[port]; 474 struct ocelot_vcap_filter *filter; 475 u32 val; 476 477 list_for_each_entry(filter, &block->rules, list) { 478 if (filter->ingress_port_mask & BIT(port) && 479 filter->action.vid_replace_ena) { 480 NL_SET_ERR_MSG_MOD(extack, 481 "Cannot change VLAN state with vlan modify rules active"); 482 return -EBUSY; 483 } 484 } 485 486 ocelot_port->vlan_aware = vlan_aware; 487 488 if (vlan_aware) 489 val = ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 490 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1); 491 else 492 val = 0; 493 ocelot_rmw_gix(ocelot, val, 494 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 495 ANA_PORT_VLAN_CFG_VLAN_POP_CNT_M, 496 ANA_PORT_VLAN_CFG, port); 497 498 ocelot_port_set_pvid(ocelot, port, ocelot_port->pvid_vlan); 499 ocelot_port_manage_port_tag(ocelot, port); 500 501 return 0; 502 } 503 EXPORT_SYMBOL(ocelot_port_vlan_filtering); 504 505 int ocelot_vlan_prepare(struct ocelot *ocelot, int port, u16 vid, bool pvid, 506 bool untagged, struct netlink_ext_ack *extack) 507 { 508 if (untagged) { 509 /* We are adding an egress-tagged VLAN */ 510 if (ocelot_port_uses_native_vlan(ocelot, port)) { 511 NL_SET_ERR_MSG_MOD(extack, 512 "Port with egress-tagged VLANs cannot have more than one egress-untagged (native) VLAN"); 513 return -EBUSY; 514 } 515 } else { 516 /* We are adding an egress-tagged VLAN */ 517 if (ocelot_port_num_untagged_vlans(ocelot, port) > 1) { 518 NL_SET_ERR_MSG_MOD(extack, 519 "Port with more than one egress-untagged VLAN cannot have egress-tagged VLANs"); 520 return -EBUSY; 521 } 522 } 523 524 return 0; 525 } 526 EXPORT_SYMBOL(ocelot_vlan_prepare); 527 528 int ocelot_vlan_add(struct ocelot *ocelot, int port, u16 vid, bool pvid, 529 bool untagged) 530 { 531 int err; 532 533 err = ocelot_vlan_member_add(ocelot, port, vid, untagged); 534 if (err) 535 return err; 536 537 /* Default ingress vlan classification */ 538 if (pvid) 539 ocelot_port_set_pvid(ocelot, port, 540 ocelot_bridge_vlan_find(ocelot, vid)); 541 542 /* Untagged egress vlan clasification */ 543 ocelot_port_manage_port_tag(ocelot, port); 544 545 return 0; 546 } 547 EXPORT_SYMBOL(ocelot_vlan_add); 548 549 int ocelot_vlan_del(struct ocelot *ocelot, int port, u16 vid) 550 { 551 struct ocelot_port *ocelot_port = ocelot->ports[port]; 552 int err; 553 554 err = ocelot_vlan_member_del(ocelot, port, vid); 555 if (err) 556 return err; 557 558 /* Ingress */ 559 if (ocelot_port->pvid_vlan && ocelot_port->pvid_vlan->vid == vid) 560 ocelot_port_set_pvid(ocelot, port, NULL); 561 562 /* Egress */ 563 ocelot_port_manage_port_tag(ocelot, port); 564 565 return 0; 566 } 567 EXPORT_SYMBOL(ocelot_vlan_del); 568 569 static void ocelot_vlan_init(struct ocelot *ocelot) 570 { 571 unsigned long all_ports = GENMASK(ocelot->num_phys_ports - 1, 0); 572 u16 port, vid; 573 574 /* Clear VLAN table, by default all ports are members of all VLANs */ 575 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_CMD_INIT, 576 ANA_TABLES_VLANACCESS); 577 ocelot_vlant_wait_for_completion(ocelot); 578 579 /* Configure the port VLAN memberships */ 580 for (vid = 1; vid < VLAN_N_VID; vid++) 581 ocelot_vlant_set_mask(ocelot, vid, 0); 582 583 /* Because VLAN filtering is enabled, we need VID 0 to get untagged 584 * traffic. It is added automatically if 8021q module is loaded, but 585 * we can't rely on it since module may be not loaded. 586 */ 587 ocelot_vlant_set_mask(ocelot, OCELOT_VLAN_UNAWARE_PVID, all_ports); 588 589 /* Set vlan ingress filter mask to all ports but the CPU port by 590 * default. 591 */ 592 ocelot_write(ocelot, all_ports, ANA_VLANMASK); 593 594 for (port = 0; port < ocelot->num_phys_ports; port++) { 595 ocelot_write_gix(ocelot, 0, REW_PORT_VLAN_CFG, port); 596 ocelot_write_gix(ocelot, 0, REW_TAG_CFG, port); 597 } 598 } 599 600 static u32 ocelot_read_eq_avail(struct ocelot *ocelot, int port) 601 { 602 return ocelot_read_rix(ocelot, QSYS_SW_STATUS, port); 603 } 604 605 static int ocelot_port_flush(struct ocelot *ocelot, int port) 606 { 607 unsigned int pause_ena; 608 int err, val; 609 610 /* Disable dequeuing from the egress queues */ 611 ocelot_rmw_rix(ocelot, QSYS_PORT_MODE_DEQUEUE_DIS, 612 QSYS_PORT_MODE_DEQUEUE_DIS, 613 QSYS_PORT_MODE, port); 614 615 /* Disable flow control */ 616 ocelot_fields_read(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, &pause_ena); 617 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, 0); 618 619 /* Disable priority flow control */ 620 ocelot_fields_write(ocelot, port, 621 QSYS_SWITCH_PORT_MODE_TX_PFC_ENA, 0); 622 623 /* Wait at least the time it takes to receive a frame of maximum length 624 * at the port. 625 * Worst-case delays for 10 kilobyte jumbo frames are: 626 * 8 ms on a 10M port 627 * 800 μs on a 100M port 628 * 80 μs on a 1G port 629 * 32 μs on a 2.5G port 630 */ 631 usleep_range(8000, 10000); 632 633 /* Disable half duplex backpressure. */ 634 ocelot_rmw_rix(ocelot, 0, SYS_FRONT_PORT_MODE_HDX_MODE, 635 SYS_FRONT_PORT_MODE, port); 636 637 /* Flush the queues associated with the port. */ 638 ocelot_rmw_gix(ocelot, REW_PORT_CFG_FLUSH_ENA, REW_PORT_CFG_FLUSH_ENA, 639 REW_PORT_CFG, port); 640 641 /* Enable dequeuing from the egress queues. */ 642 ocelot_rmw_rix(ocelot, 0, QSYS_PORT_MODE_DEQUEUE_DIS, QSYS_PORT_MODE, 643 port); 644 645 /* Wait until flushing is complete. */ 646 err = read_poll_timeout(ocelot_read_eq_avail, val, !val, 647 100, 2000000, false, ocelot, port); 648 649 /* Clear flushing again. */ 650 ocelot_rmw_gix(ocelot, 0, REW_PORT_CFG_FLUSH_ENA, REW_PORT_CFG, port); 651 652 /* Re-enable flow control */ 653 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, pause_ena); 654 655 return err; 656 } 657 658 void ocelot_phylink_mac_link_down(struct ocelot *ocelot, int port, 659 unsigned int link_an_mode, 660 phy_interface_t interface, 661 unsigned long quirks) 662 { 663 struct ocelot_port *ocelot_port = ocelot->ports[port]; 664 int err; 665 666 ocelot_port->speed = SPEED_UNKNOWN; 667 668 ocelot_port_rmwl(ocelot_port, 0, DEV_MAC_ENA_CFG_RX_ENA, 669 DEV_MAC_ENA_CFG); 670 671 if (ocelot->ops->cut_through_fwd) { 672 mutex_lock(&ocelot->fwd_domain_lock); 673 ocelot->ops->cut_through_fwd(ocelot); 674 mutex_unlock(&ocelot->fwd_domain_lock); 675 } 676 677 ocelot_fields_write(ocelot, port, QSYS_SWITCH_PORT_MODE_PORT_ENA, 0); 678 679 err = ocelot_port_flush(ocelot, port); 680 if (err) 681 dev_err(ocelot->dev, "failed to flush port %d: %d\n", 682 port, err); 683 684 /* Put the port in reset. */ 685 if (interface != PHY_INTERFACE_MODE_QSGMII || 686 !(quirks & OCELOT_QUIRK_QSGMII_PORTS_MUST_BE_UP)) 687 ocelot_port_rmwl(ocelot_port, 688 DEV_CLOCK_CFG_MAC_TX_RST | 689 DEV_CLOCK_CFG_MAC_RX_RST, 690 DEV_CLOCK_CFG_MAC_TX_RST | 691 DEV_CLOCK_CFG_MAC_RX_RST, 692 DEV_CLOCK_CFG); 693 } 694 EXPORT_SYMBOL_GPL(ocelot_phylink_mac_link_down); 695 696 void ocelot_phylink_mac_link_up(struct ocelot *ocelot, int port, 697 struct phy_device *phydev, 698 unsigned int link_an_mode, 699 phy_interface_t interface, 700 int speed, int duplex, 701 bool tx_pause, bool rx_pause, 702 unsigned long quirks) 703 { 704 struct ocelot_port *ocelot_port = ocelot->ports[port]; 705 int mac_speed, mode = 0; 706 u32 mac_fc_cfg; 707 708 ocelot_port->speed = speed; 709 710 /* The MAC might be integrated in systems where the MAC speed is fixed 711 * and it's the PCS who is performing the rate adaptation, so we have 712 * to write "1000Mbps" into the LINK_SPEED field of DEV_CLOCK_CFG 713 * (which is also its default value). 714 */ 715 if ((quirks & OCELOT_QUIRK_PCS_PERFORMS_RATE_ADAPTATION) || 716 speed == SPEED_1000) { 717 mac_speed = OCELOT_SPEED_1000; 718 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA; 719 } else if (speed == SPEED_2500) { 720 mac_speed = OCELOT_SPEED_2500; 721 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA; 722 } else if (speed == SPEED_100) { 723 mac_speed = OCELOT_SPEED_100; 724 } else { 725 mac_speed = OCELOT_SPEED_10; 726 } 727 728 if (duplex == DUPLEX_FULL) 729 mode |= DEV_MAC_MODE_CFG_FDX_ENA; 730 731 ocelot_port_writel(ocelot_port, mode, DEV_MAC_MODE_CFG); 732 733 /* Take port out of reset by clearing the MAC_TX_RST, MAC_RX_RST and 734 * PORT_RST bits in DEV_CLOCK_CFG. 735 */ 736 ocelot_port_writel(ocelot_port, DEV_CLOCK_CFG_LINK_SPEED(mac_speed), 737 DEV_CLOCK_CFG); 738 739 switch (speed) { 740 case SPEED_10: 741 mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(OCELOT_SPEED_10); 742 break; 743 case SPEED_100: 744 mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(OCELOT_SPEED_100); 745 break; 746 case SPEED_1000: 747 case SPEED_2500: 748 mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(OCELOT_SPEED_1000); 749 break; 750 default: 751 dev_err(ocelot->dev, "Unsupported speed on port %d: %d\n", 752 port, speed); 753 return; 754 } 755 756 /* Handle RX pause in all cases, with 2500base-X this is used for rate 757 * adaptation. 758 */ 759 mac_fc_cfg |= SYS_MAC_FC_CFG_RX_FC_ENA; 760 761 if (tx_pause) 762 mac_fc_cfg |= SYS_MAC_FC_CFG_TX_FC_ENA | 763 SYS_MAC_FC_CFG_PAUSE_VAL_CFG(0xffff) | 764 SYS_MAC_FC_CFG_FC_LATENCY_CFG(0x7) | 765 SYS_MAC_FC_CFG_ZERO_PAUSE_ENA; 766 767 /* Flow control. Link speed is only used here to evaluate the time 768 * specification in incoming pause frames. 769 */ 770 ocelot_write_rix(ocelot, mac_fc_cfg, SYS_MAC_FC_CFG, port); 771 772 ocelot_write_rix(ocelot, 0, ANA_POL_FLOWC, port); 773 774 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, tx_pause); 775 776 /* Undo the effects of ocelot_phylink_mac_link_down: 777 * enable MAC module 778 */ 779 ocelot_port_writel(ocelot_port, DEV_MAC_ENA_CFG_RX_ENA | 780 DEV_MAC_ENA_CFG_TX_ENA, DEV_MAC_ENA_CFG); 781 782 /* If the port supports cut-through forwarding, update the masks before 783 * enabling forwarding on the port. 784 */ 785 if (ocelot->ops->cut_through_fwd) { 786 mutex_lock(&ocelot->fwd_domain_lock); 787 ocelot->ops->cut_through_fwd(ocelot); 788 mutex_unlock(&ocelot->fwd_domain_lock); 789 } 790 791 /* Core: Enable port for frame transfer */ 792 ocelot_fields_write(ocelot, port, 793 QSYS_SWITCH_PORT_MODE_PORT_ENA, 1); 794 } 795 EXPORT_SYMBOL_GPL(ocelot_phylink_mac_link_up); 796 797 static int ocelot_port_add_txtstamp_skb(struct ocelot *ocelot, int port, 798 struct sk_buff *clone) 799 { 800 struct ocelot_port *ocelot_port = ocelot->ports[port]; 801 unsigned long flags; 802 803 spin_lock_irqsave(&ocelot->ts_id_lock, flags); 804 805 if (ocelot_port->ptp_skbs_in_flight == OCELOT_MAX_PTP_ID || 806 ocelot->ptp_skbs_in_flight == OCELOT_PTP_FIFO_SIZE) { 807 spin_unlock_irqrestore(&ocelot->ts_id_lock, flags); 808 return -EBUSY; 809 } 810 811 skb_shinfo(clone)->tx_flags |= SKBTX_IN_PROGRESS; 812 /* Store timestamp ID in OCELOT_SKB_CB(clone)->ts_id */ 813 OCELOT_SKB_CB(clone)->ts_id = ocelot_port->ts_id; 814 815 ocelot_port->ts_id++; 816 if (ocelot_port->ts_id == OCELOT_MAX_PTP_ID) 817 ocelot_port->ts_id = 0; 818 819 ocelot_port->ptp_skbs_in_flight++; 820 ocelot->ptp_skbs_in_flight++; 821 822 skb_queue_tail(&ocelot_port->tx_skbs, clone); 823 824 spin_unlock_irqrestore(&ocelot->ts_id_lock, flags); 825 826 return 0; 827 } 828 829 static bool ocelot_ptp_is_onestep_sync(struct sk_buff *skb, 830 unsigned int ptp_class) 831 { 832 struct ptp_header *hdr; 833 u8 msgtype, twostep; 834 835 hdr = ptp_parse_header(skb, ptp_class); 836 if (!hdr) 837 return false; 838 839 msgtype = ptp_get_msgtype(hdr, ptp_class); 840 twostep = hdr->flag_field[0] & 0x2; 841 842 if (msgtype == PTP_MSGTYPE_SYNC && twostep == 0) 843 return true; 844 845 return false; 846 } 847 848 int ocelot_port_txtstamp_request(struct ocelot *ocelot, int port, 849 struct sk_buff *skb, 850 struct sk_buff **clone) 851 { 852 struct ocelot_port *ocelot_port = ocelot->ports[port]; 853 u8 ptp_cmd = ocelot_port->ptp_cmd; 854 unsigned int ptp_class; 855 int err; 856 857 /* Don't do anything if PTP timestamping not enabled */ 858 if (!ptp_cmd) 859 return 0; 860 861 ptp_class = ptp_classify_raw(skb); 862 if (ptp_class == PTP_CLASS_NONE) 863 return -EINVAL; 864 865 /* Store ptp_cmd in OCELOT_SKB_CB(skb)->ptp_cmd */ 866 if (ptp_cmd == IFH_REW_OP_ORIGIN_PTP) { 867 if (ocelot_ptp_is_onestep_sync(skb, ptp_class)) { 868 OCELOT_SKB_CB(skb)->ptp_cmd = ptp_cmd; 869 return 0; 870 } 871 872 /* Fall back to two-step timestamping */ 873 ptp_cmd = IFH_REW_OP_TWO_STEP_PTP; 874 } 875 876 if (ptp_cmd == IFH_REW_OP_TWO_STEP_PTP) { 877 *clone = skb_clone_sk(skb); 878 if (!(*clone)) 879 return -ENOMEM; 880 881 err = ocelot_port_add_txtstamp_skb(ocelot, port, *clone); 882 if (err) 883 return err; 884 885 OCELOT_SKB_CB(skb)->ptp_cmd = ptp_cmd; 886 OCELOT_SKB_CB(*clone)->ptp_class = ptp_class; 887 } 888 889 return 0; 890 } 891 EXPORT_SYMBOL(ocelot_port_txtstamp_request); 892 893 static void ocelot_get_hwtimestamp(struct ocelot *ocelot, 894 struct timespec64 *ts) 895 { 896 unsigned long flags; 897 u32 val; 898 899 spin_lock_irqsave(&ocelot->ptp_clock_lock, flags); 900 901 /* Read current PTP time to get seconds */ 902 val = ocelot_read_rix(ocelot, PTP_PIN_CFG, TOD_ACC_PIN); 903 904 val &= ~(PTP_PIN_CFG_SYNC | PTP_PIN_CFG_ACTION_MASK | PTP_PIN_CFG_DOM); 905 val |= PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_SAVE); 906 ocelot_write_rix(ocelot, val, PTP_PIN_CFG, TOD_ACC_PIN); 907 ts->tv_sec = ocelot_read_rix(ocelot, PTP_PIN_TOD_SEC_LSB, TOD_ACC_PIN); 908 909 /* Read packet HW timestamp from FIFO */ 910 val = ocelot_read(ocelot, SYS_PTP_TXSTAMP); 911 ts->tv_nsec = SYS_PTP_TXSTAMP_PTP_TXSTAMP(val); 912 913 /* Sec has incremented since the ts was registered */ 914 if ((ts->tv_sec & 0x1) != !!(val & SYS_PTP_TXSTAMP_PTP_TXSTAMP_SEC)) 915 ts->tv_sec--; 916 917 spin_unlock_irqrestore(&ocelot->ptp_clock_lock, flags); 918 } 919 920 static bool ocelot_validate_ptp_skb(struct sk_buff *clone, u16 seqid) 921 { 922 struct ptp_header *hdr; 923 924 hdr = ptp_parse_header(clone, OCELOT_SKB_CB(clone)->ptp_class); 925 if (WARN_ON(!hdr)) 926 return false; 927 928 return seqid == ntohs(hdr->sequence_id); 929 } 930 931 void ocelot_get_txtstamp(struct ocelot *ocelot) 932 { 933 int budget = OCELOT_PTP_QUEUE_SZ; 934 935 while (budget--) { 936 struct sk_buff *skb, *skb_tmp, *skb_match = NULL; 937 struct skb_shared_hwtstamps shhwtstamps; 938 u32 val, id, seqid, txport; 939 struct ocelot_port *port; 940 struct timespec64 ts; 941 unsigned long flags; 942 943 val = ocelot_read(ocelot, SYS_PTP_STATUS); 944 945 /* Check if a timestamp can be retrieved */ 946 if (!(val & SYS_PTP_STATUS_PTP_MESS_VLD)) 947 break; 948 949 WARN_ON(val & SYS_PTP_STATUS_PTP_OVFL); 950 951 /* Retrieve the ts ID and Tx port */ 952 id = SYS_PTP_STATUS_PTP_MESS_ID_X(val); 953 txport = SYS_PTP_STATUS_PTP_MESS_TXPORT_X(val); 954 seqid = SYS_PTP_STATUS_PTP_MESS_SEQ_ID(val); 955 956 port = ocelot->ports[txport]; 957 958 spin_lock(&ocelot->ts_id_lock); 959 port->ptp_skbs_in_flight--; 960 ocelot->ptp_skbs_in_flight--; 961 spin_unlock(&ocelot->ts_id_lock); 962 963 /* Retrieve its associated skb */ 964 try_again: 965 spin_lock_irqsave(&port->tx_skbs.lock, flags); 966 967 skb_queue_walk_safe(&port->tx_skbs, skb, skb_tmp) { 968 if (OCELOT_SKB_CB(skb)->ts_id != id) 969 continue; 970 __skb_unlink(skb, &port->tx_skbs); 971 skb_match = skb; 972 break; 973 } 974 975 spin_unlock_irqrestore(&port->tx_skbs.lock, flags); 976 977 if (WARN_ON(!skb_match)) 978 continue; 979 980 if (!ocelot_validate_ptp_skb(skb_match, seqid)) { 981 dev_err_ratelimited(ocelot->dev, 982 "port %d received stale TX timestamp for seqid %d, discarding\n", 983 txport, seqid); 984 dev_kfree_skb_any(skb); 985 goto try_again; 986 } 987 988 /* Get the h/w timestamp */ 989 ocelot_get_hwtimestamp(ocelot, &ts); 990 991 /* Set the timestamp into the skb */ 992 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 993 shhwtstamps.hwtstamp = ktime_set(ts.tv_sec, ts.tv_nsec); 994 skb_complete_tx_timestamp(skb_match, &shhwtstamps); 995 996 /* Next ts */ 997 ocelot_write(ocelot, SYS_PTP_NXT_PTP_NXT, SYS_PTP_NXT); 998 } 999 } 1000 EXPORT_SYMBOL(ocelot_get_txtstamp); 1001 1002 static int ocelot_rx_frame_word(struct ocelot *ocelot, u8 grp, bool ifh, 1003 u32 *rval) 1004 { 1005 u32 bytes_valid, val; 1006 1007 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 1008 if (val == XTR_NOT_READY) { 1009 if (ifh) 1010 return -EIO; 1011 1012 do { 1013 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 1014 } while (val == XTR_NOT_READY); 1015 } 1016 1017 switch (val) { 1018 case XTR_ABORT: 1019 return -EIO; 1020 case XTR_EOF_0: 1021 case XTR_EOF_1: 1022 case XTR_EOF_2: 1023 case XTR_EOF_3: 1024 case XTR_PRUNED: 1025 bytes_valid = XTR_VALID_BYTES(val); 1026 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 1027 if (val == XTR_ESCAPE) 1028 *rval = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 1029 else 1030 *rval = val; 1031 1032 return bytes_valid; 1033 case XTR_ESCAPE: 1034 *rval = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 1035 1036 return 4; 1037 default: 1038 *rval = val; 1039 1040 return 4; 1041 } 1042 } 1043 1044 static int ocelot_xtr_poll_xfh(struct ocelot *ocelot, int grp, u32 *xfh) 1045 { 1046 int i, err = 0; 1047 1048 for (i = 0; i < OCELOT_TAG_LEN / 4; i++) { 1049 err = ocelot_rx_frame_word(ocelot, grp, true, &xfh[i]); 1050 if (err != 4) 1051 return (err < 0) ? err : -EIO; 1052 } 1053 1054 return 0; 1055 } 1056 1057 void ocelot_ptp_rx_timestamp(struct ocelot *ocelot, struct sk_buff *skb, 1058 u64 timestamp) 1059 { 1060 struct skb_shared_hwtstamps *shhwtstamps; 1061 u64 tod_in_ns, full_ts_in_ns; 1062 struct timespec64 ts; 1063 1064 ocelot_ptp_gettime64(&ocelot->ptp_info, &ts); 1065 1066 tod_in_ns = ktime_set(ts.tv_sec, ts.tv_nsec); 1067 if ((tod_in_ns & 0xffffffff) < timestamp) 1068 full_ts_in_ns = (((tod_in_ns >> 32) - 1) << 32) | 1069 timestamp; 1070 else 1071 full_ts_in_ns = (tod_in_ns & GENMASK_ULL(63, 32)) | 1072 timestamp; 1073 1074 shhwtstamps = skb_hwtstamps(skb); 1075 memset(shhwtstamps, 0, sizeof(struct skb_shared_hwtstamps)); 1076 shhwtstamps->hwtstamp = full_ts_in_ns; 1077 } 1078 EXPORT_SYMBOL(ocelot_ptp_rx_timestamp); 1079 1080 int ocelot_xtr_poll_frame(struct ocelot *ocelot, int grp, struct sk_buff **nskb) 1081 { 1082 u64 timestamp, src_port, len; 1083 u32 xfh[OCELOT_TAG_LEN / 4]; 1084 struct net_device *dev; 1085 struct sk_buff *skb; 1086 int sz, buf_len; 1087 u32 val, *buf; 1088 int err; 1089 1090 err = ocelot_xtr_poll_xfh(ocelot, grp, xfh); 1091 if (err) 1092 return err; 1093 1094 ocelot_xfh_get_src_port(xfh, &src_port); 1095 ocelot_xfh_get_len(xfh, &len); 1096 ocelot_xfh_get_rew_val(xfh, ×tamp); 1097 1098 if (WARN_ON(src_port >= ocelot->num_phys_ports)) 1099 return -EINVAL; 1100 1101 dev = ocelot->ops->port_to_netdev(ocelot, src_port); 1102 if (!dev) 1103 return -EINVAL; 1104 1105 skb = netdev_alloc_skb(dev, len); 1106 if (unlikely(!skb)) { 1107 netdev_err(dev, "Unable to allocate sk_buff\n"); 1108 return -ENOMEM; 1109 } 1110 1111 buf_len = len - ETH_FCS_LEN; 1112 buf = (u32 *)skb_put(skb, buf_len); 1113 1114 len = 0; 1115 do { 1116 sz = ocelot_rx_frame_word(ocelot, grp, false, &val); 1117 if (sz < 0) { 1118 err = sz; 1119 goto out_free_skb; 1120 } 1121 *buf++ = val; 1122 len += sz; 1123 } while (len < buf_len); 1124 1125 /* Read the FCS */ 1126 sz = ocelot_rx_frame_word(ocelot, grp, false, &val); 1127 if (sz < 0) { 1128 err = sz; 1129 goto out_free_skb; 1130 } 1131 1132 /* Update the statistics if part of the FCS was read before */ 1133 len -= ETH_FCS_LEN - sz; 1134 1135 if (unlikely(dev->features & NETIF_F_RXFCS)) { 1136 buf = (u32 *)skb_put(skb, ETH_FCS_LEN); 1137 *buf = val; 1138 } 1139 1140 if (ocelot->ptp) 1141 ocelot_ptp_rx_timestamp(ocelot, skb, timestamp); 1142 1143 /* Everything we see on an interface that is in the HW bridge 1144 * has already been forwarded. 1145 */ 1146 if (ocelot->ports[src_port]->bridge) 1147 skb->offload_fwd_mark = 1; 1148 1149 skb->protocol = eth_type_trans(skb, dev); 1150 1151 *nskb = skb; 1152 1153 return 0; 1154 1155 out_free_skb: 1156 kfree_skb(skb); 1157 return err; 1158 } 1159 EXPORT_SYMBOL(ocelot_xtr_poll_frame); 1160 1161 bool ocelot_can_inject(struct ocelot *ocelot, int grp) 1162 { 1163 u32 val = ocelot_read(ocelot, QS_INJ_STATUS); 1164 1165 if (!(val & QS_INJ_STATUS_FIFO_RDY(BIT(grp)))) 1166 return false; 1167 if (val & QS_INJ_STATUS_WMARK_REACHED(BIT(grp))) 1168 return false; 1169 1170 return true; 1171 } 1172 EXPORT_SYMBOL(ocelot_can_inject); 1173 1174 void ocelot_ifh_port_set(void *ifh, int port, u32 rew_op, u32 vlan_tag) 1175 { 1176 ocelot_ifh_set_bypass(ifh, 1); 1177 ocelot_ifh_set_dest(ifh, BIT_ULL(port)); 1178 ocelot_ifh_set_tag_type(ifh, IFH_TAG_TYPE_C); 1179 if (vlan_tag) 1180 ocelot_ifh_set_vlan_tci(ifh, vlan_tag); 1181 if (rew_op) 1182 ocelot_ifh_set_rew_op(ifh, rew_op); 1183 } 1184 EXPORT_SYMBOL(ocelot_ifh_port_set); 1185 1186 void ocelot_port_inject_frame(struct ocelot *ocelot, int port, int grp, 1187 u32 rew_op, struct sk_buff *skb) 1188 { 1189 u32 ifh[OCELOT_TAG_LEN / 4] = {0}; 1190 unsigned int i, count, last; 1191 1192 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) | 1193 QS_INJ_CTRL_SOF, QS_INJ_CTRL, grp); 1194 1195 ocelot_ifh_port_set(ifh, port, rew_op, skb_vlan_tag_get(skb)); 1196 1197 for (i = 0; i < OCELOT_TAG_LEN / 4; i++) 1198 ocelot_write_rix(ocelot, ifh[i], QS_INJ_WR, grp); 1199 1200 count = DIV_ROUND_UP(skb->len, 4); 1201 last = skb->len % 4; 1202 for (i = 0; i < count; i++) 1203 ocelot_write_rix(ocelot, ((u32 *)skb->data)[i], QS_INJ_WR, grp); 1204 1205 /* Add padding */ 1206 while (i < (OCELOT_BUFFER_CELL_SZ / 4)) { 1207 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp); 1208 i++; 1209 } 1210 1211 /* Indicate EOF and valid bytes in last word */ 1212 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) | 1213 QS_INJ_CTRL_VLD_BYTES(skb->len < OCELOT_BUFFER_CELL_SZ ? 0 : last) | 1214 QS_INJ_CTRL_EOF, 1215 QS_INJ_CTRL, grp); 1216 1217 /* Add dummy CRC */ 1218 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp); 1219 skb_tx_timestamp(skb); 1220 1221 skb->dev->stats.tx_packets++; 1222 skb->dev->stats.tx_bytes += skb->len; 1223 } 1224 EXPORT_SYMBOL(ocelot_port_inject_frame); 1225 1226 void ocelot_drain_cpu_queue(struct ocelot *ocelot, int grp) 1227 { 1228 while (ocelot_read(ocelot, QS_XTR_DATA_PRESENT) & BIT(grp)) 1229 ocelot_read_rix(ocelot, QS_XTR_RD, grp); 1230 } 1231 EXPORT_SYMBOL(ocelot_drain_cpu_queue); 1232 1233 int ocelot_fdb_add(struct ocelot *ocelot, int port, 1234 const unsigned char *addr, u16 vid) 1235 { 1236 int pgid = port; 1237 1238 if (port == ocelot->npi) 1239 pgid = PGID_CPU; 1240 1241 return ocelot_mact_learn(ocelot, pgid, addr, vid, ENTRYTYPE_LOCKED); 1242 } 1243 EXPORT_SYMBOL(ocelot_fdb_add); 1244 1245 int ocelot_fdb_del(struct ocelot *ocelot, int port, 1246 const unsigned char *addr, u16 vid) 1247 { 1248 return ocelot_mact_forget(ocelot, addr, vid); 1249 } 1250 EXPORT_SYMBOL(ocelot_fdb_del); 1251 1252 int ocelot_port_fdb_do_dump(const unsigned char *addr, u16 vid, 1253 bool is_static, void *data) 1254 { 1255 struct ocelot_dump_ctx *dump = data; 1256 u32 portid = NETLINK_CB(dump->cb->skb).portid; 1257 u32 seq = dump->cb->nlh->nlmsg_seq; 1258 struct nlmsghdr *nlh; 1259 struct ndmsg *ndm; 1260 1261 if (dump->idx < dump->cb->args[2]) 1262 goto skip; 1263 1264 nlh = nlmsg_put(dump->skb, portid, seq, RTM_NEWNEIGH, 1265 sizeof(*ndm), NLM_F_MULTI); 1266 if (!nlh) 1267 return -EMSGSIZE; 1268 1269 ndm = nlmsg_data(nlh); 1270 ndm->ndm_family = AF_BRIDGE; 1271 ndm->ndm_pad1 = 0; 1272 ndm->ndm_pad2 = 0; 1273 ndm->ndm_flags = NTF_SELF; 1274 ndm->ndm_type = 0; 1275 ndm->ndm_ifindex = dump->dev->ifindex; 1276 ndm->ndm_state = is_static ? NUD_NOARP : NUD_REACHABLE; 1277 1278 if (nla_put(dump->skb, NDA_LLADDR, ETH_ALEN, addr)) 1279 goto nla_put_failure; 1280 1281 if (vid && nla_put_u16(dump->skb, NDA_VLAN, vid)) 1282 goto nla_put_failure; 1283 1284 nlmsg_end(dump->skb, nlh); 1285 1286 skip: 1287 dump->idx++; 1288 return 0; 1289 1290 nla_put_failure: 1291 nlmsg_cancel(dump->skb, nlh); 1292 return -EMSGSIZE; 1293 } 1294 EXPORT_SYMBOL(ocelot_port_fdb_do_dump); 1295 1296 /* Caller must hold &ocelot->mact_lock */ 1297 static int ocelot_mact_read(struct ocelot *ocelot, int port, int row, int col, 1298 struct ocelot_mact_entry *entry) 1299 { 1300 u32 val, dst, macl, mach; 1301 char mac[ETH_ALEN]; 1302 1303 /* Set row and column to read from */ 1304 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_M_INDEX, row); 1305 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_BUCKET, col); 1306 1307 /* Issue a read command */ 1308 ocelot_write(ocelot, 1309 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_READ), 1310 ANA_TABLES_MACACCESS); 1311 1312 if (ocelot_mact_wait_for_completion(ocelot)) 1313 return -ETIMEDOUT; 1314 1315 /* Read the entry flags */ 1316 val = ocelot_read(ocelot, ANA_TABLES_MACACCESS); 1317 if (!(val & ANA_TABLES_MACACCESS_VALID)) 1318 return -EINVAL; 1319 1320 /* If the entry read has another port configured as its destination, 1321 * do not report it. 1322 */ 1323 dst = (val & ANA_TABLES_MACACCESS_DEST_IDX_M) >> 3; 1324 if (dst != port) 1325 return -EINVAL; 1326 1327 /* Get the entry's MAC address and VLAN id */ 1328 macl = ocelot_read(ocelot, ANA_TABLES_MACLDATA); 1329 mach = ocelot_read(ocelot, ANA_TABLES_MACHDATA); 1330 1331 mac[0] = (mach >> 8) & 0xff; 1332 mac[1] = (mach >> 0) & 0xff; 1333 mac[2] = (macl >> 24) & 0xff; 1334 mac[3] = (macl >> 16) & 0xff; 1335 mac[4] = (macl >> 8) & 0xff; 1336 mac[5] = (macl >> 0) & 0xff; 1337 1338 entry->vid = (mach >> 16) & 0xfff; 1339 ether_addr_copy(entry->mac, mac); 1340 1341 return 0; 1342 } 1343 1344 int ocelot_fdb_dump(struct ocelot *ocelot, int port, 1345 dsa_fdb_dump_cb_t *cb, void *data) 1346 { 1347 int err = 0; 1348 int i, j; 1349 1350 /* We could take the lock just around ocelot_mact_read, but doing so 1351 * thousands of times in a row seems rather pointless and inefficient. 1352 */ 1353 mutex_lock(&ocelot->mact_lock); 1354 1355 /* Loop through all the mac tables entries. */ 1356 for (i = 0; i < ocelot->num_mact_rows; i++) { 1357 for (j = 0; j < 4; j++) { 1358 struct ocelot_mact_entry entry; 1359 bool is_static; 1360 1361 err = ocelot_mact_read(ocelot, port, i, j, &entry); 1362 /* If the entry is invalid (wrong port, invalid...), 1363 * skip it. 1364 */ 1365 if (err == -EINVAL) 1366 continue; 1367 else if (err) 1368 break; 1369 1370 is_static = (entry.type == ENTRYTYPE_LOCKED); 1371 1372 err = cb(entry.mac, entry.vid, is_static, data); 1373 if (err) 1374 break; 1375 } 1376 } 1377 1378 mutex_unlock(&ocelot->mact_lock); 1379 1380 return err; 1381 } 1382 EXPORT_SYMBOL(ocelot_fdb_dump); 1383 1384 static void ocelot_populate_l2_ptp_trap_key(struct ocelot_vcap_filter *trap) 1385 { 1386 trap->key_type = OCELOT_VCAP_KEY_ETYPE; 1387 *(__be16 *)trap->key.etype.etype.value = htons(ETH_P_1588); 1388 *(__be16 *)trap->key.etype.etype.mask = htons(0xffff); 1389 } 1390 1391 static void 1392 ocelot_populate_ipv4_ptp_event_trap_key(struct ocelot_vcap_filter *trap) 1393 { 1394 trap->key_type = OCELOT_VCAP_KEY_IPV4; 1395 trap->key.ipv4.dport.value = PTP_EV_PORT; 1396 trap->key.ipv4.dport.mask = 0xffff; 1397 } 1398 1399 static void 1400 ocelot_populate_ipv6_ptp_event_trap_key(struct ocelot_vcap_filter *trap) 1401 { 1402 trap->key_type = OCELOT_VCAP_KEY_IPV6; 1403 trap->key.ipv6.dport.value = PTP_EV_PORT; 1404 trap->key.ipv6.dport.mask = 0xffff; 1405 } 1406 1407 static void 1408 ocelot_populate_ipv4_ptp_general_trap_key(struct ocelot_vcap_filter *trap) 1409 { 1410 trap->key_type = OCELOT_VCAP_KEY_IPV4; 1411 trap->key.ipv4.dport.value = PTP_GEN_PORT; 1412 trap->key.ipv4.dport.mask = 0xffff; 1413 } 1414 1415 static void 1416 ocelot_populate_ipv6_ptp_general_trap_key(struct ocelot_vcap_filter *trap) 1417 { 1418 trap->key_type = OCELOT_VCAP_KEY_IPV6; 1419 trap->key.ipv6.dport.value = PTP_GEN_PORT; 1420 trap->key.ipv6.dport.mask = 0xffff; 1421 } 1422 1423 static int ocelot_trap_add(struct ocelot *ocelot, int port, 1424 unsigned long cookie, 1425 void (*populate)(struct ocelot_vcap_filter *f)) 1426 { 1427 struct ocelot_vcap_block *block_vcap_is2; 1428 struct ocelot_vcap_filter *trap; 1429 bool new = false; 1430 int err; 1431 1432 block_vcap_is2 = &ocelot->block[VCAP_IS2]; 1433 1434 trap = ocelot_vcap_block_find_filter_by_id(block_vcap_is2, cookie, 1435 false); 1436 if (!trap) { 1437 trap = kzalloc(sizeof(*trap), GFP_KERNEL); 1438 if (!trap) 1439 return -ENOMEM; 1440 1441 populate(trap); 1442 trap->prio = 1; 1443 trap->id.cookie = cookie; 1444 trap->id.tc_offload = false; 1445 trap->block_id = VCAP_IS2; 1446 trap->type = OCELOT_VCAP_FILTER_OFFLOAD; 1447 trap->lookup = 0; 1448 trap->action.cpu_copy_ena = true; 1449 trap->action.mask_mode = OCELOT_MASK_MODE_PERMIT_DENY; 1450 trap->action.port_mask = 0; 1451 new = true; 1452 } 1453 1454 trap->ingress_port_mask |= BIT(port); 1455 1456 if (new) 1457 err = ocelot_vcap_filter_add(ocelot, trap, NULL); 1458 else 1459 err = ocelot_vcap_filter_replace(ocelot, trap); 1460 if (err) { 1461 trap->ingress_port_mask &= ~BIT(port); 1462 if (!trap->ingress_port_mask) 1463 kfree(trap); 1464 return err; 1465 } 1466 1467 return 0; 1468 } 1469 1470 static int ocelot_trap_del(struct ocelot *ocelot, int port, 1471 unsigned long cookie) 1472 { 1473 struct ocelot_vcap_block *block_vcap_is2; 1474 struct ocelot_vcap_filter *trap; 1475 1476 block_vcap_is2 = &ocelot->block[VCAP_IS2]; 1477 1478 trap = ocelot_vcap_block_find_filter_by_id(block_vcap_is2, cookie, 1479 false); 1480 if (!trap) 1481 return 0; 1482 1483 trap->ingress_port_mask &= ~BIT(port); 1484 if (!trap->ingress_port_mask) 1485 return ocelot_vcap_filter_del(ocelot, trap); 1486 1487 return ocelot_vcap_filter_replace(ocelot, trap); 1488 } 1489 1490 static int ocelot_l2_ptp_trap_add(struct ocelot *ocelot, int port) 1491 { 1492 unsigned long l2_cookie = ocelot->num_phys_ports + 1; 1493 1494 return ocelot_trap_add(ocelot, port, l2_cookie, 1495 ocelot_populate_l2_ptp_trap_key); 1496 } 1497 1498 static int ocelot_l2_ptp_trap_del(struct ocelot *ocelot, int port) 1499 { 1500 unsigned long l2_cookie = ocelot->num_phys_ports + 1; 1501 1502 return ocelot_trap_del(ocelot, port, l2_cookie); 1503 } 1504 1505 static int ocelot_ipv4_ptp_trap_add(struct ocelot *ocelot, int port) 1506 { 1507 unsigned long ipv4_gen_cookie = ocelot->num_phys_ports + 2; 1508 unsigned long ipv4_ev_cookie = ocelot->num_phys_ports + 3; 1509 int err; 1510 1511 err = ocelot_trap_add(ocelot, port, ipv4_ev_cookie, 1512 ocelot_populate_ipv4_ptp_event_trap_key); 1513 if (err) 1514 return err; 1515 1516 err = ocelot_trap_add(ocelot, port, ipv4_gen_cookie, 1517 ocelot_populate_ipv4_ptp_general_trap_key); 1518 if (err) 1519 ocelot_trap_del(ocelot, port, ipv4_ev_cookie); 1520 1521 return err; 1522 } 1523 1524 static int ocelot_ipv4_ptp_trap_del(struct ocelot *ocelot, int port) 1525 { 1526 unsigned long ipv4_gen_cookie = ocelot->num_phys_ports + 2; 1527 unsigned long ipv4_ev_cookie = ocelot->num_phys_ports + 3; 1528 int err; 1529 1530 err = ocelot_trap_del(ocelot, port, ipv4_ev_cookie); 1531 err |= ocelot_trap_del(ocelot, port, ipv4_gen_cookie); 1532 return err; 1533 } 1534 1535 static int ocelot_ipv6_ptp_trap_add(struct ocelot *ocelot, int port) 1536 { 1537 unsigned long ipv6_gen_cookie = ocelot->num_phys_ports + 4; 1538 unsigned long ipv6_ev_cookie = ocelot->num_phys_ports + 5; 1539 int err; 1540 1541 err = ocelot_trap_add(ocelot, port, ipv6_ev_cookie, 1542 ocelot_populate_ipv6_ptp_event_trap_key); 1543 if (err) 1544 return err; 1545 1546 err = ocelot_trap_add(ocelot, port, ipv6_gen_cookie, 1547 ocelot_populate_ipv6_ptp_general_trap_key); 1548 if (err) 1549 ocelot_trap_del(ocelot, port, ipv6_ev_cookie); 1550 1551 return err; 1552 } 1553 1554 static int ocelot_ipv6_ptp_trap_del(struct ocelot *ocelot, int port) 1555 { 1556 unsigned long ipv6_gen_cookie = ocelot->num_phys_ports + 4; 1557 unsigned long ipv6_ev_cookie = ocelot->num_phys_ports + 5; 1558 int err; 1559 1560 err = ocelot_trap_del(ocelot, port, ipv6_ev_cookie); 1561 err |= ocelot_trap_del(ocelot, port, ipv6_gen_cookie); 1562 return err; 1563 } 1564 1565 static int ocelot_setup_ptp_traps(struct ocelot *ocelot, int port, 1566 bool l2, bool l4) 1567 { 1568 int err; 1569 1570 if (l2) 1571 err = ocelot_l2_ptp_trap_add(ocelot, port); 1572 else 1573 err = ocelot_l2_ptp_trap_del(ocelot, port); 1574 if (err) 1575 return err; 1576 1577 if (l4) { 1578 err = ocelot_ipv4_ptp_trap_add(ocelot, port); 1579 if (err) 1580 goto err_ipv4; 1581 1582 err = ocelot_ipv6_ptp_trap_add(ocelot, port); 1583 if (err) 1584 goto err_ipv6; 1585 } else { 1586 err = ocelot_ipv4_ptp_trap_del(ocelot, port); 1587 1588 err |= ocelot_ipv6_ptp_trap_del(ocelot, port); 1589 } 1590 if (err) 1591 return err; 1592 1593 return 0; 1594 1595 err_ipv6: 1596 ocelot_ipv4_ptp_trap_del(ocelot, port); 1597 err_ipv4: 1598 if (l2) 1599 ocelot_l2_ptp_trap_del(ocelot, port); 1600 return err; 1601 } 1602 1603 int ocelot_hwstamp_get(struct ocelot *ocelot, int port, struct ifreq *ifr) 1604 { 1605 return copy_to_user(ifr->ifr_data, &ocelot->hwtstamp_config, 1606 sizeof(ocelot->hwtstamp_config)) ? -EFAULT : 0; 1607 } 1608 EXPORT_SYMBOL(ocelot_hwstamp_get); 1609 1610 int ocelot_hwstamp_set(struct ocelot *ocelot, int port, struct ifreq *ifr) 1611 { 1612 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1613 bool l2 = false, l4 = false; 1614 struct hwtstamp_config cfg; 1615 int err; 1616 1617 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg))) 1618 return -EFAULT; 1619 1620 /* Tx type sanity check */ 1621 switch (cfg.tx_type) { 1622 case HWTSTAMP_TX_ON: 1623 ocelot_port->ptp_cmd = IFH_REW_OP_TWO_STEP_PTP; 1624 break; 1625 case HWTSTAMP_TX_ONESTEP_SYNC: 1626 /* IFH_REW_OP_ONE_STEP_PTP updates the correctional field, we 1627 * need to update the origin time. 1628 */ 1629 ocelot_port->ptp_cmd = IFH_REW_OP_ORIGIN_PTP; 1630 break; 1631 case HWTSTAMP_TX_OFF: 1632 ocelot_port->ptp_cmd = 0; 1633 break; 1634 default: 1635 return -ERANGE; 1636 } 1637 1638 mutex_lock(&ocelot->ptp_lock); 1639 1640 switch (cfg.rx_filter) { 1641 case HWTSTAMP_FILTER_NONE: 1642 break; 1643 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 1644 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 1645 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 1646 l4 = true; 1647 break; 1648 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 1649 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 1650 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 1651 l2 = true; 1652 break; 1653 case HWTSTAMP_FILTER_PTP_V2_EVENT: 1654 case HWTSTAMP_FILTER_PTP_V2_SYNC: 1655 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 1656 l2 = true; 1657 l4 = true; 1658 break; 1659 default: 1660 mutex_unlock(&ocelot->ptp_lock); 1661 return -ERANGE; 1662 } 1663 1664 err = ocelot_setup_ptp_traps(ocelot, port, l2, l4); 1665 if (err) { 1666 mutex_unlock(&ocelot->ptp_lock); 1667 return err; 1668 } 1669 1670 if (l2 && l4) 1671 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 1672 else if (l2) 1673 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT; 1674 else if (l4) 1675 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT; 1676 else 1677 cfg.rx_filter = HWTSTAMP_FILTER_NONE; 1678 1679 /* Commit back the result & save it */ 1680 memcpy(&ocelot->hwtstamp_config, &cfg, sizeof(cfg)); 1681 mutex_unlock(&ocelot->ptp_lock); 1682 1683 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 1684 } 1685 EXPORT_SYMBOL(ocelot_hwstamp_set); 1686 1687 void ocelot_get_strings(struct ocelot *ocelot, int port, u32 sset, u8 *data) 1688 { 1689 int i; 1690 1691 if (sset != ETH_SS_STATS) 1692 return; 1693 1694 for (i = 0; i < ocelot->num_stats; i++) 1695 memcpy(data + i * ETH_GSTRING_LEN, ocelot->stats_layout[i].name, 1696 ETH_GSTRING_LEN); 1697 } 1698 EXPORT_SYMBOL(ocelot_get_strings); 1699 1700 static void ocelot_update_stats(struct ocelot *ocelot) 1701 { 1702 int i, j; 1703 1704 mutex_lock(&ocelot->stats_lock); 1705 1706 for (i = 0; i < ocelot->num_phys_ports; i++) { 1707 /* Configure the port to read the stats from */ 1708 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(i), SYS_STAT_CFG); 1709 1710 for (j = 0; j < ocelot->num_stats; j++) { 1711 u32 val; 1712 unsigned int idx = i * ocelot->num_stats + j; 1713 1714 val = ocelot_read_rix(ocelot, SYS_COUNT_RX_OCTETS, 1715 ocelot->stats_layout[j].offset); 1716 1717 if (val < (ocelot->stats[idx] & U32_MAX)) 1718 ocelot->stats[idx] += (u64)1 << 32; 1719 1720 ocelot->stats[idx] = (ocelot->stats[idx] & 1721 ~(u64)U32_MAX) + val; 1722 } 1723 } 1724 1725 mutex_unlock(&ocelot->stats_lock); 1726 } 1727 1728 static void ocelot_check_stats_work(struct work_struct *work) 1729 { 1730 struct delayed_work *del_work = to_delayed_work(work); 1731 struct ocelot *ocelot = container_of(del_work, struct ocelot, 1732 stats_work); 1733 1734 ocelot_update_stats(ocelot); 1735 1736 queue_delayed_work(ocelot->stats_queue, &ocelot->stats_work, 1737 OCELOT_STATS_CHECK_DELAY); 1738 } 1739 1740 void ocelot_get_ethtool_stats(struct ocelot *ocelot, int port, u64 *data) 1741 { 1742 int i; 1743 1744 /* check and update now */ 1745 ocelot_update_stats(ocelot); 1746 1747 /* Copy all counters */ 1748 for (i = 0; i < ocelot->num_stats; i++) 1749 *data++ = ocelot->stats[port * ocelot->num_stats + i]; 1750 } 1751 EXPORT_SYMBOL(ocelot_get_ethtool_stats); 1752 1753 int ocelot_get_sset_count(struct ocelot *ocelot, int port, int sset) 1754 { 1755 if (sset != ETH_SS_STATS) 1756 return -EOPNOTSUPP; 1757 1758 return ocelot->num_stats; 1759 } 1760 EXPORT_SYMBOL(ocelot_get_sset_count); 1761 1762 int ocelot_get_ts_info(struct ocelot *ocelot, int port, 1763 struct ethtool_ts_info *info) 1764 { 1765 info->phc_index = ocelot->ptp_clock ? 1766 ptp_clock_index(ocelot->ptp_clock) : -1; 1767 if (info->phc_index == -1) { 1768 info->so_timestamping |= SOF_TIMESTAMPING_TX_SOFTWARE | 1769 SOF_TIMESTAMPING_RX_SOFTWARE | 1770 SOF_TIMESTAMPING_SOFTWARE; 1771 return 0; 1772 } 1773 info->so_timestamping |= SOF_TIMESTAMPING_TX_SOFTWARE | 1774 SOF_TIMESTAMPING_RX_SOFTWARE | 1775 SOF_TIMESTAMPING_SOFTWARE | 1776 SOF_TIMESTAMPING_TX_HARDWARE | 1777 SOF_TIMESTAMPING_RX_HARDWARE | 1778 SOF_TIMESTAMPING_RAW_HARDWARE; 1779 info->tx_types = BIT(HWTSTAMP_TX_OFF) | BIT(HWTSTAMP_TX_ON) | 1780 BIT(HWTSTAMP_TX_ONESTEP_SYNC); 1781 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) | 1782 BIT(HWTSTAMP_FILTER_PTP_V2_EVENT) | 1783 BIT(HWTSTAMP_FILTER_PTP_V2_L2_EVENT) | 1784 BIT(HWTSTAMP_FILTER_PTP_V2_L4_EVENT); 1785 1786 return 0; 1787 } 1788 EXPORT_SYMBOL(ocelot_get_ts_info); 1789 1790 static u32 ocelot_get_bond_mask(struct ocelot *ocelot, struct net_device *bond) 1791 { 1792 u32 mask = 0; 1793 int port; 1794 1795 for (port = 0; port < ocelot->num_phys_ports; port++) { 1796 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1797 1798 if (!ocelot_port) 1799 continue; 1800 1801 if (ocelot_port->bond == bond) 1802 mask |= BIT(port); 1803 } 1804 1805 return mask; 1806 } 1807 1808 u32 ocelot_get_bridge_fwd_mask(struct ocelot *ocelot, int src_port) 1809 { 1810 struct ocelot_port *ocelot_port = ocelot->ports[src_port]; 1811 const struct net_device *bridge; 1812 u32 mask = 0; 1813 int port; 1814 1815 if (!ocelot_port || ocelot_port->stp_state != BR_STATE_FORWARDING) 1816 return 0; 1817 1818 bridge = ocelot_port->bridge; 1819 if (!bridge) 1820 return 0; 1821 1822 for (port = 0; port < ocelot->num_phys_ports; port++) { 1823 ocelot_port = ocelot->ports[port]; 1824 1825 if (!ocelot_port) 1826 continue; 1827 1828 if (ocelot_port->stp_state == BR_STATE_FORWARDING && 1829 ocelot_port->bridge == bridge) 1830 mask |= BIT(port); 1831 } 1832 1833 return mask; 1834 } 1835 EXPORT_SYMBOL_GPL(ocelot_get_bridge_fwd_mask); 1836 1837 u32 ocelot_get_dsa_8021q_cpu_mask(struct ocelot *ocelot) 1838 { 1839 u32 mask = 0; 1840 int port; 1841 1842 for (port = 0; port < ocelot->num_phys_ports; port++) { 1843 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1844 1845 if (!ocelot_port) 1846 continue; 1847 1848 if (ocelot_port->is_dsa_8021q_cpu) 1849 mask |= BIT(port); 1850 } 1851 1852 return mask; 1853 } 1854 EXPORT_SYMBOL_GPL(ocelot_get_dsa_8021q_cpu_mask); 1855 1856 void ocelot_apply_bridge_fwd_mask(struct ocelot *ocelot, bool joining) 1857 { 1858 unsigned long cpu_fwd_mask; 1859 int port; 1860 1861 lockdep_assert_held(&ocelot->fwd_domain_lock); 1862 1863 /* If cut-through forwarding is supported, update the masks before a 1864 * port joins the forwarding domain, to avoid potential underruns if it 1865 * has the highest speed from the new domain. 1866 */ 1867 if (joining && ocelot->ops->cut_through_fwd) 1868 ocelot->ops->cut_through_fwd(ocelot); 1869 1870 /* If a DSA tag_8021q CPU exists, it needs to be included in the 1871 * regular forwarding path of the front ports regardless of whether 1872 * those are bridged or standalone. 1873 * If DSA tag_8021q is not used, this returns 0, which is fine because 1874 * the hardware-based CPU port module can be a destination for packets 1875 * even if it isn't part of PGID_SRC. 1876 */ 1877 cpu_fwd_mask = ocelot_get_dsa_8021q_cpu_mask(ocelot); 1878 1879 /* Apply FWD mask. The loop is needed to add/remove the current port as 1880 * a source for the other ports. 1881 */ 1882 for (port = 0; port < ocelot->num_phys_ports; port++) { 1883 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1884 unsigned long mask; 1885 1886 if (!ocelot_port) { 1887 /* Unused ports can't send anywhere */ 1888 mask = 0; 1889 } else if (ocelot_port->is_dsa_8021q_cpu) { 1890 /* The DSA tag_8021q CPU ports need to be able to 1891 * forward packets to all other ports except for 1892 * themselves 1893 */ 1894 mask = GENMASK(ocelot->num_phys_ports - 1, 0); 1895 mask &= ~cpu_fwd_mask; 1896 } else if (ocelot_port->bridge) { 1897 struct net_device *bond = ocelot_port->bond; 1898 1899 mask = ocelot_get_bridge_fwd_mask(ocelot, port); 1900 mask |= cpu_fwd_mask; 1901 mask &= ~BIT(port); 1902 if (bond) 1903 mask &= ~ocelot_get_bond_mask(ocelot, bond); 1904 } else { 1905 /* Standalone ports forward only to DSA tag_8021q CPU 1906 * ports (if those exist), or to the hardware CPU port 1907 * module otherwise. 1908 */ 1909 mask = cpu_fwd_mask; 1910 } 1911 1912 ocelot_write_rix(ocelot, mask, ANA_PGID_PGID, PGID_SRC + port); 1913 } 1914 1915 /* If cut-through forwarding is supported and a port is leaving, there 1916 * is a chance that cut-through was disabled on the other ports due to 1917 * the port which is leaving (it has a higher link speed). We need to 1918 * update the cut-through masks of the remaining ports no earlier than 1919 * after the port has left, to prevent underruns from happening between 1920 * the cut-through update and the forwarding domain update. 1921 */ 1922 if (!joining && ocelot->ops->cut_through_fwd) 1923 ocelot->ops->cut_through_fwd(ocelot); 1924 } 1925 EXPORT_SYMBOL(ocelot_apply_bridge_fwd_mask); 1926 1927 void ocelot_bridge_stp_state_set(struct ocelot *ocelot, int port, u8 state) 1928 { 1929 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1930 u32 learn_ena = 0; 1931 1932 mutex_lock(&ocelot->fwd_domain_lock); 1933 1934 ocelot_port->stp_state = state; 1935 1936 if ((state == BR_STATE_LEARNING || state == BR_STATE_FORWARDING) && 1937 ocelot_port->learn_ena) 1938 learn_ena = ANA_PORT_PORT_CFG_LEARN_ENA; 1939 1940 ocelot_rmw_gix(ocelot, learn_ena, ANA_PORT_PORT_CFG_LEARN_ENA, 1941 ANA_PORT_PORT_CFG, port); 1942 1943 ocelot_apply_bridge_fwd_mask(ocelot, state == BR_STATE_FORWARDING); 1944 1945 mutex_unlock(&ocelot->fwd_domain_lock); 1946 } 1947 EXPORT_SYMBOL(ocelot_bridge_stp_state_set); 1948 1949 void ocelot_set_ageing_time(struct ocelot *ocelot, unsigned int msecs) 1950 { 1951 unsigned int age_period = ANA_AUTOAGE_AGE_PERIOD(msecs / 2000); 1952 1953 /* Setting AGE_PERIOD to zero effectively disables automatic aging, 1954 * which is clearly not what our intention is. So avoid that. 1955 */ 1956 if (!age_period) 1957 age_period = 1; 1958 1959 ocelot_rmw(ocelot, age_period, ANA_AUTOAGE_AGE_PERIOD_M, ANA_AUTOAGE); 1960 } 1961 EXPORT_SYMBOL(ocelot_set_ageing_time); 1962 1963 static struct ocelot_multicast *ocelot_multicast_get(struct ocelot *ocelot, 1964 const unsigned char *addr, 1965 u16 vid) 1966 { 1967 struct ocelot_multicast *mc; 1968 1969 list_for_each_entry(mc, &ocelot->multicast, list) { 1970 if (ether_addr_equal(mc->addr, addr) && mc->vid == vid) 1971 return mc; 1972 } 1973 1974 return NULL; 1975 } 1976 1977 static enum macaccess_entry_type ocelot_classify_mdb(const unsigned char *addr) 1978 { 1979 if (addr[0] == 0x01 && addr[1] == 0x00 && addr[2] == 0x5e) 1980 return ENTRYTYPE_MACv4; 1981 if (addr[0] == 0x33 && addr[1] == 0x33) 1982 return ENTRYTYPE_MACv6; 1983 return ENTRYTYPE_LOCKED; 1984 } 1985 1986 static struct ocelot_pgid *ocelot_pgid_alloc(struct ocelot *ocelot, int index, 1987 unsigned long ports) 1988 { 1989 struct ocelot_pgid *pgid; 1990 1991 pgid = kzalloc(sizeof(*pgid), GFP_KERNEL); 1992 if (!pgid) 1993 return ERR_PTR(-ENOMEM); 1994 1995 pgid->ports = ports; 1996 pgid->index = index; 1997 refcount_set(&pgid->refcount, 1); 1998 list_add_tail(&pgid->list, &ocelot->pgids); 1999 2000 return pgid; 2001 } 2002 2003 static void ocelot_pgid_free(struct ocelot *ocelot, struct ocelot_pgid *pgid) 2004 { 2005 if (!refcount_dec_and_test(&pgid->refcount)) 2006 return; 2007 2008 list_del(&pgid->list); 2009 kfree(pgid); 2010 } 2011 2012 static struct ocelot_pgid *ocelot_mdb_get_pgid(struct ocelot *ocelot, 2013 const struct ocelot_multicast *mc) 2014 { 2015 struct ocelot_pgid *pgid; 2016 int index; 2017 2018 /* According to VSC7514 datasheet 3.9.1.5 IPv4 Multicast Entries and 2019 * 3.9.1.6 IPv6 Multicast Entries, "Instead of a lookup in the 2020 * destination mask table (PGID), the destination set is programmed as 2021 * part of the entry MAC address.", and the DEST_IDX is set to 0. 2022 */ 2023 if (mc->entry_type == ENTRYTYPE_MACv4 || 2024 mc->entry_type == ENTRYTYPE_MACv6) 2025 return ocelot_pgid_alloc(ocelot, 0, mc->ports); 2026 2027 list_for_each_entry(pgid, &ocelot->pgids, list) { 2028 /* When searching for a nonreserved multicast PGID, ignore the 2029 * dummy PGID of zero that we have for MACv4/MACv6 entries 2030 */ 2031 if (pgid->index && pgid->ports == mc->ports) { 2032 refcount_inc(&pgid->refcount); 2033 return pgid; 2034 } 2035 } 2036 2037 /* Search for a free index in the nonreserved multicast PGID area */ 2038 for_each_nonreserved_multicast_dest_pgid(ocelot, index) { 2039 bool used = false; 2040 2041 list_for_each_entry(pgid, &ocelot->pgids, list) { 2042 if (pgid->index == index) { 2043 used = true; 2044 break; 2045 } 2046 } 2047 2048 if (!used) 2049 return ocelot_pgid_alloc(ocelot, index, mc->ports); 2050 } 2051 2052 return ERR_PTR(-ENOSPC); 2053 } 2054 2055 static void ocelot_encode_ports_to_mdb(unsigned char *addr, 2056 struct ocelot_multicast *mc) 2057 { 2058 ether_addr_copy(addr, mc->addr); 2059 2060 if (mc->entry_type == ENTRYTYPE_MACv4) { 2061 addr[0] = 0; 2062 addr[1] = mc->ports >> 8; 2063 addr[2] = mc->ports & 0xff; 2064 } else if (mc->entry_type == ENTRYTYPE_MACv6) { 2065 addr[0] = mc->ports >> 8; 2066 addr[1] = mc->ports & 0xff; 2067 } 2068 } 2069 2070 int ocelot_port_mdb_add(struct ocelot *ocelot, int port, 2071 const struct switchdev_obj_port_mdb *mdb) 2072 { 2073 unsigned char addr[ETH_ALEN]; 2074 struct ocelot_multicast *mc; 2075 struct ocelot_pgid *pgid; 2076 u16 vid = mdb->vid; 2077 2078 if (port == ocelot->npi) 2079 port = ocelot->num_phys_ports; 2080 2081 mc = ocelot_multicast_get(ocelot, mdb->addr, vid); 2082 if (!mc) { 2083 /* New entry */ 2084 mc = devm_kzalloc(ocelot->dev, sizeof(*mc), GFP_KERNEL); 2085 if (!mc) 2086 return -ENOMEM; 2087 2088 mc->entry_type = ocelot_classify_mdb(mdb->addr); 2089 ether_addr_copy(mc->addr, mdb->addr); 2090 mc->vid = vid; 2091 2092 list_add_tail(&mc->list, &ocelot->multicast); 2093 } else { 2094 /* Existing entry. Clean up the current port mask from 2095 * hardware now, because we'll be modifying it. 2096 */ 2097 ocelot_pgid_free(ocelot, mc->pgid); 2098 ocelot_encode_ports_to_mdb(addr, mc); 2099 ocelot_mact_forget(ocelot, addr, vid); 2100 } 2101 2102 mc->ports |= BIT(port); 2103 2104 pgid = ocelot_mdb_get_pgid(ocelot, mc); 2105 if (IS_ERR(pgid)) { 2106 dev_err(ocelot->dev, 2107 "Cannot allocate PGID for mdb %pM vid %d\n", 2108 mc->addr, mc->vid); 2109 devm_kfree(ocelot->dev, mc); 2110 return PTR_ERR(pgid); 2111 } 2112 mc->pgid = pgid; 2113 2114 ocelot_encode_ports_to_mdb(addr, mc); 2115 2116 if (mc->entry_type != ENTRYTYPE_MACv4 && 2117 mc->entry_type != ENTRYTYPE_MACv6) 2118 ocelot_write_rix(ocelot, pgid->ports, ANA_PGID_PGID, 2119 pgid->index); 2120 2121 return ocelot_mact_learn(ocelot, pgid->index, addr, vid, 2122 mc->entry_type); 2123 } 2124 EXPORT_SYMBOL(ocelot_port_mdb_add); 2125 2126 int ocelot_port_mdb_del(struct ocelot *ocelot, int port, 2127 const struct switchdev_obj_port_mdb *mdb) 2128 { 2129 unsigned char addr[ETH_ALEN]; 2130 struct ocelot_multicast *mc; 2131 struct ocelot_pgid *pgid; 2132 u16 vid = mdb->vid; 2133 2134 if (port == ocelot->npi) 2135 port = ocelot->num_phys_ports; 2136 2137 mc = ocelot_multicast_get(ocelot, mdb->addr, vid); 2138 if (!mc) 2139 return -ENOENT; 2140 2141 ocelot_encode_ports_to_mdb(addr, mc); 2142 ocelot_mact_forget(ocelot, addr, vid); 2143 2144 ocelot_pgid_free(ocelot, mc->pgid); 2145 mc->ports &= ~BIT(port); 2146 if (!mc->ports) { 2147 list_del(&mc->list); 2148 devm_kfree(ocelot->dev, mc); 2149 return 0; 2150 } 2151 2152 /* We have a PGID with fewer ports now */ 2153 pgid = ocelot_mdb_get_pgid(ocelot, mc); 2154 if (IS_ERR(pgid)) 2155 return PTR_ERR(pgid); 2156 mc->pgid = pgid; 2157 2158 ocelot_encode_ports_to_mdb(addr, mc); 2159 2160 if (mc->entry_type != ENTRYTYPE_MACv4 && 2161 mc->entry_type != ENTRYTYPE_MACv6) 2162 ocelot_write_rix(ocelot, pgid->ports, ANA_PGID_PGID, 2163 pgid->index); 2164 2165 return ocelot_mact_learn(ocelot, pgid->index, addr, vid, 2166 mc->entry_type); 2167 } 2168 EXPORT_SYMBOL(ocelot_port_mdb_del); 2169 2170 void ocelot_port_bridge_join(struct ocelot *ocelot, int port, 2171 struct net_device *bridge) 2172 { 2173 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2174 2175 mutex_lock(&ocelot->fwd_domain_lock); 2176 2177 ocelot_port->bridge = bridge; 2178 2179 ocelot_apply_bridge_fwd_mask(ocelot, true); 2180 2181 mutex_unlock(&ocelot->fwd_domain_lock); 2182 } 2183 EXPORT_SYMBOL(ocelot_port_bridge_join); 2184 2185 void ocelot_port_bridge_leave(struct ocelot *ocelot, int port, 2186 struct net_device *bridge) 2187 { 2188 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2189 2190 mutex_lock(&ocelot->fwd_domain_lock); 2191 2192 ocelot_port->bridge = NULL; 2193 2194 ocelot_port_set_pvid(ocelot, port, NULL); 2195 ocelot_port_manage_port_tag(ocelot, port); 2196 ocelot_apply_bridge_fwd_mask(ocelot, false); 2197 2198 mutex_unlock(&ocelot->fwd_domain_lock); 2199 } 2200 EXPORT_SYMBOL(ocelot_port_bridge_leave); 2201 2202 static void ocelot_set_aggr_pgids(struct ocelot *ocelot) 2203 { 2204 unsigned long visited = GENMASK(ocelot->num_phys_ports - 1, 0); 2205 int i, port, lag; 2206 2207 /* Reset destination and aggregation PGIDS */ 2208 for_each_unicast_dest_pgid(ocelot, port) 2209 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port); 2210 2211 for_each_aggr_pgid(ocelot, i) 2212 ocelot_write_rix(ocelot, GENMASK(ocelot->num_phys_ports - 1, 0), 2213 ANA_PGID_PGID, i); 2214 2215 /* The visited ports bitmask holds the list of ports offloading any 2216 * bonding interface. Initially we mark all these ports as unvisited, 2217 * then every time we visit a port in this bitmask, we know that it is 2218 * the lowest numbered port, i.e. the one whose logical ID == physical 2219 * port ID == LAG ID. So we mark as visited all further ports in the 2220 * bitmask that are offloading the same bonding interface. This way, 2221 * we set up the aggregation PGIDs only once per bonding interface. 2222 */ 2223 for (port = 0; port < ocelot->num_phys_ports; port++) { 2224 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2225 2226 if (!ocelot_port || !ocelot_port->bond) 2227 continue; 2228 2229 visited &= ~BIT(port); 2230 } 2231 2232 /* Now, set PGIDs for each active LAG */ 2233 for (lag = 0; lag < ocelot->num_phys_ports; lag++) { 2234 struct net_device *bond = ocelot->ports[lag]->bond; 2235 int num_active_ports = 0; 2236 unsigned long bond_mask; 2237 u8 aggr_idx[16]; 2238 2239 if (!bond || (visited & BIT(lag))) 2240 continue; 2241 2242 bond_mask = ocelot_get_bond_mask(ocelot, bond); 2243 2244 for_each_set_bit(port, &bond_mask, ocelot->num_phys_ports) { 2245 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2246 2247 // Destination mask 2248 ocelot_write_rix(ocelot, bond_mask, 2249 ANA_PGID_PGID, port); 2250 2251 if (ocelot_port->lag_tx_active) 2252 aggr_idx[num_active_ports++] = port; 2253 } 2254 2255 for_each_aggr_pgid(ocelot, i) { 2256 u32 ac; 2257 2258 ac = ocelot_read_rix(ocelot, ANA_PGID_PGID, i); 2259 ac &= ~bond_mask; 2260 /* Don't do division by zero if there was no active 2261 * port. Just make all aggregation codes zero. 2262 */ 2263 if (num_active_ports) 2264 ac |= BIT(aggr_idx[i % num_active_ports]); 2265 ocelot_write_rix(ocelot, ac, ANA_PGID_PGID, i); 2266 } 2267 2268 /* Mark all ports in the same LAG as visited to avoid applying 2269 * the same config again. 2270 */ 2271 for (port = lag; port < ocelot->num_phys_ports; port++) { 2272 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2273 2274 if (!ocelot_port) 2275 continue; 2276 2277 if (ocelot_port->bond == bond) 2278 visited |= BIT(port); 2279 } 2280 } 2281 } 2282 2283 /* When offloading a bonding interface, the switch ports configured under the 2284 * same bond must have the same logical port ID, equal to the physical port ID 2285 * of the lowest numbered physical port in that bond. Otherwise, in standalone/ 2286 * bridged mode, each port has a logical port ID equal to its physical port ID. 2287 */ 2288 static void ocelot_setup_logical_port_ids(struct ocelot *ocelot) 2289 { 2290 int port; 2291 2292 for (port = 0; port < ocelot->num_phys_ports; port++) { 2293 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2294 struct net_device *bond; 2295 2296 if (!ocelot_port) 2297 continue; 2298 2299 bond = ocelot_port->bond; 2300 if (bond) { 2301 int lag = __ffs(ocelot_get_bond_mask(ocelot, bond)); 2302 2303 ocelot_rmw_gix(ocelot, 2304 ANA_PORT_PORT_CFG_PORTID_VAL(lag), 2305 ANA_PORT_PORT_CFG_PORTID_VAL_M, 2306 ANA_PORT_PORT_CFG, port); 2307 } else { 2308 ocelot_rmw_gix(ocelot, 2309 ANA_PORT_PORT_CFG_PORTID_VAL(port), 2310 ANA_PORT_PORT_CFG_PORTID_VAL_M, 2311 ANA_PORT_PORT_CFG, port); 2312 } 2313 } 2314 } 2315 2316 int ocelot_port_lag_join(struct ocelot *ocelot, int port, 2317 struct net_device *bond, 2318 struct netdev_lag_upper_info *info) 2319 { 2320 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) 2321 return -EOPNOTSUPP; 2322 2323 mutex_lock(&ocelot->fwd_domain_lock); 2324 2325 ocelot->ports[port]->bond = bond; 2326 2327 ocelot_setup_logical_port_ids(ocelot); 2328 ocelot_apply_bridge_fwd_mask(ocelot, true); 2329 ocelot_set_aggr_pgids(ocelot); 2330 2331 mutex_unlock(&ocelot->fwd_domain_lock); 2332 2333 return 0; 2334 } 2335 EXPORT_SYMBOL(ocelot_port_lag_join); 2336 2337 void ocelot_port_lag_leave(struct ocelot *ocelot, int port, 2338 struct net_device *bond) 2339 { 2340 mutex_lock(&ocelot->fwd_domain_lock); 2341 2342 ocelot->ports[port]->bond = NULL; 2343 2344 ocelot_setup_logical_port_ids(ocelot); 2345 ocelot_apply_bridge_fwd_mask(ocelot, false); 2346 ocelot_set_aggr_pgids(ocelot); 2347 2348 mutex_unlock(&ocelot->fwd_domain_lock); 2349 } 2350 EXPORT_SYMBOL(ocelot_port_lag_leave); 2351 2352 void ocelot_port_lag_change(struct ocelot *ocelot, int port, bool lag_tx_active) 2353 { 2354 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2355 2356 ocelot_port->lag_tx_active = lag_tx_active; 2357 2358 /* Rebalance the LAGs */ 2359 ocelot_set_aggr_pgids(ocelot); 2360 } 2361 EXPORT_SYMBOL(ocelot_port_lag_change); 2362 2363 /* Configure the maximum SDU (L2 payload) on RX to the value specified in @sdu. 2364 * The length of VLAN tags is accounted for automatically via DEV_MAC_TAGS_CFG. 2365 * In the special case that it's the NPI port that we're configuring, the 2366 * length of the tag and optional prefix needs to be accounted for privately, 2367 * in order to be able to sustain communication at the requested @sdu. 2368 */ 2369 void ocelot_port_set_maxlen(struct ocelot *ocelot, int port, size_t sdu) 2370 { 2371 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2372 int maxlen = sdu + ETH_HLEN + ETH_FCS_LEN; 2373 int pause_start, pause_stop; 2374 int atop, atop_tot; 2375 2376 if (port == ocelot->npi) { 2377 maxlen += OCELOT_TAG_LEN; 2378 2379 if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_SHORT) 2380 maxlen += OCELOT_SHORT_PREFIX_LEN; 2381 else if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_LONG) 2382 maxlen += OCELOT_LONG_PREFIX_LEN; 2383 } 2384 2385 ocelot_port_writel(ocelot_port, maxlen, DEV_MAC_MAXLEN_CFG); 2386 2387 /* Set Pause watermark hysteresis */ 2388 pause_start = 6 * maxlen / OCELOT_BUFFER_CELL_SZ; 2389 pause_stop = 4 * maxlen / OCELOT_BUFFER_CELL_SZ; 2390 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_START, 2391 pause_start); 2392 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_STOP, 2393 pause_stop); 2394 2395 /* Tail dropping watermarks */ 2396 atop_tot = (ocelot->packet_buffer_size - 9 * maxlen) / 2397 OCELOT_BUFFER_CELL_SZ; 2398 atop = (9 * maxlen) / OCELOT_BUFFER_CELL_SZ; 2399 ocelot_write_rix(ocelot, ocelot->ops->wm_enc(atop), SYS_ATOP, port); 2400 ocelot_write(ocelot, ocelot->ops->wm_enc(atop_tot), SYS_ATOP_TOT_CFG); 2401 } 2402 EXPORT_SYMBOL(ocelot_port_set_maxlen); 2403 2404 int ocelot_get_max_mtu(struct ocelot *ocelot, int port) 2405 { 2406 int max_mtu = 65535 - ETH_HLEN - ETH_FCS_LEN; 2407 2408 if (port == ocelot->npi) { 2409 max_mtu -= OCELOT_TAG_LEN; 2410 2411 if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_SHORT) 2412 max_mtu -= OCELOT_SHORT_PREFIX_LEN; 2413 else if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_LONG) 2414 max_mtu -= OCELOT_LONG_PREFIX_LEN; 2415 } 2416 2417 return max_mtu; 2418 } 2419 EXPORT_SYMBOL(ocelot_get_max_mtu); 2420 2421 static void ocelot_port_set_learning(struct ocelot *ocelot, int port, 2422 bool enabled) 2423 { 2424 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2425 u32 val = 0; 2426 2427 if (enabled) 2428 val = ANA_PORT_PORT_CFG_LEARN_ENA; 2429 2430 ocelot_rmw_gix(ocelot, val, ANA_PORT_PORT_CFG_LEARN_ENA, 2431 ANA_PORT_PORT_CFG, port); 2432 2433 ocelot_port->learn_ena = enabled; 2434 } 2435 2436 static void ocelot_port_set_ucast_flood(struct ocelot *ocelot, int port, 2437 bool enabled) 2438 { 2439 u32 val = 0; 2440 2441 if (enabled) 2442 val = BIT(port); 2443 2444 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_UC); 2445 } 2446 2447 static void ocelot_port_set_mcast_flood(struct ocelot *ocelot, int port, 2448 bool enabled) 2449 { 2450 u32 val = 0; 2451 2452 if (enabled) 2453 val = BIT(port); 2454 2455 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_MC); 2456 } 2457 2458 static void ocelot_port_set_bcast_flood(struct ocelot *ocelot, int port, 2459 bool enabled) 2460 { 2461 u32 val = 0; 2462 2463 if (enabled) 2464 val = BIT(port); 2465 2466 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_BC); 2467 } 2468 2469 int ocelot_port_pre_bridge_flags(struct ocelot *ocelot, int port, 2470 struct switchdev_brport_flags flags) 2471 { 2472 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | 2473 BR_BCAST_FLOOD)) 2474 return -EINVAL; 2475 2476 return 0; 2477 } 2478 EXPORT_SYMBOL(ocelot_port_pre_bridge_flags); 2479 2480 void ocelot_port_bridge_flags(struct ocelot *ocelot, int port, 2481 struct switchdev_brport_flags flags) 2482 { 2483 if (flags.mask & BR_LEARNING) 2484 ocelot_port_set_learning(ocelot, port, 2485 !!(flags.val & BR_LEARNING)); 2486 2487 if (flags.mask & BR_FLOOD) 2488 ocelot_port_set_ucast_flood(ocelot, port, 2489 !!(flags.val & BR_FLOOD)); 2490 2491 if (flags.mask & BR_MCAST_FLOOD) 2492 ocelot_port_set_mcast_flood(ocelot, port, 2493 !!(flags.val & BR_MCAST_FLOOD)); 2494 2495 if (flags.mask & BR_BCAST_FLOOD) 2496 ocelot_port_set_bcast_flood(ocelot, port, 2497 !!(flags.val & BR_BCAST_FLOOD)); 2498 } 2499 EXPORT_SYMBOL(ocelot_port_bridge_flags); 2500 2501 void ocelot_init_port(struct ocelot *ocelot, int port) 2502 { 2503 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2504 2505 skb_queue_head_init(&ocelot_port->tx_skbs); 2506 2507 /* Basic L2 initialization */ 2508 2509 /* Set MAC IFG Gaps 2510 * FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 0 2511 * !FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 5 2512 */ 2513 ocelot_port_writel(ocelot_port, DEV_MAC_IFG_CFG_TX_IFG(5), 2514 DEV_MAC_IFG_CFG); 2515 2516 /* Load seed (0) and set MAC HDX late collision */ 2517 ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67) | 2518 DEV_MAC_HDX_CFG_SEED_LOAD, 2519 DEV_MAC_HDX_CFG); 2520 mdelay(1); 2521 ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67), 2522 DEV_MAC_HDX_CFG); 2523 2524 /* Set Max Length and maximum tags allowed */ 2525 ocelot_port_set_maxlen(ocelot, port, ETH_DATA_LEN); 2526 ocelot_port_writel(ocelot_port, DEV_MAC_TAGS_CFG_TAG_ID(ETH_P_8021AD) | 2527 DEV_MAC_TAGS_CFG_VLAN_AWR_ENA | 2528 DEV_MAC_TAGS_CFG_VLAN_DBL_AWR_ENA | 2529 DEV_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA, 2530 DEV_MAC_TAGS_CFG); 2531 2532 /* Set SMAC of Pause frame (00:00:00:00:00:00) */ 2533 ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_HIGH_CFG); 2534 ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_LOW_CFG); 2535 2536 /* Enable transmission of pause frames */ 2537 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, 1); 2538 2539 /* Drop frames with multicast source address */ 2540 ocelot_rmw_gix(ocelot, ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA, 2541 ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA, 2542 ANA_PORT_DROP_CFG, port); 2543 2544 /* Set default VLAN and tag type to 8021Q. */ 2545 ocelot_rmw_gix(ocelot, REW_PORT_VLAN_CFG_PORT_TPID(ETH_P_8021Q), 2546 REW_PORT_VLAN_CFG_PORT_TPID_M, 2547 REW_PORT_VLAN_CFG, port); 2548 2549 /* Disable source address learning for standalone mode */ 2550 ocelot_port_set_learning(ocelot, port, false); 2551 2552 /* Set the port's initial logical port ID value, enable receiving 2553 * frames on it, and configure the MAC address learning type to 2554 * automatic. 2555 */ 2556 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_LEARNAUTO | 2557 ANA_PORT_PORT_CFG_RECV_ENA | 2558 ANA_PORT_PORT_CFG_PORTID_VAL(port), 2559 ANA_PORT_PORT_CFG, port); 2560 2561 /* Enable vcap lookups */ 2562 ocelot_vcap_enable(ocelot, port); 2563 } 2564 EXPORT_SYMBOL(ocelot_init_port); 2565 2566 /* Configure and enable the CPU port module, which is a set of queues 2567 * accessible through register MMIO, frame DMA or Ethernet (in case 2568 * NPI mode is used). 2569 */ 2570 static void ocelot_cpu_port_init(struct ocelot *ocelot) 2571 { 2572 int cpu = ocelot->num_phys_ports; 2573 2574 /* The unicast destination PGID for the CPU port module is unused */ 2575 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, cpu); 2576 /* Instead set up a multicast destination PGID for traffic copied to 2577 * the CPU. Whitelisted MAC addresses like the port netdevice MAC 2578 * addresses will be copied to the CPU via this PGID. 2579 */ 2580 ocelot_write_rix(ocelot, BIT(cpu), ANA_PGID_PGID, PGID_CPU); 2581 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_RECV_ENA | 2582 ANA_PORT_PORT_CFG_PORTID_VAL(cpu), 2583 ANA_PORT_PORT_CFG, cpu); 2584 2585 /* Enable CPU port module */ 2586 ocelot_fields_write(ocelot, cpu, QSYS_SWITCH_PORT_MODE_PORT_ENA, 1); 2587 /* CPU port Injection/Extraction configuration */ 2588 ocelot_fields_write(ocelot, cpu, SYS_PORT_MODE_INCL_XTR_HDR, 2589 OCELOT_TAG_PREFIX_NONE); 2590 ocelot_fields_write(ocelot, cpu, SYS_PORT_MODE_INCL_INJ_HDR, 2591 OCELOT_TAG_PREFIX_NONE); 2592 2593 /* Configure the CPU port to be VLAN aware */ 2594 ocelot_write_gix(ocelot, 2595 ANA_PORT_VLAN_CFG_VLAN_VID(OCELOT_VLAN_UNAWARE_PVID) | 2596 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 2597 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1), 2598 ANA_PORT_VLAN_CFG, cpu); 2599 } 2600 2601 static void ocelot_detect_features(struct ocelot *ocelot) 2602 { 2603 int mmgt, eq_ctrl; 2604 2605 /* For Ocelot, Felix, Seville, Serval etc, SYS:MMGT:MMGT:FREECNT holds 2606 * the number of 240-byte free memory words (aka 4-cell chunks) and not 2607 * 192 bytes as the documentation incorrectly says. 2608 */ 2609 mmgt = ocelot_read(ocelot, SYS_MMGT); 2610 ocelot->packet_buffer_size = 240 * SYS_MMGT_FREECNT(mmgt); 2611 2612 eq_ctrl = ocelot_read(ocelot, QSYS_EQ_CTRL); 2613 ocelot->num_frame_refs = QSYS_MMGT_EQ_CTRL_FP_FREE_CNT(eq_ctrl); 2614 } 2615 2616 int ocelot_init(struct ocelot *ocelot) 2617 { 2618 char queue_name[32]; 2619 int i, ret; 2620 u32 port; 2621 2622 if (ocelot->ops->reset) { 2623 ret = ocelot->ops->reset(ocelot); 2624 if (ret) { 2625 dev_err(ocelot->dev, "Switch reset failed\n"); 2626 return ret; 2627 } 2628 } 2629 2630 ocelot->stats = devm_kcalloc(ocelot->dev, 2631 ocelot->num_phys_ports * ocelot->num_stats, 2632 sizeof(u64), GFP_KERNEL); 2633 if (!ocelot->stats) 2634 return -ENOMEM; 2635 2636 mutex_init(&ocelot->stats_lock); 2637 mutex_init(&ocelot->ptp_lock); 2638 mutex_init(&ocelot->mact_lock); 2639 mutex_init(&ocelot->fwd_domain_lock); 2640 spin_lock_init(&ocelot->ptp_clock_lock); 2641 spin_lock_init(&ocelot->ts_id_lock); 2642 snprintf(queue_name, sizeof(queue_name), "%s-stats", 2643 dev_name(ocelot->dev)); 2644 ocelot->stats_queue = create_singlethread_workqueue(queue_name); 2645 if (!ocelot->stats_queue) 2646 return -ENOMEM; 2647 2648 ocelot->owq = alloc_ordered_workqueue("ocelot-owq", 0); 2649 if (!ocelot->owq) { 2650 destroy_workqueue(ocelot->stats_queue); 2651 return -ENOMEM; 2652 } 2653 2654 INIT_LIST_HEAD(&ocelot->multicast); 2655 INIT_LIST_HEAD(&ocelot->pgids); 2656 INIT_LIST_HEAD(&ocelot->vlans); 2657 ocelot_detect_features(ocelot); 2658 ocelot_mact_init(ocelot); 2659 ocelot_vlan_init(ocelot); 2660 ocelot_vcap_init(ocelot); 2661 ocelot_cpu_port_init(ocelot); 2662 2663 if (ocelot->ops->psfp_init) 2664 ocelot->ops->psfp_init(ocelot); 2665 2666 for (port = 0; port < ocelot->num_phys_ports; port++) { 2667 /* Clear all counters (5 groups) */ 2668 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(port) | 2669 SYS_STAT_CFG_STAT_CLEAR_SHOT(0x7f), 2670 SYS_STAT_CFG); 2671 } 2672 2673 /* Only use S-Tag */ 2674 ocelot_write(ocelot, ETH_P_8021AD, SYS_VLAN_ETYPE_CFG); 2675 2676 /* Aggregation mode */ 2677 ocelot_write(ocelot, ANA_AGGR_CFG_AC_SMAC_ENA | 2678 ANA_AGGR_CFG_AC_DMAC_ENA | 2679 ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA | 2680 ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA | 2681 ANA_AGGR_CFG_AC_IP6_FLOW_LBL_ENA | 2682 ANA_AGGR_CFG_AC_IP6_TCPUDP_ENA, 2683 ANA_AGGR_CFG); 2684 2685 /* Set MAC age time to default value. The entry is aged after 2686 * 2*AGE_PERIOD 2687 */ 2688 ocelot_write(ocelot, 2689 ANA_AUTOAGE_AGE_PERIOD(BR_DEFAULT_AGEING_TIME / 2 / HZ), 2690 ANA_AUTOAGE); 2691 2692 /* Disable learning for frames discarded by VLAN ingress filtering */ 2693 regmap_field_write(ocelot->regfields[ANA_ADVLEARN_VLAN_CHK], 1); 2694 2695 /* Setup frame ageing - fixed value "2 sec" - in 6.5 us units */ 2696 ocelot_write(ocelot, SYS_FRM_AGING_AGE_TX_ENA | 2697 SYS_FRM_AGING_MAX_AGE(307692), SYS_FRM_AGING); 2698 2699 /* Setup flooding PGIDs */ 2700 for (i = 0; i < ocelot->num_flooding_pgids; i++) 2701 ocelot_write_rix(ocelot, ANA_FLOODING_FLD_MULTICAST(PGID_MC) | 2702 ANA_FLOODING_FLD_BROADCAST(PGID_BC) | 2703 ANA_FLOODING_FLD_UNICAST(PGID_UC), 2704 ANA_FLOODING, i); 2705 ocelot_write(ocelot, ANA_FLOODING_IPMC_FLD_MC6_DATA(PGID_MCIPV6) | 2706 ANA_FLOODING_IPMC_FLD_MC6_CTRL(PGID_MC) | 2707 ANA_FLOODING_IPMC_FLD_MC4_DATA(PGID_MCIPV4) | 2708 ANA_FLOODING_IPMC_FLD_MC4_CTRL(PGID_MC), 2709 ANA_FLOODING_IPMC); 2710 2711 for (port = 0; port < ocelot->num_phys_ports; port++) { 2712 /* Transmit the frame to the local port. */ 2713 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port); 2714 /* Do not forward BPDU frames to the front ports. */ 2715 ocelot_write_gix(ocelot, 2716 ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA(0xffff), 2717 ANA_PORT_CPU_FWD_BPDU_CFG, 2718 port); 2719 /* Ensure bridging is disabled */ 2720 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_SRC + port); 2721 } 2722 2723 for_each_nonreserved_multicast_dest_pgid(ocelot, i) { 2724 u32 val = ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports - 1, 0)); 2725 2726 ocelot_write_rix(ocelot, val, ANA_PGID_PGID, i); 2727 } 2728 2729 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_BLACKHOLE); 2730 2731 /* Allow broadcast and unknown L2 multicast to the CPU. */ 2732 ocelot_rmw_rix(ocelot, ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)), 2733 ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)), 2734 ANA_PGID_PGID, PGID_MC); 2735 ocelot_rmw_rix(ocelot, ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)), 2736 ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)), 2737 ANA_PGID_PGID, PGID_BC); 2738 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV4); 2739 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV6); 2740 2741 /* Allow manual injection via DEVCPU_QS registers, and byte swap these 2742 * registers endianness. 2743 */ 2744 ocelot_write_rix(ocelot, QS_INJ_GRP_CFG_BYTE_SWAP | 2745 QS_INJ_GRP_CFG_MODE(1), QS_INJ_GRP_CFG, 0); 2746 ocelot_write_rix(ocelot, QS_XTR_GRP_CFG_BYTE_SWAP | 2747 QS_XTR_GRP_CFG_MODE(1), QS_XTR_GRP_CFG, 0); 2748 ocelot_write(ocelot, ANA_CPUQ_CFG_CPUQ_MIRROR(2) | 2749 ANA_CPUQ_CFG_CPUQ_LRN(2) | 2750 ANA_CPUQ_CFG_CPUQ_MAC_COPY(2) | 2751 ANA_CPUQ_CFG_CPUQ_SRC_COPY(2) | 2752 ANA_CPUQ_CFG_CPUQ_LOCKED_PORTMOVE(2) | 2753 ANA_CPUQ_CFG_CPUQ_ALLBRIDGE(6) | 2754 ANA_CPUQ_CFG_CPUQ_IPMC_CTRL(6) | 2755 ANA_CPUQ_CFG_CPUQ_IGMP(6) | 2756 ANA_CPUQ_CFG_CPUQ_MLD(6), ANA_CPUQ_CFG); 2757 for (i = 0; i < 16; i++) 2758 ocelot_write_rix(ocelot, ANA_CPUQ_8021_CFG_CPUQ_GARP_VAL(6) | 2759 ANA_CPUQ_8021_CFG_CPUQ_BPDU_VAL(6), 2760 ANA_CPUQ_8021_CFG, i); 2761 2762 INIT_DELAYED_WORK(&ocelot->stats_work, ocelot_check_stats_work); 2763 queue_delayed_work(ocelot->stats_queue, &ocelot->stats_work, 2764 OCELOT_STATS_CHECK_DELAY); 2765 2766 return 0; 2767 } 2768 EXPORT_SYMBOL(ocelot_init); 2769 2770 void ocelot_deinit(struct ocelot *ocelot) 2771 { 2772 cancel_delayed_work(&ocelot->stats_work); 2773 destroy_workqueue(ocelot->stats_queue); 2774 destroy_workqueue(ocelot->owq); 2775 mutex_destroy(&ocelot->stats_lock); 2776 } 2777 EXPORT_SYMBOL(ocelot_deinit); 2778 2779 void ocelot_deinit_port(struct ocelot *ocelot, int port) 2780 { 2781 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2782 2783 skb_queue_purge(&ocelot_port->tx_skbs); 2784 } 2785 EXPORT_SYMBOL(ocelot_deinit_port); 2786 2787 MODULE_LICENSE("Dual MIT/GPL"); 2788