1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* 3 * Microsemi Ocelot Switch driver 4 * 5 * Copyright (c) 2017 Microsemi Corporation 6 */ 7 #include <linux/etherdevice.h> 8 #include <linux/ethtool.h> 9 #include <linux/if_bridge.h> 10 #include <linux/if_ether.h> 11 #include <linux/if_vlan.h> 12 #include <linux/interrupt.h> 13 #include <linux/kernel.h> 14 #include <linux/module.h> 15 #include <linux/netdevice.h> 16 #include <linux/phy.h> 17 #include <linux/skbuff.h> 18 #include <net/arp.h> 19 #include <net/netevent.h> 20 #include <net/rtnetlink.h> 21 #include <net/switchdev.h> 22 23 #include "ocelot.h" 24 25 /* MAC table entry types. 26 * ENTRYTYPE_NORMAL is subject to aging. 27 * ENTRYTYPE_LOCKED is not subject to aging. 28 * ENTRYTYPE_MACv4 is not subject to aging. For IPv4 multicast. 29 * ENTRYTYPE_MACv6 is not subject to aging. For IPv6 multicast. 30 */ 31 enum macaccess_entry_type { 32 ENTRYTYPE_NORMAL = 0, 33 ENTRYTYPE_LOCKED, 34 ENTRYTYPE_MACv4, 35 ENTRYTYPE_MACv6, 36 }; 37 38 struct ocelot_mact_entry { 39 u8 mac[ETH_ALEN]; 40 u16 vid; 41 enum macaccess_entry_type type; 42 }; 43 44 static inline int ocelot_mact_wait_for_completion(struct ocelot *ocelot) 45 { 46 unsigned int val, timeout = 10; 47 48 /* Wait for the issued mac table command to be completed, or timeout. 49 * When the command read from ANA_TABLES_MACACCESS is 50 * MACACCESS_CMD_IDLE, the issued command completed successfully. 51 */ 52 do { 53 val = ocelot_read(ocelot, ANA_TABLES_MACACCESS); 54 val &= ANA_TABLES_MACACCESS_MAC_TABLE_CMD_M; 55 } while (val != MACACCESS_CMD_IDLE && timeout--); 56 57 if (!timeout) 58 return -ETIMEDOUT; 59 60 return 0; 61 } 62 63 static void ocelot_mact_select(struct ocelot *ocelot, 64 const unsigned char mac[ETH_ALEN], 65 unsigned int vid) 66 { 67 u32 macl = 0, mach = 0; 68 69 /* Set the MAC address to handle and the vlan associated in a format 70 * understood by the hardware. 71 */ 72 mach |= vid << 16; 73 mach |= mac[0] << 8; 74 mach |= mac[1] << 0; 75 macl |= mac[2] << 24; 76 macl |= mac[3] << 16; 77 macl |= mac[4] << 8; 78 macl |= mac[5] << 0; 79 80 ocelot_write(ocelot, macl, ANA_TABLES_MACLDATA); 81 ocelot_write(ocelot, mach, ANA_TABLES_MACHDATA); 82 83 } 84 85 static int ocelot_mact_learn(struct ocelot *ocelot, int port, 86 const unsigned char mac[ETH_ALEN], 87 unsigned int vid, 88 enum macaccess_entry_type type) 89 { 90 ocelot_mact_select(ocelot, mac, vid); 91 92 /* Issue a write command */ 93 ocelot_write(ocelot, ANA_TABLES_MACACCESS_VALID | 94 ANA_TABLES_MACACCESS_DEST_IDX(port) | 95 ANA_TABLES_MACACCESS_ENTRYTYPE(type) | 96 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_LEARN), 97 ANA_TABLES_MACACCESS); 98 99 return ocelot_mact_wait_for_completion(ocelot); 100 } 101 102 static int ocelot_mact_forget(struct ocelot *ocelot, 103 const unsigned char mac[ETH_ALEN], 104 unsigned int vid) 105 { 106 ocelot_mact_select(ocelot, mac, vid); 107 108 /* Issue a forget command */ 109 ocelot_write(ocelot, 110 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_FORGET), 111 ANA_TABLES_MACACCESS); 112 113 return ocelot_mact_wait_for_completion(ocelot); 114 } 115 116 static void ocelot_mact_init(struct ocelot *ocelot) 117 { 118 /* Configure the learning mode entries attributes: 119 * - Do not copy the frame to the CPU extraction queues. 120 * - Use the vlan and mac_cpoy for dmac lookup. 121 */ 122 ocelot_rmw(ocelot, 0, 123 ANA_AGENCTRL_LEARN_CPU_COPY | ANA_AGENCTRL_IGNORE_DMAC_FLAGS 124 | ANA_AGENCTRL_LEARN_FWD_KILL 125 | ANA_AGENCTRL_LEARN_IGNORE_VLAN, 126 ANA_AGENCTRL); 127 128 /* Clear the MAC table */ 129 ocelot_write(ocelot, MACACCESS_CMD_INIT, ANA_TABLES_MACACCESS); 130 } 131 132 static inline int ocelot_vlant_wait_for_completion(struct ocelot *ocelot) 133 { 134 unsigned int val, timeout = 10; 135 136 /* Wait for the issued mac table command to be completed, or timeout. 137 * When the command read from ANA_TABLES_MACACCESS is 138 * MACACCESS_CMD_IDLE, the issued command completed successfully. 139 */ 140 do { 141 val = ocelot_read(ocelot, ANA_TABLES_VLANACCESS); 142 val &= ANA_TABLES_VLANACCESS_VLAN_TBL_CMD_M; 143 } while (val != ANA_TABLES_VLANACCESS_CMD_IDLE && timeout--); 144 145 if (!timeout) 146 return -ETIMEDOUT; 147 148 return 0; 149 } 150 151 static void ocelot_vlan_init(struct ocelot *ocelot) 152 { 153 /* Clear VLAN table, by default all ports are members of all VLANs */ 154 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_CMD_INIT, 155 ANA_TABLES_VLANACCESS); 156 ocelot_vlant_wait_for_completion(ocelot); 157 } 158 159 /* Watermark encode 160 * Bit 8: Unit; 0:1, 1:16 161 * Bit 7-0: Value to be multiplied with unit 162 */ 163 static u16 ocelot_wm_enc(u16 value) 164 { 165 if (value >= BIT(8)) 166 return BIT(8) | (value / 16); 167 168 return value; 169 } 170 171 static void ocelot_port_adjust_link(struct net_device *dev) 172 { 173 struct ocelot_port *port = netdev_priv(dev); 174 struct ocelot *ocelot = port->ocelot; 175 u8 p = port->chip_port; 176 int speed, atop_wm, mode = 0; 177 178 switch (dev->phydev->speed) { 179 case SPEED_10: 180 speed = OCELOT_SPEED_10; 181 break; 182 case SPEED_100: 183 speed = OCELOT_SPEED_100; 184 break; 185 case SPEED_1000: 186 speed = OCELOT_SPEED_1000; 187 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA; 188 break; 189 case SPEED_2500: 190 speed = OCELOT_SPEED_2500; 191 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA; 192 break; 193 default: 194 netdev_err(dev, "Unsupported PHY speed: %d\n", 195 dev->phydev->speed); 196 return; 197 } 198 199 phy_print_status(dev->phydev); 200 201 if (!dev->phydev->link) 202 return; 203 204 /* Only full duplex supported for now */ 205 ocelot_port_writel(port, DEV_MAC_MODE_CFG_FDX_ENA | 206 mode, DEV_MAC_MODE_CFG); 207 208 /* Set MAC IFG Gaps 209 * FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 0 210 * !FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 5 211 */ 212 ocelot_port_writel(port, DEV_MAC_IFG_CFG_TX_IFG(5), DEV_MAC_IFG_CFG); 213 214 /* Load seed (0) and set MAC HDX late collision */ 215 ocelot_port_writel(port, DEV_MAC_HDX_CFG_LATE_COL_POS(67) | 216 DEV_MAC_HDX_CFG_SEED_LOAD, 217 DEV_MAC_HDX_CFG); 218 mdelay(1); 219 ocelot_port_writel(port, DEV_MAC_HDX_CFG_LATE_COL_POS(67), 220 DEV_MAC_HDX_CFG); 221 222 /* Disable HDX fast control */ 223 ocelot_port_writel(port, DEV_PORT_MISC_HDX_FAST_DIS, DEV_PORT_MISC); 224 225 /* SGMII only for now */ 226 ocelot_port_writel(port, PCS1G_MODE_CFG_SGMII_MODE_ENA, PCS1G_MODE_CFG); 227 ocelot_port_writel(port, PCS1G_SD_CFG_SD_SEL, PCS1G_SD_CFG); 228 229 /* Enable PCS */ 230 ocelot_port_writel(port, PCS1G_CFG_PCS_ENA, PCS1G_CFG); 231 232 /* No aneg on SGMII */ 233 ocelot_port_writel(port, 0, PCS1G_ANEG_CFG); 234 235 /* No loopback */ 236 ocelot_port_writel(port, 0, PCS1G_LB_CFG); 237 238 /* Set Max Length and maximum tags allowed */ 239 ocelot_port_writel(port, VLAN_ETH_FRAME_LEN, DEV_MAC_MAXLEN_CFG); 240 ocelot_port_writel(port, DEV_MAC_TAGS_CFG_TAG_ID(ETH_P_8021AD) | 241 DEV_MAC_TAGS_CFG_VLAN_AWR_ENA | 242 DEV_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA, 243 DEV_MAC_TAGS_CFG); 244 245 /* Enable MAC module */ 246 ocelot_port_writel(port, DEV_MAC_ENA_CFG_RX_ENA | 247 DEV_MAC_ENA_CFG_TX_ENA, DEV_MAC_ENA_CFG); 248 249 /* Take MAC, Port, Phy (intern) and PCS (SGMII/Serdes) clock out of 250 * reset */ 251 ocelot_port_writel(port, DEV_CLOCK_CFG_LINK_SPEED(speed), 252 DEV_CLOCK_CFG); 253 254 /* Set SMAC of Pause frame (00:00:00:00:00:00) */ 255 ocelot_port_writel(port, 0, DEV_MAC_FC_MAC_HIGH_CFG); 256 ocelot_port_writel(port, 0, DEV_MAC_FC_MAC_LOW_CFG); 257 258 /* No PFC */ 259 ocelot_write_gix(ocelot, ANA_PFC_PFC_CFG_FC_LINK_SPEED(speed), 260 ANA_PFC_PFC_CFG, p); 261 262 /* Set Pause WM hysteresis 263 * 152 = 6 * VLAN_ETH_FRAME_LEN / OCELOT_BUFFER_CELL_SZ 264 * 101 = 4 * VLAN_ETH_FRAME_LEN / OCELOT_BUFFER_CELL_SZ 265 */ 266 ocelot_write_rix(ocelot, SYS_PAUSE_CFG_PAUSE_ENA | 267 SYS_PAUSE_CFG_PAUSE_STOP(101) | 268 SYS_PAUSE_CFG_PAUSE_START(152), SYS_PAUSE_CFG, p); 269 270 /* Core: Enable port for frame transfer */ 271 ocelot_write_rix(ocelot, QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE | 272 QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG(1) | 273 QSYS_SWITCH_PORT_MODE_PORT_ENA, 274 QSYS_SWITCH_PORT_MODE, p); 275 276 /* Flow control */ 277 ocelot_write_rix(ocelot, SYS_MAC_FC_CFG_PAUSE_VAL_CFG(0xffff) | 278 SYS_MAC_FC_CFG_RX_FC_ENA | SYS_MAC_FC_CFG_TX_FC_ENA | 279 SYS_MAC_FC_CFG_ZERO_PAUSE_ENA | 280 SYS_MAC_FC_CFG_FC_LATENCY_CFG(0x7) | 281 SYS_MAC_FC_CFG_FC_LINK_SPEED(speed), 282 SYS_MAC_FC_CFG, p); 283 ocelot_write_rix(ocelot, 0, ANA_POL_FLOWC, p); 284 285 /* Tail dropping watermark */ 286 atop_wm = (ocelot->shared_queue_sz - 9 * VLAN_ETH_FRAME_LEN) / OCELOT_BUFFER_CELL_SZ; 287 ocelot_write_rix(ocelot, ocelot_wm_enc(9 * VLAN_ETH_FRAME_LEN), 288 SYS_ATOP, p); 289 ocelot_write(ocelot, ocelot_wm_enc(atop_wm), SYS_ATOP_TOT_CFG); 290 } 291 292 static int ocelot_port_open(struct net_device *dev) 293 { 294 struct ocelot_port *port = netdev_priv(dev); 295 struct ocelot *ocelot = port->ocelot; 296 int err; 297 298 /* Enable receiving frames on the port, and activate auto-learning of 299 * MAC addresses. 300 */ 301 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_LEARNAUTO | 302 ANA_PORT_PORT_CFG_RECV_ENA | 303 ANA_PORT_PORT_CFG_PORTID_VAL(port->chip_port), 304 ANA_PORT_PORT_CFG, port->chip_port); 305 306 err = phy_connect_direct(dev, port->phy, &ocelot_port_adjust_link, 307 PHY_INTERFACE_MODE_NA); 308 if (err) { 309 netdev_err(dev, "Could not attach to PHY\n"); 310 return err; 311 } 312 313 dev->phydev = port->phy; 314 315 phy_attached_info(port->phy); 316 phy_start(port->phy); 317 return 0; 318 } 319 320 static int ocelot_port_stop(struct net_device *dev) 321 { 322 struct ocelot_port *port = netdev_priv(dev); 323 324 phy_disconnect(port->phy); 325 326 dev->phydev = NULL; 327 328 ocelot_port_writel(port, 0, DEV_MAC_ENA_CFG); 329 ocelot_rmw_rix(port->ocelot, 0, QSYS_SWITCH_PORT_MODE_PORT_ENA, 330 QSYS_SWITCH_PORT_MODE, port->chip_port); 331 return 0; 332 } 333 334 /* Generate the IFH for frame injection 335 * 336 * The IFH is a 128bit-value 337 * bit 127: bypass the analyzer processing 338 * bit 56-67: destination mask 339 * bit 28-29: pop_cnt: 3 disables all rewriting of the frame 340 * bit 20-27: cpu extraction queue mask 341 * bit 16: tag type 0: C-tag, 1: S-tag 342 * bit 0-11: VID 343 */ 344 static int ocelot_gen_ifh(u32 *ifh, struct frame_info *info) 345 { 346 ifh[0] = IFH_INJ_BYPASS; 347 ifh[1] = (0xff00 & info->port) >> 8; 348 ifh[2] = (0xff & info->port) << 24; 349 ifh[3] = IFH_INJ_POP_CNT_DISABLE | (info->cpuq << 20) | 350 (info->tag_type << 16) | info->vid; 351 352 return 0; 353 } 354 355 static int ocelot_port_xmit(struct sk_buff *skb, struct net_device *dev) 356 { 357 struct ocelot_port *port = netdev_priv(dev); 358 struct ocelot *ocelot = port->ocelot; 359 u32 val, ifh[IFH_LEN]; 360 struct frame_info info = {}; 361 u8 grp = 0; /* Send everything on CPU group 0 */ 362 unsigned int i, count, last; 363 364 val = ocelot_read(ocelot, QS_INJ_STATUS); 365 if (!(val & QS_INJ_STATUS_FIFO_RDY(BIT(grp))) || 366 (val & QS_INJ_STATUS_WMARK_REACHED(BIT(grp)))) 367 return NETDEV_TX_BUSY; 368 369 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) | 370 QS_INJ_CTRL_SOF, QS_INJ_CTRL, grp); 371 372 info.port = BIT(port->chip_port); 373 info.cpuq = 0xff; 374 ocelot_gen_ifh(ifh, &info); 375 376 for (i = 0; i < IFH_LEN; i++) 377 ocelot_write_rix(ocelot, ifh[i], QS_INJ_WR, grp); 378 379 count = (skb->len + 3) / 4; 380 last = skb->len % 4; 381 for (i = 0; i < count; i++) { 382 ocelot_write_rix(ocelot, ((u32 *)skb->data)[i], QS_INJ_WR, grp); 383 } 384 385 /* Add padding */ 386 while (i < (OCELOT_BUFFER_CELL_SZ / 4)) { 387 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp); 388 i++; 389 } 390 391 /* Indicate EOF and valid bytes in last word */ 392 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) | 393 QS_INJ_CTRL_VLD_BYTES(skb->len < OCELOT_BUFFER_CELL_SZ ? 0 : last) | 394 QS_INJ_CTRL_EOF, 395 QS_INJ_CTRL, grp); 396 397 /* Add dummy CRC */ 398 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp); 399 skb_tx_timestamp(skb); 400 401 dev->stats.tx_packets++; 402 dev->stats.tx_bytes += skb->len; 403 dev_kfree_skb_any(skb); 404 405 return NETDEV_TX_OK; 406 } 407 408 static void ocelot_mact_mc_reset(struct ocelot_port *port) 409 { 410 struct ocelot *ocelot = port->ocelot; 411 struct netdev_hw_addr *ha, *n; 412 413 /* Free and forget all the MAC addresses stored in the port private mc 414 * list. These are mc addresses that were previously added by calling 415 * ocelot_mact_mc_add(). 416 */ 417 list_for_each_entry_safe(ha, n, &port->mc, list) { 418 ocelot_mact_forget(ocelot, ha->addr, port->pvid); 419 list_del(&ha->list); 420 kfree(ha); 421 } 422 } 423 424 static int ocelot_mact_mc_add(struct ocelot_port *port, 425 struct netdev_hw_addr *hw_addr) 426 { 427 struct ocelot *ocelot = port->ocelot; 428 struct netdev_hw_addr *ha = kzalloc(sizeof(*ha), GFP_KERNEL); 429 430 if (!ha) 431 return -ENOMEM; 432 433 memcpy(ha, hw_addr, sizeof(*ha)); 434 list_add_tail(&ha->list, &port->mc); 435 436 ocelot_mact_learn(ocelot, PGID_CPU, ha->addr, port->pvid, 437 ENTRYTYPE_LOCKED); 438 439 return 0; 440 } 441 442 static void ocelot_set_rx_mode(struct net_device *dev) 443 { 444 struct ocelot_port *port = netdev_priv(dev); 445 struct ocelot *ocelot = port->ocelot; 446 struct netdev_hw_addr *ha; 447 int i; 448 u32 val; 449 450 /* This doesn't handle promiscuous mode because the bridge core is 451 * setting IFF_PROMISC on all slave interfaces and all frames would be 452 * forwarded to the CPU port. 453 */ 454 val = GENMASK(ocelot->num_phys_ports - 1, 0); 455 for (i = ocelot->num_phys_ports + 1; i < PGID_CPU; i++) 456 ocelot_write_rix(ocelot, val, ANA_PGID_PGID, i); 457 458 /* Handle the device multicast addresses. First remove all the 459 * previously installed addresses and then add the latest ones to the 460 * mac table. 461 */ 462 ocelot_mact_mc_reset(port); 463 netdev_for_each_mc_addr(ha, dev) 464 ocelot_mact_mc_add(port, ha); 465 } 466 467 static int ocelot_port_get_phys_port_name(struct net_device *dev, 468 char *buf, size_t len) 469 { 470 struct ocelot_port *port = netdev_priv(dev); 471 int ret; 472 473 ret = snprintf(buf, len, "p%d", port->chip_port); 474 if (ret >= len) 475 return -EINVAL; 476 477 return 0; 478 } 479 480 static int ocelot_port_set_mac_address(struct net_device *dev, void *p) 481 { 482 struct ocelot_port *port = netdev_priv(dev); 483 struct ocelot *ocelot = port->ocelot; 484 const struct sockaddr *addr = p; 485 486 /* Learn the new net device MAC address in the mac table. */ 487 ocelot_mact_learn(ocelot, PGID_CPU, addr->sa_data, port->pvid, 488 ENTRYTYPE_LOCKED); 489 /* Then forget the previous one. */ 490 ocelot_mact_forget(ocelot, dev->dev_addr, port->pvid); 491 492 ether_addr_copy(dev->dev_addr, addr->sa_data); 493 return 0; 494 } 495 496 static void ocelot_get_stats64(struct net_device *dev, 497 struct rtnl_link_stats64 *stats) 498 { 499 struct ocelot_port *port = netdev_priv(dev); 500 struct ocelot *ocelot = port->ocelot; 501 502 /* Configure the port to read the stats from */ 503 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(port->chip_port), 504 SYS_STAT_CFG); 505 506 /* Get Rx stats */ 507 stats->rx_bytes = ocelot_read(ocelot, SYS_COUNT_RX_OCTETS); 508 stats->rx_packets = ocelot_read(ocelot, SYS_COUNT_RX_SHORTS) + 509 ocelot_read(ocelot, SYS_COUNT_RX_FRAGMENTS) + 510 ocelot_read(ocelot, SYS_COUNT_RX_JABBERS) + 511 ocelot_read(ocelot, SYS_COUNT_RX_LONGS) + 512 ocelot_read(ocelot, SYS_COUNT_RX_64) + 513 ocelot_read(ocelot, SYS_COUNT_RX_65_127) + 514 ocelot_read(ocelot, SYS_COUNT_RX_128_255) + 515 ocelot_read(ocelot, SYS_COUNT_RX_256_1023) + 516 ocelot_read(ocelot, SYS_COUNT_RX_1024_1526) + 517 ocelot_read(ocelot, SYS_COUNT_RX_1527_MAX); 518 stats->multicast = ocelot_read(ocelot, SYS_COUNT_RX_MULTICAST); 519 stats->rx_dropped = dev->stats.rx_dropped; 520 521 /* Get Tx stats */ 522 stats->tx_bytes = ocelot_read(ocelot, SYS_COUNT_TX_OCTETS); 523 stats->tx_packets = ocelot_read(ocelot, SYS_COUNT_TX_64) + 524 ocelot_read(ocelot, SYS_COUNT_TX_65_127) + 525 ocelot_read(ocelot, SYS_COUNT_TX_128_511) + 526 ocelot_read(ocelot, SYS_COUNT_TX_512_1023) + 527 ocelot_read(ocelot, SYS_COUNT_TX_1024_1526) + 528 ocelot_read(ocelot, SYS_COUNT_TX_1527_MAX); 529 stats->tx_dropped = ocelot_read(ocelot, SYS_COUNT_TX_DROPS) + 530 ocelot_read(ocelot, SYS_COUNT_TX_AGING); 531 stats->collisions = ocelot_read(ocelot, SYS_COUNT_TX_COLLISION); 532 } 533 534 static int ocelot_fdb_add(struct ndmsg *ndm, struct nlattr *tb[], 535 struct net_device *dev, const unsigned char *addr, 536 u16 vid, u16 flags) 537 { 538 struct ocelot_port *port = netdev_priv(dev); 539 struct ocelot *ocelot = port->ocelot; 540 541 return ocelot_mact_learn(ocelot, port->chip_port, addr, vid, 542 ENTRYTYPE_NORMAL); 543 } 544 545 static int ocelot_fdb_del(struct ndmsg *ndm, struct nlattr *tb[], 546 struct net_device *dev, 547 const unsigned char *addr, u16 vid) 548 { 549 struct ocelot_port *port = netdev_priv(dev); 550 struct ocelot *ocelot = port->ocelot; 551 552 return ocelot_mact_forget(ocelot, addr, vid); 553 } 554 555 struct ocelot_dump_ctx { 556 struct net_device *dev; 557 struct sk_buff *skb; 558 struct netlink_callback *cb; 559 int idx; 560 }; 561 562 static int ocelot_fdb_do_dump(struct ocelot_mact_entry *entry, 563 struct ocelot_dump_ctx *dump) 564 { 565 u32 portid = NETLINK_CB(dump->cb->skb).portid; 566 u32 seq = dump->cb->nlh->nlmsg_seq; 567 struct nlmsghdr *nlh; 568 struct ndmsg *ndm; 569 570 if (dump->idx < dump->cb->args[2]) 571 goto skip; 572 573 nlh = nlmsg_put(dump->skb, portid, seq, RTM_NEWNEIGH, 574 sizeof(*ndm), NLM_F_MULTI); 575 if (!nlh) 576 return -EMSGSIZE; 577 578 ndm = nlmsg_data(nlh); 579 ndm->ndm_family = AF_BRIDGE; 580 ndm->ndm_pad1 = 0; 581 ndm->ndm_pad2 = 0; 582 ndm->ndm_flags = NTF_SELF; 583 ndm->ndm_type = 0; 584 ndm->ndm_ifindex = dump->dev->ifindex; 585 ndm->ndm_state = NUD_REACHABLE; 586 587 if (nla_put(dump->skb, NDA_LLADDR, ETH_ALEN, entry->mac)) 588 goto nla_put_failure; 589 590 if (entry->vid && nla_put_u16(dump->skb, NDA_VLAN, entry->vid)) 591 goto nla_put_failure; 592 593 nlmsg_end(dump->skb, nlh); 594 595 skip: 596 dump->idx++; 597 return 0; 598 599 nla_put_failure: 600 nlmsg_cancel(dump->skb, nlh); 601 return -EMSGSIZE; 602 } 603 604 static inline int ocelot_mact_read(struct ocelot_port *port, int row, int col, 605 struct ocelot_mact_entry *entry) 606 { 607 struct ocelot *ocelot = port->ocelot; 608 char mac[ETH_ALEN]; 609 u32 val, dst, macl, mach; 610 611 /* Set row and column to read from */ 612 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_M_INDEX, row); 613 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_BUCKET, col); 614 615 /* Issue a read command */ 616 ocelot_write(ocelot, 617 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_READ), 618 ANA_TABLES_MACACCESS); 619 620 if (ocelot_mact_wait_for_completion(ocelot)) 621 return -ETIMEDOUT; 622 623 /* Read the entry flags */ 624 val = ocelot_read(ocelot, ANA_TABLES_MACACCESS); 625 if (!(val & ANA_TABLES_MACACCESS_VALID)) 626 return -EINVAL; 627 628 /* If the entry read has another port configured as its destination, 629 * do not report it. 630 */ 631 dst = (val & ANA_TABLES_MACACCESS_DEST_IDX_M) >> 3; 632 if (dst != port->chip_port) 633 return -EINVAL; 634 635 /* Get the entry's MAC address and VLAN id */ 636 macl = ocelot_read(ocelot, ANA_TABLES_MACLDATA); 637 mach = ocelot_read(ocelot, ANA_TABLES_MACHDATA); 638 639 mac[0] = (mach >> 8) & 0xff; 640 mac[1] = (mach >> 0) & 0xff; 641 mac[2] = (macl >> 24) & 0xff; 642 mac[3] = (macl >> 16) & 0xff; 643 mac[4] = (macl >> 8) & 0xff; 644 mac[5] = (macl >> 0) & 0xff; 645 646 entry->vid = (mach >> 16) & 0xfff; 647 ether_addr_copy(entry->mac, mac); 648 649 return 0; 650 } 651 652 static int ocelot_fdb_dump(struct sk_buff *skb, struct netlink_callback *cb, 653 struct net_device *dev, 654 struct net_device *filter_dev, int *idx) 655 { 656 struct ocelot_port *port = netdev_priv(dev); 657 int i, j, ret = 0; 658 struct ocelot_dump_ctx dump = { 659 .dev = dev, 660 .skb = skb, 661 .cb = cb, 662 .idx = *idx, 663 }; 664 665 struct ocelot_mact_entry entry; 666 667 /* Loop through all the mac tables entries. There are 1024 rows of 4 668 * entries. 669 */ 670 for (i = 0; i < 1024; i++) { 671 for (j = 0; j < 4; j++) { 672 ret = ocelot_mact_read(port, i, j, &entry); 673 /* If the entry is invalid (wrong port, invalid...), 674 * skip it. 675 */ 676 if (ret == -EINVAL) 677 continue; 678 else if (ret) 679 goto end; 680 681 ret = ocelot_fdb_do_dump(&entry, &dump); 682 if (ret) 683 goto end; 684 } 685 } 686 687 end: 688 *idx = dump.idx; 689 return ret; 690 } 691 692 static const struct net_device_ops ocelot_port_netdev_ops = { 693 .ndo_open = ocelot_port_open, 694 .ndo_stop = ocelot_port_stop, 695 .ndo_start_xmit = ocelot_port_xmit, 696 .ndo_set_rx_mode = ocelot_set_rx_mode, 697 .ndo_get_phys_port_name = ocelot_port_get_phys_port_name, 698 .ndo_set_mac_address = ocelot_port_set_mac_address, 699 .ndo_get_stats64 = ocelot_get_stats64, 700 .ndo_fdb_add = ocelot_fdb_add, 701 .ndo_fdb_del = ocelot_fdb_del, 702 .ndo_fdb_dump = ocelot_fdb_dump, 703 }; 704 705 static void ocelot_get_strings(struct net_device *netdev, u32 sset, u8 *data) 706 { 707 struct ocelot_port *port = netdev_priv(netdev); 708 struct ocelot *ocelot = port->ocelot; 709 int i; 710 711 if (sset != ETH_SS_STATS) 712 return; 713 714 for (i = 0; i < ocelot->num_stats; i++) 715 memcpy(data + i * ETH_GSTRING_LEN, ocelot->stats_layout[i].name, 716 ETH_GSTRING_LEN); 717 } 718 719 static void ocelot_check_stats(struct work_struct *work) 720 { 721 struct delayed_work *del_work = to_delayed_work(work); 722 struct ocelot *ocelot = container_of(del_work, struct ocelot, stats_work); 723 int i, j; 724 725 mutex_lock(&ocelot->stats_lock); 726 727 for (i = 0; i < ocelot->num_phys_ports; i++) { 728 /* Configure the port to read the stats from */ 729 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(i), SYS_STAT_CFG); 730 731 for (j = 0; j < ocelot->num_stats; j++) { 732 u32 val; 733 unsigned int idx = i * ocelot->num_stats + j; 734 735 val = ocelot_read_rix(ocelot, SYS_COUNT_RX_OCTETS, 736 ocelot->stats_layout[j].offset); 737 738 if (val < (ocelot->stats[idx] & U32_MAX)) 739 ocelot->stats[idx] += (u64)1 << 32; 740 741 ocelot->stats[idx] = (ocelot->stats[idx] & 742 ~(u64)U32_MAX) + val; 743 } 744 } 745 746 cancel_delayed_work(&ocelot->stats_work); 747 queue_delayed_work(ocelot->stats_queue, &ocelot->stats_work, 748 OCELOT_STATS_CHECK_DELAY); 749 750 mutex_unlock(&ocelot->stats_lock); 751 } 752 753 static void ocelot_get_ethtool_stats(struct net_device *dev, 754 struct ethtool_stats *stats, u64 *data) 755 { 756 struct ocelot_port *port = netdev_priv(dev); 757 struct ocelot *ocelot = port->ocelot; 758 int i; 759 760 /* check and update now */ 761 ocelot_check_stats(&ocelot->stats_work.work); 762 763 /* Copy all counters */ 764 for (i = 0; i < ocelot->num_stats; i++) 765 *data++ = ocelot->stats[port->chip_port * ocelot->num_stats + i]; 766 } 767 768 static int ocelot_get_sset_count(struct net_device *dev, int sset) 769 { 770 struct ocelot_port *port = netdev_priv(dev); 771 struct ocelot *ocelot = port->ocelot; 772 773 if (sset != ETH_SS_STATS) 774 return -EOPNOTSUPP; 775 return ocelot->num_stats; 776 } 777 778 static const struct ethtool_ops ocelot_ethtool_ops = { 779 .get_strings = ocelot_get_strings, 780 .get_ethtool_stats = ocelot_get_ethtool_stats, 781 .get_sset_count = ocelot_get_sset_count, 782 }; 783 784 static int ocelot_port_attr_get(struct net_device *dev, 785 struct switchdev_attr *attr) 786 { 787 struct ocelot_port *ocelot_port = netdev_priv(dev); 788 struct ocelot *ocelot = ocelot_port->ocelot; 789 790 switch (attr->id) { 791 case SWITCHDEV_ATTR_ID_PORT_PARENT_ID: 792 attr->u.ppid.id_len = sizeof(ocelot->base_mac); 793 memcpy(&attr->u.ppid.id, &ocelot->base_mac, 794 attr->u.ppid.id_len); 795 break; 796 default: 797 return -EOPNOTSUPP; 798 } 799 800 return 0; 801 } 802 803 static int ocelot_port_attr_stp_state_set(struct ocelot_port *ocelot_port, 804 struct switchdev_trans *trans, 805 u8 state) 806 { 807 struct ocelot *ocelot = ocelot_port->ocelot; 808 u32 port_cfg; 809 int port, i; 810 811 if (switchdev_trans_ph_prepare(trans)) 812 return 0; 813 814 if (!(BIT(ocelot_port->chip_port) & ocelot->bridge_mask)) 815 return 0; 816 817 port_cfg = ocelot_read_gix(ocelot, ANA_PORT_PORT_CFG, 818 ocelot_port->chip_port); 819 820 switch (state) { 821 case BR_STATE_FORWARDING: 822 ocelot->bridge_fwd_mask |= BIT(ocelot_port->chip_port); 823 /* Fallthrough */ 824 case BR_STATE_LEARNING: 825 port_cfg |= ANA_PORT_PORT_CFG_LEARN_ENA; 826 break; 827 828 default: 829 port_cfg &= ~ANA_PORT_PORT_CFG_LEARN_ENA; 830 ocelot->bridge_fwd_mask &= ~BIT(ocelot_port->chip_port); 831 break; 832 } 833 834 ocelot_write_gix(ocelot, port_cfg, ANA_PORT_PORT_CFG, 835 ocelot_port->chip_port); 836 837 /* Apply FWD mask. The loop is needed to add/remove the current port as 838 * a source for the other ports. 839 */ 840 for (port = 0; port < ocelot->num_phys_ports; port++) { 841 if (ocelot->bridge_fwd_mask & BIT(port)) { 842 unsigned long mask = ocelot->bridge_fwd_mask & ~BIT(port); 843 844 for (i = 0; i < ocelot->num_phys_ports; i++) { 845 unsigned long bond_mask = ocelot->lags[i]; 846 847 if (!bond_mask) 848 continue; 849 850 if (bond_mask & BIT(port)) { 851 mask &= ~bond_mask; 852 break; 853 } 854 } 855 856 ocelot_write_rix(ocelot, 857 BIT(ocelot->num_phys_ports) | mask, 858 ANA_PGID_PGID, PGID_SRC + port); 859 } else { 860 /* Only the CPU port, this is compatible with link 861 * aggregation. 862 */ 863 ocelot_write_rix(ocelot, 864 BIT(ocelot->num_phys_ports), 865 ANA_PGID_PGID, PGID_SRC + port); 866 } 867 } 868 869 return 0; 870 } 871 872 static void ocelot_port_attr_ageing_set(struct ocelot_port *ocelot_port, 873 unsigned long ageing_clock_t) 874 { 875 struct ocelot *ocelot = ocelot_port->ocelot; 876 unsigned long ageing_jiffies = clock_t_to_jiffies(ageing_clock_t); 877 u32 ageing_time = jiffies_to_msecs(ageing_jiffies) / 1000; 878 879 ocelot_write(ocelot, ANA_AUTOAGE_AGE_PERIOD(ageing_time / 2), 880 ANA_AUTOAGE); 881 } 882 883 static void ocelot_port_attr_mc_set(struct ocelot_port *port, bool mc) 884 { 885 struct ocelot *ocelot = port->ocelot; 886 u32 val = ocelot_read_gix(ocelot, ANA_PORT_CPU_FWD_CFG, 887 port->chip_port); 888 889 if (mc) 890 val |= ANA_PORT_CPU_FWD_CFG_CPU_IGMP_REDIR_ENA | 891 ANA_PORT_CPU_FWD_CFG_CPU_MLD_REDIR_ENA | 892 ANA_PORT_CPU_FWD_CFG_CPU_IPMC_CTRL_COPY_ENA; 893 else 894 val &= ~(ANA_PORT_CPU_FWD_CFG_CPU_IGMP_REDIR_ENA | 895 ANA_PORT_CPU_FWD_CFG_CPU_MLD_REDIR_ENA | 896 ANA_PORT_CPU_FWD_CFG_CPU_IPMC_CTRL_COPY_ENA); 897 898 ocelot_write_gix(ocelot, val, ANA_PORT_CPU_FWD_CFG, port->chip_port); 899 } 900 901 static int ocelot_port_attr_set(struct net_device *dev, 902 const struct switchdev_attr *attr, 903 struct switchdev_trans *trans) 904 { 905 struct ocelot_port *ocelot_port = netdev_priv(dev); 906 int err = 0; 907 908 switch (attr->id) { 909 case SWITCHDEV_ATTR_ID_PORT_STP_STATE: 910 ocelot_port_attr_stp_state_set(ocelot_port, trans, 911 attr->u.stp_state); 912 break; 913 case SWITCHDEV_ATTR_ID_BRIDGE_AGEING_TIME: 914 ocelot_port_attr_ageing_set(ocelot_port, attr->u.ageing_time); 915 break; 916 case SWITCHDEV_ATTR_ID_BRIDGE_MC_DISABLED: 917 ocelot_port_attr_mc_set(ocelot_port, !attr->u.mc_disabled); 918 break; 919 default: 920 err = -EOPNOTSUPP; 921 break; 922 } 923 924 return err; 925 } 926 927 static struct ocelot_multicast *ocelot_multicast_get(struct ocelot *ocelot, 928 const unsigned char *addr, 929 u16 vid) 930 { 931 struct ocelot_multicast *mc; 932 933 list_for_each_entry(mc, &ocelot->multicast, list) { 934 if (ether_addr_equal(mc->addr, addr) && mc->vid == vid) 935 return mc; 936 } 937 938 return NULL; 939 } 940 941 static int ocelot_port_obj_add_mdb(struct net_device *dev, 942 const struct switchdev_obj_port_mdb *mdb, 943 struct switchdev_trans *trans) 944 { 945 struct ocelot_port *port = netdev_priv(dev); 946 struct ocelot *ocelot = port->ocelot; 947 struct ocelot_multicast *mc; 948 unsigned char addr[ETH_ALEN]; 949 u16 vid = mdb->vid; 950 bool new = false; 951 952 if (!vid) 953 vid = 1; 954 955 mc = ocelot_multicast_get(ocelot, mdb->addr, vid); 956 if (!mc) { 957 mc = devm_kzalloc(ocelot->dev, sizeof(*mc), GFP_KERNEL); 958 if (!mc) 959 return -ENOMEM; 960 961 memcpy(mc->addr, mdb->addr, ETH_ALEN); 962 mc->vid = vid; 963 964 list_add_tail(&mc->list, &ocelot->multicast); 965 new = true; 966 } 967 968 memcpy(addr, mc->addr, ETH_ALEN); 969 addr[0] = 0; 970 971 if (!new) { 972 addr[2] = mc->ports << 0; 973 addr[1] = mc->ports << 8; 974 ocelot_mact_forget(ocelot, addr, vid); 975 } 976 977 mc->ports |= BIT(port->chip_port); 978 addr[2] = mc->ports << 0; 979 addr[1] = mc->ports << 8; 980 981 return ocelot_mact_learn(ocelot, 0, addr, vid, ENTRYTYPE_MACv4); 982 } 983 984 static int ocelot_port_obj_del_mdb(struct net_device *dev, 985 const struct switchdev_obj_port_mdb *mdb) 986 { 987 struct ocelot_port *port = netdev_priv(dev); 988 struct ocelot *ocelot = port->ocelot; 989 struct ocelot_multicast *mc; 990 unsigned char addr[ETH_ALEN]; 991 u16 vid = mdb->vid; 992 993 if (!vid) 994 vid = 1; 995 996 mc = ocelot_multicast_get(ocelot, mdb->addr, vid); 997 if (!mc) 998 return -ENOENT; 999 1000 memcpy(addr, mc->addr, ETH_ALEN); 1001 addr[2] = mc->ports << 0; 1002 addr[1] = mc->ports << 8; 1003 addr[0] = 0; 1004 ocelot_mact_forget(ocelot, addr, vid); 1005 1006 mc->ports &= ~BIT(port->chip_port); 1007 if (!mc->ports) { 1008 list_del(&mc->list); 1009 devm_kfree(ocelot->dev, mc); 1010 return 0; 1011 } 1012 1013 addr[2] = mc->ports << 0; 1014 addr[1] = mc->ports << 8; 1015 1016 return ocelot_mact_learn(ocelot, 0, addr, vid, ENTRYTYPE_MACv4); 1017 } 1018 1019 static int ocelot_port_obj_add(struct net_device *dev, 1020 const struct switchdev_obj *obj, 1021 struct switchdev_trans *trans) 1022 { 1023 int ret = 0; 1024 1025 switch (obj->id) { 1026 case SWITCHDEV_OBJ_ID_PORT_MDB: 1027 ret = ocelot_port_obj_add_mdb(dev, SWITCHDEV_OBJ_PORT_MDB(obj), 1028 trans); 1029 break; 1030 default: 1031 return -EOPNOTSUPP; 1032 } 1033 1034 return ret; 1035 } 1036 1037 static int ocelot_port_obj_del(struct net_device *dev, 1038 const struct switchdev_obj *obj) 1039 { 1040 int ret = 0; 1041 1042 switch (obj->id) { 1043 case SWITCHDEV_OBJ_ID_PORT_MDB: 1044 ret = ocelot_port_obj_del_mdb(dev, SWITCHDEV_OBJ_PORT_MDB(obj)); 1045 break; 1046 default: 1047 return -EOPNOTSUPP; 1048 } 1049 1050 return ret; 1051 } 1052 1053 static const struct switchdev_ops ocelot_port_switchdev_ops = { 1054 .switchdev_port_attr_get = ocelot_port_attr_get, 1055 .switchdev_port_attr_set = ocelot_port_attr_set, 1056 .switchdev_port_obj_add = ocelot_port_obj_add, 1057 .switchdev_port_obj_del = ocelot_port_obj_del, 1058 }; 1059 1060 static int ocelot_port_bridge_join(struct ocelot_port *ocelot_port, 1061 struct net_device *bridge) 1062 { 1063 struct ocelot *ocelot = ocelot_port->ocelot; 1064 1065 if (!ocelot->bridge_mask) { 1066 ocelot->hw_bridge_dev = bridge; 1067 } else { 1068 if (ocelot->hw_bridge_dev != bridge) 1069 /* This is adding the port to a second bridge, this is 1070 * unsupported */ 1071 return -ENODEV; 1072 } 1073 1074 ocelot->bridge_mask |= BIT(ocelot_port->chip_port); 1075 1076 return 0; 1077 } 1078 1079 static void ocelot_port_bridge_leave(struct ocelot_port *ocelot_port, 1080 struct net_device *bridge) 1081 { 1082 struct ocelot *ocelot = ocelot_port->ocelot; 1083 1084 ocelot->bridge_mask &= ~BIT(ocelot_port->chip_port); 1085 1086 if (!ocelot->bridge_mask) 1087 ocelot->hw_bridge_dev = NULL; 1088 } 1089 1090 /* Checks if the net_device instance given to us originate from our driver. */ 1091 static bool ocelot_netdevice_dev_check(const struct net_device *dev) 1092 { 1093 return dev->netdev_ops == &ocelot_port_netdev_ops; 1094 } 1095 1096 static int ocelot_netdevice_port_event(struct net_device *dev, 1097 unsigned long event, 1098 struct netdev_notifier_changeupper_info *info) 1099 { 1100 struct ocelot_port *ocelot_port = netdev_priv(dev); 1101 int err = 0; 1102 1103 if (!ocelot_netdevice_dev_check(dev)) 1104 return 0; 1105 1106 switch (event) { 1107 case NETDEV_CHANGEUPPER: 1108 if (netif_is_bridge_master(info->upper_dev)) { 1109 if (info->linking) 1110 err = ocelot_port_bridge_join(ocelot_port, 1111 info->upper_dev); 1112 else 1113 ocelot_port_bridge_leave(ocelot_port, 1114 info->upper_dev); 1115 } 1116 break; 1117 default: 1118 break; 1119 } 1120 1121 return err; 1122 } 1123 1124 static int ocelot_netdevice_event(struct notifier_block *unused, 1125 unsigned long event, void *ptr) 1126 { 1127 struct netdev_notifier_changeupper_info *info = ptr; 1128 struct net_device *dev = netdev_notifier_info_to_dev(ptr); 1129 int ret = 0; 1130 1131 if (netif_is_lag_master(dev)) { 1132 struct net_device *slave; 1133 struct list_head *iter; 1134 1135 netdev_for_each_lower_dev(dev, slave, iter) { 1136 ret = ocelot_netdevice_port_event(slave, event, info); 1137 if (ret) 1138 goto notify; 1139 } 1140 } else { 1141 ret = ocelot_netdevice_port_event(dev, event, info); 1142 } 1143 1144 notify: 1145 return notifier_from_errno(ret); 1146 } 1147 1148 struct notifier_block ocelot_netdevice_nb __read_mostly = { 1149 .notifier_call = ocelot_netdevice_event, 1150 }; 1151 EXPORT_SYMBOL(ocelot_netdevice_nb); 1152 1153 int ocelot_probe_port(struct ocelot *ocelot, u8 port, 1154 void __iomem *regs, 1155 struct phy_device *phy) 1156 { 1157 struct ocelot_port *ocelot_port; 1158 struct net_device *dev; 1159 int err; 1160 1161 dev = alloc_etherdev(sizeof(struct ocelot_port)); 1162 if (!dev) 1163 return -ENOMEM; 1164 SET_NETDEV_DEV(dev, ocelot->dev); 1165 ocelot_port = netdev_priv(dev); 1166 ocelot_port->dev = dev; 1167 ocelot_port->ocelot = ocelot; 1168 ocelot_port->regs = regs; 1169 ocelot_port->chip_port = port; 1170 ocelot_port->phy = phy; 1171 INIT_LIST_HEAD(&ocelot_port->mc); 1172 ocelot->ports[port] = ocelot_port; 1173 1174 dev->netdev_ops = &ocelot_port_netdev_ops; 1175 dev->ethtool_ops = &ocelot_ethtool_ops; 1176 dev->switchdev_ops = &ocelot_port_switchdev_ops; 1177 1178 memcpy(dev->dev_addr, ocelot->base_mac, ETH_ALEN); 1179 dev->dev_addr[ETH_ALEN - 1] += port; 1180 ocelot_mact_learn(ocelot, PGID_CPU, dev->dev_addr, ocelot_port->pvid, 1181 ENTRYTYPE_LOCKED); 1182 1183 err = register_netdev(dev); 1184 if (err) { 1185 dev_err(ocelot->dev, "register_netdev failed\n"); 1186 goto err_register_netdev; 1187 } 1188 1189 return 0; 1190 1191 err_register_netdev: 1192 free_netdev(dev); 1193 return err; 1194 } 1195 EXPORT_SYMBOL(ocelot_probe_port); 1196 1197 int ocelot_init(struct ocelot *ocelot) 1198 { 1199 u32 port; 1200 int i, cpu = ocelot->num_phys_ports; 1201 char queue_name[32]; 1202 1203 ocelot->stats = devm_kcalloc(ocelot->dev, 1204 ocelot->num_phys_ports * ocelot->num_stats, 1205 sizeof(u64), GFP_KERNEL); 1206 if (!ocelot->stats) 1207 return -ENOMEM; 1208 1209 mutex_init(&ocelot->stats_lock); 1210 snprintf(queue_name, sizeof(queue_name), "%s-stats", 1211 dev_name(ocelot->dev)); 1212 ocelot->stats_queue = create_singlethread_workqueue(queue_name); 1213 if (!ocelot->stats_queue) 1214 return -ENOMEM; 1215 1216 ocelot_mact_init(ocelot); 1217 ocelot_vlan_init(ocelot); 1218 1219 for (port = 0; port < ocelot->num_phys_ports; port++) { 1220 /* Clear all counters (5 groups) */ 1221 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(port) | 1222 SYS_STAT_CFG_STAT_CLEAR_SHOT(0x7f), 1223 SYS_STAT_CFG); 1224 } 1225 1226 /* Only use S-Tag */ 1227 ocelot_write(ocelot, ETH_P_8021AD, SYS_VLAN_ETYPE_CFG); 1228 1229 /* Aggregation mode */ 1230 ocelot_write(ocelot, ANA_AGGR_CFG_AC_SMAC_ENA | 1231 ANA_AGGR_CFG_AC_DMAC_ENA | 1232 ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA | 1233 ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA, ANA_AGGR_CFG); 1234 1235 /* Set MAC age time to default value. The entry is aged after 1236 * 2*AGE_PERIOD 1237 */ 1238 ocelot_write(ocelot, 1239 ANA_AUTOAGE_AGE_PERIOD(BR_DEFAULT_AGEING_TIME / 2 / HZ), 1240 ANA_AUTOAGE); 1241 1242 /* Disable learning for frames discarded by VLAN ingress filtering */ 1243 regmap_field_write(ocelot->regfields[ANA_ADVLEARN_VLAN_CHK], 1); 1244 1245 /* Setup frame ageing - fixed value "2 sec" - in 6.5 us units */ 1246 ocelot_write(ocelot, SYS_FRM_AGING_AGE_TX_ENA | 1247 SYS_FRM_AGING_MAX_AGE(307692), SYS_FRM_AGING); 1248 1249 /* Setup flooding PGIDs */ 1250 ocelot_write_rix(ocelot, ANA_FLOODING_FLD_MULTICAST(PGID_MC) | 1251 ANA_FLOODING_FLD_BROADCAST(PGID_MC) | 1252 ANA_FLOODING_FLD_UNICAST(PGID_UC), 1253 ANA_FLOODING, 0); 1254 ocelot_write(ocelot, ANA_FLOODING_IPMC_FLD_MC6_DATA(PGID_MCIPV6) | 1255 ANA_FLOODING_IPMC_FLD_MC6_CTRL(PGID_MC) | 1256 ANA_FLOODING_IPMC_FLD_MC4_DATA(PGID_MCIPV4) | 1257 ANA_FLOODING_IPMC_FLD_MC4_CTRL(PGID_MC), 1258 ANA_FLOODING_IPMC); 1259 1260 for (port = 0; port < ocelot->num_phys_ports; port++) { 1261 /* Transmit the frame to the local port. */ 1262 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port); 1263 /* Do not forward BPDU frames to the front ports. */ 1264 ocelot_write_gix(ocelot, 1265 ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA(0xffff), 1266 ANA_PORT_CPU_FWD_BPDU_CFG, 1267 port); 1268 /* Ensure bridging is disabled */ 1269 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_SRC + port); 1270 } 1271 1272 /* Configure and enable the CPU port. */ 1273 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, cpu); 1274 ocelot_write_rix(ocelot, BIT(cpu), ANA_PGID_PGID, PGID_CPU); 1275 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_RECV_ENA | 1276 ANA_PORT_PORT_CFG_PORTID_VAL(cpu), 1277 ANA_PORT_PORT_CFG, cpu); 1278 1279 /* Allow broadcast MAC frames. */ 1280 for (i = ocelot->num_phys_ports + 1; i < PGID_CPU; i++) { 1281 u32 val = ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports - 1, 0)); 1282 1283 ocelot_write_rix(ocelot, val, ANA_PGID_PGID, i); 1284 } 1285 ocelot_write_rix(ocelot, 1286 ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports, 0)), 1287 ANA_PGID_PGID, PGID_MC); 1288 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV4); 1289 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV6); 1290 1291 /* CPU port Injection/Extraction configuration */ 1292 ocelot_write_rix(ocelot, QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE | 1293 QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG(1) | 1294 QSYS_SWITCH_PORT_MODE_PORT_ENA, 1295 QSYS_SWITCH_PORT_MODE, cpu); 1296 ocelot_write_rix(ocelot, SYS_PORT_MODE_INCL_XTR_HDR(1) | 1297 SYS_PORT_MODE_INCL_INJ_HDR(1), SYS_PORT_MODE, cpu); 1298 /* Allow manual injection via DEVCPU_QS registers, and byte swap these 1299 * registers endianness. 1300 */ 1301 ocelot_write_rix(ocelot, QS_INJ_GRP_CFG_BYTE_SWAP | 1302 QS_INJ_GRP_CFG_MODE(1), QS_INJ_GRP_CFG, 0); 1303 ocelot_write_rix(ocelot, QS_XTR_GRP_CFG_BYTE_SWAP | 1304 QS_XTR_GRP_CFG_MODE(1), QS_XTR_GRP_CFG, 0); 1305 ocelot_write(ocelot, ANA_CPUQ_CFG_CPUQ_MIRROR(2) | 1306 ANA_CPUQ_CFG_CPUQ_LRN(2) | 1307 ANA_CPUQ_CFG_CPUQ_MAC_COPY(2) | 1308 ANA_CPUQ_CFG_CPUQ_SRC_COPY(2) | 1309 ANA_CPUQ_CFG_CPUQ_LOCKED_PORTMOVE(2) | 1310 ANA_CPUQ_CFG_CPUQ_ALLBRIDGE(6) | 1311 ANA_CPUQ_CFG_CPUQ_IPMC_CTRL(6) | 1312 ANA_CPUQ_CFG_CPUQ_IGMP(6) | 1313 ANA_CPUQ_CFG_CPUQ_MLD(6), ANA_CPUQ_CFG); 1314 for (i = 0; i < 16; i++) 1315 ocelot_write_rix(ocelot, ANA_CPUQ_8021_CFG_CPUQ_GARP_VAL(6) | 1316 ANA_CPUQ_8021_CFG_CPUQ_BPDU_VAL(6), 1317 ANA_CPUQ_8021_CFG, i); 1318 1319 INIT_DELAYED_WORK(&ocelot->stats_work, ocelot_check_stats); 1320 queue_delayed_work(ocelot->stats_queue, &ocelot->stats_work, 1321 OCELOT_STATS_CHECK_DELAY); 1322 return 0; 1323 } 1324 EXPORT_SYMBOL(ocelot_init); 1325 1326 void ocelot_deinit(struct ocelot *ocelot) 1327 { 1328 destroy_workqueue(ocelot->stats_queue); 1329 mutex_destroy(&ocelot->stats_lock); 1330 } 1331 EXPORT_SYMBOL(ocelot_deinit); 1332 1333 MODULE_LICENSE("Dual MIT/GPL"); 1334