1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* 3 * Microsemi Ocelot Switch driver 4 * 5 * Copyright (c) 2017 Microsemi Corporation 6 */ 7 #include <linux/if_bridge.h> 8 #include <soc/mscc/ocelot_vcap.h> 9 #include "ocelot.h" 10 #include "ocelot_vcap.h" 11 12 #define TABLE_UPDATE_SLEEP_US 10 13 #define TABLE_UPDATE_TIMEOUT_US 100000 14 15 struct ocelot_mact_entry { 16 u8 mac[ETH_ALEN]; 17 u16 vid; 18 enum macaccess_entry_type type; 19 }; 20 21 static inline u32 ocelot_mact_read_macaccess(struct ocelot *ocelot) 22 { 23 return ocelot_read(ocelot, ANA_TABLES_MACACCESS); 24 } 25 26 static inline int ocelot_mact_wait_for_completion(struct ocelot *ocelot) 27 { 28 u32 val; 29 30 return readx_poll_timeout(ocelot_mact_read_macaccess, 31 ocelot, val, 32 (val & ANA_TABLES_MACACCESS_MAC_TABLE_CMD_M) == 33 MACACCESS_CMD_IDLE, 34 TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US); 35 } 36 37 static void ocelot_mact_select(struct ocelot *ocelot, 38 const unsigned char mac[ETH_ALEN], 39 unsigned int vid) 40 { 41 u32 macl = 0, mach = 0; 42 43 /* Set the MAC address to handle and the vlan associated in a format 44 * understood by the hardware. 45 */ 46 mach |= vid << 16; 47 mach |= mac[0] << 8; 48 mach |= mac[1] << 0; 49 macl |= mac[2] << 24; 50 macl |= mac[3] << 16; 51 macl |= mac[4] << 8; 52 macl |= mac[5] << 0; 53 54 ocelot_write(ocelot, macl, ANA_TABLES_MACLDATA); 55 ocelot_write(ocelot, mach, ANA_TABLES_MACHDATA); 56 57 } 58 59 int ocelot_mact_learn(struct ocelot *ocelot, int port, 60 const unsigned char mac[ETH_ALEN], 61 unsigned int vid, enum macaccess_entry_type type) 62 { 63 ocelot_mact_select(ocelot, mac, vid); 64 65 /* Issue a write command */ 66 ocelot_write(ocelot, ANA_TABLES_MACACCESS_VALID | 67 ANA_TABLES_MACACCESS_DEST_IDX(port) | 68 ANA_TABLES_MACACCESS_ENTRYTYPE(type) | 69 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_LEARN), 70 ANA_TABLES_MACACCESS); 71 72 return ocelot_mact_wait_for_completion(ocelot); 73 } 74 EXPORT_SYMBOL(ocelot_mact_learn); 75 76 int ocelot_mact_forget(struct ocelot *ocelot, 77 const unsigned char mac[ETH_ALEN], unsigned int vid) 78 { 79 ocelot_mact_select(ocelot, mac, vid); 80 81 /* Issue a forget command */ 82 ocelot_write(ocelot, 83 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_FORGET), 84 ANA_TABLES_MACACCESS); 85 86 return ocelot_mact_wait_for_completion(ocelot); 87 } 88 EXPORT_SYMBOL(ocelot_mact_forget); 89 90 static void ocelot_mact_init(struct ocelot *ocelot) 91 { 92 /* Configure the learning mode entries attributes: 93 * - Do not copy the frame to the CPU extraction queues. 94 * - Use the vlan and mac_cpoy for dmac lookup. 95 */ 96 ocelot_rmw(ocelot, 0, 97 ANA_AGENCTRL_LEARN_CPU_COPY | ANA_AGENCTRL_IGNORE_DMAC_FLAGS 98 | ANA_AGENCTRL_LEARN_FWD_KILL 99 | ANA_AGENCTRL_LEARN_IGNORE_VLAN, 100 ANA_AGENCTRL); 101 102 /* Clear the MAC table */ 103 ocelot_write(ocelot, MACACCESS_CMD_INIT, ANA_TABLES_MACACCESS); 104 } 105 106 static void ocelot_vcap_enable(struct ocelot *ocelot, int port) 107 { 108 ocelot_write_gix(ocelot, ANA_PORT_VCAP_S2_CFG_S2_ENA | 109 ANA_PORT_VCAP_S2_CFG_S2_IP6_CFG(0xa), 110 ANA_PORT_VCAP_S2_CFG, port); 111 112 ocelot_write_gix(ocelot, ANA_PORT_VCAP_CFG_S1_ENA, 113 ANA_PORT_VCAP_CFG, port); 114 115 ocelot_rmw_gix(ocelot, REW_PORT_CFG_ES0_EN, 116 REW_PORT_CFG_ES0_EN, 117 REW_PORT_CFG, port); 118 } 119 120 static inline u32 ocelot_vlant_read_vlanaccess(struct ocelot *ocelot) 121 { 122 return ocelot_read(ocelot, ANA_TABLES_VLANACCESS); 123 } 124 125 static inline int ocelot_vlant_wait_for_completion(struct ocelot *ocelot) 126 { 127 u32 val; 128 129 return readx_poll_timeout(ocelot_vlant_read_vlanaccess, 130 ocelot, 131 val, 132 (val & ANA_TABLES_VLANACCESS_VLAN_TBL_CMD_M) == 133 ANA_TABLES_VLANACCESS_CMD_IDLE, 134 TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US); 135 } 136 137 static int ocelot_vlant_set_mask(struct ocelot *ocelot, u16 vid, u32 mask) 138 { 139 /* Select the VID to configure */ 140 ocelot_write(ocelot, ANA_TABLES_VLANTIDX_V_INDEX(vid), 141 ANA_TABLES_VLANTIDX); 142 /* Set the vlan port members mask and issue a write command */ 143 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_VLAN_PORT_MASK(mask) | 144 ANA_TABLES_VLANACCESS_CMD_WRITE, 145 ANA_TABLES_VLANACCESS); 146 147 return ocelot_vlant_wait_for_completion(ocelot); 148 } 149 150 static int ocelot_port_set_native_vlan(struct ocelot *ocelot, int port, 151 u16 vid) 152 { 153 struct ocelot_port *ocelot_port = ocelot->ports[port]; 154 u32 val = 0; 155 156 if (ocelot_port->vid != vid) { 157 /* Always permit deleting the native VLAN (vid = 0) */ 158 if (ocelot_port->vid && vid) { 159 dev_err(ocelot->dev, 160 "Port already has a native VLAN: %d\n", 161 ocelot_port->vid); 162 return -EBUSY; 163 } 164 ocelot_port->vid = vid; 165 } 166 167 ocelot_rmw_gix(ocelot, REW_PORT_VLAN_CFG_PORT_VID(vid), 168 REW_PORT_VLAN_CFG_PORT_VID_M, 169 REW_PORT_VLAN_CFG, port); 170 171 if (ocelot_port->vlan_aware && !ocelot_port->vid) 172 /* If port is vlan-aware and tagged, drop untagged and priority 173 * tagged frames. 174 */ 175 val = ANA_PORT_DROP_CFG_DROP_UNTAGGED_ENA | 176 ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA | 177 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA; 178 ocelot_rmw_gix(ocelot, val, 179 ANA_PORT_DROP_CFG_DROP_UNTAGGED_ENA | 180 ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA | 181 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA, 182 ANA_PORT_DROP_CFG, port); 183 184 if (ocelot_port->vlan_aware) { 185 if (ocelot_port->vid) 186 /* Tag all frames except when VID == DEFAULT_VLAN */ 187 val = REW_TAG_CFG_TAG_CFG(1); 188 else 189 /* Tag all frames */ 190 val = REW_TAG_CFG_TAG_CFG(3); 191 } else { 192 /* Port tagging disabled. */ 193 val = REW_TAG_CFG_TAG_CFG(0); 194 } 195 ocelot_rmw_gix(ocelot, val, 196 REW_TAG_CFG_TAG_CFG_M, 197 REW_TAG_CFG, port); 198 199 return 0; 200 } 201 202 /* Default vlan to clasify for untagged frames (may be zero) */ 203 static void ocelot_port_set_pvid(struct ocelot *ocelot, int port, u16 pvid) 204 { 205 struct ocelot_port *ocelot_port = ocelot->ports[port]; 206 207 ocelot_port->pvid = pvid; 208 209 if (!ocelot_port->vlan_aware) 210 pvid = 0; 211 212 ocelot_rmw_gix(ocelot, 213 ANA_PORT_VLAN_CFG_VLAN_VID(pvid), 214 ANA_PORT_VLAN_CFG_VLAN_VID_M, 215 ANA_PORT_VLAN_CFG, port); 216 } 217 218 int ocelot_port_vlan_filtering(struct ocelot *ocelot, int port, 219 bool vlan_aware, struct switchdev_trans *trans) 220 { 221 struct ocelot_port *ocelot_port = ocelot->ports[port]; 222 u32 val; 223 224 if (switchdev_trans_ph_prepare(trans)) { 225 struct ocelot_vcap_block *block = &ocelot->block[VCAP_IS1]; 226 struct ocelot_vcap_filter *filter; 227 228 list_for_each_entry(filter, &block->rules, list) { 229 if (filter->ingress_port_mask & BIT(port) && 230 filter->action.vid_replace_ena) { 231 dev_err(ocelot->dev, 232 "Cannot change VLAN state with vlan modify rules active\n"); 233 return -EBUSY; 234 } 235 } 236 237 return 0; 238 } 239 240 ocelot_port->vlan_aware = vlan_aware; 241 242 if (vlan_aware) 243 val = ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 244 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1); 245 else 246 val = 0; 247 ocelot_rmw_gix(ocelot, val, 248 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 249 ANA_PORT_VLAN_CFG_VLAN_POP_CNT_M, 250 ANA_PORT_VLAN_CFG, port); 251 252 ocelot_port_set_pvid(ocelot, port, ocelot_port->pvid); 253 ocelot_port_set_native_vlan(ocelot, port, ocelot_port->vid); 254 255 return 0; 256 } 257 EXPORT_SYMBOL(ocelot_port_vlan_filtering); 258 259 int ocelot_vlan_add(struct ocelot *ocelot, int port, u16 vid, bool pvid, 260 bool untagged) 261 { 262 int ret; 263 264 /* Make the port a member of the VLAN */ 265 ocelot->vlan_mask[vid] |= BIT(port); 266 ret = ocelot_vlant_set_mask(ocelot, vid, ocelot->vlan_mask[vid]); 267 if (ret) 268 return ret; 269 270 /* Default ingress vlan classification */ 271 if (pvid) 272 ocelot_port_set_pvid(ocelot, port, vid); 273 274 /* Untagged egress vlan clasification */ 275 if (untagged) { 276 ret = ocelot_port_set_native_vlan(ocelot, port, vid); 277 if (ret) 278 return ret; 279 } 280 281 return 0; 282 } 283 EXPORT_SYMBOL(ocelot_vlan_add); 284 285 int ocelot_vlan_del(struct ocelot *ocelot, int port, u16 vid) 286 { 287 struct ocelot_port *ocelot_port = ocelot->ports[port]; 288 int ret; 289 290 /* Stop the port from being a member of the vlan */ 291 ocelot->vlan_mask[vid] &= ~BIT(port); 292 ret = ocelot_vlant_set_mask(ocelot, vid, ocelot->vlan_mask[vid]); 293 if (ret) 294 return ret; 295 296 /* Ingress */ 297 if (ocelot_port->pvid == vid) 298 ocelot_port_set_pvid(ocelot, port, 0); 299 300 /* Egress */ 301 if (ocelot_port->vid == vid) 302 ocelot_port_set_native_vlan(ocelot, port, 0); 303 304 return 0; 305 } 306 EXPORT_SYMBOL(ocelot_vlan_del); 307 308 static void ocelot_vlan_init(struct ocelot *ocelot) 309 { 310 u16 port, vid; 311 312 /* Clear VLAN table, by default all ports are members of all VLANs */ 313 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_CMD_INIT, 314 ANA_TABLES_VLANACCESS); 315 ocelot_vlant_wait_for_completion(ocelot); 316 317 /* Configure the port VLAN memberships */ 318 for (vid = 1; vid < VLAN_N_VID; vid++) { 319 ocelot->vlan_mask[vid] = 0; 320 ocelot_vlant_set_mask(ocelot, vid, ocelot->vlan_mask[vid]); 321 } 322 323 /* Because VLAN filtering is enabled, we need VID 0 to get untagged 324 * traffic. It is added automatically if 8021q module is loaded, but 325 * we can't rely on it since module may be not loaded. 326 */ 327 ocelot->vlan_mask[0] = GENMASK(ocelot->num_phys_ports - 1, 0); 328 ocelot_vlant_set_mask(ocelot, 0, ocelot->vlan_mask[0]); 329 330 /* Set vlan ingress filter mask to all ports but the CPU port by 331 * default. 332 */ 333 ocelot_write(ocelot, GENMASK(ocelot->num_phys_ports - 1, 0), 334 ANA_VLANMASK); 335 336 for (port = 0; port < ocelot->num_phys_ports; port++) { 337 ocelot_write_gix(ocelot, 0, REW_PORT_VLAN_CFG, port); 338 ocelot_write_gix(ocelot, 0, REW_TAG_CFG, port); 339 } 340 } 341 342 void ocelot_adjust_link(struct ocelot *ocelot, int port, 343 struct phy_device *phydev) 344 { 345 struct ocelot_port *ocelot_port = ocelot->ports[port]; 346 int speed, mode = 0; 347 348 switch (phydev->speed) { 349 case SPEED_10: 350 speed = OCELOT_SPEED_10; 351 break; 352 case SPEED_100: 353 speed = OCELOT_SPEED_100; 354 break; 355 case SPEED_1000: 356 speed = OCELOT_SPEED_1000; 357 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA; 358 break; 359 case SPEED_2500: 360 speed = OCELOT_SPEED_2500; 361 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA; 362 break; 363 default: 364 dev_err(ocelot->dev, "Unsupported PHY speed on port %d: %d\n", 365 port, phydev->speed); 366 return; 367 } 368 369 phy_print_status(phydev); 370 371 if (!phydev->link) 372 return; 373 374 /* Only full duplex supported for now */ 375 ocelot_port_writel(ocelot_port, DEV_MAC_MODE_CFG_FDX_ENA | 376 mode, DEV_MAC_MODE_CFG); 377 378 /* Disable HDX fast control */ 379 ocelot_port_writel(ocelot_port, DEV_PORT_MISC_HDX_FAST_DIS, 380 DEV_PORT_MISC); 381 382 /* SGMII only for now */ 383 ocelot_port_writel(ocelot_port, PCS1G_MODE_CFG_SGMII_MODE_ENA, 384 PCS1G_MODE_CFG); 385 ocelot_port_writel(ocelot_port, PCS1G_SD_CFG_SD_SEL, PCS1G_SD_CFG); 386 387 /* Enable PCS */ 388 ocelot_port_writel(ocelot_port, PCS1G_CFG_PCS_ENA, PCS1G_CFG); 389 390 /* No aneg on SGMII */ 391 ocelot_port_writel(ocelot_port, 0, PCS1G_ANEG_CFG); 392 393 /* No loopback */ 394 ocelot_port_writel(ocelot_port, 0, PCS1G_LB_CFG); 395 396 /* Enable MAC module */ 397 ocelot_port_writel(ocelot_port, DEV_MAC_ENA_CFG_RX_ENA | 398 DEV_MAC_ENA_CFG_TX_ENA, DEV_MAC_ENA_CFG); 399 400 /* Take MAC, Port, Phy (intern) and PCS (SGMII/Serdes) clock out of 401 * reset */ 402 ocelot_port_writel(ocelot_port, DEV_CLOCK_CFG_LINK_SPEED(speed), 403 DEV_CLOCK_CFG); 404 405 /* No PFC */ 406 ocelot_write_gix(ocelot, ANA_PFC_PFC_CFG_FC_LINK_SPEED(speed), 407 ANA_PFC_PFC_CFG, port); 408 409 /* Core: Enable port for frame transfer */ 410 ocelot_fields_write(ocelot, port, 411 QSYS_SWITCH_PORT_MODE_PORT_ENA, 1); 412 413 /* Flow control */ 414 ocelot_write_rix(ocelot, SYS_MAC_FC_CFG_PAUSE_VAL_CFG(0xffff) | 415 SYS_MAC_FC_CFG_RX_FC_ENA | SYS_MAC_FC_CFG_TX_FC_ENA | 416 SYS_MAC_FC_CFG_ZERO_PAUSE_ENA | 417 SYS_MAC_FC_CFG_FC_LATENCY_CFG(0x7) | 418 SYS_MAC_FC_CFG_FC_LINK_SPEED(speed), 419 SYS_MAC_FC_CFG, port); 420 ocelot_write_rix(ocelot, 0, ANA_POL_FLOWC, port); 421 } 422 EXPORT_SYMBOL(ocelot_adjust_link); 423 424 void ocelot_port_enable(struct ocelot *ocelot, int port, 425 struct phy_device *phy) 426 { 427 /* Enable receiving frames on the port, and activate auto-learning of 428 * MAC addresses. 429 */ 430 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_LEARNAUTO | 431 ANA_PORT_PORT_CFG_RECV_ENA | 432 ANA_PORT_PORT_CFG_PORTID_VAL(port), 433 ANA_PORT_PORT_CFG, port); 434 } 435 EXPORT_SYMBOL(ocelot_port_enable); 436 437 void ocelot_port_disable(struct ocelot *ocelot, int port) 438 { 439 struct ocelot_port *ocelot_port = ocelot->ports[port]; 440 441 ocelot_port_writel(ocelot_port, 0, DEV_MAC_ENA_CFG); 442 ocelot_fields_write(ocelot, port, QSYS_SWITCH_PORT_MODE_PORT_ENA, 0); 443 } 444 EXPORT_SYMBOL(ocelot_port_disable); 445 446 void ocelot_port_add_txtstamp_skb(struct ocelot *ocelot, int port, 447 struct sk_buff *clone) 448 { 449 struct ocelot_port *ocelot_port = ocelot->ports[port]; 450 451 spin_lock(&ocelot_port->ts_id_lock); 452 453 skb_shinfo(clone)->tx_flags |= SKBTX_IN_PROGRESS; 454 /* Store timestamp ID in cb[0] of sk_buff */ 455 clone->cb[0] = ocelot_port->ts_id; 456 ocelot_port->ts_id = (ocelot_port->ts_id + 1) % 4; 457 skb_queue_tail(&ocelot_port->tx_skbs, clone); 458 459 spin_unlock(&ocelot_port->ts_id_lock); 460 } 461 EXPORT_SYMBOL(ocelot_port_add_txtstamp_skb); 462 463 static void ocelot_get_hwtimestamp(struct ocelot *ocelot, 464 struct timespec64 *ts) 465 { 466 unsigned long flags; 467 u32 val; 468 469 spin_lock_irqsave(&ocelot->ptp_clock_lock, flags); 470 471 /* Read current PTP time to get seconds */ 472 val = ocelot_read_rix(ocelot, PTP_PIN_CFG, TOD_ACC_PIN); 473 474 val &= ~(PTP_PIN_CFG_SYNC | PTP_PIN_CFG_ACTION_MASK | PTP_PIN_CFG_DOM); 475 val |= PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_SAVE); 476 ocelot_write_rix(ocelot, val, PTP_PIN_CFG, TOD_ACC_PIN); 477 ts->tv_sec = ocelot_read_rix(ocelot, PTP_PIN_TOD_SEC_LSB, TOD_ACC_PIN); 478 479 /* Read packet HW timestamp from FIFO */ 480 val = ocelot_read(ocelot, SYS_PTP_TXSTAMP); 481 ts->tv_nsec = SYS_PTP_TXSTAMP_PTP_TXSTAMP(val); 482 483 /* Sec has incremented since the ts was registered */ 484 if ((ts->tv_sec & 0x1) != !!(val & SYS_PTP_TXSTAMP_PTP_TXSTAMP_SEC)) 485 ts->tv_sec--; 486 487 spin_unlock_irqrestore(&ocelot->ptp_clock_lock, flags); 488 } 489 490 void ocelot_get_txtstamp(struct ocelot *ocelot) 491 { 492 int budget = OCELOT_PTP_QUEUE_SZ; 493 494 while (budget--) { 495 struct sk_buff *skb, *skb_tmp, *skb_match = NULL; 496 struct skb_shared_hwtstamps shhwtstamps; 497 struct ocelot_port *port; 498 struct timespec64 ts; 499 unsigned long flags; 500 u32 val, id, txport; 501 502 val = ocelot_read(ocelot, SYS_PTP_STATUS); 503 504 /* Check if a timestamp can be retrieved */ 505 if (!(val & SYS_PTP_STATUS_PTP_MESS_VLD)) 506 break; 507 508 WARN_ON(val & SYS_PTP_STATUS_PTP_OVFL); 509 510 /* Retrieve the ts ID and Tx port */ 511 id = SYS_PTP_STATUS_PTP_MESS_ID_X(val); 512 txport = SYS_PTP_STATUS_PTP_MESS_TXPORT_X(val); 513 514 /* Retrieve its associated skb */ 515 port = ocelot->ports[txport]; 516 517 spin_lock_irqsave(&port->tx_skbs.lock, flags); 518 519 skb_queue_walk_safe(&port->tx_skbs, skb, skb_tmp) { 520 if (skb->cb[0] != id) 521 continue; 522 __skb_unlink(skb, &port->tx_skbs); 523 skb_match = skb; 524 break; 525 } 526 527 spin_unlock_irqrestore(&port->tx_skbs.lock, flags); 528 529 /* Get the h/w timestamp */ 530 ocelot_get_hwtimestamp(ocelot, &ts); 531 532 if (unlikely(!skb_match)) 533 continue; 534 535 /* Set the timestamp into the skb */ 536 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 537 shhwtstamps.hwtstamp = ktime_set(ts.tv_sec, ts.tv_nsec); 538 skb_complete_tx_timestamp(skb_match, &shhwtstamps); 539 540 /* Next ts */ 541 ocelot_write(ocelot, SYS_PTP_NXT_PTP_NXT, SYS_PTP_NXT); 542 } 543 } 544 EXPORT_SYMBOL(ocelot_get_txtstamp); 545 546 int ocelot_fdb_add(struct ocelot *ocelot, int port, 547 const unsigned char *addr, u16 vid) 548 { 549 int pgid = port; 550 551 if (port == ocelot->npi) 552 pgid = PGID_CPU; 553 554 return ocelot_mact_learn(ocelot, pgid, addr, vid, ENTRYTYPE_LOCKED); 555 } 556 EXPORT_SYMBOL(ocelot_fdb_add); 557 558 int ocelot_fdb_del(struct ocelot *ocelot, int port, 559 const unsigned char *addr, u16 vid) 560 { 561 return ocelot_mact_forget(ocelot, addr, vid); 562 } 563 EXPORT_SYMBOL(ocelot_fdb_del); 564 565 int ocelot_port_fdb_do_dump(const unsigned char *addr, u16 vid, 566 bool is_static, void *data) 567 { 568 struct ocelot_dump_ctx *dump = data; 569 u32 portid = NETLINK_CB(dump->cb->skb).portid; 570 u32 seq = dump->cb->nlh->nlmsg_seq; 571 struct nlmsghdr *nlh; 572 struct ndmsg *ndm; 573 574 if (dump->idx < dump->cb->args[2]) 575 goto skip; 576 577 nlh = nlmsg_put(dump->skb, portid, seq, RTM_NEWNEIGH, 578 sizeof(*ndm), NLM_F_MULTI); 579 if (!nlh) 580 return -EMSGSIZE; 581 582 ndm = nlmsg_data(nlh); 583 ndm->ndm_family = AF_BRIDGE; 584 ndm->ndm_pad1 = 0; 585 ndm->ndm_pad2 = 0; 586 ndm->ndm_flags = NTF_SELF; 587 ndm->ndm_type = 0; 588 ndm->ndm_ifindex = dump->dev->ifindex; 589 ndm->ndm_state = is_static ? NUD_NOARP : NUD_REACHABLE; 590 591 if (nla_put(dump->skb, NDA_LLADDR, ETH_ALEN, addr)) 592 goto nla_put_failure; 593 594 if (vid && nla_put_u16(dump->skb, NDA_VLAN, vid)) 595 goto nla_put_failure; 596 597 nlmsg_end(dump->skb, nlh); 598 599 skip: 600 dump->idx++; 601 return 0; 602 603 nla_put_failure: 604 nlmsg_cancel(dump->skb, nlh); 605 return -EMSGSIZE; 606 } 607 EXPORT_SYMBOL(ocelot_port_fdb_do_dump); 608 609 static int ocelot_mact_read(struct ocelot *ocelot, int port, int row, int col, 610 struct ocelot_mact_entry *entry) 611 { 612 u32 val, dst, macl, mach; 613 char mac[ETH_ALEN]; 614 615 /* Set row and column to read from */ 616 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_M_INDEX, row); 617 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_BUCKET, col); 618 619 /* Issue a read command */ 620 ocelot_write(ocelot, 621 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_READ), 622 ANA_TABLES_MACACCESS); 623 624 if (ocelot_mact_wait_for_completion(ocelot)) 625 return -ETIMEDOUT; 626 627 /* Read the entry flags */ 628 val = ocelot_read(ocelot, ANA_TABLES_MACACCESS); 629 if (!(val & ANA_TABLES_MACACCESS_VALID)) 630 return -EINVAL; 631 632 /* If the entry read has another port configured as its destination, 633 * do not report it. 634 */ 635 dst = (val & ANA_TABLES_MACACCESS_DEST_IDX_M) >> 3; 636 if (dst != port) 637 return -EINVAL; 638 639 /* Get the entry's MAC address and VLAN id */ 640 macl = ocelot_read(ocelot, ANA_TABLES_MACLDATA); 641 mach = ocelot_read(ocelot, ANA_TABLES_MACHDATA); 642 643 mac[0] = (mach >> 8) & 0xff; 644 mac[1] = (mach >> 0) & 0xff; 645 mac[2] = (macl >> 24) & 0xff; 646 mac[3] = (macl >> 16) & 0xff; 647 mac[4] = (macl >> 8) & 0xff; 648 mac[5] = (macl >> 0) & 0xff; 649 650 entry->vid = (mach >> 16) & 0xfff; 651 ether_addr_copy(entry->mac, mac); 652 653 return 0; 654 } 655 656 int ocelot_fdb_dump(struct ocelot *ocelot, int port, 657 dsa_fdb_dump_cb_t *cb, void *data) 658 { 659 int i, j; 660 661 /* Loop through all the mac tables entries. */ 662 for (i = 0; i < ocelot->num_mact_rows; i++) { 663 for (j = 0; j < 4; j++) { 664 struct ocelot_mact_entry entry; 665 bool is_static; 666 int ret; 667 668 ret = ocelot_mact_read(ocelot, port, i, j, &entry); 669 /* If the entry is invalid (wrong port, invalid...), 670 * skip it. 671 */ 672 if (ret == -EINVAL) 673 continue; 674 else if (ret) 675 return ret; 676 677 is_static = (entry.type == ENTRYTYPE_LOCKED); 678 679 ret = cb(entry.mac, entry.vid, is_static, data); 680 if (ret) 681 return ret; 682 } 683 } 684 685 return 0; 686 } 687 EXPORT_SYMBOL(ocelot_fdb_dump); 688 689 int ocelot_hwstamp_get(struct ocelot *ocelot, int port, struct ifreq *ifr) 690 { 691 return copy_to_user(ifr->ifr_data, &ocelot->hwtstamp_config, 692 sizeof(ocelot->hwtstamp_config)) ? -EFAULT : 0; 693 } 694 EXPORT_SYMBOL(ocelot_hwstamp_get); 695 696 int ocelot_hwstamp_set(struct ocelot *ocelot, int port, struct ifreq *ifr) 697 { 698 struct ocelot_port *ocelot_port = ocelot->ports[port]; 699 struct hwtstamp_config cfg; 700 701 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg))) 702 return -EFAULT; 703 704 /* reserved for future extensions */ 705 if (cfg.flags) 706 return -EINVAL; 707 708 /* Tx type sanity check */ 709 switch (cfg.tx_type) { 710 case HWTSTAMP_TX_ON: 711 ocelot_port->ptp_cmd = IFH_REW_OP_TWO_STEP_PTP; 712 break; 713 case HWTSTAMP_TX_ONESTEP_SYNC: 714 /* IFH_REW_OP_ONE_STEP_PTP updates the correctional field, we 715 * need to update the origin time. 716 */ 717 ocelot_port->ptp_cmd = IFH_REW_OP_ORIGIN_PTP; 718 break; 719 case HWTSTAMP_TX_OFF: 720 ocelot_port->ptp_cmd = 0; 721 break; 722 default: 723 return -ERANGE; 724 } 725 726 mutex_lock(&ocelot->ptp_lock); 727 728 switch (cfg.rx_filter) { 729 case HWTSTAMP_FILTER_NONE: 730 break; 731 case HWTSTAMP_FILTER_ALL: 732 case HWTSTAMP_FILTER_SOME: 733 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 734 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 735 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 736 case HWTSTAMP_FILTER_NTP_ALL: 737 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 738 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 739 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 740 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 741 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 742 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 743 case HWTSTAMP_FILTER_PTP_V2_EVENT: 744 case HWTSTAMP_FILTER_PTP_V2_SYNC: 745 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 746 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 747 break; 748 default: 749 mutex_unlock(&ocelot->ptp_lock); 750 return -ERANGE; 751 } 752 753 /* Commit back the result & save it */ 754 memcpy(&ocelot->hwtstamp_config, &cfg, sizeof(cfg)); 755 mutex_unlock(&ocelot->ptp_lock); 756 757 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 758 } 759 EXPORT_SYMBOL(ocelot_hwstamp_set); 760 761 void ocelot_get_strings(struct ocelot *ocelot, int port, u32 sset, u8 *data) 762 { 763 int i; 764 765 if (sset != ETH_SS_STATS) 766 return; 767 768 for (i = 0; i < ocelot->num_stats; i++) 769 memcpy(data + i * ETH_GSTRING_LEN, ocelot->stats_layout[i].name, 770 ETH_GSTRING_LEN); 771 } 772 EXPORT_SYMBOL(ocelot_get_strings); 773 774 static void ocelot_update_stats(struct ocelot *ocelot) 775 { 776 int i, j; 777 778 mutex_lock(&ocelot->stats_lock); 779 780 for (i = 0; i < ocelot->num_phys_ports; i++) { 781 /* Configure the port to read the stats from */ 782 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(i), SYS_STAT_CFG); 783 784 for (j = 0; j < ocelot->num_stats; j++) { 785 u32 val; 786 unsigned int idx = i * ocelot->num_stats + j; 787 788 val = ocelot_read_rix(ocelot, SYS_COUNT_RX_OCTETS, 789 ocelot->stats_layout[j].offset); 790 791 if (val < (ocelot->stats[idx] & U32_MAX)) 792 ocelot->stats[idx] += (u64)1 << 32; 793 794 ocelot->stats[idx] = (ocelot->stats[idx] & 795 ~(u64)U32_MAX) + val; 796 } 797 } 798 799 mutex_unlock(&ocelot->stats_lock); 800 } 801 802 static void ocelot_check_stats_work(struct work_struct *work) 803 { 804 struct delayed_work *del_work = to_delayed_work(work); 805 struct ocelot *ocelot = container_of(del_work, struct ocelot, 806 stats_work); 807 808 ocelot_update_stats(ocelot); 809 810 queue_delayed_work(ocelot->stats_queue, &ocelot->stats_work, 811 OCELOT_STATS_CHECK_DELAY); 812 } 813 814 void ocelot_get_ethtool_stats(struct ocelot *ocelot, int port, u64 *data) 815 { 816 int i; 817 818 /* check and update now */ 819 ocelot_update_stats(ocelot); 820 821 /* Copy all counters */ 822 for (i = 0; i < ocelot->num_stats; i++) 823 *data++ = ocelot->stats[port * ocelot->num_stats + i]; 824 } 825 EXPORT_SYMBOL(ocelot_get_ethtool_stats); 826 827 int ocelot_get_sset_count(struct ocelot *ocelot, int port, int sset) 828 { 829 if (sset != ETH_SS_STATS) 830 return -EOPNOTSUPP; 831 832 return ocelot->num_stats; 833 } 834 EXPORT_SYMBOL(ocelot_get_sset_count); 835 836 int ocelot_get_ts_info(struct ocelot *ocelot, int port, 837 struct ethtool_ts_info *info) 838 { 839 info->phc_index = ocelot->ptp_clock ? 840 ptp_clock_index(ocelot->ptp_clock) : -1; 841 if (info->phc_index == -1) { 842 info->so_timestamping |= SOF_TIMESTAMPING_TX_SOFTWARE | 843 SOF_TIMESTAMPING_RX_SOFTWARE | 844 SOF_TIMESTAMPING_SOFTWARE; 845 return 0; 846 } 847 info->so_timestamping |= SOF_TIMESTAMPING_TX_SOFTWARE | 848 SOF_TIMESTAMPING_RX_SOFTWARE | 849 SOF_TIMESTAMPING_SOFTWARE | 850 SOF_TIMESTAMPING_TX_HARDWARE | 851 SOF_TIMESTAMPING_RX_HARDWARE | 852 SOF_TIMESTAMPING_RAW_HARDWARE; 853 info->tx_types = BIT(HWTSTAMP_TX_OFF) | BIT(HWTSTAMP_TX_ON) | 854 BIT(HWTSTAMP_TX_ONESTEP_SYNC); 855 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) | BIT(HWTSTAMP_FILTER_ALL); 856 857 return 0; 858 } 859 EXPORT_SYMBOL(ocelot_get_ts_info); 860 861 void ocelot_bridge_stp_state_set(struct ocelot *ocelot, int port, u8 state) 862 { 863 u32 port_cfg; 864 int p, i; 865 866 if (!(BIT(port) & ocelot->bridge_mask)) 867 return; 868 869 port_cfg = ocelot_read_gix(ocelot, ANA_PORT_PORT_CFG, port); 870 871 switch (state) { 872 case BR_STATE_FORWARDING: 873 ocelot->bridge_fwd_mask |= BIT(port); 874 fallthrough; 875 case BR_STATE_LEARNING: 876 port_cfg |= ANA_PORT_PORT_CFG_LEARN_ENA; 877 break; 878 879 default: 880 port_cfg &= ~ANA_PORT_PORT_CFG_LEARN_ENA; 881 ocelot->bridge_fwd_mask &= ~BIT(port); 882 break; 883 } 884 885 ocelot_write_gix(ocelot, port_cfg, ANA_PORT_PORT_CFG, port); 886 887 /* Apply FWD mask. The loop is needed to add/remove the current port as 888 * a source for the other ports. 889 */ 890 for (p = 0; p < ocelot->num_phys_ports; p++) { 891 if (ocelot->bridge_fwd_mask & BIT(p)) { 892 unsigned long mask = ocelot->bridge_fwd_mask & ~BIT(p); 893 894 for (i = 0; i < ocelot->num_phys_ports; i++) { 895 unsigned long bond_mask = ocelot->lags[i]; 896 897 if (!bond_mask) 898 continue; 899 900 if (bond_mask & BIT(p)) { 901 mask &= ~bond_mask; 902 break; 903 } 904 } 905 906 ocelot_write_rix(ocelot, mask, 907 ANA_PGID_PGID, PGID_SRC + p); 908 } else { 909 ocelot_write_rix(ocelot, 0, 910 ANA_PGID_PGID, PGID_SRC + p); 911 } 912 } 913 } 914 EXPORT_SYMBOL(ocelot_bridge_stp_state_set); 915 916 void ocelot_set_ageing_time(struct ocelot *ocelot, unsigned int msecs) 917 { 918 unsigned int age_period = ANA_AUTOAGE_AGE_PERIOD(msecs / 2000); 919 920 /* Setting AGE_PERIOD to zero effectively disables automatic aging, 921 * which is clearly not what our intention is. So avoid that. 922 */ 923 if (!age_period) 924 age_period = 1; 925 926 ocelot_rmw(ocelot, age_period, ANA_AUTOAGE_AGE_PERIOD_M, ANA_AUTOAGE); 927 } 928 EXPORT_SYMBOL(ocelot_set_ageing_time); 929 930 static struct ocelot_multicast *ocelot_multicast_get(struct ocelot *ocelot, 931 const unsigned char *addr, 932 u16 vid) 933 { 934 struct ocelot_multicast *mc; 935 936 list_for_each_entry(mc, &ocelot->multicast, list) { 937 if (ether_addr_equal(mc->addr, addr) && mc->vid == vid) 938 return mc; 939 } 940 941 return NULL; 942 } 943 944 static enum macaccess_entry_type ocelot_classify_mdb(const unsigned char *addr) 945 { 946 if (addr[0] == 0x01 && addr[1] == 0x00 && addr[2] == 0x5e) 947 return ENTRYTYPE_MACv4; 948 if (addr[0] == 0x33 && addr[1] == 0x33) 949 return ENTRYTYPE_MACv6; 950 return ENTRYTYPE_LOCKED; 951 } 952 953 static struct ocelot_pgid *ocelot_pgid_alloc(struct ocelot *ocelot, int index, 954 unsigned long ports) 955 { 956 struct ocelot_pgid *pgid; 957 958 pgid = kzalloc(sizeof(*pgid), GFP_KERNEL); 959 if (!pgid) 960 return ERR_PTR(-ENOMEM); 961 962 pgid->ports = ports; 963 pgid->index = index; 964 refcount_set(&pgid->refcount, 1); 965 list_add_tail(&pgid->list, &ocelot->pgids); 966 967 return pgid; 968 } 969 970 static void ocelot_pgid_free(struct ocelot *ocelot, struct ocelot_pgid *pgid) 971 { 972 if (!refcount_dec_and_test(&pgid->refcount)) 973 return; 974 975 list_del(&pgid->list); 976 kfree(pgid); 977 } 978 979 static struct ocelot_pgid *ocelot_mdb_get_pgid(struct ocelot *ocelot, 980 const struct ocelot_multicast *mc) 981 { 982 struct ocelot_pgid *pgid; 983 int index; 984 985 /* According to VSC7514 datasheet 3.9.1.5 IPv4 Multicast Entries and 986 * 3.9.1.6 IPv6 Multicast Entries, "Instead of a lookup in the 987 * destination mask table (PGID), the destination set is programmed as 988 * part of the entry MAC address.", and the DEST_IDX is set to 0. 989 */ 990 if (mc->entry_type == ENTRYTYPE_MACv4 || 991 mc->entry_type == ENTRYTYPE_MACv6) 992 return ocelot_pgid_alloc(ocelot, 0, mc->ports); 993 994 list_for_each_entry(pgid, &ocelot->pgids, list) { 995 /* When searching for a nonreserved multicast PGID, ignore the 996 * dummy PGID of zero that we have for MACv4/MACv6 entries 997 */ 998 if (pgid->index && pgid->ports == mc->ports) { 999 refcount_inc(&pgid->refcount); 1000 return pgid; 1001 } 1002 } 1003 1004 /* Search for a free index in the nonreserved multicast PGID area */ 1005 for_each_nonreserved_multicast_dest_pgid(ocelot, index) { 1006 bool used = false; 1007 1008 list_for_each_entry(pgid, &ocelot->pgids, list) { 1009 if (pgid->index == index) { 1010 used = true; 1011 break; 1012 } 1013 } 1014 1015 if (!used) 1016 return ocelot_pgid_alloc(ocelot, index, mc->ports); 1017 } 1018 1019 return ERR_PTR(-ENOSPC); 1020 } 1021 1022 static void ocelot_encode_ports_to_mdb(unsigned char *addr, 1023 struct ocelot_multicast *mc) 1024 { 1025 ether_addr_copy(addr, mc->addr); 1026 1027 if (mc->entry_type == ENTRYTYPE_MACv4) { 1028 addr[0] = 0; 1029 addr[1] = mc->ports >> 8; 1030 addr[2] = mc->ports & 0xff; 1031 } else if (mc->entry_type == ENTRYTYPE_MACv6) { 1032 addr[0] = mc->ports >> 8; 1033 addr[1] = mc->ports & 0xff; 1034 } 1035 } 1036 1037 int ocelot_port_mdb_add(struct ocelot *ocelot, int port, 1038 const struct switchdev_obj_port_mdb *mdb) 1039 { 1040 unsigned char addr[ETH_ALEN]; 1041 struct ocelot_multicast *mc; 1042 struct ocelot_pgid *pgid; 1043 u16 vid = mdb->vid; 1044 1045 if (port == ocelot->npi) 1046 port = ocelot->num_phys_ports; 1047 1048 mc = ocelot_multicast_get(ocelot, mdb->addr, vid); 1049 if (!mc) { 1050 /* New entry */ 1051 mc = devm_kzalloc(ocelot->dev, sizeof(*mc), GFP_KERNEL); 1052 if (!mc) 1053 return -ENOMEM; 1054 1055 mc->entry_type = ocelot_classify_mdb(mdb->addr); 1056 ether_addr_copy(mc->addr, mdb->addr); 1057 mc->vid = vid; 1058 1059 list_add_tail(&mc->list, &ocelot->multicast); 1060 } else { 1061 /* Existing entry. Clean up the current port mask from 1062 * hardware now, because we'll be modifying it. 1063 */ 1064 ocelot_pgid_free(ocelot, mc->pgid); 1065 ocelot_encode_ports_to_mdb(addr, mc); 1066 ocelot_mact_forget(ocelot, addr, vid); 1067 } 1068 1069 mc->ports |= BIT(port); 1070 1071 pgid = ocelot_mdb_get_pgid(ocelot, mc); 1072 if (IS_ERR(pgid)) { 1073 dev_err(ocelot->dev, 1074 "Cannot allocate PGID for mdb %pM vid %d\n", 1075 mc->addr, mc->vid); 1076 devm_kfree(ocelot->dev, mc); 1077 return PTR_ERR(pgid); 1078 } 1079 mc->pgid = pgid; 1080 1081 ocelot_encode_ports_to_mdb(addr, mc); 1082 1083 if (mc->entry_type != ENTRYTYPE_MACv4 && 1084 mc->entry_type != ENTRYTYPE_MACv6) 1085 ocelot_write_rix(ocelot, pgid->ports, ANA_PGID_PGID, 1086 pgid->index); 1087 1088 return ocelot_mact_learn(ocelot, pgid->index, addr, vid, 1089 mc->entry_type); 1090 } 1091 EXPORT_SYMBOL(ocelot_port_mdb_add); 1092 1093 int ocelot_port_mdb_del(struct ocelot *ocelot, int port, 1094 const struct switchdev_obj_port_mdb *mdb) 1095 { 1096 unsigned char addr[ETH_ALEN]; 1097 struct ocelot_multicast *mc; 1098 struct ocelot_pgid *pgid; 1099 u16 vid = mdb->vid; 1100 1101 if (port == ocelot->npi) 1102 port = ocelot->num_phys_ports; 1103 1104 mc = ocelot_multicast_get(ocelot, mdb->addr, vid); 1105 if (!mc) 1106 return -ENOENT; 1107 1108 ocelot_encode_ports_to_mdb(addr, mc); 1109 ocelot_mact_forget(ocelot, addr, vid); 1110 1111 ocelot_pgid_free(ocelot, mc->pgid); 1112 mc->ports &= ~BIT(port); 1113 if (!mc->ports) { 1114 list_del(&mc->list); 1115 devm_kfree(ocelot->dev, mc); 1116 return 0; 1117 } 1118 1119 /* We have a PGID with fewer ports now */ 1120 pgid = ocelot_mdb_get_pgid(ocelot, mc); 1121 if (IS_ERR(pgid)) 1122 return PTR_ERR(pgid); 1123 mc->pgid = pgid; 1124 1125 ocelot_encode_ports_to_mdb(addr, mc); 1126 1127 if (mc->entry_type != ENTRYTYPE_MACv4 && 1128 mc->entry_type != ENTRYTYPE_MACv6) 1129 ocelot_write_rix(ocelot, pgid->ports, ANA_PGID_PGID, 1130 pgid->index); 1131 1132 return ocelot_mact_learn(ocelot, pgid->index, addr, vid, 1133 mc->entry_type); 1134 } 1135 EXPORT_SYMBOL(ocelot_port_mdb_del); 1136 1137 int ocelot_port_bridge_join(struct ocelot *ocelot, int port, 1138 struct net_device *bridge) 1139 { 1140 if (!ocelot->bridge_mask) { 1141 ocelot->hw_bridge_dev = bridge; 1142 } else { 1143 if (ocelot->hw_bridge_dev != bridge) 1144 /* This is adding the port to a second bridge, this is 1145 * unsupported */ 1146 return -ENODEV; 1147 } 1148 1149 ocelot->bridge_mask |= BIT(port); 1150 1151 return 0; 1152 } 1153 EXPORT_SYMBOL(ocelot_port_bridge_join); 1154 1155 int ocelot_port_bridge_leave(struct ocelot *ocelot, int port, 1156 struct net_device *bridge) 1157 { 1158 struct switchdev_trans trans; 1159 int ret; 1160 1161 ocelot->bridge_mask &= ~BIT(port); 1162 1163 if (!ocelot->bridge_mask) 1164 ocelot->hw_bridge_dev = NULL; 1165 1166 trans.ph_prepare = true; 1167 ret = ocelot_port_vlan_filtering(ocelot, port, false, &trans); 1168 if (ret) 1169 return ret; 1170 1171 trans.ph_prepare = false; 1172 ret = ocelot_port_vlan_filtering(ocelot, port, false, &trans); 1173 if (ret) 1174 return ret; 1175 1176 ocelot_port_set_pvid(ocelot, port, 0); 1177 return ocelot_port_set_native_vlan(ocelot, port, 0); 1178 } 1179 EXPORT_SYMBOL(ocelot_port_bridge_leave); 1180 1181 static void ocelot_set_aggr_pgids(struct ocelot *ocelot) 1182 { 1183 int i, port, lag; 1184 1185 /* Reset destination and aggregation PGIDS */ 1186 for_each_unicast_dest_pgid(ocelot, port) 1187 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port); 1188 1189 for_each_aggr_pgid(ocelot, i) 1190 ocelot_write_rix(ocelot, GENMASK(ocelot->num_phys_ports - 1, 0), 1191 ANA_PGID_PGID, i); 1192 1193 /* Now, set PGIDs for each LAG */ 1194 for (lag = 0; lag < ocelot->num_phys_ports; lag++) { 1195 unsigned long bond_mask; 1196 int aggr_count = 0; 1197 u8 aggr_idx[16]; 1198 1199 bond_mask = ocelot->lags[lag]; 1200 if (!bond_mask) 1201 continue; 1202 1203 for_each_set_bit(port, &bond_mask, ocelot->num_phys_ports) { 1204 // Destination mask 1205 ocelot_write_rix(ocelot, bond_mask, 1206 ANA_PGID_PGID, port); 1207 aggr_idx[aggr_count] = port; 1208 aggr_count++; 1209 } 1210 1211 for_each_aggr_pgid(ocelot, i) { 1212 u32 ac; 1213 1214 ac = ocelot_read_rix(ocelot, ANA_PGID_PGID, i); 1215 ac &= ~bond_mask; 1216 ac |= BIT(aggr_idx[i % aggr_count]); 1217 ocelot_write_rix(ocelot, ac, ANA_PGID_PGID, i); 1218 } 1219 } 1220 } 1221 1222 static void ocelot_setup_lag(struct ocelot *ocelot, int lag) 1223 { 1224 unsigned long bond_mask = ocelot->lags[lag]; 1225 unsigned int p; 1226 1227 for_each_set_bit(p, &bond_mask, ocelot->num_phys_ports) { 1228 u32 port_cfg = ocelot_read_gix(ocelot, ANA_PORT_PORT_CFG, p); 1229 1230 port_cfg &= ~ANA_PORT_PORT_CFG_PORTID_VAL_M; 1231 1232 /* Use lag port as logical port for port i */ 1233 ocelot_write_gix(ocelot, port_cfg | 1234 ANA_PORT_PORT_CFG_PORTID_VAL(lag), 1235 ANA_PORT_PORT_CFG, p); 1236 } 1237 } 1238 1239 int ocelot_port_lag_join(struct ocelot *ocelot, int port, 1240 struct net_device *bond) 1241 { 1242 struct net_device *ndev; 1243 u32 bond_mask = 0; 1244 int lag, lp; 1245 1246 rcu_read_lock(); 1247 for_each_netdev_in_bond_rcu(bond, ndev) { 1248 struct ocelot_port_private *priv = netdev_priv(ndev); 1249 1250 bond_mask |= BIT(priv->chip_port); 1251 } 1252 rcu_read_unlock(); 1253 1254 lp = __ffs(bond_mask); 1255 1256 /* If the new port is the lowest one, use it as the logical port from 1257 * now on 1258 */ 1259 if (port == lp) { 1260 lag = port; 1261 ocelot->lags[port] = bond_mask; 1262 bond_mask &= ~BIT(port); 1263 if (bond_mask) { 1264 lp = __ffs(bond_mask); 1265 ocelot->lags[lp] = 0; 1266 } 1267 } else { 1268 lag = lp; 1269 ocelot->lags[lp] |= BIT(port); 1270 } 1271 1272 ocelot_setup_lag(ocelot, lag); 1273 ocelot_set_aggr_pgids(ocelot); 1274 1275 return 0; 1276 } 1277 EXPORT_SYMBOL(ocelot_port_lag_join); 1278 1279 void ocelot_port_lag_leave(struct ocelot *ocelot, int port, 1280 struct net_device *bond) 1281 { 1282 u32 port_cfg; 1283 int i; 1284 1285 /* Remove port from any lag */ 1286 for (i = 0; i < ocelot->num_phys_ports; i++) 1287 ocelot->lags[i] &= ~BIT(port); 1288 1289 /* if it was the logical port of the lag, move the lag config to the 1290 * next port 1291 */ 1292 if (ocelot->lags[port]) { 1293 int n = __ffs(ocelot->lags[port]); 1294 1295 ocelot->lags[n] = ocelot->lags[port]; 1296 ocelot->lags[port] = 0; 1297 1298 ocelot_setup_lag(ocelot, n); 1299 } 1300 1301 port_cfg = ocelot_read_gix(ocelot, ANA_PORT_PORT_CFG, port); 1302 port_cfg &= ~ANA_PORT_PORT_CFG_PORTID_VAL_M; 1303 ocelot_write_gix(ocelot, port_cfg | ANA_PORT_PORT_CFG_PORTID_VAL(port), 1304 ANA_PORT_PORT_CFG, port); 1305 1306 ocelot_set_aggr_pgids(ocelot); 1307 } 1308 EXPORT_SYMBOL(ocelot_port_lag_leave); 1309 1310 /* Configure the maximum SDU (L2 payload) on RX to the value specified in @sdu. 1311 * The length of VLAN tags is accounted for automatically via DEV_MAC_TAGS_CFG. 1312 * In the special case that it's the NPI port that we're configuring, the 1313 * length of the tag and optional prefix needs to be accounted for privately, 1314 * in order to be able to sustain communication at the requested @sdu. 1315 */ 1316 void ocelot_port_set_maxlen(struct ocelot *ocelot, int port, size_t sdu) 1317 { 1318 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1319 int maxlen = sdu + ETH_HLEN + ETH_FCS_LEN; 1320 int pause_start, pause_stop; 1321 int atop, atop_tot; 1322 1323 if (port == ocelot->npi) { 1324 maxlen += OCELOT_TAG_LEN; 1325 1326 if (ocelot->inj_prefix == OCELOT_TAG_PREFIX_SHORT) 1327 maxlen += OCELOT_SHORT_PREFIX_LEN; 1328 else if (ocelot->inj_prefix == OCELOT_TAG_PREFIX_LONG) 1329 maxlen += OCELOT_LONG_PREFIX_LEN; 1330 } 1331 1332 ocelot_port_writel(ocelot_port, maxlen, DEV_MAC_MAXLEN_CFG); 1333 1334 /* Set Pause watermark hysteresis */ 1335 pause_start = 6 * maxlen / OCELOT_BUFFER_CELL_SZ; 1336 pause_stop = 4 * maxlen / OCELOT_BUFFER_CELL_SZ; 1337 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_START, 1338 pause_start); 1339 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_STOP, 1340 pause_stop); 1341 1342 /* Tail dropping watermarks */ 1343 atop_tot = (ocelot->shared_queue_sz - 9 * maxlen) / 1344 OCELOT_BUFFER_CELL_SZ; 1345 atop = (9 * maxlen) / OCELOT_BUFFER_CELL_SZ; 1346 ocelot_write_rix(ocelot, ocelot->ops->wm_enc(atop), SYS_ATOP, port); 1347 ocelot_write(ocelot, ocelot->ops->wm_enc(atop_tot), SYS_ATOP_TOT_CFG); 1348 } 1349 EXPORT_SYMBOL(ocelot_port_set_maxlen); 1350 1351 int ocelot_get_max_mtu(struct ocelot *ocelot, int port) 1352 { 1353 int max_mtu = 65535 - ETH_HLEN - ETH_FCS_LEN; 1354 1355 if (port == ocelot->npi) { 1356 max_mtu -= OCELOT_TAG_LEN; 1357 1358 if (ocelot->inj_prefix == OCELOT_TAG_PREFIX_SHORT) 1359 max_mtu -= OCELOT_SHORT_PREFIX_LEN; 1360 else if (ocelot->inj_prefix == OCELOT_TAG_PREFIX_LONG) 1361 max_mtu -= OCELOT_LONG_PREFIX_LEN; 1362 } 1363 1364 return max_mtu; 1365 } 1366 EXPORT_SYMBOL(ocelot_get_max_mtu); 1367 1368 void ocelot_init_port(struct ocelot *ocelot, int port) 1369 { 1370 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1371 1372 skb_queue_head_init(&ocelot_port->tx_skbs); 1373 spin_lock_init(&ocelot_port->ts_id_lock); 1374 1375 /* Basic L2 initialization */ 1376 1377 /* Set MAC IFG Gaps 1378 * FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 0 1379 * !FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 5 1380 */ 1381 ocelot_port_writel(ocelot_port, DEV_MAC_IFG_CFG_TX_IFG(5), 1382 DEV_MAC_IFG_CFG); 1383 1384 /* Load seed (0) and set MAC HDX late collision */ 1385 ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67) | 1386 DEV_MAC_HDX_CFG_SEED_LOAD, 1387 DEV_MAC_HDX_CFG); 1388 mdelay(1); 1389 ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67), 1390 DEV_MAC_HDX_CFG); 1391 1392 /* Set Max Length and maximum tags allowed */ 1393 ocelot_port_set_maxlen(ocelot, port, ETH_DATA_LEN); 1394 ocelot_port_writel(ocelot_port, DEV_MAC_TAGS_CFG_TAG_ID(ETH_P_8021AD) | 1395 DEV_MAC_TAGS_CFG_VLAN_AWR_ENA | 1396 DEV_MAC_TAGS_CFG_VLAN_DBL_AWR_ENA | 1397 DEV_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA, 1398 DEV_MAC_TAGS_CFG); 1399 1400 /* Set SMAC of Pause frame (00:00:00:00:00:00) */ 1401 ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_HIGH_CFG); 1402 ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_LOW_CFG); 1403 1404 /* Enable transmission of pause frames */ 1405 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, 1); 1406 1407 /* Drop frames with multicast source address */ 1408 ocelot_rmw_gix(ocelot, ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA, 1409 ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA, 1410 ANA_PORT_DROP_CFG, port); 1411 1412 /* Set default VLAN and tag type to 8021Q. */ 1413 ocelot_rmw_gix(ocelot, REW_PORT_VLAN_CFG_PORT_TPID(ETH_P_8021Q), 1414 REW_PORT_VLAN_CFG_PORT_TPID_M, 1415 REW_PORT_VLAN_CFG, port); 1416 1417 /* Enable vcap lookups */ 1418 ocelot_vcap_enable(ocelot, port); 1419 } 1420 EXPORT_SYMBOL(ocelot_init_port); 1421 1422 /* Configure and enable the CPU port module, which is a set of queues 1423 * accessible through register MMIO, frame DMA or Ethernet (in case 1424 * NPI mode is used). 1425 */ 1426 static void ocelot_cpu_port_init(struct ocelot *ocelot) 1427 { 1428 int cpu = ocelot->num_phys_ports; 1429 1430 /* The unicast destination PGID for the CPU port module is unused */ 1431 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, cpu); 1432 /* Instead set up a multicast destination PGID for traffic copied to 1433 * the CPU. Whitelisted MAC addresses like the port netdevice MAC 1434 * addresses will be copied to the CPU via this PGID. 1435 */ 1436 ocelot_write_rix(ocelot, BIT(cpu), ANA_PGID_PGID, PGID_CPU); 1437 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_RECV_ENA | 1438 ANA_PORT_PORT_CFG_PORTID_VAL(cpu), 1439 ANA_PORT_PORT_CFG, cpu); 1440 1441 /* Enable CPU port module */ 1442 ocelot_fields_write(ocelot, cpu, QSYS_SWITCH_PORT_MODE_PORT_ENA, 1); 1443 /* CPU port Injection/Extraction configuration */ 1444 ocelot_fields_write(ocelot, cpu, SYS_PORT_MODE_INCL_XTR_HDR, 1445 ocelot->xtr_prefix); 1446 ocelot_fields_write(ocelot, cpu, SYS_PORT_MODE_INCL_INJ_HDR, 1447 ocelot->inj_prefix); 1448 1449 /* Configure the CPU port to be VLAN aware */ 1450 ocelot_write_gix(ocelot, ANA_PORT_VLAN_CFG_VLAN_VID(0) | 1451 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 1452 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1), 1453 ANA_PORT_VLAN_CFG, cpu); 1454 } 1455 1456 int ocelot_init(struct ocelot *ocelot) 1457 { 1458 char queue_name[32]; 1459 int i, ret; 1460 u32 port; 1461 1462 if (ocelot->ops->reset) { 1463 ret = ocelot->ops->reset(ocelot); 1464 if (ret) { 1465 dev_err(ocelot->dev, "Switch reset failed\n"); 1466 return ret; 1467 } 1468 } 1469 1470 ocelot->lags = devm_kcalloc(ocelot->dev, ocelot->num_phys_ports, 1471 sizeof(u32), GFP_KERNEL); 1472 if (!ocelot->lags) 1473 return -ENOMEM; 1474 1475 ocelot->stats = devm_kcalloc(ocelot->dev, 1476 ocelot->num_phys_ports * ocelot->num_stats, 1477 sizeof(u64), GFP_KERNEL); 1478 if (!ocelot->stats) 1479 return -ENOMEM; 1480 1481 mutex_init(&ocelot->stats_lock); 1482 mutex_init(&ocelot->ptp_lock); 1483 spin_lock_init(&ocelot->ptp_clock_lock); 1484 snprintf(queue_name, sizeof(queue_name), "%s-stats", 1485 dev_name(ocelot->dev)); 1486 ocelot->stats_queue = create_singlethread_workqueue(queue_name); 1487 if (!ocelot->stats_queue) 1488 return -ENOMEM; 1489 1490 INIT_LIST_HEAD(&ocelot->multicast); 1491 INIT_LIST_HEAD(&ocelot->pgids); 1492 ocelot_mact_init(ocelot); 1493 ocelot_vlan_init(ocelot); 1494 ocelot_vcap_init(ocelot); 1495 ocelot_cpu_port_init(ocelot); 1496 1497 for (port = 0; port < ocelot->num_phys_ports; port++) { 1498 /* Clear all counters (5 groups) */ 1499 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(port) | 1500 SYS_STAT_CFG_STAT_CLEAR_SHOT(0x7f), 1501 SYS_STAT_CFG); 1502 } 1503 1504 /* Only use S-Tag */ 1505 ocelot_write(ocelot, ETH_P_8021AD, SYS_VLAN_ETYPE_CFG); 1506 1507 /* Aggregation mode */ 1508 ocelot_write(ocelot, ANA_AGGR_CFG_AC_SMAC_ENA | 1509 ANA_AGGR_CFG_AC_DMAC_ENA | 1510 ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA | 1511 ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA, ANA_AGGR_CFG); 1512 1513 /* Set MAC age time to default value. The entry is aged after 1514 * 2*AGE_PERIOD 1515 */ 1516 ocelot_write(ocelot, 1517 ANA_AUTOAGE_AGE_PERIOD(BR_DEFAULT_AGEING_TIME / 2 / HZ), 1518 ANA_AUTOAGE); 1519 1520 /* Disable learning for frames discarded by VLAN ingress filtering */ 1521 regmap_field_write(ocelot->regfields[ANA_ADVLEARN_VLAN_CHK], 1); 1522 1523 /* Setup frame ageing - fixed value "2 sec" - in 6.5 us units */ 1524 ocelot_write(ocelot, SYS_FRM_AGING_AGE_TX_ENA | 1525 SYS_FRM_AGING_MAX_AGE(307692), SYS_FRM_AGING); 1526 1527 /* Setup flooding PGIDs */ 1528 ocelot_write_rix(ocelot, ANA_FLOODING_FLD_MULTICAST(PGID_MC) | 1529 ANA_FLOODING_FLD_BROADCAST(PGID_MC) | 1530 ANA_FLOODING_FLD_UNICAST(PGID_UC), 1531 ANA_FLOODING, 0); 1532 ocelot_write(ocelot, ANA_FLOODING_IPMC_FLD_MC6_DATA(PGID_MCIPV6) | 1533 ANA_FLOODING_IPMC_FLD_MC6_CTRL(PGID_MC) | 1534 ANA_FLOODING_IPMC_FLD_MC4_DATA(PGID_MCIPV4) | 1535 ANA_FLOODING_IPMC_FLD_MC4_CTRL(PGID_MC), 1536 ANA_FLOODING_IPMC); 1537 1538 for (port = 0; port < ocelot->num_phys_ports; port++) { 1539 /* Transmit the frame to the local port. */ 1540 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port); 1541 /* Do not forward BPDU frames to the front ports. */ 1542 ocelot_write_gix(ocelot, 1543 ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA(0xffff), 1544 ANA_PORT_CPU_FWD_BPDU_CFG, 1545 port); 1546 /* Ensure bridging is disabled */ 1547 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_SRC + port); 1548 } 1549 1550 /* Allow broadcast MAC frames. */ 1551 for_each_nonreserved_multicast_dest_pgid(ocelot, i) { 1552 u32 val = ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports - 1, 0)); 1553 1554 ocelot_write_rix(ocelot, val, ANA_PGID_PGID, i); 1555 } 1556 ocelot_write_rix(ocelot, 1557 ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports, 0)), 1558 ANA_PGID_PGID, PGID_MC); 1559 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV4); 1560 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV6); 1561 1562 /* Allow manual injection via DEVCPU_QS registers, and byte swap these 1563 * registers endianness. 1564 */ 1565 ocelot_write_rix(ocelot, QS_INJ_GRP_CFG_BYTE_SWAP | 1566 QS_INJ_GRP_CFG_MODE(1), QS_INJ_GRP_CFG, 0); 1567 ocelot_write_rix(ocelot, QS_XTR_GRP_CFG_BYTE_SWAP | 1568 QS_XTR_GRP_CFG_MODE(1), QS_XTR_GRP_CFG, 0); 1569 ocelot_write(ocelot, ANA_CPUQ_CFG_CPUQ_MIRROR(2) | 1570 ANA_CPUQ_CFG_CPUQ_LRN(2) | 1571 ANA_CPUQ_CFG_CPUQ_MAC_COPY(2) | 1572 ANA_CPUQ_CFG_CPUQ_SRC_COPY(2) | 1573 ANA_CPUQ_CFG_CPUQ_LOCKED_PORTMOVE(2) | 1574 ANA_CPUQ_CFG_CPUQ_ALLBRIDGE(6) | 1575 ANA_CPUQ_CFG_CPUQ_IPMC_CTRL(6) | 1576 ANA_CPUQ_CFG_CPUQ_IGMP(6) | 1577 ANA_CPUQ_CFG_CPUQ_MLD(6), ANA_CPUQ_CFG); 1578 for (i = 0; i < 16; i++) 1579 ocelot_write_rix(ocelot, ANA_CPUQ_8021_CFG_CPUQ_GARP_VAL(6) | 1580 ANA_CPUQ_8021_CFG_CPUQ_BPDU_VAL(6), 1581 ANA_CPUQ_8021_CFG, i); 1582 1583 INIT_DELAYED_WORK(&ocelot->stats_work, ocelot_check_stats_work); 1584 queue_delayed_work(ocelot->stats_queue, &ocelot->stats_work, 1585 OCELOT_STATS_CHECK_DELAY); 1586 1587 return 0; 1588 } 1589 EXPORT_SYMBOL(ocelot_init); 1590 1591 void ocelot_deinit(struct ocelot *ocelot) 1592 { 1593 cancel_delayed_work(&ocelot->stats_work); 1594 destroy_workqueue(ocelot->stats_queue); 1595 mutex_destroy(&ocelot->stats_lock); 1596 } 1597 EXPORT_SYMBOL(ocelot_deinit); 1598 1599 void ocelot_deinit_port(struct ocelot *ocelot, int port) 1600 { 1601 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1602 1603 skb_queue_purge(&ocelot_port->tx_skbs); 1604 } 1605 EXPORT_SYMBOL(ocelot_deinit_port); 1606 1607 MODULE_LICENSE("Dual MIT/GPL"); 1608