1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* 3 * Microsemi Ocelot Switch driver 4 * 5 * Copyright (c) 2017 Microsemi Corporation 6 */ 7 #include <linux/if_bridge.h> 8 #include <soc/mscc/ocelot_vcap.h> 9 #include "ocelot.h" 10 #include "ocelot_vcap.h" 11 12 #define TABLE_UPDATE_SLEEP_US 10 13 #define TABLE_UPDATE_TIMEOUT_US 100000 14 15 struct ocelot_mact_entry { 16 u8 mac[ETH_ALEN]; 17 u16 vid; 18 enum macaccess_entry_type type; 19 }; 20 21 static inline u32 ocelot_mact_read_macaccess(struct ocelot *ocelot) 22 { 23 return ocelot_read(ocelot, ANA_TABLES_MACACCESS); 24 } 25 26 static inline int ocelot_mact_wait_for_completion(struct ocelot *ocelot) 27 { 28 u32 val; 29 30 return readx_poll_timeout(ocelot_mact_read_macaccess, 31 ocelot, val, 32 (val & ANA_TABLES_MACACCESS_MAC_TABLE_CMD_M) == 33 MACACCESS_CMD_IDLE, 34 TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US); 35 } 36 37 static void ocelot_mact_select(struct ocelot *ocelot, 38 const unsigned char mac[ETH_ALEN], 39 unsigned int vid) 40 { 41 u32 macl = 0, mach = 0; 42 43 /* Set the MAC address to handle and the vlan associated in a format 44 * understood by the hardware. 45 */ 46 mach |= vid << 16; 47 mach |= mac[0] << 8; 48 mach |= mac[1] << 0; 49 macl |= mac[2] << 24; 50 macl |= mac[3] << 16; 51 macl |= mac[4] << 8; 52 macl |= mac[5] << 0; 53 54 ocelot_write(ocelot, macl, ANA_TABLES_MACLDATA); 55 ocelot_write(ocelot, mach, ANA_TABLES_MACHDATA); 56 57 } 58 59 int ocelot_mact_learn(struct ocelot *ocelot, int port, 60 const unsigned char mac[ETH_ALEN], 61 unsigned int vid, enum macaccess_entry_type type) 62 { 63 ocelot_mact_select(ocelot, mac, vid); 64 65 /* Issue a write command */ 66 ocelot_write(ocelot, ANA_TABLES_MACACCESS_VALID | 67 ANA_TABLES_MACACCESS_DEST_IDX(port) | 68 ANA_TABLES_MACACCESS_ENTRYTYPE(type) | 69 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_LEARN), 70 ANA_TABLES_MACACCESS); 71 72 return ocelot_mact_wait_for_completion(ocelot); 73 } 74 EXPORT_SYMBOL(ocelot_mact_learn); 75 76 int ocelot_mact_forget(struct ocelot *ocelot, 77 const unsigned char mac[ETH_ALEN], unsigned int vid) 78 { 79 ocelot_mact_select(ocelot, mac, vid); 80 81 /* Issue a forget command */ 82 ocelot_write(ocelot, 83 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_FORGET), 84 ANA_TABLES_MACACCESS); 85 86 return ocelot_mact_wait_for_completion(ocelot); 87 } 88 EXPORT_SYMBOL(ocelot_mact_forget); 89 90 static void ocelot_mact_init(struct ocelot *ocelot) 91 { 92 /* Configure the learning mode entries attributes: 93 * - Do not copy the frame to the CPU extraction queues. 94 * - Use the vlan and mac_cpoy for dmac lookup. 95 */ 96 ocelot_rmw(ocelot, 0, 97 ANA_AGENCTRL_LEARN_CPU_COPY | ANA_AGENCTRL_IGNORE_DMAC_FLAGS 98 | ANA_AGENCTRL_LEARN_FWD_KILL 99 | ANA_AGENCTRL_LEARN_IGNORE_VLAN, 100 ANA_AGENCTRL); 101 102 /* Clear the MAC table */ 103 ocelot_write(ocelot, MACACCESS_CMD_INIT, ANA_TABLES_MACACCESS); 104 } 105 106 static void ocelot_vcap_enable(struct ocelot *ocelot, int port) 107 { 108 ocelot_write_gix(ocelot, ANA_PORT_VCAP_S2_CFG_S2_ENA | 109 ANA_PORT_VCAP_S2_CFG_S2_IP6_CFG(0xa), 110 ANA_PORT_VCAP_S2_CFG, port); 111 112 ocelot_write_gix(ocelot, ANA_PORT_VCAP_CFG_S1_ENA, 113 ANA_PORT_VCAP_CFG, port); 114 115 ocelot_rmw_gix(ocelot, REW_PORT_CFG_ES0_EN, 116 REW_PORT_CFG_ES0_EN, 117 REW_PORT_CFG, port); 118 } 119 120 static inline u32 ocelot_vlant_read_vlanaccess(struct ocelot *ocelot) 121 { 122 return ocelot_read(ocelot, ANA_TABLES_VLANACCESS); 123 } 124 125 static inline int ocelot_vlant_wait_for_completion(struct ocelot *ocelot) 126 { 127 u32 val; 128 129 return readx_poll_timeout(ocelot_vlant_read_vlanaccess, 130 ocelot, 131 val, 132 (val & ANA_TABLES_VLANACCESS_VLAN_TBL_CMD_M) == 133 ANA_TABLES_VLANACCESS_CMD_IDLE, 134 TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US); 135 } 136 137 static int ocelot_vlant_set_mask(struct ocelot *ocelot, u16 vid, u32 mask) 138 { 139 /* Select the VID to configure */ 140 ocelot_write(ocelot, ANA_TABLES_VLANTIDX_V_INDEX(vid), 141 ANA_TABLES_VLANTIDX); 142 /* Set the vlan port members mask and issue a write command */ 143 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_VLAN_PORT_MASK(mask) | 144 ANA_TABLES_VLANACCESS_CMD_WRITE, 145 ANA_TABLES_VLANACCESS); 146 147 return ocelot_vlant_wait_for_completion(ocelot); 148 } 149 150 static int ocelot_port_set_native_vlan(struct ocelot *ocelot, int port, 151 u16 vid) 152 { 153 struct ocelot_port *ocelot_port = ocelot->ports[port]; 154 u32 val = 0; 155 156 if (ocelot_port->vid != vid) { 157 /* Always permit deleting the native VLAN (vid = 0) */ 158 if (ocelot_port->vid && vid) { 159 dev_err(ocelot->dev, 160 "Port already has a native VLAN: %d\n", 161 ocelot_port->vid); 162 return -EBUSY; 163 } 164 ocelot_port->vid = vid; 165 } 166 167 ocelot_rmw_gix(ocelot, REW_PORT_VLAN_CFG_PORT_VID(vid), 168 REW_PORT_VLAN_CFG_PORT_VID_M, 169 REW_PORT_VLAN_CFG, port); 170 171 if (ocelot_port->vlan_aware && !ocelot_port->vid) 172 /* If port is vlan-aware and tagged, drop untagged and priority 173 * tagged frames. 174 */ 175 val = ANA_PORT_DROP_CFG_DROP_UNTAGGED_ENA | 176 ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA | 177 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA; 178 ocelot_rmw_gix(ocelot, val, 179 ANA_PORT_DROP_CFG_DROP_UNTAGGED_ENA | 180 ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA | 181 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA, 182 ANA_PORT_DROP_CFG, port); 183 184 if (ocelot_port->vlan_aware) { 185 if (ocelot_port->vid) 186 /* Tag all frames except when VID == DEFAULT_VLAN */ 187 val = REW_TAG_CFG_TAG_CFG(1); 188 else 189 /* Tag all frames */ 190 val = REW_TAG_CFG_TAG_CFG(3); 191 } else { 192 /* Port tagging disabled. */ 193 val = REW_TAG_CFG_TAG_CFG(0); 194 } 195 ocelot_rmw_gix(ocelot, val, 196 REW_TAG_CFG_TAG_CFG_M, 197 REW_TAG_CFG, port); 198 199 return 0; 200 } 201 202 int ocelot_port_vlan_filtering(struct ocelot *ocelot, int port, 203 bool vlan_aware, struct switchdev_trans *trans) 204 { 205 struct ocelot_port *ocelot_port = ocelot->ports[port]; 206 u32 val; 207 208 if (switchdev_trans_ph_prepare(trans)) { 209 struct ocelot_vcap_block *block = &ocelot->block[VCAP_IS1]; 210 struct ocelot_vcap_filter *filter; 211 212 list_for_each_entry(filter, &block->rules, list) { 213 if (filter->ingress_port_mask & BIT(port) && 214 filter->action.vid_replace_ena) { 215 dev_err(ocelot->dev, 216 "Cannot change VLAN state with vlan modify rules active\n"); 217 return -EBUSY; 218 } 219 } 220 221 return 0; 222 } 223 224 ocelot_port->vlan_aware = vlan_aware; 225 226 if (vlan_aware) 227 val = ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 228 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1); 229 else 230 val = 0; 231 ocelot_rmw_gix(ocelot, val, 232 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 233 ANA_PORT_VLAN_CFG_VLAN_POP_CNT_M, 234 ANA_PORT_VLAN_CFG, port); 235 236 ocelot_port_set_native_vlan(ocelot, port, ocelot_port->vid); 237 238 return 0; 239 } 240 EXPORT_SYMBOL(ocelot_port_vlan_filtering); 241 242 /* Default vlan to clasify for untagged frames (may be zero) */ 243 static void ocelot_port_set_pvid(struct ocelot *ocelot, int port, u16 pvid) 244 { 245 struct ocelot_port *ocelot_port = ocelot->ports[port]; 246 247 ocelot_rmw_gix(ocelot, 248 ANA_PORT_VLAN_CFG_VLAN_VID(pvid), 249 ANA_PORT_VLAN_CFG_VLAN_VID_M, 250 ANA_PORT_VLAN_CFG, port); 251 252 ocelot_port->pvid = pvid; 253 } 254 255 int ocelot_vlan_add(struct ocelot *ocelot, int port, u16 vid, bool pvid, 256 bool untagged) 257 { 258 int ret; 259 260 /* Make the port a member of the VLAN */ 261 ocelot->vlan_mask[vid] |= BIT(port); 262 ret = ocelot_vlant_set_mask(ocelot, vid, ocelot->vlan_mask[vid]); 263 if (ret) 264 return ret; 265 266 /* Default ingress vlan classification */ 267 if (pvid) 268 ocelot_port_set_pvid(ocelot, port, vid); 269 270 /* Untagged egress vlan clasification */ 271 if (untagged) { 272 ret = ocelot_port_set_native_vlan(ocelot, port, vid); 273 if (ret) 274 return ret; 275 } 276 277 return 0; 278 } 279 EXPORT_SYMBOL(ocelot_vlan_add); 280 281 int ocelot_vlan_del(struct ocelot *ocelot, int port, u16 vid) 282 { 283 struct ocelot_port *ocelot_port = ocelot->ports[port]; 284 int ret; 285 286 /* Stop the port from being a member of the vlan */ 287 ocelot->vlan_mask[vid] &= ~BIT(port); 288 ret = ocelot_vlant_set_mask(ocelot, vid, ocelot->vlan_mask[vid]); 289 if (ret) 290 return ret; 291 292 /* Ingress */ 293 if (ocelot_port->pvid == vid) 294 ocelot_port_set_pvid(ocelot, port, 0); 295 296 /* Egress */ 297 if (ocelot_port->vid == vid) 298 ocelot_port_set_native_vlan(ocelot, port, 0); 299 300 return 0; 301 } 302 EXPORT_SYMBOL(ocelot_vlan_del); 303 304 static void ocelot_vlan_init(struct ocelot *ocelot) 305 { 306 u16 port, vid; 307 308 /* Clear VLAN table, by default all ports are members of all VLANs */ 309 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_CMD_INIT, 310 ANA_TABLES_VLANACCESS); 311 ocelot_vlant_wait_for_completion(ocelot); 312 313 /* Configure the port VLAN memberships */ 314 for (vid = 1; vid < VLAN_N_VID; vid++) { 315 ocelot->vlan_mask[vid] = 0; 316 ocelot_vlant_set_mask(ocelot, vid, ocelot->vlan_mask[vid]); 317 } 318 319 /* Because VLAN filtering is enabled, we need VID 0 to get untagged 320 * traffic. It is added automatically if 8021q module is loaded, but 321 * we can't rely on it since module may be not loaded. 322 */ 323 ocelot->vlan_mask[0] = GENMASK(ocelot->num_phys_ports - 1, 0); 324 ocelot_vlant_set_mask(ocelot, 0, ocelot->vlan_mask[0]); 325 326 /* Set vlan ingress filter mask to all ports but the CPU port by 327 * default. 328 */ 329 ocelot_write(ocelot, GENMASK(ocelot->num_phys_ports - 1, 0), 330 ANA_VLANMASK); 331 332 for (port = 0; port < ocelot->num_phys_ports; port++) { 333 ocelot_write_gix(ocelot, 0, REW_PORT_VLAN_CFG, port); 334 ocelot_write_gix(ocelot, 0, REW_TAG_CFG, port); 335 } 336 } 337 338 void ocelot_adjust_link(struct ocelot *ocelot, int port, 339 struct phy_device *phydev) 340 { 341 struct ocelot_port *ocelot_port = ocelot->ports[port]; 342 int speed, mode = 0; 343 344 switch (phydev->speed) { 345 case SPEED_10: 346 speed = OCELOT_SPEED_10; 347 break; 348 case SPEED_100: 349 speed = OCELOT_SPEED_100; 350 break; 351 case SPEED_1000: 352 speed = OCELOT_SPEED_1000; 353 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA; 354 break; 355 case SPEED_2500: 356 speed = OCELOT_SPEED_2500; 357 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA; 358 break; 359 default: 360 dev_err(ocelot->dev, "Unsupported PHY speed on port %d: %d\n", 361 port, phydev->speed); 362 return; 363 } 364 365 phy_print_status(phydev); 366 367 if (!phydev->link) 368 return; 369 370 /* Only full duplex supported for now */ 371 ocelot_port_writel(ocelot_port, DEV_MAC_MODE_CFG_FDX_ENA | 372 mode, DEV_MAC_MODE_CFG); 373 374 /* Disable HDX fast control */ 375 ocelot_port_writel(ocelot_port, DEV_PORT_MISC_HDX_FAST_DIS, 376 DEV_PORT_MISC); 377 378 /* SGMII only for now */ 379 ocelot_port_writel(ocelot_port, PCS1G_MODE_CFG_SGMII_MODE_ENA, 380 PCS1G_MODE_CFG); 381 ocelot_port_writel(ocelot_port, PCS1G_SD_CFG_SD_SEL, PCS1G_SD_CFG); 382 383 /* Enable PCS */ 384 ocelot_port_writel(ocelot_port, PCS1G_CFG_PCS_ENA, PCS1G_CFG); 385 386 /* No aneg on SGMII */ 387 ocelot_port_writel(ocelot_port, 0, PCS1G_ANEG_CFG); 388 389 /* No loopback */ 390 ocelot_port_writel(ocelot_port, 0, PCS1G_LB_CFG); 391 392 /* Enable MAC module */ 393 ocelot_port_writel(ocelot_port, DEV_MAC_ENA_CFG_RX_ENA | 394 DEV_MAC_ENA_CFG_TX_ENA, DEV_MAC_ENA_CFG); 395 396 /* Take MAC, Port, Phy (intern) and PCS (SGMII/Serdes) clock out of 397 * reset */ 398 ocelot_port_writel(ocelot_port, DEV_CLOCK_CFG_LINK_SPEED(speed), 399 DEV_CLOCK_CFG); 400 401 /* No PFC */ 402 ocelot_write_gix(ocelot, ANA_PFC_PFC_CFG_FC_LINK_SPEED(speed), 403 ANA_PFC_PFC_CFG, port); 404 405 /* Core: Enable port for frame transfer */ 406 ocelot_fields_write(ocelot, port, 407 QSYS_SWITCH_PORT_MODE_PORT_ENA, 1); 408 409 /* Flow control */ 410 ocelot_write_rix(ocelot, SYS_MAC_FC_CFG_PAUSE_VAL_CFG(0xffff) | 411 SYS_MAC_FC_CFG_RX_FC_ENA | SYS_MAC_FC_CFG_TX_FC_ENA | 412 SYS_MAC_FC_CFG_ZERO_PAUSE_ENA | 413 SYS_MAC_FC_CFG_FC_LATENCY_CFG(0x7) | 414 SYS_MAC_FC_CFG_FC_LINK_SPEED(speed), 415 SYS_MAC_FC_CFG, port); 416 ocelot_write_rix(ocelot, 0, ANA_POL_FLOWC, port); 417 } 418 EXPORT_SYMBOL(ocelot_adjust_link); 419 420 void ocelot_port_enable(struct ocelot *ocelot, int port, 421 struct phy_device *phy) 422 { 423 /* Enable receiving frames on the port, and activate auto-learning of 424 * MAC addresses. 425 */ 426 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_LEARNAUTO | 427 ANA_PORT_PORT_CFG_RECV_ENA | 428 ANA_PORT_PORT_CFG_PORTID_VAL(port), 429 ANA_PORT_PORT_CFG, port); 430 } 431 EXPORT_SYMBOL(ocelot_port_enable); 432 433 void ocelot_port_disable(struct ocelot *ocelot, int port) 434 { 435 struct ocelot_port *ocelot_port = ocelot->ports[port]; 436 437 ocelot_port_writel(ocelot_port, 0, DEV_MAC_ENA_CFG); 438 ocelot_fields_write(ocelot, port, QSYS_SWITCH_PORT_MODE_PORT_ENA, 0); 439 } 440 EXPORT_SYMBOL(ocelot_port_disable); 441 442 void ocelot_port_add_txtstamp_skb(struct ocelot *ocelot, int port, 443 struct sk_buff *clone) 444 { 445 struct ocelot_port *ocelot_port = ocelot->ports[port]; 446 447 spin_lock(&ocelot_port->ts_id_lock); 448 449 skb_shinfo(clone)->tx_flags |= SKBTX_IN_PROGRESS; 450 /* Store timestamp ID in cb[0] of sk_buff */ 451 clone->cb[0] = ocelot_port->ts_id; 452 ocelot_port->ts_id = (ocelot_port->ts_id + 1) % 4; 453 skb_queue_tail(&ocelot_port->tx_skbs, clone); 454 455 spin_unlock(&ocelot_port->ts_id_lock); 456 } 457 EXPORT_SYMBOL(ocelot_port_add_txtstamp_skb); 458 459 static void ocelot_get_hwtimestamp(struct ocelot *ocelot, 460 struct timespec64 *ts) 461 { 462 unsigned long flags; 463 u32 val; 464 465 spin_lock_irqsave(&ocelot->ptp_clock_lock, flags); 466 467 /* Read current PTP time to get seconds */ 468 val = ocelot_read_rix(ocelot, PTP_PIN_CFG, TOD_ACC_PIN); 469 470 val &= ~(PTP_PIN_CFG_SYNC | PTP_PIN_CFG_ACTION_MASK | PTP_PIN_CFG_DOM); 471 val |= PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_SAVE); 472 ocelot_write_rix(ocelot, val, PTP_PIN_CFG, TOD_ACC_PIN); 473 ts->tv_sec = ocelot_read_rix(ocelot, PTP_PIN_TOD_SEC_LSB, TOD_ACC_PIN); 474 475 /* Read packet HW timestamp from FIFO */ 476 val = ocelot_read(ocelot, SYS_PTP_TXSTAMP); 477 ts->tv_nsec = SYS_PTP_TXSTAMP_PTP_TXSTAMP(val); 478 479 /* Sec has incremented since the ts was registered */ 480 if ((ts->tv_sec & 0x1) != !!(val & SYS_PTP_TXSTAMP_PTP_TXSTAMP_SEC)) 481 ts->tv_sec--; 482 483 spin_unlock_irqrestore(&ocelot->ptp_clock_lock, flags); 484 } 485 486 void ocelot_get_txtstamp(struct ocelot *ocelot) 487 { 488 int budget = OCELOT_PTP_QUEUE_SZ; 489 490 while (budget--) { 491 struct sk_buff *skb, *skb_tmp, *skb_match = NULL; 492 struct skb_shared_hwtstamps shhwtstamps; 493 struct ocelot_port *port; 494 struct timespec64 ts; 495 unsigned long flags; 496 u32 val, id, txport; 497 498 val = ocelot_read(ocelot, SYS_PTP_STATUS); 499 500 /* Check if a timestamp can be retrieved */ 501 if (!(val & SYS_PTP_STATUS_PTP_MESS_VLD)) 502 break; 503 504 WARN_ON(val & SYS_PTP_STATUS_PTP_OVFL); 505 506 /* Retrieve the ts ID and Tx port */ 507 id = SYS_PTP_STATUS_PTP_MESS_ID_X(val); 508 txport = SYS_PTP_STATUS_PTP_MESS_TXPORT_X(val); 509 510 /* Retrieve its associated skb */ 511 port = ocelot->ports[txport]; 512 513 spin_lock_irqsave(&port->tx_skbs.lock, flags); 514 515 skb_queue_walk_safe(&port->tx_skbs, skb, skb_tmp) { 516 if (skb->cb[0] != id) 517 continue; 518 __skb_unlink(skb, &port->tx_skbs); 519 skb_match = skb; 520 break; 521 } 522 523 spin_unlock_irqrestore(&port->tx_skbs.lock, flags); 524 525 /* Get the h/w timestamp */ 526 ocelot_get_hwtimestamp(ocelot, &ts); 527 528 if (unlikely(!skb_match)) 529 continue; 530 531 /* Set the timestamp into the skb */ 532 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 533 shhwtstamps.hwtstamp = ktime_set(ts.tv_sec, ts.tv_nsec); 534 skb_complete_tx_timestamp(skb_match, &shhwtstamps); 535 536 /* Next ts */ 537 ocelot_write(ocelot, SYS_PTP_NXT_PTP_NXT, SYS_PTP_NXT); 538 } 539 } 540 EXPORT_SYMBOL(ocelot_get_txtstamp); 541 542 int ocelot_fdb_add(struct ocelot *ocelot, int port, 543 const unsigned char *addr, u16 vid) 544 { 545 struct ocelot_port *ocelot_port = ocelot->ports[port]; 546 int pgid = port; 547 548 if (port == ocelot->npi) 549 pgid = PGID_CPU; 550 551 if (!vid) { 552 if (!ocelot_port->vlan_aware) 553 /* If the bridge is not VLAN aware and no VID was 554 * provided, set it to pvid to ensure the MAC entry 555 * matches incoming untagged packets 556 */ 557 vid = ocelot_port->pvid; 558 else 559 /* If the bridge is VLAN aware a VID must be provided as 560 * otherwise the learnt entry wouldn't match any frame. 561 */ 562 return -EINVAL; 563 } 564 565 return ocelot_mact_learn(ocelot, pgid, addr, vid, ENTRYTYPE_LOCKED); 566 } 567 EXPORT_SYMBOL(ocelot_fdb_add); 568 569 int ocelot_fdb_del(struct ocelot *ocelot, int port, 570 const unsigned char *addr, u16 vid) 571 { 572 return ocelot_mact_forget(ocelot, addr, vid); 573 } 574 EXPORT_SYMBOL(ocelot_fdb_del); 575 576 int ocelot_port_fdb_do_dump(const unsigned char *addr, u16 vid, 577 bool is_static, void *data) 578 { 579 struct ocelot_dump_ctx *dump = data; 580 u32 portid = NETLINK_CB(dump->cb->skb).portid; 581 u32 seq = dump->cb->nlh->nlmsg_seq; 582 struct nlmsghdr *nlh; 583 struct ndmsg *ndm; 584 585 if (dump->idx < dump->cb->args[2]) 586 goto skip; 587 588 nlh = nlmsg_put(dump->skb, portid, seq, RTM_NEWNEIGH, 589 sizeof(*ndm), NLM_F_MULTI); 590 if (!nlh) 591 return -EMSGSIZE; 592 593 ndm = nlmsg_data(nlh); 594 ndm->ndm_family = AF_BRIDGE; 595 ndm->ndm_pad1 = 0; 596 ndm->ndm_pad2 = 0; 597 ndm->ndm_flags = NTF_SELF; 598 ndm->ndm_type = 0; 599 ndm->ndm_ifindex = dump->dev->ifindex; 600 ndm->ndm_state = is_static ? NUD_NOARP : NUD_REACHABLE; 601 602 if (nla_put(dump->skb, NDA_LLADDR, ETH_ALEN, addr)) 603 goto nla_put_failure; 604 605 if (vid && nla_put_u16(dump->skb, NDA_VLAN, vid)) 606 goto nla_put_failure; 607 608 nlmsg_end(dump->skb, nlh); 609 610 skip: 611 dump->idx++; 612 return 0; 613 614 nla_put_failure: 615 nlmsg_cancel(dump->skb, nlh); 616 return -EMSGSIZE; 617 } 618 EXPORT_SYMBOL(ocelot_port_fdb_do_dump); 619 620 static int ocelot_mact_read(struct ocelot *ocelot, int port, int row, int col, 621 struct ocelot_mact_entry *entry) 622 { 623 u32 val, dst, macl, mach; 624 char mac[ETH_ALEN]; 625 626 /* Set row and column to read from */ 627 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_M_INDEX, row); 628 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_BUCKET, col); 629 630 /* Issue a read command */ 631 ocelot_write(ocelot, 632 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_READ), 633 ANA_TABLES_MACACCESS); 634 635 if (ocelot_mact_wait_for_completion(ocelot)) 636 return -ETIMEDOUT; 637 638 /* Read the entry flags */ 639 val = ocelot_read(ocelot, ANA_TABLES_MACACCESS); 640 if (!(val & ANA_TABLES_MACACCESS_VALID)) 641 return -EINVAL; 642 643 /* If the entry read has another port configured as its destination, 644 * do not report it. 645 */ 646 dst = (val & ANA_TABLES_MACACCESS_DEST_IDX_M) >> 3; 647 if (dst != port) 648 return -EINVAL; 649 650 /* Get the entry's MAC address and VLAN id */ 651 macl = ocelot_read(ocelot, ANA_TABLES_MACLDATA); 652 mach = ocelot_read(ocelot, ANA_TABLES_MACHDATA); 653 654 mac[0] = (mach >> 8) & 0xff; 655 mac[1] = (mach >> 0) & 0xff; 656 mac[2] = (macl >> 24) & 0xff; 657 mac[3] = (macl >> 16) & 0xff; 658 mac[4] = (macl >> 8) & 0xff; 659 mac[5] = (macl >> 0) & 0xff; 660 661 entry->vid = (mach >> 16) & 0xfff; 662 ether_addr_copy(entry->mac, mac); 663 664 return 0; 665 } 666 667 int ocelot_fdb_dump(struct ocelot *ocelot, int port, 668 dsa_fdb_dump_cb_t *cb, void *data) 669 { 670 int i, j; 671 672 /* Loop through all the mac tables entries. */ 673 for (i = 0; i < ocelot->num_mact_rows; i++) { 674 for (j = 0; j < 4; j++) { 675 struct ocelot_mact_entry entry; 676 bool is_static; 677 int ret; 678 679 ret = ocelot_mact_read(ocelot, port, i, j, &entry); 680 /* If the entry is invalid (wrong port, invalid...), 681 * skip it. 682 */ 683 if (ret == -EINVAL) 684 continue; 685 else if (ret) 686 return ret; 687 688 is_static = (entry.type == ENTRYTYPE_LOCKED); 689 690 ret = cb(entry.mac, entry.vid, is_static, data); 691 if (ret) 692 return ret; 693 } 694 } 695 696 return 0; 697 } 698 EXPORT_SYMBOL(ocelot_fdb_dump); 699 700 int ocelot_hwstamp_get(struct ocelot *ocelot, int port, struct ifreq *ifr) 701 { 702 return copy_to_user(ifr->ifr_data, &ocelot->hwtstamp_config, 703 sizeof(ocelot->hwtstamp_config)) ? -EFAULT : 0; 704 } 705 EXPORT_SYMBOL(ocelot_hwstamp_get); 706 707 int ocelot_hwstamp_set(struct ocelot *ocelot, int port, struct ifreq *ifr) 708 { 709 struct ocelot_port *ocelot_port = ocelot->ports[port]; 710 struct hwtstamp_config cfg; 711 712 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg))) 713 return -EFAULT; 714 715 /* reserved for future extensions */ 716 if (cfg.flags) 717 return -EINVAL; 718 719 /* Tx type sanity check */ 720 switch (cfg.tx_type) { 721 case HWTSTAMP_TX_ON: 722 ocelot_port->ptp_cmd = IFH_REW_OP_TWO_STEP_PTP; 723 break; 724 case HWTSTAMP_TX_ONESTEP_SYNC: 725 /* IFH_REW_OP_ONE_STEP_PTP updates the correctional field, we 726 * need to update the origin time. 727 */ 728 ocelot_port->ptp_cmd = IFH_REW_OP_ORIGIN_PTP; 729 break; 730 case HWTSTAMP_TX_OFF: 731 ocelot_port->ptp_cmd = 0; 732 break; 733 default: 734 return -ERANGE; 735 } 736 737 mutex_lock(&ocelot->ptp_lock); 738 739 switch (cfg.rx_filter) { 740 case HWTSTAMP_FILTER_NONE: 741 break; 742 case HWTSTAMP_FILTER_ALL: 743 case HWTSTAMP_FILTER_SOME: 744 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 745 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 746 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 747 case HWTSTAMP_FILTER_NTP_ALL: 748 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 749 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 750 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 751 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 752 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 753 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 754 case HWTSTAMP_FILTER_PTP_V2_EVENT: 755 case HWTSTAMP_FILTER_PTP_V2_SYNC: 756 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 757 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 758 break; 759 default: 760 mutex_unlock(&ocelot->ptp_lock); 761 return -ERANGE; 762 } 763 764 /* Commit back the result & save it */ 765 memcpy(&ocelot->hwtstamp_config, &cfg, sizeof(cfg)); 766 mutex_unlock(&ocelot->ptp_lock); 767 768 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 769 } 770 EXPORT_SYMBOL(ocelot_hwstamp_set); 771 772 void ocelot_get_strings(struct ocelot *ocelot, int port, u32 sset, u8 *data) 773 { 774 int i; 775 776 if (sset != ETH_SS_STATS) 777 return; 778 779 for (i = 0; i < ocelot->num_stats; i++) 780 memcpy(data + i * ETH_GSTRING_LEN, ocelot->stats_layout[i].name, 781 ETH_GSTRING_LEN); 782 } 783 EXPORT_SYMBOL(ocelot_get_strings); 784 785 static void ocelot_update_stats(struct ocelot *ocelot) 786 { 787 int i, j; 788 789 mutex_lock(&ocelot->stats_lock); 790 791 for (i = 0; i < ocelot->num_phys_ports; i++) { 792 /* Configure the port to read the stats from */ 793 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(i), SYS_STAT_CFG); 794 795 for (j = 0; j < ocelot->num_stats; j++) { 796 u32 val; 797 unsigned int idx = i * ocelot->num_stats + j; 798 799 val = ocelot_read_rix(ocelot, SYS_COUNT_RX_OCTETS, 800 ocelot->stats_layout[j].offset); 801 802 if (val < (ocelot->stats[idx] & U32_MAX)) 803 ocelot->stats[idx] += (u64)1 << 32; 804 805 ocelot->stats[idx] = (ocelot->stats[idx] & 806 ~(u64)U32_MAX) + val; 807 } 808 } 809 810 mutex_unlock(&ocelot->stats_lock); 811 } 812 813 static void ocelot_check_stats_work(struct work_struct *work) 814 { 815 struct delayed_work *del_work = to_delayed_work(work); 816 struct ocelot *ocelot = container_of(del_work, struct ocelot, 817 stats_work); 818 819 ocelot_update_stats(ocelot); 820 821 queue_delayed_work(ocelot->stats_queue, &ocelot->stats_work, 822 OCELOT_STATS_CHECK_DELAY); 823 } 824 825 void ocelot_get_ethtool_stats(struct ocelot *ocelot, int port, u64 *data) 826 { 827 int i; 828 829 /* check and update now */ 830 ocelot_update_stats(ocelot); 831 832 /* Copy all counters */ 833 for (i = 0; i < ocelot->num_stats; i++) 834 *data++ = ocelot->stats[port * ocelot->num_stats + i]; 835 } 836 EXPORT_SYMBOL(ocelot_get_ethtool_stats); 837 838 int ocelot_get_sset_count(struct ocelot *ocelot, int port, int sset) 839 { 840 if (sset != ETH_SS_STATS) 841 return -EOPNOTSUPP; 842 843 return ocelot->num_stats; 844 } 845 EXPORT_SYMBOL(ocelot_get_sset_count); 846 847 int ocelot_get_ts_info(struct ocelot *ocelot, int port, 848 struct ethtool_ts_info *info) 849 { 850 info->phc_index = ocelot->ptp_clock ? 851 ptp_clock_index(ocelot->ptp_clock) : -1; 852 if (info->phc_index == -1) { 853 info->so_timestamping |= SOF_TIMESTAMPING_TX_SOFTWARE | 854 SOF_TIMESTAMPING_RX_SOFTWARE | 855 SOF_TIMESTAMPING_SOFTWARE; 856 return 0; 857 } 858 info->so_timestamping |= SOF_TIMESTAMPING_TX_SOFTWARE | 859 SOF_TIMESTAMPING_RX_SOFTWARE | 860 SOF_TIMESTAMPING_SOFTWARE | 861 SOF_TIMESTAMPING_TX_HARDWARE | 862 SOF_TIMESTAMPING_RX_HARDWARE | 863 SOF_TIMESTAMPING_RAW_HARDWARE; 864 info->tx_types = BIT(HWTSTAMP_TX_OFF) | BIT(HWTSTAMP_TX_ON) | 865 BIT(HWTSTAMP_TX_ONESTEP_SYNC); 866 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) | BIT(HWTSTAMP_FILTER_ALL); 867 868 return 0; 869 } 870 EXPORT_SYMBOL(ocelot_get_ts_info); 871 872 void ocelot_bridge_stp_state_set(struct ocelot *ocelot, int port, u8 state) 873 { 874 u32 port_cfg; 875 int p, i; 876 877 if (!(BIT(port) & ocelot->bridge_mask)) 878 return; 879 880 port_cfg = ocelot_read_gix(ocelot, ANA_PORT_PORT_CFG, port); 881 882 switch (state) { 883 case BR_STATE_FORWARDING: 884 ocelot->bridge_fwd_mask |= BIT(port); 885 fallthrough; 886 case BR_STATE_LEARNING: 887 port_cfg |= ANA_PORT_PORT_CFG_LEARN_ENA; 888 break; 889 890 default: 891 port_cfg &= ~ANA_PORT_PORT_CFG_LEARN_ENA; 892 ocelot->bridge_fwd_mask &= ~BIT(port); 893 break; 894 } 895 896 ocelot_write_gix(ocelot, port_cfg, ANA_PORT_PORT_CFG, port); 897 898 /* Apply FWD mask. The loop is needed to add/remove the current port as 899 * a source for the other ports. 900 */ 901 for (p = 0; p < ocelot->num_phys_ports; p++) { 902 if (ocelot->bridge_fwd_mask & BIT(p)) { 903 unsigned long mask = ocelot->bridge_fwd_mask & ~BIT(p); 904 905 for (i = 0; i < ocelot->num_phys_ports; i++) { 906 unsigned long bond_mask = ocelot->lags[i]; 907 908 if (!bond_mask) 909 continue; 910 911 if (bond_mask & BIT(p)) { 912 mask &= ~bond_mask; 913 break; 914 } 915 } 916 917 ocelot_write_rix(ocelot, mask, 918 ANA_PGID_PGID, PGID_SRC + p); 919 } else { 920 ocelot_write_rix(ocelot, 0, 921 ANA_PGID_PGID, PGID_SRC + p); 922 } 923 } 924 } 925 EXPORT_SYMBOL(ocelot_bridge_stp_state_set); 926 927 void ocelot_set_ageing_time(struct ocelot *ocelot, unsigned int msecs) 928 { 929 unsigned int age_period = ANA_AUTOAGE_AGE_PERIOD(msecs / 2000); 930 931 /* Setting AGE_PERIOD to zero effectively disables automatic aging, 932 * which is clearly not what our intention is. So avoid that. 933 */ 934 if (!age_period) 935 age_period = 1; 936 937 ocelot_rmw(ocelot, age_period, ANA_AUTOAGE_AGE_PERIOD_M, ANA_AUTOAGE); 938 } 939 EXPORT_SYMBOL(ocelot_set_ageing_time); 940 941 static struct ocelot_multicast *ocelot_multicast_get(struct ocelot *ocelot, 942 const unsigned char *addr, 943 u16 vid) 944 { 945 struct ocelot_multicast *mc; 946 947 list_for_each_entry(mc, &ocelot->multicast, list) { 948 if (ether_addr_equal(mc->addr, addr) && mc->vid == vid) 949 return mc; 950 } 951 952 return NULL; 953 } 954 955 static enum macaccess_entry_type ocelot_classify_mdb(const unsigned char *addr) 956 { 957 if (addr[0] == 0x01 && addr[1] == 0x00 && addr[2] == 0x5e) 958 return ENTRYTYPE_MACv4; 959 if (addr[0] == 0x33 && addr[1] == 0x33) 960 return ENTRYTYPE_MACv6; 961 return ENTRYTYPE_LOCKED; 962 } 963 964 static struct ocelot_pgid *ocelot_pgid_alloc(struct ocelot *ocelot, int index, 965 unsigned long ports) 966 { 967 struct ocelot_pgid *pgid; 968 969 pgid = kzalloc(sizeof(*pgid), GFP_KERNEL); 970 if (!pgid) 971 return ERR_PTR(-ENOMEM); 972 973 pgid->ports = ports; 974 pgid->index = index; 975 refcount_set(&pgid->refcount, 1); 976 list_add_tail(&pgid->list, &ocelot->pgids); 977 978 return pgid; 979 } 980 981 static void ocelot_pgid_free(struct ocelot *ocelot, struct ocelot_pgid *pgid) 982 { 983 if (!refcount_dec_and_test(&pgid->refcount)) 984 return; 985 986 list_del(&pgid->list); 987 kfree(pgid); 988 } 989 990 static struct ocelot_pgid *ocelot_mdb_get_pgid(struct ocelot *ocelot, 991 const struct ocelot_multicast *mc) 992 { 993 struct ocelot_pgid *pgid; 994 int index; 995 996 /* According to VSC7514 datasheet 3.9.1.5 IPv4 Multicast Entries and 997 * 3.9.1.6 IPv6 Multicast Entries, "Instead of a lookup in the 998 * destination mask table (PGID), the destination set is programmed as 999 * part of the entry MAC address.", and the DEST_IDX is set to 0. 1000 */ 1001 if (mc->entry_type == ENTRYTYPE_MACv4 || 1002 mc->entry_type == ENTRYTYPE_MACv6) 1003 return ocelot_pgid_alloc(ocelot, 0, mc->ports); 1004 1005 list_for_each_entry(pgid, &ocelot->pgids, list) { 1006 /* When searching for a nonreserved multicast PGID, ignore the 1007 * dummy PGID of zero that we have for MACv4/MACv6 entries 1008 */ 1009 if (pgid->index && pgid->ports == mc->ports) { 1010 refcount_inc(&pgid->refcount); 1011 return pgid; 1012 } 1013 } 1014 1015 /* Search for a free index in the nonreserved multicast PGID area */ 1016 for_each_nonreserved_multicast_dest_pgid(ocelot, index) { 1017 bool used = false; 1018 1019 list_for_each_entry(pgid, &ocelot->pgids, list) { 1020 if (pgid->index == index) { 1021 used = true; 1022 break; 1023 } 1024 } 1025 1026 if (!used) 1027 return ocelot_pgid_alloc(ocelot, index, mc->ports); 1028 } 1029 1030 return ERR_PTR(-ENOSPC); 1031 } 1032 1033 static void ocelot_encode_ports_to_mdb(unsigned char *addr, 1034 struct ocelot_multicast *mc) 1035 { 1036 ether_addr_copy(addr, mc->addr); 1037 1038 if (mc->entry_type == ENTRYTYPE_MACv4) { 1039 addr[0] = 0; 1040 addr[1] = mc->ports >> 8; 1041 addr[2] = mc->ports & 0xff; 1042 } else if (mc->entry_type == ENTRYTYPE_MACv6) { 1043 addr[0] = mc->ports >> 8; 1044 addr[1] = mc->ports & 0xff; 1045 } 1046 } 1047 1048 int ocelot_port_mdb_add(struct ocelot *ocelot, int port, 1049 const struct switchdev_obj_port_mdb *mdb) 1050 { 1051 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1052 unsigned char addr[ETH_ALEN]; 1053 struct ocelot_multicast *mc; 1054 struct ocelot_pgid *pgid; 1055 u16 vid = mdb->vid; 1056 1057 if (port == ocelot->npi) 1058 port = ocelot->num_phys_ports; 1059 1060 if (!vid) 1061 vid = ocelot_port->pvid; 1062 1063 mc = ocelot_multicast_get(ocelot, mdb->addr, vid); 1064 if (!mc) { 1065 /* New entry */ 1066 mc = devm_kzalloc(ocelot->dev, sizeof(*mc), GFP_KERNEL); 1067 if (!mc) 1068 return -ENOMEM; 1069 1070 mc->entry_type = ocelot_classify_mdb(mdb->addr); 1071 ether_addr_copy(mc->addr, mdb->addr); 1072 mc->vid = vid; 1073 1074 list_add_tail(&mc->list, &ocelot->multicast); 1075 } else { 1076 /* Existing entry. Clean up the current port mask from 1077 * hardware now, because we'll be modifying it. 1078 */ 1079 ocelot_pgid_free(ocelot, mc->pgid); 1080 ocelot_encode_ports_to_mdb(addr, mc); 1081 ocelot_mact_forget(ocelot, addr, vid); 1082 } 1083 1084 mc->ports |= BIT(port); 1085 1086 pgid = ocelot_mdb_get_pgid(ocelot, mc); 1087 if (IS_ERR(pgid)) { 1088 dev_err(ocelot->dev, 1089 "Cannot allocate PGID for mdb %pM vid %d\n", 1090 mc->addr, mc->vid); 1091 devm_kfree(ocelot->dev, mc); 1092 return PTR_ERR(pgid); 1093 } 1094 mc->pgid = pgid; 1095 1096 ocelot_encode_ports_to_mdb(addr, mc); 1097 1098 if (mc->entry_type != ENTRYTYPE_MACv4 && 1099 mc->entry_type != ENTRYTYPE_MACv6) 1100 ocelot_write_rix(ocelot, pgid->ports, ANA_PGID_PGID, 1101 pgid->index); 1102 1103 return ocelot_mact_learn(ocelot, pgid->index, addr, vid, 1104 mc->entry_type); 1105 } 1106 EXPORT_SYMBOL(ocelot_port_mdb_add); 1107 1108 int ocelot_port_mdb_del(struct ocelot *ocelot, int port, 1109 const struct switchdev_obj_port_mdb *mdb) 1110 { 1111 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1112 unsigned char addr[ETH_ALEN]; 1113 struct ocelot_multicast *mc; 1114 struct ocelot_pgid *pgid; 1115 u16 vid = mdb->vid; 1116 1117 if (port == ocelot->npi) 1118 port = ocelot->num_phys_ports; 1119 1120 if (!vid) 1121 vid = ocelot_port->pvid; 1122 1123 mc = ocelot_multicast_get(ocelot, mdb->addr, vid); 1124 if (!mc) 1125 return -ENOENT; 1126 1127 ocelot_encode_ports_to_mdb(addr, mc); 1128 ocelot_mact_forget(ocelot, addr, vid); 1129 1130 ocelot_pgid_free(ocelot, mc->pgid); 1131 mc->ports &= ~BIT(port); 1132 if (!mc->ports) { 1133 list_del(&mc->list); 1134 devm_kfree(ocelot->dev, mc); 1135 return 0; 1136 } 1137 1138 /* We have a PGID with fewer ports now */ 1139 pgid = ocelot_mdb_get_pgid(ocelot, mc); 1140 if (IS_ERR(pgid)) 1141 return PTR_ERR(pgid); 1142 mc->pgid = pgid; 1143 1144 ocelot_encode_ports_to_mdb(addr, mc); 1145 1146 if (mc->entry_type != ENTRYTYPE_MACv4 && 1147 mc->entry_type != ENTRYTYPE_MACv6) 1148 ocelot_write_rix(ocelot, pgid->ports, ANA_PGID_PGID, 1149 pgid->index); 1150 1151 return ocelot_mact_learn(ocelot, pgid->index, addr, vid, 1152 mc->entry_type); 1153 } 1154 EXPORT_SYMBOL(ocelot_port_mdb_del); 1155 1156 int ocelot_port_bridge_join(struct ocelot *ocelot, int port, 1157 struct net_device *bridge) 1158 { 1159 if (!ocelot->bridge_mask) { 1160 ocelot->hw_bridge_dev = bridge; 1161 } else { 1162 if (ocelot->hw_bridge_dev != bridge) 1163 /* This is adding the port to a second bridge, this is 1164 * unsupported */ 1165 return -ENODEV; 1166 } 1167 1168 ocelot->bridge_mask |= BIT(port); 1169 1170 return 0; 1171 } 1172 EXPORT_SYMBOL(ocelot_port_bridge_join); 1173 1174 int ocelot_port_bridge_leave(struct ocelot *ocelot, int port, 1175 struct net_device *bridge) 1176 { 1177 struct switchdev_trans trans; 1178 int ret; 1179 1180 ocelot->bridge_mask &= ~BIT(port); 1181 1182 if (!ocelot->bridge_mask) 1183 ocelot->hw_bridge_dev = NULL; 1184 1185 trans.ph_prepare = true; 1186 ret = ocelot_port_vlan_filtering(ocelot, port, false, &trans); 1187 if (ret) 1188 return ret; 1189 1190 trans.ph_prepare = false; 1191 ret = ocelot_port_vlan_filtering(ocelot, port, false, &trans); 1192 if (ret) 1193 return ret; 1194 1195 ocelot_port_set_pvid(ocelot, port, 0); 1196 return ocelot_port_set_native_vlan(ocelot, port, 0); 1197 } 1198 EXPORT_SYMBOL(ocelot_port_bridge_leave); 1199 1200 static void ocelot_set_aggr_pgids(struct ocelot *ocelot) 1201 { 1202 int i, port, lag; 1203 1204 /* Reset destination and aggregation PGIDS */ 1205 for_each_unicast_dest_pgid(ocelot, port) 1206 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port); 1207 1208 for_each_aggr_pgid(ocelot, i) 1209 ocelot_write_rix(ocelot, GENMASK(ocelot->num_phys_ports - 1, 0), 1210 ANA_PGID_PGID, i); 1211 1212 /* Now, set PGIDs for each LAG */ 1213 for (lag = 0; lag < ocelot->num_phys_ports; lag++) { 1214 unsigned long bond_mask; 1215 int aggr_count = 0; 1216 u8 aggr_idx[16]; 1217 1218 bond_mask = ocelot->lags[lag]; 1219 if (!bond_mask) 1220 continue; 1221 1222 for_each_set_bit(port, &bond_mask, ocelot->num_phys_ports) { 1223 // Destination mask 1224 ocelot_write_rix(ocelot, bond_mask, 1225 ANA_PGID_PGID, port); 1226 aggr_idx[aggr_count] = port; 1227 aggr_count++; 1228 } 1229 1230 for_each_aggr_pgid(ocelot, i) { 1231 u32 ac; 1232 1233 ac = ocelot_read_rix(ocelot, ANA_PGID_PGID, i); 1234 ac &= ~bond_mask; 1235 ac |= BIT(aggr_idx[i % aggr_count]); 1236 ocelot_write_rix(ocelot, ac, ANA_PGID_PGID, i); 1237 } 1238 } 1239 } 1240 1241 static void ocelot_setup_lag(struct ocelot *ocelot, int lag) 1242 { 1243 unsigned long bond_mask = ocelot->lags[lag]; 1244 unsigned int p; 1245 1246 for_each_set_bit(p, &bond_mask, ocelot->num_phys_ports) { 1247 u32 port_cfg = ocelot_read_gix(ocelot, ANA_PORT_PORT_CFG, p); 1248 1249 port_cfg &= ~ANA_PORT_PORT_CFG_PORTID_VAL_M; 1250 1251 /* Use lag port as logical port for port i */ 1252 ocelot_write_gix(ocelot, port_cfg | 1253 ANA_PORT_PORT_CFG_PORTID_VAL(lag), 1254 ANA_PORT_PORT_CFG, p); 1255 } 1256 } 1257 1258 int ocelot_port_lag_join(struct ocelot *ocelot, int port, 1259 struct net_device *bond) 1260 { 1261 struct net_device *ndev; 1262 u32 bond_mask = 0; 1263 int lag, lp; 1264 1265 rcu_read_lock(); 1266 for_each_netdev_in_bond_rcu(bond, ndev) { 1267 struct ocelot_port_private *priv = netdev_priv(ndev); 1268 1269 bond_mask |= BIT(priv->chip_port); 1270 } 1271 rcu_read_unlock(); 1272 1273 lp = __ffs(bond_mask); 1274 1275 /* If the new port is the lowest one, use it as the logical port from 1276 * now on 1277 */ 1278 if (port == lp) { 1279 lag = port; 1280 ocelot->lags[port] = bond_mask; 1281 bond_mask &= ~BIT(port); 1282 if (bond_mask) { 1283 lp = __ffs(bond_mask); 1284 ocelot->lags[lp] = 0; 1285 } 1286 } else { 1287 lag = lp; 1288 ocelot->lags[lp] |= BIT(port); 1289 } 1290 1291 ocelot_setup_lag(ocelot, lag); 1292 ocelot_set_aggr_pgids(ocelot); 1293 1294 return 0; 1295 } 1296 EXPORT_SYMBOL(ocelot_port_lag_join); 1297 1298 void ocelot_port_lag_leave(struct ocelot *ocelot, int port, 1299 struct net_device *bond) 1300 { 1301 u32 port_cfg; 1302 int i; 1303 1304 /* Remove port from any lag */ 1305 for (i = 0; i < ocelot->num_phys_ports; i++) 1306 ocelot->lags[i] &= ~BIT(port); 1307 1308 /* if it was the logical port of the lag, move the lag config to the 1309 * next port 1310 */ 1311 if (ocelot->lags[port]) { 1312 int n = __ffs(ocelot->lags[port]); 1313 1314 ocelot->lags[n] = ocelot->lags[port]; 1315 ocelot->lags[port] = 0; 1316 1317 ocelot_setup_lag(ocelot, n); 1318 } 1319 1320 port_cfg = ocelot_read_gix(ocelot, ANA_PORT_PORT_CFG, port); 1321 port_cfg &= ~ANA_PORT_PORT_CFG_PORTID_VAL_M; 1322 ocelot_write_gix(ocelot, port_cfg | ANA_PORT_PORT_CFG_PORTID_VAL(port), 1323 ANA_PORT_PORT_CFG, port); 1324 1325 ocelot_set_aggr_pgids(ocelot); 1326 } 1327 EXPORT_SYMBOL(ocelot_port_lag_leave); 1328 1329 /* Configure the maximum SDU (L2 payload) on RX to the value specified in @sdu. 1330 * The length of VLAN tags is accounted for automatically via DEV_MAC_TAGS_CFG. 1331 * In the special case that it's the NPI port that we're configuring, the 1332 * length of the tag and optional prefix needs to be accounted for privately, 1333 * in order to be able to sustain communication at the requested @sdu. 1334 */ 1335 void ocelot_port_set_maxlen(struct ocelot *ocelot, int port, size_t sdu) 1336 { 1337 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1338 int maxlen = sdu + ETH_HLEN + ETH_FCS_LEN; 1339 int pause_start, pause_stop; 1340 int atop, atop_tot; 1341 1342 if (port == ocelot->npi) { 1343 maxlen += OCELOT_TAG_LEN; 1344 1345 if (ocelot->inj_prefix == OCELOT_TAG_PREFIX_SHORT) 1346 maxlen += OCELOT_SHORT_PREFIX_LEN; 1347 else if (ocelot->inj_prefix == OCELOT_TAG_PREFIX_LONG) 1348 maxlen += OCELOT_LONG_PREFIX_LEN; 1349 } 1350 1351 ocelot_port_writel(ocelot_port, maxlen, DEV_MAC_MAXLEN_CFG); 1352 1353 /* Set Pause watermark hysteresis */ 1354 pause_start = 6 * maxlen / OCELOT_BUFFER_CELL_SZ; 1355 pause_stop = 4 * maxlen / OCELOT_BUFFER_CELL_SZ; 1356 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_START, 1357 pause_start); 1358 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_STOP, 1359 pause_stop); 1360 1361 /* Tail dropping watermarks */ 1362 atop_tot = (ocelot->shared_queue_sz - 9 * maxlen) / 1363 OCELOT_BUFFER_CELL_SZ; 1364 atop = (9 * maxlen) / OCELOT_BUFFER_CELL_SZ; 1365 ocelot_write_rix(ocelot, ocelot->ops->wm_enc(atop), SYS_ATOP, port); 1366 ocelot_write(ocelot, ocelot->ops->wm_enc(atop_tot), SYS_ATOP_TOT_CFG); 1367 } 1368 EXPORT_SYMBOL(ocelot_port_set_maxlen); 1369 1370 int ocelot_get_max_mtu(struct ocelot *ocelot, int port) 1371 { 1372 int max_mtu = 65535 - ETH_HLEN - ETH_FCS_LEN; 1373 1374 if (port == ocelot->npi) { 1375 max_mtu -= OCELOT_TAG_LEN; 1376 1377 if (ocelot->inj_prefix == OCELOT_TAG_PREFIX_SHORT) 1378 max_mtu -= OCELOT_SHORT_PREFIX_LEN; 1379 else if (ocelot->inj_prefix == OCELOT_TAG_PREFIX_LONG) 1380 max_mtu -= OCELOT_LONG_PREFIX_LEN; 1381 } 1382 1383 return max_mtu; 1384 } 1385 EXPORT_SYMBOL(ocelot_get_max_mtu); 1386 1387 void ocelot_init_port(struct ocelot *ocelot, int port) 1388 { 1389 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1390 1391 skb_queue_head_init(&ocelot_port->tx_skbs); 1392 spin_lock_init(&ocelot_port->ts_id_lock); 1393 1394 /* Basic L2 initialization */ 1395 1396 /* Set MAC IFG Gaps 1397 * FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 0 1398 * !FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 5 1399 */ 1400 ocelot_port_writel(ocelot_port, DEV_MAC_IFG_CFG_TX_IFG(5), 1401 DEV_MAC_IFG_CFG); 1402 1403 /* Load seed (0) and set MAC HDX late collision */ 1404 ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67) | 1405 DEV_MAC_HDX_CFG_SEED_LOAD, 1406 DEV_MAC_HDX_CFG); 1407 mdelay(1); 1408 ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67), 1409 DEV_MAC_HDX_CFG); 1410 1411 /* Set Max Length and maximum tags allowed */ 1412 ocelot_port_set_maxlen(ocelot, port, ETH_DATA_LEN); 1413 ocelot_port_writel(ocelot_port, DEV_MAC_TAGS_CFG_TAG_ID(ETH_P_8021AD) | 1414 DEV_MAC_TAGS_CFG_VLAN_AWR_ENA | 1415 DEV_MAC_TAGS_CFG_VLAN_DBL_AWR_ENA | 1416 DEV_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA, 1417 DEV_MAC_TAGS_CFG); 1418 1419 /* Set SMAC of Pause frame (00:00:00:00:00:00) */ 1420 ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_HIGH_CFG); 1421 ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_LOW_CFG); 1422 1423 /* Enable transmission of pause frames */ 1424 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, 1); 1425 1426 /* Drop frames with multicast source address */ 1427 ocelot_rmw_gix(ocelot, ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA, 1428 ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA, 1429 ANA_PORT_DROP_CFG, port); 1430 1431 /* Set default VLAN and tag type to 8021Q. */ 1432 ocelot_rmw_gix(ocelot, REW_PORT_VLAN_CFG_PORT_TPID(ETH_P_8021Q), 1433 REW_PORT_VLAN_CFG_PORT_TPID_M, 1434 REW_PORT_VLAN_CFG, port); 1435 1436 /* Enable vcap lookups */ 1437 ocelot_vcap_enable(ocelot, port); 1438 } 1439 EXPORT_SYMBOL(ocelot_init_port); 1440 1441 /* Configure and enable the CPU port module, which is a set of queues 1442 * accessible through register MMIO, frame DMA or Ethernet (in case 1443 * NPI mode is used). 1444 */ 1445 static void ocelot_cpu_port_init(struct ocelot *ocelot) 1446 { 1447 int cpu = ocelot->num_phys_ports; 1448 1449 /* The unicast destination PGID for the CPU port module is unused */ 1450 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, cpu); 1451 /* Instead set up a multicast destination PGID for traffic copied to 1452 * the CPU. Whitelisted MAC addresses like the port netdevice MAC 1453 * addresses will be copied to the CPU via this PGID. 1454 */ 1455 ocelot_write_rix(ocelot, BIT(cpu), ANA_PGID_PGID, PGID_CPU); 1456 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_RECV_ENA | 1457 ANA_PORT_PORT_CFG_PORTID_VAL(cpu), 1458 ANA_PORT_PORT_CFG, cpu); 1459 1460 /* Enable CPU port module */ 1461 ocelot_fields_write(ocelot, cpu, QSYS_SWITCH_PORT_MODE_PORT_ENA, 1); 1462 /* CPU port Injection/Extraction configuration */ 1463 ocelot_fields_write(ocelot, cpu, SYS_PORT_MODE_INCL_XTR_HDR, 1464 ocelot->xtr_prefix); 1465 ocelot_fields_write(ocelot, cpu, SYS_PORT_MODE_INCL_INJ_HDR, 1466 ocelot->inj_prefix); 1467 1468 /* Configure the CPU port to be VLAN aware */ 1469 ocelot_write_gix(ocelot, ANA_PORT_VLAN_CFG_VLAN_VID(0) | 1470 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 1471 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1), 1472 ANA_PORT_VLAN_CFG, cpu); 1473 } 1474 1475 int ocelot_init(struct ocelot *ocelot) 1476 { 1477 char queue_name[32]; 1478 int i, ret; 1479 u32 port; 1480 1481 if (ocelot->ops->reset) { 1482 ret = ocelot->ops->reset(ocelot); 1483 if (ret) { 1484 dev_err(ocelot->dev, "Switch reset failed\n"); 1485 return ret; 1486 } 1487 } 1488 1489 ocelot->lags = devm_kcalloc(ocelot->dev, ocelot->num_phys_ports, 1490 sizeof(u32), GFP_KERNEL); 1491 if (!ocelot->lags) 1492 return -ENOMEM; 1493 1494 ocelot->stats = devm_kcalloc(ocelot->dev, 1495 ocelot->num_phys_ports * ocelot->num_stats, 1496 sizeof(u64), GFP_KERNEL); 1497 if (!ocelot->stats) 1498 return -ENOMEM; 1499 1500 mutex_init(&ocelot->stats_lock); 1501 mutex_init(&ocelot->ptp_lock); 1502 spin_lock_init(&ocelot->ptp_clock_lock); 1503 snprintf(queue_name, sizeof(queue_name), "%s-stats", 1504 dev_name(ocelot->dev)); 1505 ocelot->stats_queue = create_singlethread_workqueue(queue_name); 1506 if (!ocelot->stats_queue) 1507 return -ENOMEM; 1508 1509 INIT_LIST_HEAD(&ocelot->multicast); 1510 INIT_LIST_HEAD(&ocelot->pgids); 1511 ocelot_mact_init(ocelot); 1512 ocelot_vlan_init(ocelot); 1513 ocelot_vcap_init(ocelot); 1514 ocelot_cpu_port_init(ocelot); 1515 1516 for (port = 0; port < ocelot->num_phys_ports; port++) { 1517 /* Clear all counters (5 groups) */ 1518 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(port) | 1519 SYS_STAT_CFG_STAT_CLEAR_SHOT(0x7f), 1520 SYS_STAT_CFG); 1521 } 1522 1523 /* Only use S-Tag */ 1524 ocelot_write(ocelot, ETH_P_8021AD, SYS_VLAN_ETYPE_CFG); 1525 1526 /* Aggregation mode */ 1527 ocelot_write(ocelot, ANA_AGGR_CFG_AC_SMAC_ENA | 1528 ANA_AGGR_CFG_AC_DMAC_ENA | 1529 ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA | 1530 ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA, ANA_AGGR_CFG); 1531 1532 /* Set MAC age time to default value. The entry is aged after 1533 * 2*AGE_PERIOD 1534 */ 1535 ocelot_write(ocelot, 1536 ANA_AUTOAGE_AGE_PERIOD(BR_DEFAULT_AGEING_TIME / 2 / HZ), 1537 ANA_AUTOAGE); 1538 1539 /* Disable learning for frames discarded by VLAN ingress filtering */ 1540 regmap_field_write(ocelot->regfields[ANA_ADVLEARN_VLAN_CHK], 1); 1541 1542 /* Setup frame ageing - fixed value "2 sec" - in 6.5 us units */ 1543 ocelot_write(ocelot, SYS_FRM_AGING_AGE_TX_ENA | 1544 SYS_FRM_AGING_MAX_AGE(307692), SYS_FRM_AGING); 1545 1546 /* Setup flooding PGIDs */ 1547 ocelot_write_rix(ocelot, ANA_FLOODING_FLD_MULTICAST(PGID_MC) | 1548 ANA_FLOODING_FLD_BROADCAST(PGID_MC) | 1549 ANA_FLOODING_FLD_UNICAST(PGID_UC), 1550 ANA_FLOODING, 0); 1551 ocelot_write(ocelot, ANA_FLOODING_IPMC_FLD_MC6_DATA(PGID_MCIPV6) | 1552 ANA_FLOODING_IPMC_FLD_MC6_CTRL(PGID_MC) | 1553 ANA_FLOODING_IPMC_FLD_MC4_DATA(PGID_MCIPV4) | 1554 ANA_FLOODING_IPMC_FLD_MC4_CTRL(PGID_MC), 1555 ANA_FLOODING_IPMC); 1556 1557 for (port = 0; port < ocelot->num_phys_ports; port++) { 1558 /* Transmit the frame to the local port. */ 1559 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port); 1560 /* Do not forward BPDU frames to the front ports. */ 1561 ocelot_write_gix(ocelot, 1562 ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA(0xffff), 1563 ANA_PORT_CPU_FWD_BPDU_CFG, 1564 port); 1565 /* Ensure bridging is disabled */ 1566 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_SRC + port); 1567 } 1568 1569 /* Allow broadcast MAC frames. */ 1570 for_each_nonreserved_multicast_dest_pgid(ocelot, i) { 1571 u32 val = ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports - 1, 0)); 1572 1573 ocelot_write_rix(ocelot, val, ANA_PGID_PGID, i); 1574 } 1575 ocelot_write_rix(ocelot, 1576 ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports, 0)), 1577 ANA_PGID_PGID, PGID_MC); 1578 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV4); 1579 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV6); 1580 1581 /* Allow manual injection via DEVCPU_QS registers, and byte swap these 1582 * registers endianness. 1583 */ 1584 ocelot_write_rix(ocelot, QS_INJ_GRP_CFG_BYTE_SWAP | 1585 QS_INJ_GRP_CFG_MODE(1), QS_INJ_GRP_CFG, 0); 1586 ocelot_write_rix(ocelot, QS_XTR_GRP_CFG_BYTE_SWAP | 1587 QS_XTR_GRP_CFG_MODE(1), QS_XTR_GRP_CFG, 0); 1588 ocelot_write(ocelot, ANA_CPUQ_CFG_CPUQ_MIRROR(2) | 1589 ANA_CPUQ_CFG_CPUQ_LRN(2) | 1590 ANA_CPUQ_CFG_CPUQ_MAC_COPY(2) | 1591 ANA_CPUQ_CFG_CPUQ_SRC_COPY(2) | 1592 ANA_CPUQ_CFG_CPUQ_LOCKED_PORTMOVE(2) | 1593 ANA_CPUQ_CFG_CPUQ_ALLBRIDGE(6) | 1594 ANA_CPUQ_CFG_CPUQ_IPMC_CTRL(6) | 1595 ANA_CPUQ_CFG_CPUQ_IGMP(6) | 1596 ANA_CPUQ_CFG_CPUQ_MLD(6), ANA_CPUQ_CFG); 1597 for (i = 0; i < 16; i++) 1598 ocelot_write_rix(ocelot, ANA_CPUQ_8021_CFG_CPUQ_GARP_VAL(6) | 1599 ANA_CPUQ_8021_CFG_CPUQ_BPDU_VAL(6), 1600 ANA_CPUQ_8021_CFG, i); 1601 1602 INIT_DELAYED_WORK(&ocelot->stats_work, ocelot_check_stats_work); 1603 queue_delayed_work(ocelot->stats_queue, &ocelot->stats_work, 1604 OCELOT_STATS_CHECK_DELAY); 1605 1606 return 0; 1607 } 1608 EXPORT_SYMBOL(ocelot_init); 1609 1610 void ocelot_deinit(struct ocelot *ocelot) 1611 { 1612 cancel_delayed_work(&ocelot->stats_work); 1613 destroy_workqueue(ocelot->stats_queue); 1614 mutex_destroy(&ocelot->stats_lock); 1615 } 1616 EXPORT_SYMBOL(ocelot_deinit); 1617 1618 void ocelot_deinit_port(struct ocelot *ocelot, int port) 1619 { 1620 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1621 1622 skb_queue_purge(&ocelot_port->tx_skbs); 1623 } 1624 EXPORT_SYMBOL(ocelot_deinit_port); 1625 1626 MODULE_LICENSE("Dual MIT/GPL"); 1627