1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* 3 * Microsemi Ocelot Switch driver 4 * 5 * Copyright (c) 2017 Microsemi Corporation 6 */ 7 #include <linux/dsa/ocelot.h> 8 #include <linux/if_bridge.h> 9 #include <linux/ptp_classify.h> 10 #include <soc/mscc/ocelot_vcap.h> 11 #include "ocelot.h" 12 #include "ocelot_vcap.h" 13 14 #define TABLE_UPDATE_SLEEP_US 10 15 #define TABLE_UPDATE_TIMEOUT_US 100000 16 17 struct ocelot_mact_entry { 18 u8 mac[ETH_ALEN]; 19 u16 vid; 20 enum macaccess_entry_type type; 21 }; 22 23 /* Caller must hold &ocelot->mact_lock */ 24 static inline u32 ocelot_mact_read_macaccess(struct ocelot *ocelot) 25 { 26 return ocelot_read(ocelot, ANA_TABLES_MACACCESS); 27 } 28 29 /* Caller must hold &ocelot->mact_lock */ 30 static inline int ocelot_mact_wait_for_completion(struct ocelot *ocelot) 31 { 32 u32 val; 33 34 return readx_poll_timeout(ocelot_mact_read_macaccess, 35 ocelot, val, 36 (val & ANA_TABLES_MACACCESS_MAC_TABLE_CMD_M) == 37 MACACCESS_CMD_IDLE, 38 TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US); 39 } 40 41 /* Caller must hold &ocelot->mact_lock */ 42 static void ocelot_mact_select(struct ocelot *ocelot, 43 const unsigned char mac[ETH_ALEN], 44 unsigned int vid) 45 { 46 u32 macl = 0, mach = 0; 47 48 /* Set the MAC address to handle and the vlan associated in a format 49 * understood by the hardware. 50 */ 51 mach |= vid << 16; 52 mach |= mac[0] << 8; 53 mach |= mac[1] << 0; 54 macl |= mac[2] << 24; 55 macl |= mac[3] << 16; 56 macl |= mac[4] << 8; 57 macl |= mac[5] << 0; 58 59 ocelot_write(ocelot, macl, ANA_TABLES_MACLDATA); 60 ocelot_write(ocelot, mach, ANA_TABLES_MACHDATA); 61 62 } 63 64 static int __ocelot_mact_learn(struct ocelot *ocelot, int port, 65 const unsigned char mac[ETH_ALEN], 66 unsigned int vid, enum macaccess_entry_type type) 67 { 68 u32 cmd = ANA_TABLES_MACACCESS_VALID | 69 ANA_TABLES_MACACCESS_DEST_IDX(port) | 70 ANA_TABLES_MACACCESS_ENTRYTYPE(type) | 71 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_LEARN); 72 unsigned int mc_ports; 73 int err; 74 75 /* Set MAC_CPU_COPY if the CPU port is used by a multicast entry */ 76 if (type == ENTRYTYPE_MACv4) 77 mc_ports = (mac[1] << 8) | mac[2]; 78 else if (type == ENTRYTYPE_MACv6) 79 mc_ports = (mac[0] << 8) | mac[1]; 80 else 81 mc_ports = 0; 82 83 if (mc_ports & BIT(ocelot->num_phys_ports)) 84 cmd |= ANA_TABLES_MACACCESS_MAC_CPU_COPY; 85 86 ocelot_mact_select(ocelot, mac, vid); 87 88 /* Issue a write command */ 89 ocelot_write(ocelot, cmd, ANA_TABLES_MACACCESS); 90 91 err = ocelot_mact_wait_for_completion(ocelot); 92 93 return err; 94 } 95 96 int ocelot_mact_learn(struct ocelot *ocelot, int port, 97 const unsigned char mac[ETH_ALEN], 98 unsigned int vid, enum macaccess_entry_type type) 99 { 100 int ret; 101 102 mutex_lock(&ocelot->mact_lock); 103 ret = __ocelot_mact_learn(ocelot, port, mac, vid, type); 104 mutex_unlock(&ocelot->mact_lock); 105 106 return ret; 107 } 108 EXPORT_SYMBOL(ocelot_mact_learn); 109 110 int ocelot_mact_forget(struct ocelot *ocelot, 111 const unsigned char mac[ETH_ALEN], unsigned int vid) 112 { 113 int err; 114 115 mutex_lock(&ocelot->mact_lock); 116 117 ocelot_mact_select(ocelot, mac, vid); 118 119 /* Issue a forget command */ 120 ocelot_write(ocelot, 121 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_FORGET), 122 ANA_TABLES_MACACCESS); 123 124 err = ocelot_mact_wait_for_completion(ocelot); 125 126 mutex_unlock(&ocelot->mact_lock); 127 128 return err; 129 } 130 EXPORT_SYMBOL(ocelot_mact_forget); 131 132 int ocelot_mact_lookup(struct ocelot *ocelot, int *dst_idx, 133 const unsigned char mac[ETH_ALEN], 134 unsigned int vid, enum macaccess_entry_type *type) 135 { 136 int val; 137 138 mutex_lock(&ocelot->mact_lock); 139 140 ocelot_mact_select(ocelot, mac, vid); 141 142 /* Issue a read command with MACACCESS_VALID=1. */ 143 ocelot_write(ocelot, ANA_TABLES_MACACCESS_VALID | 144 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_READ), 145 ANA_TABLES_MACACCESS); 146 147 if (ocelot_mact_wait_for_completion(ocelot)) { 148 mutex_unlock(&ocelot->mact_lock); 149 return -ETIMEDOUT; 150 } 151 152 /* Read back the entry flags */ 153 val = ocelot_read(ocelot, ANA_TABLES_MACACCESS); 154 155 mutex_unlock(&ocelot->mact_lock); 156 157 if (!(val & ANA_TABLES_MACACCESS_VALID)) 158 return -ENOENT; 159 160 *dst_idx = ANA_TABLES_MACACCESS_DEST_IDX_X(val); 161 *type = ANA_TABLES_MACACCESS_ENTRYTYPE_X(val); 162 163 return 0; 164 } 165 EXPORT_SYMBOL(ocelot_mact_lookup); 166 167 int ocelot_mact_learn_streamdata(struct ocelot *ocelot, int dst_idx, 168 const unsigned char mac[ETH_ALEN], 169 unsigned int vid, 170 enum macaccess_entry_type type, 171 int sfid, int ssid) 172 { 173 int ret; 174 175 mutex_lock(&ocelot->mact_lock); 176 177 ocelot_write(ocelot, 178 (sfid < 0 ? 0 : ANA_TABLES_STREAMDATA_SFID_VALID) | 179 ANA_TABLES_STREAMDATA_SFID(sfid) | 180 (ssid < 0 ? 0 : ANA_TABLES_STREAMDATA_SSID_VALID) | 181 ANA_TABLES_STREAMDATA_SSID(ssid), 182 ANA_TABLES_STREAMDATA); 183 184 ret = __ocelot_mact_learn(ocelot, dst_idx, mac, vid, type); 185 186 mutex_unlock(&ocelot->mact_lock); 187 188 return ret; 189 } 190 EXPORT_SYMBOL(ocelot_mact_learn_streamdata); 191 192 static void ocelot_mact_init(struct ocelot *ocelot) 193 { 194 /* Configure the learning mode entries attributes: 195 * - Do not copy the frame to the CPU extraction queues. 196 * - Use the vlan and mac_cpoy for dmac lookup. 197 */ 198 ocelot_rmw(ocelot, 0, 199 ANA_AGENCTRL_LEARN_CPU_COPY | ANA_AGENCTRL_IGNORE_DMAC_FLAGS 200 | ANA_AGENCTRL_LEARN_FWD_KILL 201 | ANA_AGENCTRL_LEARN_IGNORE_VLAN, 202 ANA_AGENCTRL); 203 204 /* Clear the MAC table. We are not concurrent with anyone, so 205 * holding &ocelot->mact_lock is pointless. 206 */ 207 ocelot_write(ocelot, MACACCESS_CMD_INIT, ANA_TABLES_MACACCESS); 208 } 209 210 static void ocelot_vcap_enable(struct ocelot *ocelot, int port) 211 { 212 ocelot_write_gix(ocelot, ANA_PORT_VCAP_S2_CFG_S2_ENA | 213 ANA_PORT_VCAP_S2_CFG_S2_IP6_CFG(0xa), 214 ANA_PORT_VCAP_S2_CFG, port); 215 216 ocelot_write_gix(ocelot, ANA_PORT_VCAP_CFG_S1_ENA, 217 ANA_PORT_VCAP_CFG, port); 218 219 ocelot_rmw_gix(ocelot, REW_PORT_CFG_ES0_EN, 220 REW_PORT_CFG_ES0_EN, 221 REW_PORT_CFG, port); 222 } 223 224 static inline u32 ocelot_vlant_read_vlanaccess(struct ocelot *ocelot) 225 { 226 return ocelot_read(ocelot, ANA_TABLES_VLANACCESS); 227 } 228 229 static inline int ocelot_vlant_wait_for_completion(struct ocelot *ocelot) 230 { 231 u32 val; 232 233 return readx_poll_timeout(ocelot_vlant_read_vlanaccess, 234 ocelot, 235 val, 236 (val & ANA_TABLES_VLANACCESS_VLAN_TBL_CMD_M) == 237 ANA_TABLES_VLANACCESS_CMD_IDLE, 238 TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US); 239 } 240 241 static int ocelot_vlant_set_mask(struct ocelot *ocelot, u16 vid, u32 mask) 242 { 243 /* Select the VID to configure */ 244 ocelot_write(ocelot, ANA_TABLES_VLANTIDX_V_INDEX(vid), 245 ANA_TABLES_VLANTIDX); 246 /* Set the vlan port members mask and issue a write command */ 247 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_VLAN_PORT_MASK(mask) | 248 ANA_TABLES_VLANACCESS_CMD_WRITE, 249 ANA_TABLES_VLANACCESS); 250 251 return ocelot_vlant_wait_for_completion(ocelot); 252 } 253 254 static int ocelot_port_num_untagged_vlans(struct ocelot *ocelot, int port) 255 { 256 struct ocelot_bridge_vlan *vlan; 257 int num_untagged = 0; 258 259 list_for_each_entry(vlan, &ocelot->vlans, list) { 260 if (!(vlan->portmask & BIT(port))) 261 continue; 262 263 if (vlan->untagged & BIT(port)) 264 num_untagged++; 265 } 266 267 return num_untagged; 268 } 269 270 static int ocelot_port_num_tagged_vlans(struct ocelot *ocelot, int port) 271 { 272 struct ocelot_bridge_vlan *vlan; 273 int num_tagged = 0; 274 275 list_for_each_entry(vlan, &ocelot->vlans, list) { 276 if (!(vlan->portmask & BIT(port))) 277 continue; 278 279 if (!(vlan->untagged & BIT(port))) 280 num_tagged++; 281 } 282 283 return num_tagged; 284 } 285 286 /* We use native VLAN when we have to mix egress-tagged VLANs with exactly 287 * _one_ egress-untagged VLAN (_the_ native VLAN) 288 */ 289 static bool ocelot_port_uses_native_vlan(struct ocelot *ocelot, int port) 290 { 291 return ocelot_port_num_tagged_vlans(ocelot, port) && 292 ocelot_port_num_untagged_vlans(ocelot, port) == 1; 293 } 294 295 static struct ocelot_bridge_vlan * 296 ocelot_port_find_native_vlan(struct ocelot *ocelot, int port) 297 { 298 struct ocelot_bridge_vlan *vlan; 299 300 list_for_each_entry(vlan, &ocelot->vlans, list) 301 if (vlan->portmask & BIT(port) && vlan->untagged & BIT(port)) 302 return vlan; 303 304 return NULL; 305 } 306 307 /* Keep in sync REW_TAG_CFG_TAG_CFG and, if applicable, 308 * REW_PORT_VLAN_CFG_PORT_VID, with the bridge VLAN table and VLAN awareness 309 * state of the port. 310 */ 311 static void ocelot_port_manage_port_tag(struct ocelot *ocelot, int port) 312 { 313 struct ocelot_port *ocelot_port = ocelot->ports[port]; 314 enum ocelot_port_tag_config tag_cfg; 315 bool uses_native_vlan = false; 316 317 if (ocelot_port->vlan_aware) { 318 uses_native_vlan = ocelot_port_uses_native_vlan(ocelot, port); 319 320 if (uses_native_vlan) 321 tag_cfg = OCELOT_PORT_TAG_NATIVE; 322 else if (ocelot_port_num_untagged_vlans(ocelot, port)) 323 tag_cfg = OCELOT_PORT_TAG_DISABLED; 324 else 325 tag_cfg = OCELOT_PORT_TAG_TRUNK; 326 } else { 327 tag_cfg = OCELOT_PORT_TAG_DISABLED; 328 } 329 330 ocelot_rmw_gix(ocelot, REW_TAG_CFG_TAG_CFG(tag_cfg), 331 REW_TAG_CFG_TAG_CFG_M, 332 REW_TAG_CFG, port); 333 334 if (uses_native_vlan) { 335 struct ocelot_bridge_vlan *native_vlan; 336 337 /* Not having a native VLAN is impossible, because 338 * ocelot_port_num_untagged_vlans has returned 1. 339 * So there is no use in checking for NULL here. 340 */ 341 native_vlan = ocelot_port_find_native_vlan(ocelot, port); 342 343 ocelot_rmw_gix(ocelot, 344 REW_PORT_VLAN_CFG_PORT_VID(native_vlan->vid), 345 REW_PORT_VLAN_CFG_PORT_VID_M, 346 REW_PORT_VLAN_CFG, port); 347 } 348 } 349 350 /* Default vlan to clasify for untagged frames (may be zero) */ 351 static void ocelot_port_set_pvid(struct ocelot *ocelot, int port, 352 const struct ocelot_bridge_vlan *pvid_vlan) 353 { 354 struct ocelot_port *ocelot_port = ocelot->ports[port]; 355 u16 pvid = OCELOT_VLAN_UNAWARE_PVID; 356 u32 val = 0; 357 358 ocelot_port->pvid_vlan = pvid_vlan; 359 360 if (ocelot_port->vlan_aware && pvid_vlan) 361 pvid = pvid_vlan->vid; 362 363 ocelot_rmw_gix(ocelot, 364 ANA_PORT_VLAN_CFG_VLAN_VID(pvid), 365 ANA_PORT_VLAN_CFG_VLAN_VID_M, 366 ANA_PORT_VLAN_CFG, port); 367 368 /* If there's no pvid, we should drop not only untagged traffic (which 369 * happens automatically), but also 802.1p traffic which gets 370 * classified to VLAN 0, but that is always in our RX filter, so it 371 * would get accepted were it not for this setting. 372 */ 373 if (!pvid_vlan && ocelot_port->vlan_aware) 374 val = ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA | 375 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA; 376 377 ocelot_rmw_gix(ocelot, val, 378 ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA | 379 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA, 380 ANA_PORT_DROP_CFG, port); 381 } 382 383 static struct ocelot_bridge_vlan *ocelot_bridge_vlan_find(struct ocelot *ocelot, 384 u16 vid) 385 { 386 struct ocelot_bridge_vlan *vlan; 387 388 list_for_each_entry(vlan, &ocelot->vlans, list) 389 if (vlan->vid == vid) 390 return vlan; 391 392 return NULL; 393 } 394 395 static int ocelot_vlan_member_add(struct ocelot *ocelot, int port, u16 vid, 396 bool untagged) 397 { 398 struct ocelot_bridge_vlan *vlan = ocelot_bridge_vlan_find(ocelot, vid); 399 unsigned long portmask; 400 int err; 401 402 if (vlan) { 403 portmask = vlan->portmask | BIT(port); 404 405 err = ocelot_vlant_set_mask(ocelot, vid, portmask); 406 if (err) 407 return err; 408 409 vlan->portmask = portmask; 410 /* Bridge VLANs can be overwritten with a different 411 * egress-tagging setting, so make sure to override an untagged 412 * with a tagged VID if that's going on. 413 */ 414 if (untagged) 415 vlan->untagged |= BIT(port); 416 else 417 vlan->untagged &= ~BIT(port); 418 419 return 0; 420 } 421 422 vlan = kzalloc(sizeof(*vlan), GFP_KERNEL); 423 if (!vlan) 424 return -ENOMEM; 425 426 portmask = BIT(port); 427 428 err = ocelot_vlant_set_mask(ocelot, vid, portmask); 429 if (err) { 430 kfree(vlan); 431 return err; 432 } 433 434 vlan->vid = vid; 435 vlan->portmask = portmask; 436 if (untagged) 437 vlan->untagged = BIT(port); 438 INIT_LIST_HEAD(&vlan->list); 439 list_add_tail(&vlan->list, &ocelot->vlans); 440 441 return 0; 442 } 443 444 static int ocelot_vlan_member_del(struct ocelot *ocelot, int port, u16 vid) 445 { 446 struct ocelot_bridge_vlan *vlan = ocelot_bridge_vlan_find(ocelot, vid); 447 unsigned long portmask; 448 int err; 449 450 if (!vlan) 451 return 0; 452 453 portmask = vlan->portmask & ~BIT(port); 454 455 err = ocelot_vlant_set_mask(ocelot, vid, portmask); 456 if (err) 457 return err; 458 459 vlan->portmask = portmask; 460 if (vlan->portmask) 461 return 0; 462 463 list_del(&vlan->list); 464 kfree(vlan); 465 466 return 0; 467 } 468 469 int ocelot_port_vlan_filtering(struct ocelot *ocelot, int port, 470 bool vlan_aware, struct netlink_ext_ack *extack) 471 { 472 struct ocelot_vcap_block *block = &ocelot->block[VCAP_IS1]; 473 struct ocelot_port *ocelot_port = ocelot->ports[port]; 474 struct ocelot_vcap_filter *filter; 475 u32 val; 476 477 list_for_each_entry(filter, &block->rules, list) { 478 if (filter->ingress_port_mask & BIT(port) && 479 filter->action.vid_replace_ena) { 480 NL_SET_ERR_MSG_MOD(extack, 481 "Cannot change VLAN state with vlan modify rules active"); 482 return -EBUSY; 483 } 484 } 485 486 ocelot_port->vlan_aware = vlan_aware; 487 488 if (vlan_aware) 489 val = ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 490 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1); 491 else 492 val = 0; 493 ocelot_rmw_gix(ocelot, val, 494 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 495 ANA_PORT_VLAN_CFG_VLAN_POP_CNT_M, 496 ANA_PORT_VLAN_CFG, port); 497 498 ocelot_port_set_pvid(ocelot, port, ocelot_port->pvid_vlan); 499 ocelot_port_manage_port_tag(ocelot, port); 500 501 return 0; 502 } 503 EXPORT_SYMBOL(ocelot_port_vlan_filtering); 504 505 int ocelot_vlan_prepare(struct ocelot *ocelot, int port, u16 vid, bool pvid, 506 bool untagged, struct netlink_ext_ack *extack) 507 { 508 if (untagged) { 509 /* We are adding an egress-tagged VLAN */ 510 if (ocelot_port_uses_native_vlan(ocelot, port)) { 511 NL_SET_ERR_MSG_MOD(extack, 512 "Port with egress-tagged VLANs cannot have more than one egress-untagged (native) VLAN"); 513 return -EBUSY; 514 } 515 } else { 516 /* We are adding an egress-tagged VLAN */ 517 if (ocelot_port_num_untagged_vlans(ocelot, port) > 1) { 518 NL_SET_ERR_MSG_MOD(extack, 519 "Port with more than one egress-untagged VLAN cannot have egress-tagged VLANs"); 520 return -EBUSY; 521 } 522 } 523 524 return 0; 525 } 526 EXPORT_SYMBOL(ocelot_vlan_prepare); 527 528 int ocelot_vlan_add(struct ocelot *ocelot, int port, u16 vid, bool pvid, 529 bool untagged) 530 { 531 int err; 532 533 err = ocelot_vlan_member_add(ocelot, port, vid, untagged); 534 if (err) 535 return err; 536 537 /* Default ingress vlan classification */ 538 if (pvid) 539 ocelot_port_set_pvid(ocelot, port, 540 ocelot_bridge_vlan_find(ocelot, vid)); 541 542 /* Untagged egress vlan clasification */ 543 ocelot_port_manage_port_tag(ocelot, port); 544 545 return 0; 546 } 547 EXPORT_SYMBOL(ocelot_vlan_add); 548 549 int ocelot_vlan_del(struct ocelot *ocelot, int port, u16 vid) 550 { 551 struct ocelot_port *ocelot_port = ocelot->ports[port]; 552 int err; 553 554 err = ocelot_vlan_member_del(ocelot, port, vid); 555 if (err) 556 return err; 557 558 /* Ingress */ 559 if (ocelot_port->pvid_vlan && ocelot_port->pvid_vlan->vid == vid) 560 ocelot_port_set_pvid(ocelot, port, NULL); 561 562 /* Egress */ 563 ocelot_port_manage_port_tag(ocelot, port); 564 565 return 0; 566 } 567 EXPORT_SYMBOL(ocelot_vlan_del); 568 569 static void ocelot_vlan_init(struct ocelot *ocelot) 570 { 571 unsigned long all_ports = GENMASK(ocelot->num_phys_ports - 1, 0); 572 u16 port, vid; 573 574 /* Clear VLAN table, by default all ports are members of all VLANs */ 575 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_CMD_INIT, 576 ANA_TABLES_VLANACCESS); 577 ocelot_vlant_wait_for_completion(ocelot); 578 579 /* Configure the port VLAN memberships */ 580 for (vid = 1; vid < VLAN_N_VID; vid++) 581 ocelot_vlant_set_mask(ocelot, vid, 0); 582 583 /* Because VLAN filtering is enabled, we need VID 0 to get untagged 584 * traffic. It is added automatically if 8021q module is loaded, but 585 * we can't rely on it since module may be not loaded. 586 */ 587 ocelot_vlant_set_mask(ocelot, OCELOT_VLAN_UNAWARE_PVID, all_ports); 588 589 /* Set vlan ingress filter mask to all ports but the CPU port by 590 * default. 591 */ 592 ocelot_write(ocelot, all_ports, ANA_VLANMASK); 593 594 for (port = 0; port < ocelot->num_phys_ports; port++) { 595 ocelot_write_gix(ocelot, 0, REW_PORT_VLAN_CFG, port); 596 ocelot_write_gix(ocelot, 0, REW_TAG_CFG, port); 597 } 598 } 599 600 static u32 ocelot_read_eq_avail(struct ocelot *ocelot, int port) 601 { 602 return ocelot_read_rix(ocelot, QSYS_SW_STATUS, port); 603 } 604 605 static int ocelot_port_flush(struct ocelot *ocelot, int port) 606 { 607 unsigned int pause_ena; 608 int err, val; 609 610 /* Disable dequeuing from the egress queues */ 611 ocelot_rmw_rix(ocelot, QSYS_PORT_MODE_DEQUEUE_DIS, 612 QSYS_PORT_MODE_DEQUEUE_DIS, 613 QSYS_PORT_MODE, port); 614 615 /* Disable flow control */ 616 ocelot_fields_read(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, &pause_ena); 617 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, 0); 618 619 /* Disable priority flow control */ 620 ocelot_fields_write(ocelot, port, 621 QSYS_SWITCH_PORT_MODE_TX_PFC_ENA, 0); 622 623 /* Wait at least the time it takes to receive a frame of maximum length 624 * at the port. 625 * Worst-case delays for 10 kilobyte jumbo frames are: 626 * 8 ms on a 10M port 627 * 800 μs on a 100M port 628 * 80 μs on a 1G port 629 * 32 μs on a 2.5G port 630 */ 631 usleep_range(8000, 10000); 632 633 /* Disable half duplex backpressure. */ 634 ocelot_rmw_rix(ocelot, 0, SYS_FRONT_PORT_MODE_HDX_MODE, 635 SYS_FRONT_PORT_MODE, port); 636 637 /* Flush the queues associated with the port. */ 638 ocelot_rmw_gix(ocelot, REW_PORT_CFG_FLUSH_ENA, REW_PORT_CFG_FLUSH_ENA, 639 REW_PORT_CFG, port); 640 641 /* Enable dequeuing from the egress queues. */ 642 ocelot_rmw_rix(ocelot, 0, QSYS_PORT_MODE_DEQUEUE_DIS, QSYS_PORT_MODE, 643 port); 644 645 /* Wait until flushing is complete. */ 646 err = read_poll_timeout(ocelot_read_eq_avail, val, !val, 647 100, 2000000, false, ocelot, port); 648 649 /* Clear flushing again. */ 650 ocelot_rmw_gix(ocelot, 0, REW_PORT_CFG_FLUSH_ENA, REW_PORT_CFG, port); 651 652 /* Re-enable flow control */ 653 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, pause_ena); 654 655 return err; 656 } 657 658 void ocelot_phylink_mac_link_down(struct ocelot *ocelot, int port, 659 unsigned int link_an_mode, 660 phy_interface_t interface, 661 unsigned long quirks) 662 { 663 struct ocelot_port *ocelot_port = ocelot->ports[port]; 664 int err; 665 666 ocelot_port->speed = SPEED_UNKNOWN; 667 668 ocelot_port_rmwl(ocelot_port, 0, DEV_MAC_ENA_CFG_RX_ENA, 669 DEV_MAC_ENA_CFG); 670 671 if (ocelot->ops->cut_through_fwd) { 672 mutex_lock(&ocelot->fwd_domain_lock); 673 ocelot->ops->cut_through_fwd(ocelot); 674 mutex_unlock(&ocelot->fwd_domain_lock); 675 } 676 677 ocelot_fields_write(ocelot, port, QSYS_SWITCH_PORT_MODE_PORT_ENA, 0); 678 679 err = ocelot_port_flush(ocelot, port); 680 if (err) 681 dev_err(ocelot->dev, "failed to flush port %d: %d\n", 682 port, err); 683 684 /* Put the port in reset. */ 685 if (interface != PHY_INTERFACE_MODE_QSGMII || 686 !(quirks & OCELOT_QUIRK_QSGMII_PORTS_MUST_BE_UP)) 687 ocelot_port_rmwl(ocelot_port, 688 DEV_CLOCK_CFG_MAC_TX_RST | 689 DEV_CLOCK_CFG_MAC_RX_RST, 690 DEV_CLOCK_CFG_MAC_TX_RST | 691 DEV_CLOCK_CFG_MAC_RX_RST, 692 DEV_CLOCK_CFG); 693 } 694 EXPORT_SYMBOL_GPL(ocelot_phylink_mac_link_down); 695 696 void ocelot_phylink_mac_link_up(struct ocelot *ocelot, int port, 697 struct phy_device *phydev, 698 unsigned int link_an_mode, 699 phy_interface_t interface, 700 int speed, int duplex, 701 bool tx_pause, bool rx_pause, 702 unsigned long quirks) 703 { 704 struct ocelot_port *ocelot_port = ocelot->ports[port]; 705 int mac_speed, mode = 0; 706 u32 mac_fc_cfg; 707 708 ocelot_port->speed = speed; 709 710 /* The MAC might be integrated in systems where the MAC speed is fixed 711 * and it's the PCS who is performing the rate adaptation, so we have 712 * to write "1000Mbps" into the LINK_SPEED field of DEV_CLOCK_CFG 713 * (which is also its default value). 714 */ 715 if ((quirks & OCELOT_QUIRK_PCS_PERFORMS_RATE_ADAPTATION) || 716 speed == SPEED_1000) { 717 mac_speed = OCELOT_SPEED_1000; 718 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA; 719 } else if (speed == SPEED_2500) { 720 mac_speed = OCELOT_SPEED_2500; 721 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA; 722 } else if (speed == SPEED_100) { 723 mac_speed = OCELOT_SPEED_100; 724 } else { 725 mac_speed = OCELOT_SPEED_10; 726 } 727 728 if (duplex == DUPLEX_FULL) 729 mode |= DEV_MAC_MODE_CFG_FDX_ENA; 730 731 ocelot_port_writel(ocelot_port, mode, DEV_MAC_MODE_CFG); 732 733 /* Take port out of reset by clearing the MAC_TX_RST, MAC_RX_RST and 734 * PORT_RST bits in DEV_CLOCK_CFG. 735 */ 736 ocelot_port_writel(ocelot_port, DEV_CLOCK_CFG_LINK_SPEED(mac_speed), 737 DEV_CLOCK_CFG); 738 739 switch (speed) { 740 case SPEED_10: 741 mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(OCELOT_SPEED_10); 742 break; 743 case SPEED_100: 744 mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(OCELOT_SPEED_100); 745 break; 746 case SPEED_1000: 747 case SPEED_2500: 748 mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(OCELOT_SPEED_1000); 749 break; 750 default: 751 dev_err(ocelot->dev, "Unsupported speed on port %d: %d\n", 752 port, speed); 753 return; 754 } 755 756 /* Handle RX pause in all cases, with 2500base-X this is used for rate 757 * adaptation. 758 */ 759 mac_fc_cfg |= SYS_MAC_FC_CFG_RX_FC_ENA; 760 761 if (tx_pause) 762 mac_fc_cfg |= SYS_MAC_FC_CFG_TX_FC_ENA | 763 SYS_MAC_FC_CFG_PAUSE_VAL_CFG(0xffff) | 764 SYS_MAC_FC_CFG_FC_LATENCY_CFG(0x7) | 765 SYS_MAC_FC_CFG_ZERO_PAUSE_ENA; 766 767 /* Flow control. Link speed is only used here to evaluate the time 768 * specification in incoming pause frames. 769 */ 770 ocelot_write_rix(ocelot, mac_fc_cfg, SYS_MAC_FC_CFG, port); 771 772 ocelot_write_rix(ocelot, 0, ANA_POL_FLOWC, port); 773 774 /* Don't attempt to send PAUSE frames on the NPI port, it's broken */ 775 if (port != ocelot->npi) 776 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, 777 tx_pause); 778 779 /* Undo the effects of ocelot_phylink_mac_link_down: 780 * enable MAC module 781 */ 782 ocelot_port_writel(ocelot_port, DEV_MAC_ENA_CFG_RX_ENA | 783 DEV_MAC_ENA_CFG_TX_ENA, DEV_MAC_ENA_CFG); 784 785 /* If the port supports cut-through forwarding, update the masks before 786 * enabling forwarding on the port. 787 */ 788 if (ocelot->ops->cut_through_fwd) { 789 mutex_lock(&ocelot->fwd_domain_lock); 790 ocelot->ops->cut_through_fwd(ocelot); 791 mutex_unlock(&ocelot->fwd_domain_lock); 792 } 793 794 /* Core: Enable port for frame transfer */ 795 ocelot_fields_write(ocelot, port, 796 QSYS_SWITCH_PORT_MODE_PORT_ENA, 1); 797 } 798 EXPORT_SYMBOL_GPL(ocelot_phylink_mac_link_up); 799 800 static int ocelot_port_add_txtstamp_skb(struct ocelot *ocelot, int port, 801 struct sk_buff *clone) 802 { 803 struct ocelot_port *ocelot_port = ocelot->ports[port]; 804 unsigned long flags; 805 806 spin_lock_irqsave(&ocelot->ts_id_lock, flags); 807 808 if (ocelot_port->ptp_skbs_in_flight == OCELOT_MAX_PTP_ID || 809 ocelot->ptp_skbs_in_flight == OCELOT_PTP_FIFO_SIZE) { 810 spin_unlock_irqrestore(&ocelot->ts_id_lock, flags); 811 return -EBUSY; 812 } 813 814 skb_shinfo(clone)->tx_flags |= SKBTX_IN_PROGRESS; 815 /* Store timestamp ID in OCELOT_SKB_CB(clone)->ts_id */ 816 OCELOT_SKB_CB(clone)->ts_id = ocelot_port->ts_id; 817 818 ocelot_port->ts_id++; 819 if (ocelot_port->ts_id == OCELOT_MAX_PTP_ID) 820 ocelot_port->ts_id = 0; 821 822 ocelot_port->ptp_skbs_in_flight++; 823 ocelot->ptp_skbs_in_flight++; 824 825 skb_queue_tail(&ocelot_port->tx_skbs, clone); 826 827 spin_unlock_irqrestore(&ocelot->ts_id_lock, flags); 828 829 return 0; 830 } 831 832 static bool ocelot_ptp_is_onestep_sync(struct sk_buff *skb, 833 unsigned int ptp_class) 834 { 835 struct ptp_header *hdr; 836 u8 msgtype, twostep; 837 838 hdr = ptp_parse_header(skb, ptp_class); 839 if (!hdr) 840 return false; 841 842 msgtype = ptp_get_msgtype(hdr, ptp_class); 843 twostep = hdr->flag_field[0] & 0x2; 844 845 if (msgtype == PTP_MSGTYPE_SYNC && twostep == 0) 846 return true; 847 848 return false; 849 } 850 851 int ocelot_port_txtstamp_request(struct ocelot *ocelot, int port, 852 struct sk_buff *skb, 853 struct sk_buff **clone) 854 { 855 struct ocelot_port *ocelot_port = ocelot->ports[port]; 856 u8 ptp_cmd = ocelot_port->ptp_cmd; 857 unsigned int ptp_class; 858 int err; 859 860 /* Don't do anything if PTP timestamping not enabled */ 861 if (!ptp_cmd) 862 return 0; 863 864 ptp_class = ptp_classify_raw(skb); 865 if (ptp_class == PTP_CLASS_NONE) 866 return -EINVAL; 867 868 /* Store ptp_cmd in OCELOT_SKB_CB(skb)->ptp_cmd */ 869 if (ptp_cmd == IFH_REW_OP_ORIGIN_PTP) { 870 if (ocelot_ptp_is_onestep_sync(skb, ptp_class)) { 871 OCELOT_SKB_CB(skb)->ptp_cmd = ptp_cmd; 872 return 0; 873 } 874 875 /* Fall back to two-step timestamping */ 876 ptp_cmd = IFH_REW_OP_TWO_STEP_PTP; 877 } 878 879 if (ptp_cmd == IFH_REW_OP_TWO_STEP_PTP) { 880 *clone = skb_clone_sk(skb); 881 if (!(*clone)) 882 return -ENOMEM; 883 884 err = ocelot_port_add_txtstamp_skb(ocelot, port, *clone); 885 if (err) 886 return err; 887 888 OCELOT_SKB_CB(skb)->ptp_cmd = ptp_cmd; 889 OCELOT_SKB_CB(*clone)->ptp_class = ptp_class; 890 } 891 892 return 0; 893 } 894 EXPORT_SYMBOL(ocelot_port_txtstamp_request); 895 896 static void ocelot_get_hwtimestamp(struct ocelot *ocelot, 897 struct timespec64 *ts) 898 { 899 unsigned long flags; 900 u32 val; 901 902 spin_lock_irqsave(&ocelot->ptp_clock_lock, flags); 903 904 /* Read current PTP time to get seconds */ 905 val = ocelot_read_rix(ocelot, PTP_PIN_CFG, TOD_ACC_PIN); 906 907 val &= ~(PTP_PIN_CFG_SYNC | PTP_PIN_CFG_ACTION_MASK | PTP_PIN_CFG_DOM); 908 val |= PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_SAVE); 909 ocelot_write_rix(ocelot, val, PTP_PIN_CFG, TOD_ACC_PIN); 910 ts->tv_sec = ocelot_read_rix(ocelot, PTP_PIN_TOD_SEC_LSB, TOD_ACC_PIN); 911 912 /* Read packet HW timestamp from FIFO */ 913 val = ocelot_read(ocelot, SYS_PTP_TXSTAMP); 914 ts->tv_nsec = SYS_PTP_TXSTAMP_PTP_TXSTAMP(val); 915 916 /* Sec has incremented since the ts was registered */ 917 if ((ts->tv_sec & 0x1) != !!(val & SYS_PTP_TXSTAMP_PTP_TXSTAMP_SEC)) 918 ts->tv_sec--; 919 920 spin_unlock_irqrestore(&ocelot->ptp_clock_lock, flags); 921 } 922 923 static bool ocelot_validate_ptp_skb(struct sk_buff *clone, u16 seqid) 924 { 925 struct ptp_header *hdr; 926 927 hdr = ptp_parse_header(clone, OCELOT_SKB_CB(clone)->ptp_class); 928 if (WARN_ON(!hdr)) 929 return false; 930 931 return seqid == ntohs(hdr->sequence_id); 932 } 933 934 void ocelot_get_txtstamp(struct ocelot *ocelot) 935 { 936 int budget = OCELOT_PTP_QUEUE_SZ; 937 938 while (budget--) { 939 struct sk_buff *skb, *skb_tmp, *skb_match = NULL; 940 struct skb_shared_hwtstamps shhwtstamps; 941 u32 val, id, seqid, txport; 942 struct ocelot_port *port; 943 struct timespec64 ts; 944 unsigned long flags; 945 946 val = ocelot_read(ocelot, SYS_PTP_STATUS); 947 948 /* Check if a timestamp can be retrieved */ 949 if (!(val & SYS_PTP_STATUS_PTP_MESS_VLD)) 950 break; 951 952 WARN_ON(val & SYS_PTP_STATUS_PTP_OVFL); 953 954 /* Retrieve the ts ID and Tx port */ 955 id = SYS_PTP_STATUS_PTP_MESS_ID_X(val); 956 txport = SYS_PTP_STATUS_PTP_MESS_TXPORT_X(val); 957 seqid = SYS_PTP_STATUS_PTP_MESS_SEQ_ID(val); 958 959 port = ocelot->ports[txport]; 960 961 spin_lock(&ocelot->ts_id_lock); 962 port->ptp_skbs_in_flight--; 963 ocelot->ptp_skbs_in_flight--; 964 spin_unlock(&ocelot->ts_id_lock); 965 966 /* Retrieve its associated skb */ 967 try_again: 968 spin_lock_irqsave(&port->tx_skbs.lock, flags); 969 970 skb_queue_walk_safe(&port->tx_skbs, skb, skb_tmp) { 971 if (OCELOT_SKB_CB(skb)->ts_id != id) 972 continue; 973 __skb_unlink(skb, &port->tx_skbs); 974 skb_match = skb; 975 break; 976 } 977 978 spin_unlock_irqrestore(&port->tx_skbs.lock, flags); 979 980 if (WARN_ON(!skb_match)) 981 continue; 982 983 if (!ocelot_validate_ptp_skb(skb_match, seqid)) { 984 dev_err_ratelimited(ocelot->dev, 985 "port %d received stale TX timestamp for seqid %d, discarding\n", 986 txport, seqid); 987 dev_kfree_skb_any(skb); 988 goto try_again; 989 } 990 991 /* Get the h/w timestamp */ 992 ocelot_get_hwtimestamp(ocelot, &ts); 993 994 /* Set the timestamp into the skb */ 995 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 996 shhwtstamps.hwtstamp = ktime_set(ts.tv_sec, ts.tv_nsec); 997 skb_complete_tx_timestamp(skb_match, &shhwtstamps); 998 999 /* Next ts */ 1000 ocelot_write(ocelot, SYS_PTP_NXT_PTP_NXT, SYS_PTP_NXT); 1001 } 1002 } 1003 EXPORT_SYMBOL(ocelot_get_txtstamp); 1004 1005 static int ocelot_rx_frame_word(struct ocelot *ocelot, u8 grp, bool ifh, 1006 u32 *rval) 1007 { 1008 u32 bytes_valid, val; 1009 1010 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 1011 if (val == XTR_NOT_READY) { 1012 if (ifh) 1013 return -EIO; 1014 1015 do { 1016 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 1017 } while (val == XTR_NOT_READY); 1018 } 1019 1020 switch (val) { 1021 case XTR_ABORT: 1022 return -EIO; 1023 case XTR_EOF_0: 1024 case XTR_EOF_1: 1025 case XTR_EOF_2: 1026 case XTR_EOF_3: 1027 case XTR_PRUNED: 1028 bytes_valid = XTR_VALID_BYTES(val); 1029 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 1030 if (val == XTR_ESCAPE) 1031 *rval = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 1032 else 1033 *rval = val; 1034 1035 return bytes_valid; 1036 case XTR_ESCAPE: 1037 *rval = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 1038 1039 return 4; 1040 default: 1041 *rval = val; 1042 1043 return 4; 1044 } 1045 } 1046 1047 static int ocelot_xtr_poll_xfh(struct ocelot *ocelot, int grp, u32 *xfh) 1048 { 1049 int i, err = 0; 1050 1051 for (i = 0; i < OCELOT_TAG_LEN / 4; i++) { 1052 err = ocelot_rx_frame_word(ocelot, grp, true, &xfh[i]); 1053 if (err != 4) 1054 return (err < 0) ? err : -EIO; 1055 } 1056 1057 return 0; 1058 } 1059 1060 void ocelot_ptp_rx_timestamp(struct ocelot *ocelot, struct sk_buff *skb, 1061 u64 timestamp) 1062 { 1063 struct skb_shared_hwtstamps *shhwtstamps; 1064 u64 tod_in_ns, full_ts_in_ns; 1065 struct timespec64 ts; 1066 1067 ocelot_ptp_gettime64(&ocelot->ptp_info, &ts); 1068 1069 tod_in_ns = ktime_set(ts.tv_sec, ts.tv_nsec); 1070 if ((tod_in_ns & 0xffffffff) < timestamp) 1071 full_ts_in_ns = (((tod_in_ns >> 32) - 1) << 32) | 1072 timestamp; 1073 else 1074 full_ts_in_ns = (tod_in_ns & GENMASK_ULL(63, 32)) | 1075 timestamp; 1076 1077 shhwtstamps = skb_hwtstamps(skb); 1078 memset(shhwtstamps, 0, sizeof(struct skb_shared_hwtstamps)); 1079 shhwtstamps->hwtstamp = full_ts_in_ns; 1080 } 1081 EXPORT_SYMBOL(ocelot_ptp_rx_timestamp); 1082 1083 int ocelot_xtr_poll_frame(struct ocelot *ocelot, int grp, struct sk_buff **nskb) 1084 { 1085 u64 timestamp, src_port, len; 1086 u32 xfh[OCELOT_TAG_LEN / 4]; 1087 struct net_device *dev; 1088 struct sk_buff *skb; 1089 int sz, buf_len; 1090 u32 val, *buf; 1091 int err; 1092 1093 err = ocelot_xtr_poll_xfh(ocelot, grp, xfh); 1094 if (err) 1095 return err; 1096 1097 ocelot_xfh_get_src_port(xfh, &src_port); 1098 ocelot_xfh_get_len(xfh, &len); 1099 ocelot_xfh_get_rew_val(xfh, ×tamp); 1100 1101 if (WARN_ON(src_port >= ocelot->num_phys_ports)) 1102 return -EINVAL; 1103 1104 dev = ocelot->ops->port_to_netdev(ocelot, src_port); 1105 if (!dev) 1106 return -EINVAL; 1107 1108 skb = netdev_alloc_skb(dev, len); 1109 if (unlikely(!skb)) { 1110 netdev_err(dev, "Unable to allocate sk_buff\n"); 1111 return -ENOMEM; 1112 } 1113 1114 buf_len = len - ETH_FCS_LEN; 1115 buf = (u32 *)skb_put(skb, buf_len); 1116 1117 len = 0; 1118 do { 1119 sz = ocelot_rx_frame_word(ocelot, grp, false, &val); 1120 if (sz < 0) { 1121 err = sz; 1122 goto out_free_skb; 1123 } 1124 *buf++ = val; 1125 len += sz; 1126 } while (len < buf_len); 1127 1128 /* Read the FCS */ 1129 sz = ocelot_rx_frame_word(ocelot, grp, false, &val); 1130 if (sz < 0) { 1131 err = sz; 1132 goto out_free_skb; 1133 } 1134 1135 /* Update the statistics if part of the FCS was read before */ 1136 len -= ETH_FCS_LEN - sz; 1137 1138 if (unlikely(dev->features & NETIF_F_RXFCS)) { 1139 buf = (u32 *)skb_put(skb, ETH_FCS_LEN); 1140 *buf = val; 1141 } 1142 1143 if (ocelot->ptp) 1144 ocelot_ptp_rx_timestamp(ocelot, skb, timestamp); 1145 1146 /* Everything we see on an interface that is in the HW bridge 1147 * has already been forwarded. 1148 */ 1149 if (ocelot->ports[src_port]->bridge) 1150 skb->offload_fwd_mark = 1; 1151 1152 skb->protocol = eth_type_trans(skb, dev); 1153 1154 *nskb = skb; 1155 1156 return 0; 1157 1158 out_free_skb: 1159 kfree_skb(skb); 1160 return err; 1161 } 1162 EXPORT_SYMBOL(ocelot_xtr_poll_frame); 1163 1164 bool ocelot_can_inject(struct ocelot *ocelot, int grp) 1165 { 1166 u32 val = ocelot_read(ocelot, QS_INJ_STATUS); 1167 1168 if (!(val & QS_INJ_STATUS_FIFO_RDY(BIT(grp)))) 1169 return false; 1170 if (val & QS_INJ_STATUS_WMARK_REACHED(BIT(grp))) 1171 return false; 1172 1173 return true; 1174 } 1175 EXPORT_SYMBOL(ocelot_can_inject); 1176 1177 void ocelot_ifh_port_set(void *ifh, int port, u32 rew_op, u32 vlan_tag) 1178 { 1179 ocelot_ifh_set_bypass(ifh, 1); 1180 ocelot_ifh_set_dest(ifh, BIT_ULL(port)); 1181 ocelot_ifh_set_tag_type(ifh, IFH_TAG_TYPE_C); 1182 if (vlan_tag) 1183 ocelot_ifh_set_vlan_tci(ifh, vlan_tag); 1184 if (rew_op) 1185 ocelot_ifh_set_rew_op(ifh, rew_op); 1186 } 1187 EXPORT_SYMBOL(ocelot_ifh_port_set); 1188 1189 void ocelot_port_inject_frame(struct ocelot *ocelot, int port, int grp, 1190 u32 rew_op, struct sk_buff *skb) 1191 { 1192 u32 ifh[OCELOT_TAG_LEN / 4] = {0}; 1193 unsigned int i, count, last; 1194 1195 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) | 1196 QS_INJ_CTRL_SOF, QS_INJ_CTRL, grp); 1197 1198 ocelot_ifh_port_set(ifh, port, rew_op, skb_vlan_tag_get(skb)); 1199 1200 for (i = 0; i < OCELOT_TAG_LEN / 4; i++) 1201 ocelot_write_rix(ocelot, ifh[i], QS_INJ_WR, grp); 1202 1203 count = DIV_ROUND_UP(skb->len, 4); 1204 last = skb->len % 4; 1205 for (i = 0; i < count; i++) 1206 ocelot_write_rix(ocelot, ((u32 *)skb->data)[i], QS_INJ_WR, grp); 1207 1208 /* Add padding */ 1209 while (i < (OCELOT_BUFFER_CELL_SZ / 4)) { 1210 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp); 1211 i++; 1212 } 1213 1214 /* Indicate EOF and valid bytes in last word */ 1215 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) | 1216 QS_INJ_CTRL_VLD_BYTES(skb->len < OCELOT_BUFFER_CELL_SZ ? 0 : last) | 1217 QS_INJ_CTRL_EOF, 1218 QS_INJ_CTRL, grp); 1219 1220 /* Add dummy CRC */ 1221 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp); 1222 skb_tx_timestamp(skb); 1223 1224 skb->dev->stats.tx_packets++; 1225 skb->dev->stats.tx_bytes += skb->len; 1226 } 1227 EXPORT_SYMBOL(ocelot_port_inject_frame); 1228 1229 void ocelot_drain_cpu_queue(struct ocelot *ocelot, int grp) 1230 { 1231 while (ocelot_read(ocelot, QS_XTR_DATA_PRESENT) & BIT(grp)) 1232 ocelot_read_rix(ocelot, QS_XTR_RD, grp); 1233 } 1234 EXPORT_SYMBOL(ocelot_drain_cpu_queue); 1235 1236 int ocelot_fdb_add(struct ocelot *ocelot, int port, 1237 const unsigned char *addr, u16 vid) 1238 { 1239 int pgid = port; 1240 1241 if (port == ocelot->npi) 1242 pgid = PGID_CPU; 1243 1244 return ocelot_mact_learn(ocelot, pgid, addr, vid, ENTRYTYPE_LOCKED); 1245 } 1246 EXPORT_SYMBOL(ocelot_fdb_add); 1247 1248 int ocelot_fdb_del(struct ocelot *ocelot, int port, 1249 const unsigned char *addr, u16 vid) 1250 { 1251 return ocelot_mact_forget(ocelot, addr, vid); 1252 } 1253 EXPORT_SYMBOL(ocelot_fdb_del); 1254 1255 int ocelot_port_fdb_do_dump(const unsigned char *addr, u16 vid, 1256 bool is_static, void *data) 1257 { 1258 struct ocelot_dump_ctx *dump = data; 1259 u32 portid = NETLINK_CB(dump->cb->skb).portid; 1260 u32 seq = dump->cb->nlh->nlmsg_seq; 1261 struct nlmsghdr *nlh; 1262 struct ndmsg *ndm; 1263 1264 if (dump->idx < dump->cb->args[2]) 1265 goto skip; 1266 1267 nlh = nlmsg_put(dump->skb, portid, seq, RTM_NEWNEIGH, 1268 sizeof(*ndm), NLM_F_MULTI); 1269 if (!nlh) 1270 return -EMSGSIZE; 1271 1272 ndm = nlmsg_data(nlh); 1273 ndm->ndm_family = AF_BRIDGE; 1274 ndm->ndm_pad1 = 0; 1275 ndm->ndm_pad2 = 0; 1276 ndm->ndm_flags = NTF_SELF; 1277 ndm->ndm_type = 0; 1278 ndm->ndm_ifindex = dump->dev->ifindex; 1279 ndm->ndm_state = is_static ? NUD_NOARP : NUD_REACHABLE; 1280 1281 if (nla_put(dump->skb, NDA_LLADDR, ETH_ALEN, addr)) 1282 goto nla_put_failure; 1283 1284 if (vid && nla_put_u16(dump->skb, NDA_VLAN, vid)) 1285 goto nla_put_failure; 1286 1287 nlmsg_end(dump->skb, nlh); 1288 1289 skip: 1290 dump->idx++; 1291 return 0; 1292 1293 nla_put_failure: 1294 nlmsg_cancel(dump->skb, nlh); 1295 return -EMSGSIZE; 1296 } 1297 EXPORT_SYMBOL(ocelot_port_fdb_do_dump); 1298 1299 /* Caller must hold &ocelot->mact_lock */ 1300 static int ocelot_mact_read(struct ocelot *ocelot, int port, int row, int col, 1301 struct ocelot_mact_entry *entry) 1302 { 1303 u32 val, dst, macl, mach; 1304 char mac[ETH_ALEN]; 1305 1306 /* Set row and column to read from */ 1307 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_M_INDEX, row); 1308 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_BUCKET, col); 1309 1310 /* Issue a read command */ 1311 ocelot_write(ocelot, 1312 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_READ), 1313 ANA_TABLES_MACACCESS); 1314 1315 if (ocelot_mact_wait_for_completion(ocelot)) 1316 return -ETIMEDOUT; 1317 1318 /* Read the entry flags */ 1319 val = ocelot_read(ocelot, ANA_TABLES_MACACCESS); 1320 if (!(val & ANA_TABLES_MACACCESS_VALID)) 1321 return -EINVAL; 1322 1323 /* If the entry read has another port configured as its destination, 1324 * do not report it. 1325 */ 1326 dst = (val & ANA_TABLES_MACACCESS_DEST_IDX_M) >> 3; 1327 if (dst != port) 1328 return -EINVAL; 1329 1330 /* Get the entry's MAC address and VLAN id */ 1331 macl = ocelot_read(ocelot, ANA_TABLES_MACLDATA); 1332 mach = ocelot_read(ocelot, ANA_TABLES_MACHDATA); 1333 1334 mac[0] = (mach >> 8) & 0xff; 1335 mac[1] = (mach >> 0) & 0xff; 1336 mac[2] = (macl >> 24) & 0xff; 1337 mac[3] = (macl >> 16) & 0xff; 1338 mac[4] = (macl >> 8) & 0xff; 1339 mac[5] = (macl >> 0) & 0xff; 1340 1341 entry->vid = (mach >> 16) & 0xfff; 1342 ether_addr_copy(entry->mac, mac); 1343 1344 return 0; 1345 } 1346 1347 int ocelot_mact_flush(struct ocelot *ocelot, int port) 1348 { 1349 int err; 1350 1351 mutex_lock(&ocelot->mact_lock); 1352 1353 /* Program ageing filter for a single port */ 1354 ocelot_write(ocelot, ANA_ANAGEFIL_PID_EN | ANA_ANAGEFIL_PID_VAL(port), 1355 ANA_ANAGEFIL); 1356 1357 /* Flushing dynamic FDB entries requires two successive age scans */ 1358 ocelot_write(ocelot, 1359 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_AGE), 1360 ANA_TABLES_MACACCESS); 1361 1362 err = ocelot_mact_wait_for_completion(ocelot); 1363 if (err) { 1364 mutex_unlock(&ocelot->mact_lock); 1365 return err; 1366 } 1367 1368 /* And second... */ 1369 ocelot_write(ocelot, 1370 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_AGE), 1371 ANA_TABLES_MACACCESS); 1372 1373 err = ocelot_mact_wait_for_completion(ocelot); 1374 1375 /* Restore ageing filter */ 1376 ocelot_write(ocelot, 0, ANA_ANAGEFIL); 1377 1378 mutex_unlock(&ocelot->mact_lock); 1379 1380 return err; 1381 } 1382 EXPORT_SYMBOL_GPL(ocelot_mact_flush); 1383 1384 int ocelot_fdb_dump(struct ocelot *ocelot, int port, 1385 dsa_fdb_dump_cb_t *cb, void *data) 1386 { 1387 int err = 0; 1388 int i, j; 1389 1390 /* We could take the lock just around ocelot_mact_read, but doing so 1391 * thousands of times in a row seems rather pointless and inefficient. 1392 */ 1393 mutex_lock(&ocelot->mact_lock); 1394 1395 /* Loop through all the mac tables entries. */ 1396 for (i = 0; i < ocelot->num_mact_rows; i++) { 1397 for (j = 0; j < 4; j++) { 1398 struct ocelot_mact_entry entry; 1399 bool is_static; 1400 1401 err = ocelot_mact_read(ocelot, port, i, j, &entry); 1402 /* If the entry is invalid (wrong port, invalid...), 1403 * skip it. 1404 */ 1405 if (err == -EINVAL) 1406 continue; 1407 else if (err) 1408 break; 1409 1410 is_static = (entry.type == ENTRYTYPE_LOCKED); 1411 1412 err = cb(entry.mac, entry.vid, is_static, data); 1413 if (err) 1414 break; 1415 } 1416 } 1417 1418 mutex_unlock(&ocelot->mact_lock); 1419 1420 return err; 1421 } 1422 EXPORT_SYMBOL(ocelot_fdb_dump); 1423 1424 static void ocelot_populate_l2_ptp_trap_key(struct ocelot_vcap_filter *trap) 1425 { 1426 trap->key_type = OCELOT_VCAP_KEY_ETYPE; 1427 *(__be16 *)trap->key.etype.etype.value = htons(ETH_P_1588); 1428 *(__be16 *)trap->key.etype.etype.mask = htons(0xffff); 1429 } 1430 1431 static void 1432 ocelot_populate_ipv4_ptp_event_trap_key(struct ocelot_vcap_filter *trap) 1433 { 1434 trap->key_type = OCELOT_VCAP_KEY_IPV4; 1435 trap->key.ipv4.proto.value[0] = IPPROTO_UDP; 1436 trap->key.ipv4.proto.mask[0] = 0xff; 1437 trap->key.ipv4.dport.value = PTP_EV_PORT; 1438 trap->key.ipv4.dport.mask = 0xffff; 1439 } 1440 1441 static void 1442 ocelot_populate_ipv6_ptp_event_trap_key(struct ocelot_vcap_filter *trap) 1443 { 1444 trap->key_type = OCELOT_VCAP_KEY_IPV6; 1445 trap->key.ipv4.proto.value[0] = IPPROTO_UDP; 1446 trap->key.ipv4.proto.mask[0] = 0xff; 1447 trap->key.ipv6.dport.value = PTP_EV_PORT; 1448 trap->key.ipv6.dport.mask = 0xffff; 1449 } 1450 1451 static void 1452 ocelot_populate_ipv4_ptp_general_trap_key(struct ocelot_vcap_filter *trap) 1453 { 1454 trap->key_type = OCELOT_VCAP_KEY_IPV4; 1455 trap->key.ipv4.proto.value[0] = IPPROTO_UDP; 1456 trap->key.ipv4.proto.mask[0] = 0xff; 1457 trap->key.ipv4.dport.value = PTP_GEN_PORT; 1458 trap->key.ipv4.dport.mask = 0xffff; 1459 } 1460 1461 static void 1462 ocelot_populate_ipv6_ptp_general_trap_key(struct ocelot_vcap_filter *trap) 1463 { 1464 trap->key_type = OCELOT_VCAP_KEY_IPV6; 1465 trap->key.ipv4.proto.value[0] = IPPROTO_UDP; 1466 trap->key.ipv4.proto.mask[0] = 0xff; 1467 trap->key.ipv6.dport.value = PTP_GEN_PORT; 1468 trap->key.ipv6.dport.mask = 0xffff; 1469 } 1470 1471 static int ocelot_trap_add(struct ocelot *ocelot, int port, 1472 unsigned long cookie, 1473 void (*populate)(struct ocelot_vcap_filter *f)) 1474 { 1475 struct ocelot_vcap_block *block_vcap_is2; 1476 struct ocelot_vcap_filter *trap; 1477 bool new = false; 1478 int err; 1479 1480 block_vcap_is2 = &ocelot->block[VCAP_IS2]; 1481 1482 trap = ocelot_vcap_block_find_filter_by_id(block_vcap_is2, cookie, 1483 false); 1484 if (!trap) { 1485 trap = kzalloc(sizeof(*trap), GFP_KERNEL); 1486 if (!trap) 1487 return -ENOMEM; 1488 1489 populate(trap); 1490 trap->prio = 1; 1491 trap->id.cookie = cookie; 1492 trap->id.tc_offload = false; 1493 trap->block_id = VCAP_IS2; 1494 trap->type = OCELOT_VCAP_FILTER_OFFLOAD; 1495 trap->lookup = 0; 1496 trap->action.cpu_copy_ena = true; 1497 trap->action.mask_mode = OCELOT_MASK_MODE_PERMIT_DENY; 1498 trap->action.port_mask = 0; 1499 new = true; 1500 } 1501 1502 trap->ingress_port_mask |= BIT(port); 1503 1504 if (new) 1505 err = ocelot_vcap_filter_add(ocelot, trap, NULL); 1506 else 1507 err = ocelot_vcap_filter_replace(ocelot, trap); 1508 if (err) { 1509 trap->ingress_port_mask &= ~BIT(port); 1510 if (!trap->ingress_port_mask) 1511 kfree(trap); 1512 return err; 1513 } 1514 1515 return 0; 1516 } 1517 1518 static int ocelot_trap_del(struct ocelot *ocelot, int port, 1519 unsigned long cookie) 1520 { 1521 struct ocelot_vcap_block *block_vcap_is2; 1522 struct ocelot_vcap_filter *trap; 1523 1524 block_vcap_is2 = &ocelot->block[VCAP_IS2]; 1525 1526 trap = ocelot_vcap_block_find_filter_by_id(block_vcap_is2, cookie, 1527 false); 1528 if (!trap) 1529 return 0; 1530 1531 trap->ingress_port_mask &= ~BIT(port); 1532 if (!trap->ingress_port_mask) 1533 return ocelot_vcap_filter_del(ocelot, trap); 1534 1535 return ocelot_vcap_filter_replace(ocelot, trap); 1536 } 1537 1538 static int ocelot_l2_ptp_trap_add(struct ocelot *ocelot, int port) 1539 { 1540 unsigned long l2_cookie = ocelot->num_phys_ports + 1; 1541 1542 return ocelot_trap_add(ocelot, port, l2_cookie, 1543 ocelot_populate_l2_ptp_trap_key); 1544 } 1545 1546 static int ocelot_l2_ptp_trap_del(struct ocelot *ocelot, int port) 1547 { 1548 unsigned long l2_cookie = ocelot->num_phys_ports + 1; 1549 1550 return ocelot_trap_del(ocelot, port, l2_cookie); 1551 } 1552 1553 static int ocelot_ipv4_ptp_trap_add(struct ocelot *ocelot, int port) 1554 { 1555 unsigned long ipv4_gen_cookie = ocelot->num_phys_ports + 2; 1556 unsigned long ipv4_ev_cookie = ocelot->num_phys_ports + 3; 1557 int err; 1558 1559 err = ocelot_trap_add(ocelot, port, ipv4_ev_cookie, 1560 ocelot_populate_ipv4_ptp_event_trap_key); 1561 if (err) 1562 return err; 1563 1564 err = ocelot_trap_add(ocelot, port, ipv4_gen_cookie, 1565 ocelot_populate_ipv4_ptp_general_trap_key); 1566 if (err) 1567 ocelot_trap_del(ocelot, port, ipv4_ev_cookie); 1568 1569 return err; 1570 } 1571 1572 static int ocelot_ipv4_ptp_trap_del(struct ocelot *ocelot, int port) 1573 { 1574 unsigned long ipv4_gen_cookie = ocelot->num_phys_ports + 2; 1575 unsigned long ipv4_ev_cookie = ocelot->num_phys_ports + 3; 1576 int err; 1577 1578 err = ocelot_trap_del(ocelot, port, ipv4_ev_cookie); 1579 err |= ocelot_trap_del(ocelot, port, ipv4_gen_cookie); 1580 return err; 1581 } 1582 1583 static int ocelot_ipv6_ptp_trap_add(struct ocelot *ocelot, int port) 1584 { 1585 unsigned long ipv6_gen_cookie = ocelot->num_phys_ports + 4; 1586 unsigned long ipv6_ev_cookie = ocelot->num_phys_ports + 5; 1587 int err; 1588 1589 err = ocelot_trap_add(ocelot, port, ipv6_ev_cookie, 1590 ocelot_populate_ipv6_ptp_event_trap_key); 1591 if (err) 1592 return err; 1593 1594 err = ocelot_trap_add(ocelot, port, ipv6_gen_cookie, 1595 ocelot_populate_ipv6_ptp_general_trap_key); 1596 if (err) 1597 ocelot_trap_del(ocelot, port, ipv6_ev_cookie); 1598 1599 return err; 1600 } 1601 1602 static int ocelot_ipv6_ptp_trap_del(struct ocelot *ocelot, int port) 1603 { 1604 unsigned long ipv6_gen_cookie = ocelot->num_phys_ports + 4; 1605 unsigned long ipv6_ev_cookie = ocelot->num_phys_ports + 5; 1606 int err; 1607 1608 err = ocelot_trap_del(ocelot, port, ipv6_ev_cookie); 1609 err |= ocelot_trap_del(ocelot, port, ipv6_gen_cookie); 1610 return err; 1611 } 1612 1613 static int ocelot_setup_ptp_traps(struct ocelot *ocelot, int port, 1614 bool l2, bool l4) 1615 { 1616 int err; 1617 1618 if (l2) 1619 err = ocelot_l2_ptp_trap_add(ocelot, port); 1620 else 1621 err = ocelot_l2_ptp_trap_del(ocelot, port); 1622 if (err) 1623 return err; 1624 1625 if (l4) { 1626 err = ocelot_ipv4_ptp_trap_add(ocelot, port); 1627 if (err) 1628 goto err_ipv4; 1629 1630 err = ocelot_ipv6_ptp_trap_add(ocelot, port); 1631 if (err) 1632 goto err_ipv6; 1633 } else { 1634 err = ocelot_ipv4_ptp_trap_del(ocelot, port); 1635 1636 err |= ocelot_ipv6_ptp_trap_del(ocelot, port); 1637 } 1638 if (err) 1639 return err; 1640 1641 return 0; 1642 1643 err_ipv6: 1644 ocelot_ipv4_ptp_trap_del(ocelot, port); 1645 err_ipv4: 1646 if (l2) 1647 ocelot_l2_ptp_trap_del(ocelot, port); 1648 return err; 1649 } 1650 1651 int ocelot_hwstamp_get(struct ocelot *ocelot, int port, struct ifreq *ifr) 1652 { 1653 return copy_to_user(ifr->ifr_data, &ocelot->hwtstamp_config, 1654 sizeof(ocelot->hwtstamp_config)) ? -EFAULT : 0; 1655 } 1656 EXPORT_SYMBOL(ocelot_hwstamp_get); 1657 1658 int ocelot_hwstamp_set(struct ocelot *ocelot, int port, struct ifreq *ifr) 1659 { 1660 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1661 bool l2 = false, l4 = false; 1662 struct hwtstamp_config cfg; 1663 int err; 1664 1665 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg))) 1666 return -EFAULT; 1667 1668 /* Tx type sanity check */ 1669 switch (cfg.tx_type) { 1670 case HWTSTAMP_TX_ON: 1671 ocelot_port->ptp_cmd = IFH_REW_OP_TWO_STEP_PTP; 1672 break; 1673 case HWTSTAMP_TX_ONESTEP_SYNC: 1674 /* IFH_REW_OP_ONE_STEP_PTP updates the correctional field, we 1675 * need to update the origin time. 1676 */ 1677 ocelot_port->ptp_cmd = IFH_REW_OP_ORIGIN_PTP; 1678 break; 1679 case HWTSTAMP_TX_OFF: 1680 ocelot_port->ptp_cmd = 0; 1681 break; 1682 default: 1683 return -ERANGE; 1684 } 1685 1686 mutex_lock(&ocelot->ptp_lock); 1687 1688 switch (cfg.rx_filter) { 1689 case HWTSTAMP_FILTER_NONE: 1690 break; 1691 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 1692 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 1693 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 1694 l4 = true; 1695 break; 1696 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 1697 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 1698 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 1699 l2 = true; 1700 break; 1701 case HWTSTAMP_FILTER_PTP_V2_EVENT: 1702 case HWTSTAMP_FILTER_PTP_V2_SYNC: 1703 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 1704 l2 = true; 1705 l4 = true; 1706 break; 1707 default: 1708 mutex_unlock(&ocelot->ptp_lock); 1709 return -ERANGE; 1710 } 1711 1712 err = ocelot_setup_ptp_traps(ocelot, port, l2, l4); 1713 if (err) { 1714 mutex_unlock(&ocelot->ptp_lock); 1715 return err; 1716 } 1717 1718 if (l2 && l4) 1719 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 1720 else if (l2) 1721 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT; 1722 else if (l4) 1723 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT; 1724 else 1725 cfg.rx_filter = HWTSTAMP_FILTER_NONE; 1726 1727 /* Commit back the result & save it */ 1728 memcpy(&ocelot->hwtstamp_config, &cfg, sizeof(cfg)); 1729 mutex_unlock(&ocelot->ptp_lock); 1730 1731 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 1732 } 1733 EXPORT_SYMBOL(ocelot_hwstamp_set); 1734 1735 void ocelot_get_strings(struct ocelot *ocelot, int port, u32 sset, u8 *data) 1736 { 1737 int i; 1738 1739 if (sset != ETH_SS_STATS) 1740 return; 1741 1742 for (i = 0; i < ocelot->num_stats; i++) 1743 memcpy(data + i * ETH_GSTRING_LEN, ocelot->stats_layout[i].name, 1744 ETH_GSTRING_LEN); 1745 } 1746 EXPORT_SYMBOL(ocelot_get_strings); 1747 1748 static void ocelot_update_stats(struct ocelot *ocelot) 1749 { 1750 int i, j; 1751 1752 mutex_lock(&ocelot->stats_lock); 1753 1754 for (i = 0; i < ocelot->num_phys_ports; i++) { 1755 /* Configure the port to read the stats from */ 1756 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(i), SYS_STAT_CFG); 1757 1758 for (j = 0; j < ocelot->num_stats; j++) { 1759 u32 val; 1760 unsigned int idx = i * ocelot->num_stats + j; 1761 1762 val = ocelot_read_rix(ocelot, SYS_COUNT_RX_OCTETS, 1763 ocelot->stats_layout[j].offset); 1764 1765 if (val < (ocelot->stats[idx] & U32_MAX)) 1766 ocelot->stats[idx] += (u64)1 << 32; 1767 1768 ocelot->stats[idx] = (ocelot->stats[idx] & 1769 ~(u64)U32_MAX) + val; 1770 } 1771 } 1772 1773 mutex_unlock(&ocelot->stats_lock); 1774 } 1775 1776 static void ocelot_check_stats_work(struct work_struct *work) 1777 { 1778 struct delayed_work *del_work = to_delayed_work(work); 1779 struct ocelot *ocelot = container_of(del_work, struct ocelot, 1780 stats_work); 1781 1782 ocelot_update_stats(ocelot); 1783 1784 queue_delayed_work(ocelot->stats_queue, &ocelot->stats_work, 1785 OCELOT_STATS_CHECK_DELAY); 1786 } 1787 1788 void ocelot_get_ethtool_stats(struct ocelot *ocelot, int port, u64 *data) 1789 { 1790 int i; 1791 1792 /* check and update now */ 1793 ocelot_update_stats(ocelot); 1794 1795 /* Copy all counters */ 1796 for (i = 0; i < ocelot->num_stats; i++) 1797 *data++ = ocelot->stats[port * ocelot->num_stats + i]; 1798 } 1799 EXPORT_SYMBOL(ocelot_get_ethtool_stats); 1800 1801 int ocelot_get_sset_count(struct ocelot *ocelot, int port, int sset) 1802 { 1803 if (sset != ETH_SS_STATS) 1804 return -EOPNOTSUPP; 1805 1806 return ocelot->num_stats; 1807 } 1808 EXPORT_SYMBOL(ocelot_get_sset_count); 1809 1810 int ocelot_get_ts_info(struct ocelot *ocelot, int port, 1811 struct ethtool_ts_info *info) 1812 { 1813 info->phc_index = ocelot->ptp_clock ? 1814 ptp_clock_index(ocelot->ptp_clock) : -1; 1815 if (info->phc_index == -1) { 1816 info->so_timestamping |= SOF_TIMESTAMPING_TX_SOFTWARE | 1817 SOF_TIMESTAMPING_RX_SOFTWARE | 1818 SOF_TIMESTAMPING_SOFTWARE; 1819 return 0; 1820 } 1821 info->so_timestamping |= SOF_TIMESTAMPING_TX_SOFTWARE | 1822 SOF_TIMESTAMPING_RX_SOFTWARE | 1823 SOF_TIMESTAMPING_SOFTWARE | 1824 SOF_TIMESTAMPING_TX_HARDWARE | 1825 SOF_TIMESTAMPING_RX_HARDWARE | 1826 SOF_TIMESTAMPING_RAW_HARDWARE; 1827 info->tx_types = BIT(HWTSTAMP_TX_OFF) | BIT(HWTSTAMP_TX_ON) | 1828 BIT(HWTSTAMP_TX_ONESTEP_SYNC); 1829 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) | 1830 BIT(HWTSTAMP_FILTER_PTP_V2_EVENT) | 1831 BIT(HWTSTAMP_FILTER_PTP_V2_L2_EVENT) | 1832 BIT(HWTSTAMP_FILTER_PTP_V2_L4_EVENT); 1833 1834 return 0; 1835 } 1836 EXPORT_SYMBOL(ocelot_get_ts_info); 1837 1838 static u32 ocelot_get_bond_mask(struct ocelot *ocelot, struct net_device *bond) 1839 { 1840 u32 mask = 0; 1841 int port; 1842 1843 for (port = 0; port < ocelot->num_phys_ports; port++) { 1844 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1845 1846 if (!ocelot_port) 1847 continue; 1848 1849 if (ocelot_port->bond == bond) 1850 mask |= BIT(port); 1851 } 1852 1853 return mask; 1854 } 1855 1856 u32 ocelot_get_bridge_fwd_mask(struct ocelot *ocelot, int src_port) 1857 { 1858 struct ocelot_port *ocelot_port = ocelot->ports[src_port]; 1859 const struct net_device *bridge; 1860 u32 mask = 0; 1861 int port; 1862 1863 if (!ocelot_port || ocelot_port->stp_state != BR_STATE_FORWARDING) 1864 return 0; 1865 1866 bridge = ocelot_port->bridge; 1867 if (!bridge) 1868 return 0; 1869 1870 for (port = 0; port < ocelot->num_phys_ports; port++) { 1871 ocelot_port = ocelot->ports[port]; 1872 1873 if (!ocelot_port) 1874 continue; 1875 1876 if (ocelot_port->stp_state == BR_STATE_FORWARDING && 1877 ocelot_port->bridge == bridge) 1878 mask |= BIT(port); 1879 } 1880 1881 return mask; 1882 } 1883 EXPORT_SYMBOL_GPL(ocelot_get_bridge_fwd_mask); 1884 1885 u32 ocelot_get_dsa_8021q_cpu_mask(struct ocelot *ocelot) 1886 { 1887 u32 mask = 0; 1888 int port; 1889 1890 for (port = 0; port < ocelot->num_phys_ports; port++) { 1891 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1892 1893 if (!ocelot_port) 1894 continue; 1895 1896 if (ocelot_port->is_dsa_8021q_cpu) 1897 mask |= BIT(port); 1898 } 1899 1900 return mask; 1901 } 1902 EXPORT_SYMBOL_GPL(ocelot_get_dsa_8021q_cpu_mask); 1903 1904 void ocelot_apply_bridge_fwd_mask(struct ocelot *ocelot, bool joining) 1905 { 1906 unsigned long cpu_fwd_mask; 1907 int port; 1908 1909 lockdep_assert_held(&ocelot->fwd_domain_lock); 1910 1911 /* If cut-through forwarding is supported, update the masks before a 1912 * port joins the forwarding domain, to avoid potential underruns if it 1913 * has the highest speed from the new domain. 1914 */ 1915 if (joining && ocelot->ops->cut_through_fwd) 1916 ocelot->ops->cut_through_fwd(ocelot); 1917 1918 /* If a DSA tag_8021q CPU exists, it needs to be included in the 1919 * regular forwarding path of the front ports regardless of whether 1920 * those are bridged or standalone. 1921 * If DSA tag_8021q is not used, this returns 0, which is fine because 1922 * the hardware-based CPU port module can be a destination for packets 1923 * even if it isn't part of PGID_SRC. 1924 */ 1925 cpu_fwd_mask = ocelot_get_dsa_8021q_cpu_mask(ocelot); 1926 1927 /* Apply FWD mask. The loop is needed to add/remove the current port as 1928 * a source for the other ports. 1929 */ 1930 for (port = 0; port < ocelot->num_phys_ports; port++) { 1931 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1932 unsigned long mask; 1933 1934 if (!ocelot_port) { 1935 /* Unused ports can't send anywhere */ 1936 mask = 0; 1937 } else if (ocelot_port->is_dsa_8021q_cpu) { 1938 /* The DSA tag_8021q CPU ports need to be able to 1939 * forward packets to all other ports except for 1940 * themselves 1941 */ 1942 mask = GENMASK(ocelot->num_phys_ports - 1, 0); 1943 mask &= ~cpu_fwd_mask; 1944 } else if (ocelot_port->bridge) { 1945 struct net_device *bond = ocelot_port->bond; 1946 1947 mask = ocelot_get_bridge_fwd_mask(ocelot, port); 1948 mask |= cpu_fwd_mask; 1949 mask &= ~BIT(port); 1950 if (bond) 1951 mask &= ~ocelot_get_bond_mask(ocelot, bond); 1952 } else { 1953 /* Standalone ports forward only to DSA tag_8021q CPU 1954 * ports (if those exist), or to the hardware CPU port 1955 * module otherwise. 1956 */ 1957 mask = cpu_fwd_mask; 1958 } 1959 1960 ocelot_write_rix(ocelot, mask, ANA_PGID_PGID, PGID_SRC + port); 1961 } 1962 1963 /* If cut-through forwarding is supported and a port is leaving, there 1964 * is a chance that cut-through was disabled on the other ports due to 1965 * the port which is leaving (it has a higher link speed). We need to 1966 * update the cut-through masks of the remaining ports no earlier than 1967 * after the port has left, to prevent underruns from happening between 1968 * the cut-through update and the forwarding domain update. 1969 */ 1970 if (!joining && ocelot->ops->cut_through_fwd) 1971 ocelot->ops->cut_through_fwd(ocelot); 1972 } 1973 EXPORT_SYMBOL(ocelot_apply_bridge_fwd_mask); 1974 1975 void ocelot_bridge_stp_state_set(struct ocelot *ocelot, int port, u8 state) 1976 { 1977 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1978 u32 learn_ena = 0; 1979 1980 mutex_lock(&ocelot->fwd_domain_lock); 1981 1982 ocelot_port->stp_state = state; 1983 1984 if ((state == BR_STATE_LEARNING || state == BR_STATE_FORWARDING) && 1985 ocelot_port->learn_ena) 1986 learn_ena = ANA_PORT_PORT_CFG_LEARN_ENA; 1987 1988 ocelot_rmw_gix(ocelot, learn_ena, ANA_PORT_PORT_CFG_LEARN_ENA, 1989 ANA_PORT_PORT_CFG, port); 1990 1991 ocelot_apply_bridge_fwd_mask(ocelot, state == BR_STATE_FORWARDING); 1992 1993 mutex_unlock(&ocelot->fwd_domain_lock); 1994 } 1995 EXPORT_SYMBOL(ocelot_bridge_stp_state_set); 1996 1997 void ocelot_set_ageing_time(struct ocelot *ocelot, unsigned int msecs) 1998 { 1999 unsigned int age_period = ANA_AUTOAGE_AGE_PERIOD(msecs / 2000); 2000 2001 /* Setting AGE_PERIOD to zero effectively disables automatic aging, 2002 * which is clearly not what our intention is. So avoid that. 2003 */ 2004 if (!age_period) 2005 age_period = 1; 2006 2007 ocelot_rmw(ocelot, age_period, ANA_AUTOAGE_AGE_PERIOD_M, ANA_AUTOAGE); 2008 } 2009 EXPORT_SYMBOL(ocelot_set_ageing_time); 2010 2011 static struct ocelot_multicast *ocelot_multicast_get(struct ocelot *ocelot, 2012 const unsigned char *addr, 2013 u16 vid) 2014 { 2015 struct ocelot_multicast *mc; 2016 2017 list_for_each_entry(mc, &ocelot->multicast, list) { 2018 if (ether_addr_equal(mc->addr, addr) && mc->vid == vid) 2019 return mc; 2020 } 2021 2022 return NULL; 2023 } 2024 2025 static enum macaccess_entry_type ocelot_classify_mdb(const unsigned char *addr) 2026 { 2027 if (addr[0] == 0x01 && addr[1] == 0x00 && addr[2] == 0x5e) 2028 return ENTRYTYPE_MACv4; 2029 if (addr[0] == 0x33 && addr[1] == 0x33) 2030 return ENTRYTYPE_MACv6; 2031 return ENTRYTYPE_LOCKED; 2032 } 2033 2034 static struct ocelot_pgid *ocelot_pgid_alloc(struct ocelot *ocelot, int index, 2035 unsigned long ports) 2036 { 2037 struct ocelot_pgid *pgid; 2038 2039 pgid = kzalloc(sizeof(*pgid), GFP_KERNEL); 2040 if (!pgid) 2041 return ERR_PTR(-ENOMEM); 2042 2043 pgid->ports = ports; 2044 pgid->index = index; 2045 refcount_set(&pgid->refcount, 1); 2046 list_add_tail(&pgid->list, &ocelot->pgids); 2047 2048 return pgid; 2049 } 2050 2051 static void ocelot_pgid_free(struct ocelot *ocelot, struct ocelot_pgid *pgid) 2052 { 2053 if (!refcount_dec_and_test(&pgid->refcount)) 2054 return; 2055 2056 list_del(&pgid->list); 2057 kfree(pgid); 2058 } 2059 2060 static struct ocelot_pgid *ocelot_mdb_get_pgid(struct ocelot *ocelot, 2061 const struct ocelot_multicast *mc) 2062 { 2063 struct ocelot_pgid *pgid; 2064 int index; 2065 2066 /* According to VSC7514 datasheet 3.9.1.5 IPv4 Multicast Entries and 2067 * 3.9.1.6 IPv6 Multicast Entries, "Instead of a lookup in the 2068 * destination mask table (PGID), the destination set is programmed as 2069 * part of the entry MAC address.", and the DEST_IDX is set to 0. 2070 */ 2071 if (mc->entry_type == ENTRYTYPE_MACv4 || 2072 mc->entry_type == ENTRYTYPE_MACv6) 2073 return ocelot_pgid_alloc(ocelot, 0, mc->ports); 2074 2075 list_for_each_entry(pgid, &ocelot->pgids, list) { 2076 /* When searching for a nonreserved multicast PGID, ignore the 2077 * dummy PGID of zero that we have for MACv4/MACv6 entries 2078 */ 2079 if (pgid->index && pgid->ports == mc->ports) { 2080 refcount_inc(&pgid->refcount); 2081 return pgid; 2082 } 2083 } 2084 2085 /* Search for a free index in the nonreserved multicast PGID area */ 2086 for_each_nonreserved_multicast_dest_pgid(ocelot, index) { 2087 bool used = false; 2088 2089 list_for_each_entry(pgid, &ocelot->pgids, list) { 2090 if (pgid->index == index) { 2091 used = true; 2092 break; 2093 } 2094 } 2095 2096 if (!used) 2097 return ocelot_pgid_alloc(ocelot, index, mc->ports); 2098 } 2099 2100 return ERR_PTR(-ENOSPC); 2101 } 2102 2103 static void ocelot_encode_ports_to_mdb(unsigned char *addr, 2104 struct ocelot_multicast *mc) 2105 { 2106 ether_addr_copy(addr, mc->addr); 2107 2108 if (mc->entry_type == ENTRYTYPE_MACv4) { 2109 addr[0] = 0; 2110 addr[1] = mc->ports >> 8; 2111 addr[2] = mc->ports & 0xff; 2112 } else if (mc->entry_type == ENTRYTYPE_MACv6) { 2113 addr[0] = mc->ports >> 8; 2114 addr[1] = mc->ports & 0xff; 2115 } 2116 } 2117 2118 int ocelot_port_mdb_add(struct ocelot *ocelot, int port, 2119 const struct switchdev_obj_port_mdb *mdb) 2120 { 2121 unsigned char addr[ETH_ALEN]; 2122 struct ocelot_multicast *mc; 2123 struct ocelot_pgid *pgid; 2124 u16 vid = mdb->vid; 2125 2126 if (port == ocelot->npi) 2127 port = ocelot->num_phys_ports; 2128 2129 mc = ocelot_multicast_get(ocelot, mdb->addr, vid); 2130 if (!mc) { 2131 /* New entry */ 2132 mc = devm_kzalloc(ocelot->dev, sizeof(*mc), GFP_KERNEL); 2133 if (!mc) 2134 return -ENOMEM; 2135 2136 mc->entry_type = ocelot_classify_mdb(mdb->addr); 2137 ether_addr_copy(mc->addr, mdb->addr); 2138 mc->vid = vid; 2139 2140 list_add_tail(&mc->list, &ocelot->multicast); 2141 } else { 2142 /* Existing entry. Clean up the current port mask from 2143 * hardware now, because we'll be modifying it. 2144 */ 2145 ocelot_pgid_free(ocelot, mc->pgid); 2146 ocelot_encode_ports_to_mdb(addr, mc); 2147 ocelot_mact_forget(ocelot, addr, vid); 2148 } 2149 2150 mc->ports |= BIT(port); 2151 2152 pgid = ocelot_mdb_get_pgid(ocelot, mc); 2153 if (IS_ERR(pgid)) { 2154 dev_err(ocelot->dev, 2155 "Cannot allocate PGID for mdb %pM vid %d\n", 2156 mc->addr, mc->vid); 2157 devm_kfree(ocelot->dev, mc); 2158 return PTR_ERR(pgid); 2159 } 2160 mc->pgid = pgid; 2161 2162 ocelot_encode_ports_to_mdb(addr, mc); 2163 2164 if (mc->entry_type != ENTRYTYPE_MACv4 && 2165 mc->entry_type != ENTRYTYPE_MACv6) 2166 ocelot_write_rix(ocelot, pgid->ports, ANA_PGID_PGID, 2167 pgid->index); 2168 2169 return ocelot_mact_learn(ocelot, pgid->index, addr, vid, 2170 mc->entry_type); 2171 } 2172 EXPORT_SYMBOL(ocelot_port_mdb_add); 2173 2174 int ocelot_port_mdb_del(struct ocelot *ocelot, int port, 2175 const struct switchdev_obj_port_mdb *mdb) 2176 { 2177 unsigned char addr[ETH_ALEN]; 2178 struct ocelot_multicast *mc; 2179 struct ocelot_pgid *pgid; 2180 u16 vid = mdb->vid; 2181 2182 if (port == ocelot->npi) 2183 port = ocelot->num_phys_ports; 2184 2185 mc = ocelot_multicast_get(ocelot, mdb->addr, vid); 2186 if (!mc) 2187 return -ENOENT; 2188 2189 ocelot_encode_ports_to_mdb(addr, mc); 2190 ocelot_mact_forget(ocelot, addr, vid); 2191 2192 ocelot_pgid_free(ocelot, mc->pgid); 2193 mc->ports &= ~BIT(port); 2194 if (!mc->ports) { 2195 list_del(&mc->list); 2196 devm_kfree(ocelot->dev, mc); 2197 return 0; 2198 } 2199 2200 /* We have a PGID with fewer ports now */ 2201 pgid = ocelot_mdb_get_pgid(ocelot, mc); 2202 if (IS_ERR(pgid)) 2203 return PTR_ERR(pgid); 2204 mc->pgid = pgid; 2205 2206 ocelot_encode_ports_to_mdb(addr, mc); 2207 2208 if (mc->entry_type != ENTRYTYPE_MACv4 && 2209 mc->entry_type != ENTRYTYPE_MACv6) 2210 ocelot_write_rix(ocelot, pgid->ports, ANA_PGID_PGID, 2211 pgid->index); 2212 2213 return ocelot_mact_learn(ocelot, pgid->index, addr, vid, 2214 mc->entry_type); 2215 } 2216 EXPORT_SYMBOL(ocelot_port_mdb_del); 2217 2218 void ocelot_port_bridge_join(struct ocelot *ocelot, int port, 2219 struct net_device *bridge) 2220 { 2221 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2222 2223 mutex_lock(&ocelot->fwd_domain_lock); 2224 2225 ocelot_port->bridge = bridge; 2226 2227 ocelot_apply_bridge_fwd_mask(ocelot, true); 2228 2229 mutex_unlock(&ocelot->fwd_domain_lock); 2230 } 2231 EXPORT_SYMBOL(ocelot_port_bridge_join); 2232 2233 void ocelot_port_bridge_leave(struct ocelot *ocelot, int port, 2234 struct net_device *bridge) 2235 { 2236 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2237 2238 mutex_lock(&ocelot->fwd_domain_lock); 2239 2240 ocelot_port->bridge = NULL; 2241 2242 ocelot_port_set_pvid(ocelot, port, NULL); 2243 ocelot_port_manage_port_tag(ocelot, port); 2244 ocelot_apply_bridge_fwd_mask(ocelot, false); 2245 2246 mutex_unlock(&ocelot->fwd_domain_lock); 2247 } 2248 EXPORT_SYMBOL(ocelot_port_bridge_leave); 2249 2250 static void ocelot_set_aggr_pgids(struct ocelot *ocelot) 2251 { 2252 unsigned long visited = GENMASK(ocelot->num_phys_ports - 1, 0); 2253 int i, port, lag; 2254 2255 /* Reset destination and aggregation PGIDS */ 2256 for_each_unicast_dest_pgid(ocelot, port) 2257 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port); 2258 2259 for_each_aggr_pgid(ocelot, i) 2260 ocelot_write_rix(ocelot, GENMASK(ocelot->num_phys_ports - 1, 0), 2261 ANA_PGID_PGID, i); 2262 2263 /* The visited ports bitmask holds the list of ports offloading any 2264 * bonding interface. Initially we mark all these ports as unvisited, 2265 * then every time we visit a port in this bitmask, we know that it is 2266 * the lowest numbered port, i.e. the one whose logical ID == physical 2267 * port ID == LAG ID. So we mark as visited all further ports in the 2268 * bitmask that are offloading the same bonding interface. This way, 2269 * we set up the aggregation PGIDs only once per bonding interface. 2270 */ 2271 for (port = 0; port < ocelot->num_phys_ports; port++) { 2272 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2273 2274 if (!ocelot_port || !ocelot_port->bond) 2275 continue; 2276 2277 visited &= ~BIT(port); 2278 } 2279 2280 /* Now, set PGIDs for each active LAG */ 2281 for (lag = 0; lag < ocelot->num_phys_ports; lag++) { 2282 struct net_device *bond = ocelot->ports[lag]->bond; 2283 int num_active_ports = 0; 2284 unsigned long bond_mask; 2285 u8 aggr_idx[16]; 2286 2287 if (!bond || (visited & BIT(lag))) 2288 continue; 2289 2290 bond_mask = ocelot_get_bond_mask(ocelot, bond); 2291 2292 for_each_set_bit(port, &bond_mask, ocelot->num_phys_ports) { 2293 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2294 2295 // Destination mask 2296 ocelot_write_rix(ocelot, bond_mask, 2297 ANA_PGID_PGID, port); 2298 2299 if (ocelot_port->lag_tx_active) 2300 aggr_idx[num_active_ports++] = port; 2301 } 2302 2303 for_each_aggr_pgid(ocelot, i) { 2304 u32 ac; 2305 2306 ac = ocelot_read_rix(ocelot, ANA_PGID_PGID, i); 2307 ac &= ~bond_mask; 2308 /* Don't do division by zero if there was no active 2309 * port. Just make all aggregation codes zero. 2310 */ 2311 if (num_active_ports) 2312 ac |= BIT(aggr_idx[i % num_active_ports]); 2313 ocelot_write_rix(ocelot, ac, ANA_PGID_PGID, i); 2314 } 2315 2316 /* Mark all ports in the same LAG as visited to avoid applying 2317 * the same config again. 2318 */ 2319 for (port = lag; port < ocelot->num_phys_ports; port++) { 2320 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2321 2322 if (!ocelot_port) 2323 continue; 2324 2325 if (ocelot_port->bond == bond) 2326 visited |= BIT(port); 2327 } 2328 } 2329 } 2330 2331 /* When offloading a bonding interface, the switch ports configured under the 2332 * same bond must have the same logical port ID, equal to the physical port ID 2333 * of the lowest numbered physical port in that bond. Otherwise, in standalone/ 2334 * bridged mode, each port has a logical port ID equal to its physical port ID. 2335 */ 2336 static void ocelot_setup_logical_port_ids(struct ocelot *ocelot) 2337 { 2338 int port; 2339 2340 for (port = 0; port < ocelot->num_phys_ports; port++) { 2341 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2342 struct net_device *bond; 2343 2344 if (!ocelot_port) 2345 continue; 2346 2347 bond = ocelot_port->bond; 2348 if (bond) { 2349 int lag = __ffs(ocelot_get_bond_mask(ocelot, bond)); 2350 2351 ocelot_rmw_gix(ocelot, 2352 ANA_PORT_PORT_CFG_PORTID_VAL(lag), 2353 ANA_PORT_PORT_CFG_PORTID_VAL_M, 2354 ANA_PORT_PORT_CFG, port); 2355 } else { 2356 ocelot_rmw_gix(ocelot, 2357 ANA_PORT_PORT_CFG_PORTID_VAL(port), 2358 ANA_PORT_PORT_CFG_PORTID_VAL_M, 2359 ANA_PORT_PORT_CFG, port); 2360 } 2361 } 2362 } 2363 2364 int ocelot_port_lag_join(struct ocelot *ocelot, int port, 2365 struct net_device *bond, 2366 struct netdev_lag_upper_info *info) 2367 { 2368 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) 2369 return -EOPNOTSUPP; 2370 2371 mutex_lock(&ocelot->fwd_domain_lock); 2372 2373 ocelot->ports[port]->bond = bond; 2374 2375 ocelot_setup_logical_port_ids(ocelot); 2376 ocelot_apply_bridge_fwd_mask(ocelot, true); 2377 ocelot_set_aggr_pgids(ocelot); 2378 2379 mutex_unlock(&ocelot->fwd_domain_lock); 2380 2381 return 0; 2382 } 2383 EXPORT_SYMBOL(ocelot_port_lag_join); 2384 2385 void ocelot_port_lag_leave(struct ocelot *ocelot, int port, 2386 struct net_device *bond) 2387 { 2388 mutex_lock(&ocelot->fwd_domain_lock); 2389 2390 ocelot->ports[port]->bond = NULL; 2391 2392 ocelot_setup_logical_port_ids(ocelot); 2393 ocelot_apply_bridge_fwd_mask(ocelot, false); 2394 ocelot_set_aggr_pgids(ocelot); 2395 2396 mutex_unlock(&ocelot->fwd_domain_lock); 2397 } 2398 EXPORT_SYMBOL(ocelot_port_lag_leave); 2399 2400 void ocelot_port_lag_change(struct ocelot *ocelot, int port, bool lag_tx_active) 2401 { 2402 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2403 2404 ocelot_port->lag_tx_active = lag_tx_active; 2405 2406 /* Rebalance the LAGs */ 2407 ocelot_set_aggr_pgids(ocelot); 2408 } 2409 EXPORT_SYMBOL(ocelot_port_lag_change); 2410 2411 /* Configure the maximum SDU (L2 payload) on RX to the value specified in @sdu. 2412 * The length of VLAN tags is accounted for automatically via DEV_MAC_TAGS_CFG. 2413 * In the special case that it's the NPI port that we're configuring, the 2414 * length of the tag and optional prefix needs to be accounted for privately, 2415 * in order to be able to sustain communication at the requested @sdu. 2416 */ 2417 void ocelot_port_set_maxlen(struct ocelot *ocelot, int port, size_t sdu) 2418 { 2419 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2420 int maxlen = sdu + ETH_HLEN + ETH_FCS_LEN; 2421 int pause_start, pause_stop; 2422 int atop, atop_tot; 2423 2424 if (port == ocelot->npi) { 2425 maxlen += OCELOT_TAG_LEN; 2426 2427 if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_SHORT) 2428 maxlen += OCELOT_SHORT_PREFIX_LEN; 2429 else if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_LONG) 2430 maxlen += OCELOT_LONG_PREFIX_LEN; 2431 } 2432 2433 ocelot_port_writel(ocelot_port, maxlen, DEV_MAC_MAXLEN_CFG); 2434 2435 /* Set Pause watermark hysteresis */ 2436 pause_start = 6 * maxlen / OCELOT_BUFFER_CELL_SZ; 2437 pause_stop = 4 * maxlen / OCELOT_BUFFER_CELL_SZ; 2438 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_START, 2439 pause_start); 2440 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_STOP, 2441 pause_stop); 2442 2443 /* Tail dropping watermarks */ 2444 atop_tot = (ocelot->packet_buffer_size - 9 * maxlen) / 2445 OCELOT_BUFFER_CELL_SZ; 2446 atop = (9 * maxlen) / OCELOT_BUFFER_CELL_SZ; 2447 ocelot_write_rix(ocelot, ocelot->ops->wm_enc(atop), SYS_ATOP, port); 2448 ocelot_write(ocelot, ocelot->ops->wm_enc(atop_tot), SYS_ATOP_TOT_CFG); 2449 } 2450 EXPORT_SYMBOL(ocelot_port_set_maxlen); 2451 2452 int ocelot_get_max_mtu(struct ocelot *ocelot, int port) 2453 { 2454 int max_mtu = 65535 - ETH_HLEN - ETH_FCS_LEN; 2455 2456 if (port == ocelot->npi) { 2457 max_mtu -= OCELOT_TAG_LEN; 2458 2459 if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_SHORT) 2460 max_mtu -= OCELOT_SHORT_PREFIX_LEN; 2461 else if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_LONG) 2462 max_mtu -= OCELOT_LONG_PREFIX_LEN; 2463 } 2464 2465 return max_mtu; 2466 } 2467 EXPORT_SYMBOL(ocelot_get_max_mtu); 2468 2469 static void ocelot_port_set_learning(struct ocelot *ocelot, int port, 2470 bool enabled) 2471 { 2472 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2473 u32 val = 0; 2474 2475 if (enabled) 2476 val = ANA_PORT_PORT_CFG_LEARN_ENA; 2477 2478 ocelot_rmw_gix(ocelot, val, ANA_PORT_PORT_CFG_LEARN_ENA, 2479 ANA_PORT_PORT_CFG, port); 2480 2481 ocelot_port->learn_ena = enabled; 2482 } 2483 2484 static void ocelot_port_set_ucast_flood(struct ocelot *ocelot, int port, 2485 bool enabled) 2486 { 2487 u32 val = 0; 2488 2489 if (enabled) 2490 val = BIT(port); 2491 2492 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_UC); 2493 } 2494 2495 static void ocelot_port_set_mcast_flood(struct ocelot *ocelot, int port, 2496 bool enabled) 2497 { 2498 u32 val = 0; 2499 2500 if (enabled) 2501 val = BIT(port); 2502 2503 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_MC); 2504 } 2505 2506 static void ocelot_port_set_bcast_flood(struct ocelot *ocelot, int port, 2507 bool enabled) 2508 { 2509 u32 val = 0; 2510 2511 if (enabled) 2512 val = BIT(port); 2513 2514 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_BC); 2515 } 2516 2517 int ocelot_port_pre_bridge_flags(struct ocelot *ocelot, int port, 2518 struct switchdev_brport_flags flags) 2519 { 2520 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | 2521 BR_BCAST_FLOOD)) 2522 return -EINVAL; 2523 2524 return 0; 2525 } 2526 EXPORT_SYMBOL(ocelot_port_pre_bridge_flags); 2527 2528 void ocelot_port_bridge_flags(struct ocelot *ocelot, int port, 2529 struct switchdev_brport_flags flags) 2530 { 2531 if (flags.mask & BR_LEARNING) 2532 ocelot_port_set_learning(ocelot, port, 2533 !!(flags.val & BR_LEARNING)); 2534 2535 if (flags.mask & BR_FLOOD) 2536 ocelot_port_set_ucast_flood(ocelot, port, 2537 !!(flags.val & BR_FLOOD)); 2538 2539 if (flags.mask & BR_MCAST_FLOOD) 2540 ocelot_port_set_mcast_flood(ocelot, port, 2541 !!(flags.val & BR_MCAST_FLOOD)); 2542 2543 if (flags.mask & BR_BCAST_FLOOD) 2544 ocelot_port_set_bcast_flood(ocelot, port, 2545 !!(flags.val & BR_BCAST_FLOOD)); 2546 } 2547 EXPORT_SYMBOL(ocelot_port_bridge_flags); 2548 2549 void ocelot_init_port(struct ocelot *ocelot, int port) 2550 { 2551 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2552 2553 skb_queue_head_init(&ocelot_port->tx_skbs); 2554 2555 /* Basic L2 initialization */ 2556 2557 /* Set MAC IFG Gaps 2558 * FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 0 2559 * !FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 5 2560 */ 2561 ocelot_port_writel(ocelot_port, DEV_MAC_IFG_CFG_TX_IFG(5), 2562 DEV_MAC_IFG_CFG); 2563 2564 /* Load seed (0) and set MAC HDX late collision */ 2565 ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67) | 2566 DEV_MAC_HDX_CFG_SEED_LOAD, 2567 DEV_MAC_HDX_CFG); 2568 mdelay(1); 2569 ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67), 2570 DEV_MAC_HDX_CFG); 2571 2572 /* Set Max Length and maximum tags allowed */ 2573 ocelot_port_set_maxlen(ocelot, port, ETH_DATA_LEN); 2574 ocelot_port_writel(ocelot_port, DEV_MAC_TAGS_CFG_TAG_ID(ETH_P_8021AD) | 2575 DEV_MAC_TAGS_CFG_VLAN_AWR_ENA | 2576 DEV_MAC_TAGS_CFG_VLAN_DBL_AWR_ENA | 2577 DEV_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA, 2578 DEV_MAC_TAGS_CFG); 2579 2580 /* Set SMAC of Pause frame (00:00:00:00:00:00) */ 2581 ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_HIGH_CFG); 2582 ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_LOW_CFG); 2583 2584 /* Enable transmission of pause frames */ 2585 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, 1); 2586 2587 /* Drop frames with multicast source address */ 2588 ocelot_rmw_gix(ocelot, ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA, 2589 ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA, 2590 ANA_PORT_DROP_CFG, port); 2591 2592 /* Set default VLAN and tag type to 8021Q. */ 2593 ocelot_rmw_gix(ocelot, REW_PORT_VLAN_CFG_PORT_TPID(ETH_P_8021Q), 2594 REW_PORT_VLAN_CFG_PORT_TPID_M, 2595 REW_PORT_VLAN_CFG, port); 2596 2597 /* Disable source address learning for standalone mode */ 2598 ocelot_port_set_learning(ocelot, port, false); 2599 2600 /* Set the port's initial logical port ID value, enable receiving 2601 * frames on it, and configure the MAC address learning type to 2602 * automatic. 2603 */ 2604 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_LEARNAUTO | 2605 ANA_PORT_PORT_CFG_RECV_ENA | 2606 ANA_PORT_PORT_CFG_PORTID_VAL(port), 2607 ANA_PORT_PORT_CFG, port); 2608 2609 /* Enable vcap lookups */ 2610 ocelot_vcap_enable(ocelot, port); 2611 } 2612 EXPORT_SYMBOL(ocelot_init_port); 2613 2614 /* Configure and enable the CPU port module, which is a set of queues 2615 * accessible through register MMIO, frame DMA or Ethernet (in case 2616 * NPI mode is used). 2617 */ 2618 static void ocelot_cpu_port_init(struct ocelot *ocelot) 2619 { 2620 int cpu = ocelot->num_phys_ports; 2621 2622 /* The unicast destination PGID for the CPU port module is unused */ 2623 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, cpu); 2624 /* Instead set up a multicast destination PGID for traffic copied to 2625 * the CPU. Whitelisted MAC addresses like the port netdevice MAC 2626 * addresses will be copied to the CPU via this PGID. 2627 */ 2628 ocelot_write_rix(ocelot, BIT(cpu), ANA_PGID_PGID, PGID_CPU); 2629 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_RECV_ENA | 2630 ANA_PORT_PORT_CFG_PORTID_VAL(cpu), 2631 ANA_PORT_PORT_CFG, cpu); 2632 2633 /* Enable CPU port module */ 2634 ocelot_fields_write(ocelot, cpu, QSYS_SWITCH_PORT_MODE_PORT_ENA, 1); 2635 /* CPU port Injection/Extraction configuration */ 2636 ocelot_fields_write(ocelot, cpu, SYS_PORT_MODE_INCL_XTR_HDR, 2637 OCELOT_TAG_PREFIX_NONE); 2638 ocelot_fields_write(ocelot, cpu, SYS_PORT_MODE_INCL_INJ_HDR, 2639 OCELOT_TAG_PREFIX_NONE); 2640 2641 /* Configure the CPU port to be VLAN aware */ 2642 ocelot_write_gix(ocelot, 2643 ANA_PORT_VLAN_CFG_VLAN_VID(OCELOT_VLAN_UNAWARE_PVID) | 2644 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 2645 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1), 2646 ANA_PORT_VLAN_CFG, cpu); 2647 } 2648 2649 static void ocelot_detect_features(struct ocelot *ocelot) 2650 { 2651 int mmgt, eq_ctrl; 2652 2653 /* For Ocelot, Felix, Seville, Serval etc, SYS:MMGT:MMGT:FREECNT holds 2654 * the number of 240-byte free memory words (aka 4-cell chunks) and not 2655 * 192 bytes as the documentation incorrectly says. 2656 */ 2657 mmgt = ocelot_read(ocelot, SYS_MMGT); 2658 ocelot->packet_buffer_size = 240 * SYS_MMGT_FREECNT(mmgt); 2659 2660 eq_ctrl = ocelot_read(ocelot, QSYS_EQ_CTRL); 2661 ocelot->num_frame_refs = QSYS_MMGT_EQ_CTRL_FP_FREE_CNT(eq_ctrl); 2662 } 2663 2664 int ocelot_init(struct ocelot *ocelot) 2665 { 2666 char queue_name[32]; 2667 int i, ret; 2668 u32 port; 2669 2670 if (ocelot->ops->reset) { 2671 ret = ocelot->ops->reset(ocelot); 2672 if (ret) { 2673 dev_err(ocelot->dev, "Switch reset failed\n"); 2674 return ret; 2675 } 2676 } 2677 2678 ocelot->stats = devm_kcalloc(ocelot->dev, 2679 ocelot->num_phys_ports * ocelot->num_stats, 2680 sizeof(u64), GFP_KERNEL); 2681 if (!ocelot->stats) 2682 return -ENOMEM; 2683 2684 mutex_init(&ocelot->stats_lock); 2685 mutex_init(&ocelot->ptp_lock); 2686 mutex_init(&ocelot->mact_lock); 2687 mutex_init(&ocelot->fwd_domain_lock); 2688 spin_lock_init(&ocelot->ptp_clock_lock); 2689 spin_lock_init(&ocelot->ts_id_lock); 2690 snprintf(queue_name, sizeof(queue_name), "%s-stats", 2691 dev_name(ocelot->dev)); 2692 ocelot->stats_queue = create_singlethread_workqueue(queue_name); 2693 if (!ocelot->stats_queue) 2694 return -ENOMEM; 2695 2696 ocelot->owq = alloc_ordered_workqueue("ocelot-owq", 0); 2697 if (!ocelot->owq) { 2698 destroy_workqueue(ocelot->stats_queue); 2699 return -ENOMEM; 2700 } 2701 2702 INIT_LIST_HEAD(&ocelot->multicast); 2703 INIT_LIST_HEAD(&ocelot->pgids); 2704 INIT_LIST_HEAD(&ocelot->vlans); 2705 ocelot_detect_features(ocelot); 2706 ocelot_mact_init(ocelot); 2707 ocelot_vlan_init(ocelot); 2708 ocelot_vcap_init(ocelot); 2709 ocelot_cpu_port_init(ocelot); 2710 2711 if (ocelot->ops->psfp_init) 2712 ocelot->ops->psfp_init(ocelot); 2713 2714 for (port = 0; port < ocelot->num_phys_ports; port++) { 2715 /* Clear all counters (5 groups) */ 2716 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(port) | 2717 SYS_STAT_CFG_STAT_CLEAR_SHOT(0x7f), 2718 SYS_STAT_CFG); 2719 } 2720 2721 /* Only use S-Tag */ 2722 ocelot_write(ocelot, ETH_P_8021AD, SYS_VLAN_ETYPE_CFG); 2723 2724 /* Aggregation mode */ 2725 ocelot_write(ocelot, ANA_AGGR_CFG_AC_SMAC_ENA | 2726 ANA_AGGR_CFG_AC_DMAC_ENA | 2727 ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA | 2728 ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA | 2729 ANA_AGGR_CFG_AC_IP6_FLOW_LBL_ENA | 2730 ANA_AGGR_CFG_AC_IP6_TCPUDP_ENA, 2731 ANA_AGGR_CFG); 2732 2733 /* Set MAC age time to default value. The entry is aged after 2734 * 2*AGE_PERIOD 2735 */ 2736 ocelot_write(ocelot, 2737 ANA_AUTOAGE_AGE_PERIOD(BR_DEFAULT_AGEING_TIME / 2 / HZ), 2738 ANA_AUTOAGE); 2739 2740 /* Disable learning for frames discarded by VLAN ingress filtering */ 2741 regmap_field_write(ocelot->regfields[ANA_ADVLEARN_VLAN_CHK], 1); 2742 2743 /* Setup frame ageing - fixed value "2 sec" - in 6.5 us units */ 2744 ocelot_write(ocelot, SYS_FRM_AGING_AGE_TX_ENA | 2745 SYS_FRM_AGING_MAX_AGE(307692), SYS_FRM_AGING); 2746 2747 /* Setup flooding PGIDs */ 2748 for (i = 0; i < ocelot->num_flooding_pgids; i++) 2749 ocelot_write_rix(ocelot, ANA_FLOODING_FLD_MULTICAST(PGID_MC) | 2750 ANA_FLOODING_FLD_BROADCAST(PGID_BC) | 2751 ANA_FLOODING_FLD_UNICAST(PGID_UC), 2752 ANA_FLOODING, i); 2753 ocelot_write(ocelot, ANA_FLOODING_IPMC_FLD_MC6_DATA(PGID_MCIPV6) | 2754 ANA_FLOODING_IPMC_FLD_MC6_CTRL(PGID_MC) | 2755 ANA_FLOODING_IPMC_FLD_MC4_DATA(PGID_MCIPV4) | 2756 ANA_FLOODING_IPMC_FLD_MC4_CTRL(PGID_MC), 2757 ANA_FLOODING_IPMC); 2758 2759 for (port = 0; port < ocelot->num_phys_ports; port++) { 2760 /* Transmit the frame to the local port. */ 2761 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port); 2762 /* Do not forward BPDU frames to the front ports. */ 2763 ocelot_write_gix(ocelot, 2764 ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA(0xffff), 2765 ANA_PORT_CPU_FWD_BPDU_CFG, 2766 port); 2767 /* Ensure bridging is disabled */ 2768 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_SRC + port); 2769 } 2770 2771 for_each_nonreserved_multicast_dest_pgid(ocelot, i) { 2772 u32 val = ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports - 1, 0)); 2773 2774 ocelot_write_rix(ocelot, val, ANA_PGID_PGID, i); 2775 } 2776 2777 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_BLACKHOLE); 2778 2779 /* Allow broadcast and unknown L2 multicast to the CPU. */ 2780 ocelot_rmw_rix(ocelot, ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)), 2781 ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)), 2782 ANA_PGID_PGID, PGID_MC); 2783 ocelot_rmw_rix(ocelot, ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)), 2784 ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)), 2785 ANA_PGID_PGID, PGID_BC); 2786 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV4); 2787 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV6); 2788 2789 /* Allow manual injection via DEVCPU_QS registers, and byte swap these 2790 * registers endianness. 2791 */ 2792 ocelot_write_rix(ocelot, QS_INJ_GRP_CFG_BYTE_SWAP | 2793 QS_INJ_GRP_CFG_MODE(1), QS_INJ_GRP_CFG, 0); 2794 ocelot_write_rix(ocelot, QS_XTR_GRP_CFG_BYTE_SWAP | 2795 QS_XTR_GRP_CFG_MODE(1), QS_XTR_GRP_CFG, 0); 2796 ocelot_write(ocelot, ANA_CPUQ_CFG_CPUQ_MIRROR(2) | 2797 ANA_CPUQ_CFG_CPUQ_LRN(2) | 2798 ANA_CPUQ_CFG_CPUQ_MAC_COPY(2) | 2799 ANA_CPUQ_CFG_CPUQ_SRC_COPY(2) | 2800 ANA_CPUQ_CFG_CPUQ_LOCKED_PORTMOVE(2) | 2801 ANA_CPUQ_CFG_CPUQ_ALLBRIDGE(6) | 2802 ANA_CPUQ_CFG_CPUQ_IPMC_CTRL(6) | 2803 ANA_CPUQ_CFG_CPUQ_IGMP(6) | 2804 ANA_CPUQ_CFG_CPUQ_MLD(6), ANA_CPUQ_CFG); 2805 for (i = 0; i < 16; i++) 2806 ocelot_write_rix(ocelot, ANA_CPUQ_8021_CFG_CPUQ_GARP_VAL(6) | 2807 ANA_CPUQ_8021_CFG_CPUQ_BPDU_VAL(6), 2808 ANA_CPUQ_8021_CFG, i); 2809 2810 INIT_DELAYED_WORK(&ocelot->stats_work, ocelot_check_stats_work); 2811 queue_delayed_work(ocelot->stats_queue, &ocelot->stats_work, 2812 OCELOT_STATS_CHECK_DELAY); 2813 2814 return 0; 2815 } 2816 EXPORT_SYMBOL(ocelot_init); 2817 2818 void ocelot_deinit(struct ocelot *ocelot) 2819 { 2820 cancel_delayed_work(&ocelot->stats_work); 2821 destroy_workqueue(ocelot->stats_queue); 2822 destroy_workqueue(ocelot->owq); 2823 mutex_destroy(&ocelot->stats_lock); 2824 } 2825 EXPORT_SYMBOL(ocelot_deinit); 2826 2827 void ocelot_deinit_port(struct ocelot *ocelot, int port) 2828 { 2829 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2830 2831 skb_queue_purge(&ocelot_port->tx_skbs); 2832 } 2833 EXPORT_SYMBOL(ocelot_deinit_port); 2834 2835 MODULE_LICENSE("Dual MIT/GPL"); 2836