1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* 3 * Microsemi Ocelot Switch driver 4 * 5 * Copyright (c) 2017 Microsemi Corporation 6 */ 7 #include <linux/etherdevice.h> 8 #include <linux/ethtool.h> 9 #include <linux/if_bridge.h> 10 #include <linux/if_ether.h> 11 #include <linux/if_vlan.h> 12 #include <linux/interrupt.h> 13 #include <linux/kernel.h> 14 #include <linux/module.h> 15 #include <linux/netdevice.h> 16 #include <linux/phy.h> 17 #include <linux/ptp_clock_kernel.h> 18 #include <linux/skbuff.h> 19 #include <linux/iopoll.h> 20 #include <net/arp.h> 21 #include <net/netevent.h> 22 #include <net/rtnetlink.h> 23 #include <net/switchdev.h> 24 #include <net/dsa.h> 25 26 #include "ocelot.h" 27 #include "ocelot_ace.h" 28 29 #define TABLE_UPDATE_SLEEP_US 10 30 #define TABLE_UPDATE_TIMEOUT_US 100000 31 32 /* MAC table entry types. 33 * ENTRYTYPE_NORMAL is subject to aging. 34 * ENTRYTYPE_LOCKED is not subject to aging. 35 * ENTRYTYPE_MACv4 is not subject to aging. For IPv4 multicast. 36 * ENTRYTYPE_MACv6 is not subject to aging. For IPv6 multicast. 37 */ 38 enum macaccess_entry_type { 39 ENTRYTYPE_NORMAL = 0, 40 ENTRYTYPE_LOCKED, 41 ENTRYTYPE_MACv4, 42 ENTRYTYPE_MACv6, 43 }; 44 45 struct ocelot_mact_entry { 46 u8 mac[ETH_ALEN]; 47 u16 vid; 48 enum macaccess_entry_type type; 49 }; 50 51 static inline u32 ocelot_mact_read_macaccess(struct ocelot *ocelot) 52 { 53 return ocelot_read(ocelot, ANA_TABLES_MACACCESS); 54 } 55 56 static inline int ocelot_mact_wait_for_completion(struct ocelot *ocelot) 57 { 58 u32 val; 59 60 return readx_poll_timeout(ocelot_mact_read_macaccess, 61 ocelot, val, 62 (val & ANA_TABLES_MACACCESS_MAC_TABLE_CMD_M) == 63 MACACCESS_CMD_IDLE, 64 TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US); 65 } 66 67 static void ocelot_mact_select(struct ocelot *ocelot, 68 const unsigned char mac[ETH_ALEN], 69 unsigned int vid) 70 { 71 u32 macl = 0, mach = 0; 72 73 /* Set the MAC address to handle and the vlan associated in a format 74 * understood by the hardware. 75 */ 76 mach |= vid << 16; 77 mach |= mac[0] << 8; 78 mach |= mac[1] << 0; 79 macl |= mac[2] << 24; 80 macl |= mac[3] << 16; 81 macl |= mac[4] << 8; 82 macl |= mac[5] << 0; 83 84 ocelot_write(ocelot, macl, ANA_TABLES_MACLDATA); 85 ocelot_write(ocelot, mach, ANA_TABLES_MACHDATA); 86 87 } 88 89 static int ocelot_mact_learn(struct ocelot *ocelot, int port, 90 const unsigned char mac[ETH_ALEN], 91 unsigned int vid, 92 enum macaccess_entry_type type) 93 { 94 ocelot_mact_select(ocelot, mac, vid); 95 96 /* Issue a write command */ 97 ocelot_write(ocelot, ANA_TABLES_MACACCESS_VALID | 98 ANA_TABLES_MACACCESS_DEST_IDX(port) | 99 ANA_TABLES_MACACCESS_ENTRYTYPE(type) | 100 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_LEARN), 101 ANA_TABLES_MACACCESS); 102 103 return ocelot_mact_wait_for_completion(ocelot); 104 } 105 106 static int ocelot_mact_forget(struct ocelot *ocelot, 107 const unsigned char mac[ETH_ALEN], 108 unsigned int vid) 109 { 110 ocelot_mact_select(ocelot, mac, vid); 111 112 /* Issue a forget command */ 113 ocelot_write(ocelot, 114 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_FORGET), 115 ANA_TABLES_MACACCESS); 116 117 return ocelot_mact_wait_for_completion(ocelot); 118 } 119 120 static void ocelot_mact_init(struct ocelot *ocelot) 121 { 122 /* Configure the learning mode entries attributes: 123 * - Do not copy the frame to the CPU extraction queues. 124 * - Use the vlan and mac_cpoy for dmac lookup. 125 */ 126 ocelot_rmw(ocelot, 0, 127 ANA_AGENCTRL_LEARN_CPU_COPY | ANA_AGENCTRL_IGNORE_DMAC_FLAGS 128 | ANA_AGENCTRL_LEARN_FWD_KILL 129 | ANA_AGENCTRL_LEARN_IGNORE_VLAN, 130 ANA_AGENCTRL); 131 132 /* Clear the MAC table */ 133 ocelot_write(ocelot, MACACCESS_CMD_INIT, ANA_TABLES_MACACCESS); 134 } 135 136 static void ocelot_vcap_enable(struct ocelot *ocelot, struct ocelot_port *port) 137 { 138 ocelot_write_gix(ocelot, ANA_PORT_VCAP_S2_CFG_S2_ENA | 139 ANA_PORT_VCAP_S2_CFG_S2_IP6_CFG(0xa), 140 ANA_PORT_VCAP_S2_CFG, port->chip_port); 141 } 142 143 static inline u32 ocelot_vlant_read_vlanaccess(struct ocelot *ocelot) 144 { 145 return ocelot_read(ocelot, ANA_TABLES_VLANACCESS); 146 } 147 148 static inline int ocelot_vlant_wait_for_completion(struct ocelot *ocelot) 149 { 150 u32 val; 151 152 return readx_poll_timeout(ocelot_vlant_read_vlanaccess, 153 ocelot, 154 val, 155 (val & ANA_TABLES_VLANACCESS_VLAN_TBL_CMD_M) == 156 ANA_TABLES_VLANACCESS_CMD_IDLE, 157 TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US); 158 } 159 160 static int ocelot_vlant_set_mask(struct ocelot *ocelot, u16 vid, u32 mask) 161 { 162 /* Select the VID to configure */ 163 ocelot_write(ocelot, ANA_TABLES_VLANTIDX_V_INDEX(vid), 164 ANA_TABLES_VLANTIDX); 165 /* Set the vlan port members mask and issue a write command */ 166 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_VLAN_PORT_MASK(mask) | 167 ANA_TABLES_VLANACCESS_CMD_WRITE, 168 ANA_TABLES_VLANACCESS); 169 170 return ocelot_vlant_wait_for_completion(ocelot); 171 } 172 173 static void ocelot_vlan_mode(struct ocelot_port *port, 174 netdev_features_t features) 175 { 176 struct ocelot *ocelot = port->ocelot; 177 u8 p = port->chip_port; 178 u32 val; 179 180 /* Filtering */ 181 val = ocelot_read(ocelot, ANA_VLANMASK); 182 if (features & NETIF_F_HW_VLAN_CTAG_FILTER) 183 val |= BIT(p); 184 else 185 val &= ~BIT(p); 186 ocelot_write(ocelot, val, ANA_VLANMASK); 187 } 188 189 static void ocelot_port_vlan_filtering(struct ocelot *ocelot, int port, 190 bool vlan_aware) 191 { 192 struct ocelot_port *ocelot_port = ocelot->ports[port]; 193 u32 val; 194 195 if (vlan_aware) 196 val = ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 197 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1); 198 else 199 val = 0; 200 ocelot_rmw_gix(ocelot, val, 201 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 202 ANA_PORT_VLAN_CFG_VLAN_POP_CNT_M, 203 ANA_PORT_VLAN_CFG, port); 204 205 if (vlan_aware && !ocelot_port->vid) 206 /* If port is vlan-aware and tagged, drop untagged and priority 207 * tagged frames. 208 */ 209 val = ANA_PORT_DROP_CFG_DROP_UNTAGGED_ENA | 210 ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA | 211 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA; 212 else 213 val = 0; 214 ocelot_rmw_gix(ocelot, val, 215 ANA_PORT_DROP_CFG_DROP_UNTAGGED_ENA | 216 ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA | 217 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA, 218 ANA_PORT_DROP_CFG, port); 219 220 if (vlan_aware) { 221 if (ocelot_port->vid) 222 /* Tag all frames except when VID == DEFAULT_VLAN */ 223 val |= REW_TAG_CFG_TAG_CFG(1); 224 else 225 /* Tag all frames */ 226 val |= REW_TAG_CFG_TAG_CFG(3); 227 } else { 228 /* Port tagging disabled. */ 229 val = REW_TAG_CFG_TAG_CFG(0); 230 } 231 ocelot_rmw_gix(ocelot, val, 232 REW_TAG_CFG_TAG_CFG_M, 233 REW_TAG_CFG, port); 234 235 ocelot_port->vlan_aware = vlan_aware; 236 } 237 238 static int ocelot_port_set_native_vlan(struct ocelot *ocelot, int port, 239 u16 vid) 240 { 241 struct ocelot_port *ocelot_port = ocelot->ports[port]; 242 243 if (ocelot_port->vid != vid) { 244 /* Always permit deleting the native VLAN (vid = 0) */ 245 if (ocelot_port->vid && vid) { 246 dev_err(ocelot->dev, 247 "Port already has a native VLAN: %d\n", 248 ocelot_port->vid); 249 return -EBUSY; 250 } 251 ocelot_port->vid = vid; 252 } 253 254 ocelot_rmw_gix(ocelot, REW_PORT_VLAN_CFG_PORT_VID(vid), 255 REW_PORT_VLAN_CFG_PORT_VID_M, 256 REW_PORT_VLAN_CFG, port); 257 258 return 0; 259 } 260 261 /* Default vlan to clasify for untagged frames (may be zero) */ 262 static void ocelot_port_set_pvid(struct ocelot *ocelot, int port, u16 pvid) 263 { 264 struct ocelot_port *ocelot_port = ocelot->ports[port]; 265 266 ocelot_rmw_gix(ocelot, 267 ANA_PORT_VLAN_CFG_VLAN_VID(pvid), 268 ANA_PORT_VLAN_CFG_VLAN_VID_M, 269 ANA_PORT_VLAN_CFG, port); 270 271 ocelot_port->pvid = pvid; 272 } 273 274 static int ocelot_vlan_add(struct ocelot *ocelot, int port, u16 vid, bool pvid, 275 bool untagged) 276 { 277 int ret; 278 279 /* Make the port a member of the VLAN */ 280 ocelot->vlan_mask[vid] |= BIT(port); 281 ret = ocelot_vlant_set_mask(ocelot, vid, ocelot->vlan_mask[vid]); 282 if (ret) 283 return ret; 284 285 /* Default ingress vlan classification */ 286 if (pvid) 287 ocelot_port_set_pvid(ocelot, port, vid); 288 289 /* Untagged egress vlan clasification */ 290 if (untagged) { 291 ret = ocelot_port_set_native_vlan(ocelot, port, vid); 292 if (ret) 293 return ret; 294 } 295 296 return 0; 297 } 298 299 static int ocelot_vlan_vid_add(struct net_device *dev, u16 vid, bool pvid, 300 bool untagged) 301 { 302 struct ocelot_port *ocelot_port = netdev_priv(dev); 303 struct ocelot *ocelot = ocelot_port->ocelot; 304 int port = ocelot_port->chip_port; 305 int ret; 306 307 ret = ocelot_vlan_add(ocelot, port, vid, pvid, untagged); 308 if (ret) 309 return ret; 310 311 /* Add the port MAC address to with the right VLAN information */ 312 ocelot_mact_learn(ocelot, PGID_CPU, dev->dev_addr, vid, 313 ENTRYTYPE_LOCKED); 314 315 return 0; 316 } 317 318 static int ocelot_vlan_del(struct ocelot *ocelot, int port, u16 vid) 319 { 320 struct ocelot_port *ocelot_port = ocelot->ports[port]; 321 int ret; 322 323 /* Stop the port from being a member of the vlan */ 324 ocelot->vlan_mask[vid] &= ~BIT(port); 325 ret = ocelot_vlant_set_mask(ocelot, vid, ocelot->vlan_mask[vid]); 326 if (ret) 327 return ret; 328 329 /* Ingress */ 330 if (ocelot_port->pvid == vid) 331 ocelot_port_set_pvid(ocelot, port, 0); 332 333 /* Egress */ 334 if (ocelot_port->vid == vid) 335 ocelot_port_set_native_vlan(ocelot, port, 0); 336 337 return 0; 338 } 339 340 static int ocelot_vlan_vid_del(struct net_device *dev, u16 vid) 341 { 342 struct ocelot_port *ocelot_port = netdev_priv(dev); 343 struct ocelot *ocelot = ocelot_port->ocelot; 344 int port = ocelot_port->chip_port; 345 int ret; 346 347 /* 8021q removes VID 0 on module unload for all interfaces 348 * with VLAN filtering feature. We need to keep it to receive 349 * untagged traffic. 350 */ 351 if (vid == 0) 352 return 0; 353 354 ret = ocelot_vlan_del(ocelot, port, vid); 355 if (ret) 356 return ret; 357 358 /* Del the port MAC address to with the right VLAN information */ 359 ocelot_mact_forget(ocelot, dev->dev_addr, vid); 360 361 return 0; 362 } 363 364 static void ocelot_vlan_init(struct ocelot *ocelot) 365 { 366 u16 port, vid; 367 368 /* Clear VLAN table, by default all ports are members of all VLANs */ 369 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_CMD_INIT, 370 ANA_TABLES_VLANACCESS); 371 ocelot_vlant_wait_for_completion(ocelot); 372 373 /* Configure the port VLAN memberships */ 374 for (vid = 1; vid < VLAN_N_VID; vid++) { 375 ocelot->vlan_mask[vid] = 0; 376 ocelot_vlant_set_mask(ocelot, vid, ocelot->vlan_mask[vid]); 377 } 378 379 /* Because VLAN filtering is enabled, we need VID 0 to get untagged 380 * traffic. It is added automatically if 8021q module is loaded, but 381 * we can't rely on it since module may be not loaded. 382 */ 383 ocelot->vlan_mask[0] = GENMASK(ocelot->num_phys_ports - 1, 0); 384 ocelot_vlant_set_mask(ocelot, 0, ocelot->vlan_mask[0]); 385 386 /* Configure the CPU port to be VLAN aware */ 387 ocelot_write_gix(ocelot, ANA_PORT_VLAN_CFG_VLAN_VID(0) | 388 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 389 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1), 390 ANA_PORT_VLAN_CFG, ocelot->num_phys_ports); 391 392 /* Set vlan ingress filter mask to all ports but the CPU port by 393 * default. 394 */ 395 ocelot_write(ocelot, GENMASK(9, 0), ANA_VLANMASK); 396 397 for (port = 0; port < ocelot->num_phys_ports; port++) { 398 ocelot_write_gix(ocelot, 0, REW_PORT_VLAN_CFG, port); 399 ocelot_write_gix(ocelot, 0, REW_TAG_CFG, port); 400 } 401 } 402 403 /* Watermark encode 404 * Bit 8: Unit; 0:1, 1:16 405 * Bit 7-0: Value to be multiplied with unit 406 */ 407 static u16 ocelot_wm_enc(u16 value) 408 { 409 if (value >= BIT(8)) 410 return BIT(8) | (value / 16); 411 412 return value; 413 } 414 415 static void ocelot_port_adjust_link(struct net_device *dev) 416 { 417 struct ocelot_port *port = netdev_priv(dev); 418 struct ocelot *ocelot = port->ocelot; 419 u8 p = port->chip_port; 420 int speed, atop_wm, mode = 0; 421 422 switch (dev->phydev->speed) { 423 case SPEED_10: 424 speed = OCELOT_SPEED_10; 425 break; 426 case SPEED_100: 427 speed = OCELOT_SPEED_100; 428 break; 429 case SPEED_1000: 430 speed = OCELOT_SPEED_1000; 431 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA; 432 break; 433 case SPEED_2500: 434 speed = OCELOT_SPEED_2500; 435 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA; 436 break; 437 default: 438 netdev_err(dev, "Unsupported PHY speed: %d\n", 439 dev->phydev->speed); 440 return; 441 } 442 443 phy_print_status(dev->phydev); 444 445 if (!dev->phydev->link) 446 return; 447 448 /* Only full duplex supported for now */ 449 ocelot_port_writel(port, DEV_MAC_MODE_CFG_FDX_ENA | 450 mode, DEV_MAC_MODE_CFG); 451 452 /* Set MAC IFG Gaps 453 * FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 0 454 * !FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 5 455 */ 456 ocelot_port_writel(port, DEV_MAC_IFG_CFG_TX_IFG(5), DEV_MAC_IFG_CFG); 457 458 /* Load seed (0) and set MAC HDX late collision */ 459 ocelot_port_writel(port, DEV_MAC_HDX_CFG_LATE_COL_POS(67) | 460 DEV_MAC_HDX_CFG_SEED_LOAD, 461 DEV_MAC_HDX_CFG); 462 mdelay(1); 463 ocelot_port_writel(port, DEV_MAC_HDX_CFG_LATE_COL_POS(67), 464 DEV_MAC_HDX_CFG); 465 466 /* Disable HDX fast control */ 467 ocelot_port_writel(port, DEV_PORT_MISC_HDX_FAST_DIS, DEV_PORT_MISC); 468 469 /* SGMII only for now */ 470 ocelot_port_writel(port, PCS1G_MODE_CFG_SGMII_MODE_ENA, PCS1G_MODE_CFG); 471 ocelot_port_writel(port, PCS1G_SD_CFG_SD_SEL, PCS1G_SD_CFG); 472 473 /* Enable PCS */ 474 ocelot_port_writel(port, PCS1G_CFG_PCS_ENA, PCS1G_CFG); 475 476 /* No aneg on SGMII */ 477 ocelot_port_writel(port, 0, PCS1G_ANEG_CFG); 478 479 /* No loopback */ 480 ocelot_port_writel(port, 0, PCS1G_LB_CFG); 481 482 /* Set Max Length and maximum tags allowed */ 483 ocelot_port_writel(port, VLAN_ETH_FRAME_LEN, DEV_MAC_MAXLEN_CFG); 484 ocelot_port_writel(port, DEV_MAC_TAGS_CFG_TAG_ID(ETH_P_8021AD) | 485 DEV_MAC_TAGS_CFG_VLAN_AWR_ENA | 486 DEV_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA, 487 DEV_MAC_TAGS_CFG); 488 489 /* Enable MAC module */ 490 ocelot_port_writel(port, DEV_MAC_ENA_CFG_RX_ENA | 491 DEV_MAC_ENA_CFG_TX_ENA, DEV_MAC_ENA_CFG); 492 493 /* Take MAC, Port, Phy (intern) and PCS (SGMII/Serdes) clock out of 494 * reset */ 495 ocelot_port_writel(port, DEV_CLOCK_CFG_LINK_SPEED(speed), 496 DEV_CLOCK_CFG); 497 498 /* Set SMAC of Pause frame (00:00:00:00:00:00) */ 499 ocelot_port_writel(port, 0, DEV_MAC_FC_MAC_HIGH_CFG); 500 ocelot_port_writel(port, 0, DEV_MAC_FC_MAC_LOW_CFG); 501 502 /* No PFC */ 503 ocelot_write_gix(ocelot, ANA_PFC_PFC_CFG_FC_LINK_SPEED(speed), 504 ANA_PFC_PFC_CFG, p); 505 506 /* Set Pause WM hysteresis 507 * 152 = 6 * VLAN_ETH_FRAME_LEN / OCELOT_BUFFER_CELL_SZ 508 * 101 = 4 * VLAN_ETH_FRAME_LEN / OCELOT_BUFFER_CELL_SZ 509 */ 510 ocelot_write_rix(ocelot, SYS_PAUSE_CFG_PAUSE_ENA | 511 SYS_PAUSE_CFG_PAUSE_STOP(101) | 512 SYS_PAUSE_CFG_PAUSE_START(152), SYS_PAUSE_CFG, p); 513 514 /* Core: Enable port for frame transfer */ 515 ocelot_write_rix(ocelot, QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE | 516 QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG(1) | 517 QSYS_SWITCH_PORT_MODE_PORT_ENA, 518 QSYS_SWITCH_PORT_MODE, p); 519 520 /* Flow control */ 521 ocelot_write_rix(ocelot, SYS_MAC_FC_CFG_PAUSE_VAL_CFG(0xffff) | 522 SYS_MAC_FC_CFG_RX_FC_ENA | SYS_MAC_FC_CFG_TX_FC_ENA | 523 SYS_MAC_FC_CFG_ZERO_PAUSE_ENA | 524 SYS_MAC_FC_CFG_FC_LATENCY_CFG(0x7) | 525 SYS_MAC_FC_CFG_FC_LINK_SPEED(speed), 526 SYS_MAC_FC_CFG, p); 527 ocelot_write_rix(ocelot, 0, ANA_POL_FLOWC, p); 528 529 /* Tail dropping watermark */ 530 atop_wm = (ocelot->shared_queue_sz - 9 * VLAN_ETH_FRAME_LEN) / OCELOT_BUFFER_CELL_SZ; 531 ocelot_write_rix(ocelot, ocelot_wm_enc(9 * VLAN_ETH_FRAME_LEN), 532 SYS_ATOP, p); 533 ocelot_write(ocelot, ocelot_wm_enc(atop_wm), SYS_ATOP_TOT_CFG); 534 } 535 536 static int ocelot_port_open(struct net_device *dev) 537 { 538 struct ocelot_port *port = netdev_priv(dev); 539 struct ocelot *ocelot = port->ocelot; 540 int err; 541 542 /* Enable receiving frames on the port, and activate auto-learning of 543 * MAC addresses. 544 */ 545 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_LEARNAUTO | 546 ANA_PORT_PORT_CFG_RECV_ENA | 547 ANA_PORT_PORT_CFG_PORTID_VAL(port->chip_port), 548 ANA_PORT_PORT_CFG, port->chip_port); 549 550 if (port->serdes) { 551 err = phy_set_mode_ext(port->serdes, PHY_MODE_ETHERNET, 552 port->phy_mode); 553 if (err) { 554 netdev_err(dev, "Could not set mode of SerDes\n"); 555 return err; 556 } 557 } 558 559 err = phy_connect_direct(dev, port->phy, &ocelot_port_adjust_link, 560 port->phy_mode); 561 if (err) { 562 netdev_err(dev, "Could not attach to PHY\n"); 563 return err; 564 } 565 566 dev->phydev = port->phy; 567 568 phy_attached_info(port->phy); 569 phy_start(port->phy); 570 return 0; 571 } 572 573 static int ocelot_port_stop(struct net_device *dev) 574 { 575 struct ocelot_port *port = netdev_priv(dev); 576 577 phy_disconnect(port->phy); 578 579 dev->phydev = NULL; 580 581 ocelot_port_writel(port, 0, DEV_MAC_ENA_CFG); 582 ocelot_rmw_rix(port->ocelot, 0, QSYS_SWITCH_PORT_MODE_PORT_ENA, 583 QSYS_SWITCH_PORT_MODE, port->chip_port); 584 return 0; 585 } 586 587 /* Generate the IFH for frame injection 588 * 589 * The IFH is a 128bit-value 590 * bit 127: bypass the analyzer processing 591 * bit 56-67: destination mask 592 * bit 28-29: pop_cnt: 3 disables all rewriting of the frame 593 * bit 20-27: cpu extraction queue mask 594 * bit 16: tag type 0: C-tag, 1: S-tag 595 * bit 0-11: VID 596 */ 597 static int ocelot_gen_ifh(u32 *ifh, struct frame_info *info) 598 { 599 ifh[0] = IFH_INJ_BYPASS | ((0x1ff & info->rew_op) << 21); 600 ifh[1] = (0xf00 & info->port) >> 8; 601 ifh[2] = (0xff & info->port) << 24; 602 ifh[3] = (info->tag_type << 16) | info->vid; 603 604 return 0; 605 } 606 607 static int ocelot_port_xmit(struct sk_buff *skb, struct net_device *dev) 608 { 609 struct skb_shared_info *shinfo = skb_shinfo(skb); 610 struct ocelot_port *port = netdev_priv(dev); 611 struct ocelot *ocelot = port->ocelot; 612 u32 val, ifh[IFH_LEN]; 613 struct frame_info info = {}; 614 u8 grp = 0; /* Send everything on CPU group 0 */ 615 unsigned int i, count, last; 616 617 val = ocelot_read(ocelot, QS_INJ_STATUS); 618 if (!(val & QS_INJ_STATUS_FIFO_RDY(BIT(grp))) || 619 (val & QS_INJ_STATUS_WMARK_REACHED(BIT(grp)))) 620 return NETDEV_TX_BUSY; 621 622 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) | 623 QS_INJ_CTRL_SOF, QS_INJ_CTRL, grp); 624 625 info.port = BIT(port->chip_port); 626 info.tag_type = IFH_TAG_TYPE_C; 627 info.vid = skb_vlan_tag_get(skb); 628 629 /* Check if timestamping is needed */ 630 if (ocelot->ptp && shinfo->tx_flags & SKBTX_HW_TSTAMP) { 631 info.rew_op = port->ptp_cmd; 632 if (port->ptp_cmd == IFH_REW_OP_TWO_STEP_PTP) 633 info.rew_op |= (port->ts_id % 4) << 3; 634 } 635 636 ocelot_gen_ifh(ifh, &info); 637 638 for (i = 0; i < IFH_LEN; i++) 639 ocelot_write_rix(ocelot, (__force u32)cpu_to_be32(ifh[i]), 640 QS_INJ_WR, grp); 641 642 count = (skb->len + 3) / 4; 643 last = skb->len % 4; 644 for (i = 0; i < count; i++) { 645 ocelot_write_rix(ocelot, ((u32 *)skb->data)[i], QS_INJ_WR, grp); 646 } 647 648 /* Add padding */ 649 while (i < (OCELOT_BUFFER_CELL_SZ / 4)) { 650 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp); 651 i++; 652 } 653 654 /* Indicate EOF and valid bytes in last word */ 655 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) | 656 QS_INJ_CTRL_VLD_BYTES(skb->len < OCELOT_BUFFER_CELL_SZ ? 0 : last) | 657 QS_INJ_CTRL_EOF, 658 QS_INJ_CTRL, grp); 659 660 /* Add dummy CRC */ 661 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp); 662 skb_tx_timestamp(skb); 663 664 dev->stats.tx_packets++; 665 dev->stats.tx_bytes += skb->len; 666 667 if (ocelot->ptp && shinfo->tx_flags & SKBTX_HW_TSTAMP && 668 port->ptp_cmd == IFH_REW_OP_TWO_STEP_PTP) { 669 struct ocelot_skb *oskb = 670 kzalloc(sizeof(struct ocelot_skb), GFP_ATOMIC); 671 672 if (unlikely(!oskb)) 673 goto out; 674 675 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 676 677 oskb->skb = skb; 678 oskb->id = port->ts_id % 4; 679 port->ts_id++; 680 681 list_add_tail(&oskb->head, &port->skbs); 682 683 return NETDEV_TX_OK; 684 } 685 686 out: 687 dev_kfree_skb_any(skb); 688 return NETDEV_TX_OK; 689 } 690 691 void ocelot_get_hwtimestamp(struct ocelot *ocelot, struct timespec64 *ts) 692 { 693 unsigned long flags; 694 u32 val; 695 696 spin_lock_irqsave(&ocelot->ptp_clock_lock, flags); 697 698 /* Read current PTP time to get seconds */ 699 val = ocelot_read_rix(ocelot, PTP_PIN_CFG, TOD_ACC_PIN); 700 701 val &= ~(PTP_PIN_CFG_SYNC | PTP_PIN_CFG_ACTION_MASK | PTP_PIN_CFG_DOM); 702 val |= PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_SAVE); 703 ocelot_write_rix(ocelot, val, PTP_PIN_CFG, TOD_ACC_PIN); 704 ts->tv_sec = ocelot_read_rix(ocelot, PTP_PIN_TOD_SEC_LSB, TOD_ACC_PIN); 705 706 /* Read packet HW timestamp from FIFO */ 707 val = ocelot_read(ocelot, SYS_PTP_TXSTAMP); 708 ts->tv_nsec = SYS_PTP_TXSTAMP_PTP_TXSTAMP(val); 709 710 /* Sec has incremented since the ts was registered */ 711 if ((ts->tv_sec & 0x1) != !!(val & SYS_PTP_TXSTAMP_PTP_TXSTAMP_SEC)) 712 ts->tv_sec--; 713 714 spin_unlock_irqrestore(&ocelot->ptp_clock_lock, flags); 715 } 716 EXPORT_SYMBOL(ocelot_get_hwtimestamp); 717 718 static int ocelot_mc_unsync(struct net_device *dev, const unsigned char *addr) 719 { 720 struct ocelot_port *port = netdev_priv(dev); 721 722 return ocelot_mact_forget(port->ocelot, addr, port->pvid); 723 } 724 725 static int ocelot_mc_sync(struct net_device *dev, const unsigned char *addr) 726 { 727 struct ocelot_port *port = netdev_priv(dev); 728 729 return ocelot_mact_learn(port->ocelot, PGID_CPU, addr, port->pvid, 730 ENTRYTYPE_LOCKED); 731 } 732 733 static void ocelot_set_rx_mode(struct net_device *dev) 734 { 735 struct ocelot_port *port = netdev_priv(dev); 736 struct ocelot *ocelot = port->ocelot; 737 int i; 738 u32 val; 739 740 /* This doesn't handle promiscuous mode because the bridge core is 741 * setting IFF_PROMISC on all slave interfaces and all frames would be 742 * forwarded to the CPU port. 743 */ 744 val = GENMASK(ocelot->num_phys_ports - 1, 0); 745 for (i = ocelot->num_phys_ports + 1; i < PGID_CPU; i++) 746 ocelot_write_rix(ocelot, val, ANA_PGID_PGID, i); 747 748 __dev_mc_sync(dev, ocelot_mc_sync, ocelot_mc_unsync); 749 } 750 751 static int ocelot_port_get_phys_port_name(struct net_device *dev, 752 char *buf, size_t len) 753 { 754 struct ocelot_port *port = netdev_priv(dev); 755 int ret; 756 757 ret = snprintf(buf, len, "p%d", port->chip_port); 758 if (ret >= len) 759 return -EINVAL; 760 761 return 0; 762 } 763 764 static int ocelot_port_set_mac_address(struct net_device *dev, void *p) 765 { 766 struct ocelot_port *port = netdev_priv(dev); 767 struct ocelot *ocelot = port->ocelot; 768 const struct sockaddr *addr = p; 769 770 /* Learn the new net device MAC address in the mac table. */ 771 ocelot_mact_learn(ocelot, PGID_CPU, addr->sa_data, port->pvid, 772 ENTRYTYPE_LOCKED); 773 /* Then forget the previous one. */ 774 ocelot_mact_forget(ocelot, dev->dev_addr, port->pvid); 775 776 ether_addr_copy(dev->dev_addr, addr->sa_data); 777 return 0; 778 } 779 780 static void ocelot_get_stats64(struct net_device *dev, 781 struct rtnl_link_stats64 *stats) 782 { 783 struct ocelot_port *port = netdev_priv(dev); 784 struct ocelot *ocelot = port->ocelot; 785 786 /* Configure the port to read the stats from */ 787 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(port->chip_port), 788 SYS_STAT_CFG); 789 790 /* Get Rx stats */ 791 stats->rx_bytes = ocelot_read(ocelot, SYS_COUNT_RX_OCTETS); 792 stats->rx_packets = ocelot_read(ocelot, SYS_COUNT_RX_SHORTS) + 793 ocelot_read(ocelot, SYS_COUNT_RX_FRAGMENTS) + 794 ocelot_read(ocelot, SYS_COUNT_RX_JABBERS) + 795 ocelot_read(ocelot, SYS_COUNT_RX_LONGS) + 796 ocelot_read(ocelot, SYS_COUNT_RX_64) + 797 ocelot_read(ocelot, SYS_COUNT_RX_65_127) + 798 ocelot_read(ocelot, SYS_COUNT_RX_128_255) + 799 ocelot_read(ocelot, SYS_COUNT_RX_256_1023) + 800 ocelot_read(ocelot, SYS_COUNT_RX_1024_1526) + 801 ocelot_read(ocelot, SYS_COUNT_RX_1527_MAX); 802 stats->multicast = ocelot_read(ocelot, SYS_COUNT_RX_MULTICAST); 803 stats->rx_dropped = dev->stats.rx_dropped; 804 805 /* Get Tx stats */ 806 stats->tx_bytes = ocelot_read(ocelot, SYS_COUNT_TX_OCTETS); 807 stats->tx_packets = ocelot_read(ocelot, SYS_COUNT_TX_64) + 808 ocelot_read(ocelot, SYS_COUNT_TX_65_127) + 809 ocelot_read(ocelot, SYS_COUNT_TX_128_511) + 810 ocelot_read(ocelot, SYS_COUNT_TX_512_1023) + 811 ocelot_read(ocelot, SYS_COUNT_TX_1024_1526) + 812 ocelot_read(ocelot, SYS_COUNT_TX_1527_MAX); 813 stats->tx_dropped = ocelot_read(ocelot, SYS_COUNT_TX_DROPS) + 814 ocelot_read(ocelot, SYS_COUNT_TX_AGING); 815 stats->collisions = ocelot_read(ocelot, SYS_COUNT_TX_COLLISION); 816 } 817 818 static int ocelot_fdb_add(struct ocelot *ocelot, int port, 819 const unsigned char *addr, u16 vid) 820 { 821 struct ocelot_port *ocelot_port = ocelot->ports[port]; 822 823 if (!vid) { 824 if (!ocelot_port->vlan_aware) 825 /* If the bridge is not VLAN aware and no VID was 826 * provided, set it to pvid to ensure the MAC entry 827 * matches incoming untagged packets 828 */ 829 vid = ocelot_port->pvid; 830 else 831 /* If the bridge is VLAN aware a VID must be provided as 832 * otherwise the learnt entry wouldn't match any frame. 833 */ 834 return -EINVAL; 835 } 836 837 return ocelot_mact_learn(ocelot, port, addr, vid, ENTRYTYPE_LOCKED); 838 } 839 840 static int ocelot_port_fdb_add(struct ndmsg *ndm, struct nlattr *tb[], 841 struct net_device *dev, 842 const unsigned char *addr, 843 u16 vid, u16 flags, 844 struct netlink_ext_ack *extack) 845 { 846 struct ocelot_port *ocelot_port = netdev_priv(dev); 847 struct ocelot *ocelot = ocelot_port->ocelot; 848 849 return ocelot_fdb_add(ocelot, ocelot_port->chip_port, addr, vid); 850 } 851 852 static int ocelot_fdb_del(struct ocelot *ocelot, int port, 853 const unsigned char *addr, u16 vid) 854 { 855 return ocelot_mact_forget(ocelot, addr, vid); 856 } 857 858 static int ocelot_port_fdb_del(struct ndmsg *ndm, struct nlattr *tb[], 859 struct net_device *dev, 860 const unsigned char *addr, u16 vid) 861 { 862 struct ocelot_port *ocelot_port = netdev_priv(dev); 863 struct ocelot *ocelot = ocelot_port->ocelot; 864 865 return ocelot_fdb_del(ocelot, ocelot_port->chip_port, addr, vid); 866 } 867 868 struct ocelot_dump_ctx { 869 struct net_device *dev; 870 struct sk_buff *skb; 871 struct netlink_callback *cb; 872 int idx; 873 }; 874 875 static int ocelot_port_fdb_do_dump(const unsigned char *addr, u16 vid, 876 bool is_static, void *data) 877 { 878 struct ocelot_dump_ctx *dump = data; 879 u32 portid = NETLINK_CB(dump->cb->skb).portid; 880 u32 seq = dump->cb->nlh->nlmsg_seq; 881 struct nlmsghdr *nlh; 882 struct ndmsg *ndm; 883 884 if (dump->idx < dump->cb->args[2]) 885 goto skip; 886 887 nlh = nlmsg_put(dump->skb, portid, seq, RTM_NEWNEIGH, 888 sizeof(*ndm), NLM_F_MULTI); 889 if (!nlh) 890 return -EMSGSIZE; 891 892 ndm = nlmsg_data(nlh); 893 ndm->ndm_family = AF_BRIDGE; 894 ndm->ndm_pad1 = 0; 895 ndm->ndm_pad2 = 0; 896 ndm->ndm_flags = NTF_SELF; 897 ndm->ndm_type = 0; 898 ndm->ndm_ifindex = dump->dev->ifindex; 899 ndm->ndm_state = is_static ? NUD_NOARP : NUD_REACHABLE; 900 901 if (nla_put(dump->skb, NDA_LLADDR, ETH_ALEN, addr)) 902 goto nla_put_failure; 903 904 if (vid && nla_put_u16(dump->skb, NDA_VLAN, vid)) 905 goto nla_put_failure; 906 907 nlmsg_end(dump->skb, nlh); 908 909 skip: 910 dump->idx++; 911 return 0; 912 913 nla_put_failure: 914 nlmsg_cancel(dump->skb, nlh); 915 return -EMSGSIZE; 916 } 917 918 static int ocelot_mact_read(struct ocelot *ocelot, int port, int row, int col, 919 struct ocelot_mact_entry *entry) 920 { 921 u32 val, dst, macl, mach; 922 char mac[ETH_ALEN]; 923 924 /* Set row and column to read from */ 925 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_M_INDEX, row); 926 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_BUCKET, col); 927 928 /* Issue a read command */ 929 ocelot_write(ocelot, 930 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_READ), 931 ANA_TABLES_MACACCESS); 932 933 if (ocelot_mact_wait_for_completion(ocelot)) 934 return -ETIMEDOUT; 935 936 /* Read the entry flags */ 937 val = ocelot_read(ocelot, ANA_TABLES_MACACCESS); 938 if (!(val & ANA_TABLES_MACACCESS_VALID)) 939 return -EINVAL; 940 941 /* If the entry read has another port configured as its destination, 942 * do not report it. 943 */ 944 dst = (val & ANA_TABLES_MACACCESS_DEST_IDX_M) >> 3; 945 if (dst != port) 946 return -EINVAL; 947 948 /* Get the entry's MAC address and VLAN id */ 949 macl = ocelot_read(ocelot, ANA_TABLES_MACLDATA); 950 mach = ocelot_read(ocelot, ANA_TABLES_MACHDATA); 951 952 mac[0] = (mach >> 8) & 0xff; 953 mac[1] = (mach >> 0) & 0xff; 954 mac[2] = (macl >> 24) & 0xff; 955 mac[3] = (macl >> 16) & 0xff; 956 mac[4] = (macl >> 8) & 0xff; 957 mac[5] = (macl >> 0) & 0xff; 958 959 entry->vid = (mach >> 16) & 0xfff; 960 ether_addr_copy(entry->mac, mac); 961 962 return 0; 963 } 964 965 static int ocelot_fdb_dump(struct ocelot *ocelot, int port, 966 dsa_fdb_dump_cb_t *cb, void *data) 967 { 968 int i, j; 969 970 /* Loop through all the mac tables entries. There are 1024 rows of 4 971 * entries. 972 */ 973 for (i = 0; i < 1024; i++) { 974 for (j = 0; j < 4; j++) { 975 struct ocelot_mact_entry entry; 976 bool is_static; 977 int ret; 978 979 ret = ocelot_mact_read(ocelot, port, i, j, &entry); 980 /* If the entry is invalid (wrong port, invalid...), 981 * skip it. 982 */ 983 if (ret == -EINVAL) 984 continue; 985 else if (ret) 986 return ret; 987 988 is_static = (entry.type == ENTRYTYPE_LOCKED); 989 990 ret = cb(entry.mac, entry.vid, is_static, data); 991 if (ret) 992 return ret; 993 } 994 } 995 996 return 0; 997 } 998 999 static int ocelot_port_fdb_dump(struct sk_buff *skb, 1000 struct netlink_callback *cb, 1001 struct net_device *dev, 1002 struct net_device *filter_dev, int *idx) 1003 { 1004 struct ocelot_port *ocelot_port = netdev_priv(dev); 1005 struct ocelot *ocelot = ocelot_port->ocelot; 1006 struct ocelot_dump_ctx dump = { 1007 .dev = dev, 1008 .skb = skb, 1009 .cb = cb, 1010 .idx = *idx, 1011 }; 1012 int ret; 1013 1014 ret = ocelot_fdb_dump(ocelot, ocelot_port->chip_port, 1015 ocelot_port_fdb_do_dump, &dump); 1016 1017 *idx = dump.idx; 1018 1019 return ret; 1020 } 1021 1022 static int ocelot_vlan_rx_add_vid(struct net_device *dev, __be16 proto, 1023 u16 vid) 1024 { 1025 return ocelot_vlan_vid_add(dev, vid, false, false); 1026 } 1027 1028 static int ocelot_vlan_rx_kill_vid(struct net_device *dev, __be16 proto, 1029 u16 vid) 1030 { 1031 return ocelot_vlan_vid_del(dev, vid); 1032 } 1033 1034 static int ocelot_set_features(struct net_device *dev, 1035 netdev_features_t features) 1036 { 1037 struct ocelot_port *port = netdev_priv(dev); 1038 netdev_features_t changed = dev->features ^ features; 1039 1040 if ((dev->features & NETIF_F_HW_TC) > (features & NETIF_F_HW_TC) && 1041 port->tc.offload_cnt) { 1042 netdev_err(dev, 1043 "Cannot disable HW TC offload while offloads active\n"); 1044 return -EBUSY; 1045 } 1046 1047 if (changed & NETIF_F_HW_VLAN_CTAG_FILTER) 1048 ocelot_vlan_mode(port, features); 1049 1050 return 0; 1051 } 1052 1053 static int ocelot_get_port_parent_id(struct net_device *dev, 1054 struct netdev_phys_item_id *ppid) 1055 { 1056 struct ocelot_port *ocelot_port = netdev_priv(dev); 1057 struct ocelot *ocelot = ocelot_port->ocelot; 1058 1059 ppid->id_len = sizeof(ocelot->base_mac); 1060 memcpy(&ppid->id, &ocelot->base_mac, ppid->id_len); 1061 1062 return 0; 1063 } 1064 1065 static int ocelot_hwstamp_get(struct ocelot *ocelot, int port, 1066 struct ifreq *ifr) 1067 { 1068 return copy_to_user(ifr->ifr_data, &ocelot->hwtstamp_config, 1069 sizeof(ocelot->hwtstamp_config)) ? -EFAULT : 0; 1070 } 1071 1072 static int ocelot_hwstamp_set(struct ocelot *ocelot, int port, 1073 struct ifreq *ifr) 1074 { 1075 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1076 struct hwtstamp_config cfg; 1077 1078 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg))) 1079 return -EFAULT; 1080 1081 /* reserved for future extensions */ 1082 if (cfg.flags) 1083 return -EINVAL; 1084 1085 /* Tx type sanity check */ 1086 switch (cfg.tx_type) { 1087 case HWTSTAMP_TX_ON: 1088 ocelot_port->ptp_cmd = IFH_REW_OP_TWO_STEP_PTP; 1089 break; 1090 case HWTSTAMP_TX_ONESTEP_SYNC: 1091 /* IFH_REW_OP_ONE_STEP_PTP updates the correctional field, we 1092 * need to update the origin time. 1093 */ 1094 ocelot_port->ptp_cmd = IFH_REW_OP_ORIGIN_PTP; 1095 break; 1096 case HWTSTAMP_TX_OFF: 1097 ocelot_port->ptp_cmd = 0; 1098 break; 1099 default: 1100 return -ERANGE; 1101 } 1102 1103 mutex_lock(&ocelot->ptp_lock); 1104 1105 switch (cfg.rx_filter) { 1106 case HWTSTAMP_FILTER_NONE: 1107 break; 1108 case HWTSTAMP_FILTER_ALL: 1109 case HWTSTAMP_FILTER_SOME: 1110 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 1111 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 1112 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 1113 case HWTSTAMP_FILTER_NTP_ALL: 1114 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 1115 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 1116 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 1117 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 1118 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 1119 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 1120 case HWTSTAMP_FILTER_PTP_V2_EVENT: 1121 case HWTSTAMP_FILTER_PTP_V2_SYNC: 1122 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 1123 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 1124 break; 1125 default: 1126 mutex_unlock(&ocelot->ptp_lock); 1127 return -ERANGE; 1128 } 1129 1130 /* Commit back the result & save it */ 1131 memcpy(&ocelot->hwtstamp_config, &cfg, sizeof(cfg)); 1132 mutex_unlock(&ocelot->ptp_lock); 1133 1134 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 1135 } 1136 1137 static int ocelot_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 1138 { 1139 struct ocelot_port *ocelot_port = netdev_priv(dev); 1140 struct ocelot *ocelot = ocelot_port->ocelot; 1141 int port = ocelot_port->chip_port; 1142 1143 /* The function is only used for PTP operations for now */ 1144 if (!ocelot->ptp) 1145 return -EOPNOTSUPP; 1146 1147 switch (cmd) { 1148 case SIOCSHWTSTAMP: 1149 return ocelot_hwstamp_set(ocelot, port, ifr); 1150 case SIOCGHWTSTAMP: 1151 return ocelot_hwstamp_get(ocelot, port, ifr); 1152 default: 1153 return -EOPNOTSUPP; 1154 } 1155 } 1156 1157 static const struct net_device_ops ocelot_port_netdev_ops = { 1158 .ndo_open = ocelot_port_open, 1159 .ndo_stop = ocelot_port_stop, 1160 .ndo_start_xmit = ocelot_port_xmit, 1161 .ndo_set_rx_mode = ocelot_set_rx_mode, 1162 .ndo_get_phys_port_name = ocelot_port_get_phys_port_name, 1163 .ndo_set_mac_address = ocelot_port_set_mac_address, 1164 .ndo_get_stats64 = ocelot_get_stats64, 1165 .ndo_fdb_add = ocelot_port_fdb_add, 1166 .ndo_fdb_del = ocelot_port_fdb_del, 1167 .ndo_fdb_dump = ocelot_port_fdb_dump, 1168 .ndo_vlan_rx_add_vid = ocelot_vlan_rx_add_vid, 1169 .ndo_vlan_rx_kill_vid = ocelot_vlan_rx_kill_vid, 1170 .ndo_set_features = ocelot_set_features, 1171 .ndo_get_port_parent_id = ocelot_get_port_parent_id, 1172 .ndo_setup_tc = ocelot_setup_tc, 1173 .ndo_do_ioctl = ocelot_ioctl, 1174 }; 1175 1176 static void ocelot_get_strings(struct net_device *netdev, u32 sset, u8 *data) 1177 { 1178 struct ocelot_port *port = netdev_priv(netdev); 1179 struct ocelot *ocelot = port->ocelot; 1180 int i; 1181 1182 if (sset != ETH_SS_STATS) 1183 return; 1184 1185 for (i = 0; i < ocelot->num_stats; i++) 1186 memcpy(data + i * ETH_GSTRING_LEN, ocelot->stats_layout[i].name, 1187 ETH_GSTRING_LEN); 1188 } 1189 1190 static void ocelot_update_stats(struct ocelot *ocelot) 1191 { 1192 int i, j; 1193 1194 mutex_lock(&ocelot->stats_lock); 1195 1196 for (i = 0; i < ocelot->num_phys_ports; i++) { 1197 /* Configure the port to read the stats from */ 1198 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(i), SYS_STAT_CFG); 1199 1200 for (j = 0; j < ocelot->num_stats; j++) { 1201 u32 val; 1202 unsigned int idx = i * ocelot->num_stats + j; 1203 1204 val = ocelot_read_rix(ocelot, SYS_COUNT_RX_OCTETS, 1205 ocelot->stats_layout[j].offset); 1206 1207 if (val < (ocelot->stats[idx] & U32_MAX)) 1208 ocelot->stats[idx] += (u64)1 << 32; 1209 1210 ocelot->stats[idx] = (ocelot->stats[idx] & 1211 ~(u64)U32_MAX) + val; 1212 } 1213 } 1214 1215 mutex_unlock(&ocelot->stats_lock); 1216 } 1217 1218 static void ocelot_check_stats_work(struct work_struct *work) 1219 { 1220 struct delayed_work *del_work = to_delayed_work(work); 1221 struct ocelot *ocelot = container_of(del_work, struct ocelot, 1222 stats_work); 1223 1224 ocelot_update_stats(ocelot); 1225 1226 queue_delayed_work(ocelot->stats_queue, &ocelot->stats_work, 1227 OCELOT_STATS_CHECK_DELAY); 1228 } 1229 1230 static void ocelot_get_ethtool_stats(struct net_device *dev, 1231 struct ethtool_stats *stats, u64 *data) 1232 { 1233 struct ocelot_port *port = netdev_priv(dev); 1234 struct ocelot *ocelot = port->ocelot; 1235 int i; 1236 1237 /* check and update now */ 1238 ocelot_update_stats(ocelot); 1239 1240 /* Copy all counters */ 1241 for (i = 0; i < ocelot->num_stats; i++) 1242 *data++ = ocelot->stats[port->chip_port * ocelot->num_stats + i]; 1243 } 1244 1245 static int ocelot_get_sset_count(struct net_device *dev, int sset) 1246 { 1247 struct ocelot_port *port = netdev_priv(dev); 1248 struct ocelot *ocelot = port->ocelot; 1249 1250 if (sset != ETH_SS_STATS) 1251 return -EOPNOTSUPP; 1252 return ocelot->num_stats; 1253 } 1254 1255 static int ocelot_get_ts_info(struct net_device *dev, 1256 struct ethtool_ts_info *info) 1257 { 1258 struct ocelot_port *ocelot_port = netdev_priv(dev); 1259 struct ocelot *ocelot = ocelot_port->ocelot; 1260 1261 if (!ocelot->ptp) 1262 return ethtool_op_get_ts_info(dev, info); 1263 1264 info->phc_index = ocelot->ptp_clock ? 1265 ptp_clock_index(ocelot->ptp_clock) : -1; 1266 info->so_timestamping |= SOF_TIMESTAMPING_TX_SOFTWARE | 1267 SOF_TIMESTAMPING_RX_SOFTWARE | 1268 SOF_TIMESTAMPING_SOFTWARE | 1269 SOF_TIMESTAMPING_TX_HARDWARE | 1270 SOF_TIMESTAMPING_RX_HARDWARE | 1271 SOF_TIMESTAMPING_RAW_HARDWARE; 1272 info->tx_types = BIT(HWTSTAMP_TX_OFF) | BIT(HWTSTAMP_TX_ON) | 1273 BIT(HWTSTAMP_TX_ONESTEP_SYNC); 1274 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) | BIT(HWTSTAMP_FILTER_ALL); 1275 1276 return 0; 1277 } 1278 1279 static const struct ethtool_ops ocelot_ethtool_ops = { 1280 .get_strings = ocelot_get_strings, 1281 .get_ethtool_stats = ocelot_get_ethtool_stats, 1282 .get_sset_count = ocelot_get_sset_count, 1283 .get_link_ksettings = phy_ethtool_get_link_ksettings, 1284 .set_link_ksettings = phy_ethtool_set_link_ksettings, 1285 .get_ts_info = ocelot_get_ts_info, 1286 }; 1287 1288 static void ocelot_bridge_stp_state_set(struct ocelot *ocelot, int port, 1289 u8 state) 1290 { 1291 u32 port_cfg; 1292 int p, i; 1293 1294 if (!(BIT(port) & ocelot->bridge_mask)) 1295 return; 1296 1297 port_cfg = ocelot_read_gix(ocelot, ANA_PORT_PORT_CFG, port); 1298 1299 switch (state) { 1300 case BR_STATE_FORWARDING: 1301 ocelot->bridge_fwd_mask |= BIT(port); 1302 /* Fallthrough */ 1303 case BR_STATE_LEARNING: 1304 port_cfg |= ANA_PORT_PORT_CFG_LEARN_ENA; 1305 break; 1306 1307 default: 1308 port_cfg &= ~ANA_PORT_PORT_CFG_LEARN_ENA; 1309 ocelot->bridge_fwd_mask &= ~BIT(port); 1310 break; 1311 } 1312 1313 ocelot_write_gix(ocelot, port_cfg, ANA_PORT_PORT_CFG, port); 1314 1315 /* Apply FWD mask. The loop is needed to add/remove the current port as 1316 * a source for the other ports. 1317 */ 1318 for (p = 0; p < ocelot->num_phys_ports; p++) { 1319 if (ocelot->bridge_fwd_mask & BIT(p)) { 1320 unsigned long mask = ocelot->bridge_fwd_mask & ~BIT(p); 1321 1322 for (i = 0; i < ocelot->num_phys_ports; i++) { 1323 unsigned long bond_mask = ocelot->lags[i]; 1324 1325 if (!bond_mask) 1326 continue; 1327 1328 if (bond_mask & BIT(p)) { 1329 mask &= ~bond_mask; 1330 break; 1331 } 1332 } 1333 1334 ocelot_write_rix(ocelot, 1335 BIT(ocelot->num_phys_ports) | mask, 1336 ANA_PGID_PGID, PGID_SRC + p); 1337 } else { 1338 /* Only the CPU port, this is compatible with link 1339 * aggregation. 1340 */ 1341 ocelot_write_rix(ocelot, 1342 BIT(ocelot->num_phys_ports), 1343 ANA_PGID_PGID, PGID_SRC + p); 1344 } 1345 } 1346 } 1347 1348 static void ocelot_port_attr_stp_state_set(struct ocelot *ocelot, int port, 1349 struct switchdev_trans *trans, 1350 u8 state) 1351 { 1352 if (switchdev_trans_ph_prepare(trans)) 1353 return; 1354 1355 ocelot_bridge_stp_state_set(ocelot, port, state); 1356 } 1357 1358 static void ocelot_set_ageing_time(struct ocelot *ocelot, unsigned int msecs) 1359 { 1360 ocelot_write(ocelot, ANA_AUTOAGE_AGE_PERIOD(msecs / 2), 1361 ANA_AUTOAGE); 1362 } 1363 1364 static void ocelot_port_attr_ageing_set(struct ocelot *ocelot, int port, 1365 unsigned long ageing_clock_t) 1366 { 1367 unsigned long ageing_jiffies = clock_t_to_jiffies(ageing_clock_t); 1368 u32 ageing_time = jiffies_to_msecs(ageing_jiffies) / 1000; 1369 1370 ocelot_set_ageing_time(ocelot, ageing_time); 1371 } 1372 1373 static void ocelot_port_attr_mc_set(struct ocelot *ocelot, int port, bool mc) 1374 { 1375 u32 cpu_fwd_mcast = ANA_PORT_CPU_FWD_CFG_CPU_IGMP_REDIR_ENA | 1376 ANA_PORT_CPU_FWD_CFG_CPU_MLD_REDIR_ENA | 1377 ANA_PORT_CPU_FWD_CFG_CPU_IPMC_CTRL_COPY_ENA; 1378 u32 val = 0; 1379 1380 if (mc) 1381 val = cpu_fwd_mcast; 1382 1383 ocelot_rmw_gix(ocelot, val, cpu_fwd_mcast, 1384 ANA_PORT_CPU_FWD_CFG, port); 1385 } 1386 1387 static int ocelot_port_attr_set(struct net_device *dev, 1388 const struct switchdev_attr *attr, 1389 struct switchdev_trans *trans) 1390 { 1391 struct ocelot_port *ocelot_port = netdev_priv(dev); 1392 struct ocelot *ocelot = ocelot_port->ocelot; 1393 int port = ocelot_port->chip_port; 1394 int err = 0; 1395 1396 switch (attr->id) { 1397 case SWITCHDEV_ATTR_ID_PORT_STP_STATE: 1398 ocelot_port_attr_stp_state_set(ocelot, port, trans, 1399 attr->u.stp_state); 1400 break; 1401 case SWITCHDEV_ATTR_ID_BRIDGE_AGEING_TIME: 1402 ocelot_port_attr_ageing_set(ocelot, port, attr->u.ageing_time); 1403 break; 1404 case SWITCHDEV_ATTR_ID_BRIDGE_VLAN_FILTERING: 1405 ocelot_port_vlan_filtering(ocelot, port, 1406 attr->u.vlan_filtering); 1407 break; 1408 case SWITCHDEV_ATTR_ID_BRIDGE_MC_DISABLED: 1409 ocelot_port_attr_mc_set(ocelot, port, !attr->u.mc_disabled); 1410 break; 1411 default: 1412 err = -EOPNOTSUPP; 1413 break; 1414 } 1415 1416 return err; 1417 } 1418 1419 static int ocelot_port_obj_add_vlan(struct net_device *dev, 1420 const struct switchdev_obj_port_vlan *vlan, 1421 struct switchdev_trans *trans) 1422 { 1423 int ret; 1424 u16 vid; 1425 1426 for (vid = vlan->vid_begin; vid <= vlan->vid_end; vid++) { 1427 ret = ocelot_vlan_vid_add(dev, vid, 1428 vlan->flags & BRIDGE_VLAN_INFO_PVID, 1429 vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED); 1430 if (ret) 1431 return ret; 1432 } 1433 1434 return 0; 1435 } 1436 1437 static int ocelot_port_vlan_del_vlan(struct net_device *dev, 1438 const struct switchdev_obj_port_vlan *vlan) 1439 { 1440 int ret; 1441 u16 vid; 1442 1443 for (vid = vlan->vid_begin; vid <= vlan->vid_end; vid++) { 1444 ret = ocelot_vlan_vid_del(dev, vid); 1445 1446 if (ret) 1447 return ret; 1448 } 1449 1450 return 0; 1451 } 1452 1453 static struct ocelot_multicast *ocelot_multicast_get(struct ocelot *ocelot, 1454 const unsigned char *addr, 1455 u16 vid) 1456 { 1457 struct ocelot_multicast *mc; 1458 1459 list_for_each_entry(mc, &ocelot->multicast, list) { 1460 if (ether_addr_equal(mc->addr, addr) && mc->vid == vid) 1461 return mc; 1462 } 1463 1464 return NULL; 1465 } 1466 1467 static int ocelot_port_obj_add_mdb(struct net_device *dev, 1468 const struct switchdev_obj_port_mdb *mdb, 1469 struct switchdev_trans *trans) 1470 { 1471 struct ocelot_port *port = netdev_priv(dev); 1472 struct ocelot *ocelot = port->ocelot; 1473 struct ocelot_multicast *mc; 1474 unsigned char addr[ETH_ALEN]; 1475 u16 vid = mdb->vid; 1476 bool new = false; 1477 1478 if (!vid) 1479 vid = port->pvid; 1480 1481 mc = ocelot_multicast_get(ocelot, mdb->addr, vid); 1482 if (!mc) { 1483 mc = devm_kzalloc(ocelot->dev, sizeof(*mc), GFP_KERNEL); 1484 if (!mc) 1485 return -ENOMEM; 1486 1487 memcpy(mc->addr, mdb->addr, ETH_ALEN); 1488 mc->vid = vid; 1489 1490 list_add_tail(&mc->list, &ocelot->multicast); 1491 new = true; 1492 } 1493 1494 memcpy(addr, mc->addr, ETH_ALEN); 1495 addr[0] = 0; 1496 1497 if (!new) { 1498 addr[2] = mc->ports << 0; 1499 addr[1] = mc->ports << 8; 1500 ocelot_mact_forget(ocelot, addr, vid); 1501 } 1502 1503 mc->ports |= BIT(port->chip_port); 1504 addr[2] = mc->ports << 0; 1505 addr[1] = mc->ports << 8; 1506 1507 return ocelot_mact_learn(ocelot, 0, addr, vid, ENTRYTYPE_MACv4); 1508 } 1509 1510 static int ocelot_port_obj_del_mdb(struct net_device *dev, 1511 const struct switchdev_obj_port_mdb *mdb) 1512 { 1513 struct ocelot_port *port = netdev_priv(dev); 1514 struct ocelot *ocelot = port->ocelot; 1515 struct ocelot_multicast *mc; 1516 unsigned char addr[ETH_ALEN]; 1517 u16 vid = mdb->vid; 1518 1519 if (!vid) 1520 vid = port->pvid; 1521 1522 mc = ocelot_multicast_get(ocelot, mdb->addr, vid); 1523 if (!mc) 1524 return -ENOENT; 1525 1526 memcpy(addr, mc->addr, ETH_ALEN); 1527 addr[2] = mc->ports << 0; 1528 addr[1] = mc->ports << 8; 1529 addr[0] = 0; 1530 ocelot_mact_forget(ocelot, addr, vid); 1531 1532 mc->ports &= ~BIT(port->chip_port); 1533 if (!mc->ports) { 1534 list_del(&mc->list); 1535 devm_kfree(ocelot->dev, mc); 1536 return 0; 1537 } 1538 1539 addr[2] = mc->ports << 0; 1540 addr[1] = mc->ports << 8; 1541 1542 return ocelot_mact_learn(ocelot, 0, addr, vid, ENTRYTYPE_MACv4); 1543 } 1544 1545 static int ocelot_port_obj_add(struct net_device *dev, 1546 const struct switchdev_obj *obj, 1547 struct switchdev_trans *trans, 1548 struct netlink_ext_ack *extack) 1549 { 1550 int ret = 0; 1551 1552 switch (obj->id) { 1553 case SWITCHDEV_OBJ_ID_PORT_VLAN: 1554 ret = ocelot_port_obj_add_vlan(dev, 1555 SWITCHDEV_OBJ_PORT_VLAN(obj), 1556 trans); 1557 break; 1558 case SWITCHDEV_OBJ_ID_PORT_MDB: 1559 ret = ocelot_port_obj_add_mdb(dev, SWITCHDEV_OBJ_PORT_MDB(obj), 1560 trans); 1561 break; 1562 default: 1563 return -EOPNOTSUPP; 1564 } 1565 1566 return ret; 1567 } 1568 1569 static int ocelot_port_obj_del(struct net_device *dev, 1570 const struct switchdev_obj *obj) 1571 { 1572 int ret = 0; 1573 1574 switch (obj->id) { 1575 case SWITCHDEV_OBJ_ID_PORT_VLAN: 1576 ret = ocelot_port_vlan_del_vlan(dev, 1577 SWITCHDEV_OBJ_PORT_VLAN(obj)); 1578 break; 1579 case SWITCHDEV_OBJ_ID_PORT_MDB: 1580 ret = ocelot_port_obj_del_mdb(dev, SWITCHDEV_OBJ_PORT_MDB(obj)); 1581 break; 1582 default: 1583 return -EOPNOTSUPP; 1584 } 1585 1586 return ret; 1587 } 1588 1589 static int ocelot_port_bridge_join(struct ocelot_port *ocelot_port, 1590 struct net_device *bridge) 1591 { 1592 struct ocelot *ocelot = ocelot_port->ocelot; 1593 1594 if (!ocelot->bridge_mask) { 1595 ocelot->hw_bridge_dev = bridge; 1596 } else { 1597 if (ocelot->hw_bridge_dev != bridge) 1598 /* This is adding the port to a second bridge, this is 1599 * unsupported */ 1600 return -ENODEV; 1601 } 1602 1603 ocelot->bridge_mask |= BIT(ocelot_port->chip_port); 1604 1605 return 0; 1606 } 1607 1608 static int ocelot_port_bridge_leave(struct ocelot_port *ocelot_port, 1609 struct net_device *bridge) 1610 { 1611 struct ocelot *ocelot = ocelot_port->ocelot; 1612 int port = ocelot_port->chip_port; 1613 1614 ocelot->bridge_mask &= ~BIT(port); 1615 1616 if (!ocelot->bridge_mask) 1617 ocelot->hw_bridge_dev = NULL; 1618 1619 ocelot_port_vlan_filtering(ocelot, port, 0); 1620 ocelot_port_set_pvid(ocelot, port, 0); 1621 return ocelot_port_set_native_vlan(ocelot, port, 0); 1622 } 1623 1624 static void ocelot_set_aggr_pgids(struct ocelot *ocelot) 1625 { 1626 int i, port, lag; 1627 1628 /* Reset destination and aggregation PGIDS */ 1629 for (port = 0; port < ocelot->num_phys_ports; port++) 1630 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port); 1631 1632 for (i = PGID_AGGR; i < PGID_SRC; i++) 1633 ocelot_write_rix(ocelot, GENMASK(ocelot->num_phys_ports - 1, 0), 1634 ANA_PGID_PGID, i); 1635 1636 /* Now, set PGIDs for each LAG */ 1637 for (lag = 0; lag < ocelot->num_phys_ports; lag++) { 1638 unsigned long bond_mask; 1639 int aggr_count = 0; 1640 u8 aggr_idx[16]; 1641 1642 bond_mask = ocelot->lags[lag]; 1643 if (!bond_mask) 1644 continue; 1645 1646 for_each_set_bit(port, &bond_mask, ocelot->num_phys_ports) { 1647 // Destination mask 1648 ocelot_write_rix(ocelot, bond_mask, 1649 ANA_PGID_PGID, port); 1650 aggr_idx[aggr_count] = port; 1651 aggr_count++; 1652 } 1653 1654 for (i = PGID_AGGR; i < PGID_SRC; i++) { 1655 u32 ac; 1656 1657 ac = ocelot_read_rix(ocelot, ANA_PGID_PGID, i); 1658 ac &= ~bond_mask; 1659 ac |= BIT(aggr_idx[i % aggr_count]); 1660 ocelot_write_rix(ocelot, ac, ANA_PGID_PGID, i); 1661 } 1662 } 1663 } 1664 1665 static void ocelot_setup_lag(struct ocelot *ocelot, int lag) 1666 { 1667 unsigned long bond_mask = ocelot->lags[lag]; 1668 unsigned int p; 1669 1670 for_each_set_bit(p, &bond_mask, ocelot->num_phys_ports) { 1671 u32 port_cfg = ocelot_read_gix(ocelot, ANA_PORT_PORT_CFG, p); 1672 1673 port_cfg &= ~ANA_PORT_PORT_CFG_PORTID_VAL_M; 1674 1675 /* Use lag port as logical port for port i */ 1676 ocelot_write_gix(ocelot, port_cfg | 1677 ANA_PORT_PORT_CFG_PORTID_VAL(lag), 1678 ANA_PORT_PORT_CFG, p); 1679 } 1680 } 1681 1682 static int ocelot_port_lag_join(struct ocelot_port *ocelot_port, 1683 struct net_device *bond) 1684 { 1685 struct ocelot *ocelot = ocelot_port->ocelot; 1686 int p = ocelot_port->chip_port; 1687 int lag, lp; 1688 struct net_device *ndev; 1689 u32 bond_mask = 0; 1690 1691 rcu_read_lock(); 1692 for_each_netdev_in_bond_rcu(bond, ndev) { 1693 struct ocelot_port *port = netdev_priv(ndev); 1694 1695 bond_mask |= BIT(port->chip_port); 1696 } 1697 rcu_read_unlock(); 1698 1699 lp = __ffs(bond_mask); 1700 1701 /* If the new port is the lowest one, use it as the logical port from 1702 * now on 1703 */ 1704 if (p == lp) { 1705 lag = p; 1706 ocelot->lags[p] = bond_mask; 1707 bond_mask &= ~BIT(p); 1708 if (bond_mask) { 1709 lp = __ffs(bond_mask); 1710 ocelot->lags[lp] = 0; 1711 } 1712 } else { 1713 lag = lp; 1714 ocelot->lags[lp] |= BIT(p); 1715 } 1716 1717 ocelot_setup_lag(ocelot, lag); 1718 ocelot_set_aggr_pgids(ocelot); 1719 1720 return 0; 1721 } 1722 1723 static void ocelot_port_lag_leave(struct ocelot_port *ocelot_port, 1724 struct net_device *bond) 1725 { 1726 struct ocelot *ocelot = ocelot_port->ocelot; 1727 int p = ocelot_port->chip_port; 1728 u32 port_cfg; 1729 int i; 1730 1731 /* Remove port from any lag */ 1732 for (i = 0; i < ocelot->num_phys_ports; i++) 1733 ocelot->lags[i] &= ~BIT(ocelot_port->chip_port); 1734 1735 /* if it was the logical port of the lag, move the lag config to the 1736 * next port 1737 */ 1738 if (ocelot->lags[p]) { 1739 int n = __ffs(ocelot->lags[p]); 1740 1741 ocelot->lags[n] = ocelot->lags[p]; 1742 ocelot->lags[p] = 0; 1743 1744 ocelot_setup_lag(ocelot, n); 1745 } 1746 1747 port_cfg = ocelot_read_gix(ocelot, ANA_PORT_PORT_CFG, p); 1748 port_cfg &= ~ANA_PORT_PORT_CFG_PORTID_VAL_M; 1749 ocelot_write_gix(ocelot, port_cfg | ANA_PORT_PORT_CFG_PORTID_VAL(p), 1750 ANA_PORT_PORT_CFG, p); 1751 1752 ocelot_set_aggr_pgids(ocelot); 1753 } 1754 1755 /* Checks if the net_device instance given to us originate from our driver. */ 1756 static bool ocelot_netdevice_dev_check(const struct net_device *dev) 1757 { 1758 return dev->netdev_ops == &ocelot_port_netdev_ops; 1759 } 1760 1761 static int ocelot_netdevice_port_event(struct net_device *dev, 1762 unsigned long event, 1763 struct netdev_notifier_changeupper_info *info) 1764 { 1765 struct ocelot_port *ocelot_port = netdev_priv(dev); 1766 int err = 0; 1767 1768 switch (event) { 1769 case NETDEV_CHANGEUPPER: 1770 if (netif_is_bridge_master(info->upper_dev)) { 1771 if (info->linking) 1772 err = ocelot_port_bridge_join(ocelot_port, 1773 info->upper_dev); 1774 else 1775 err = ocelot_port_bridge_leave(ocelot_port, 1776 info->upper_dev); 1777 } 1778 if (netif_is_lag_master(info->upper_dev)) { 1779 if (info->linking) 1780 err = ocelot_port_lag_join(ocelot_port, 1781 info->upper_dev); 1782 else 1783 ocelot_port_lag_leave(ocelot_port, 1784 info->upper_dev); 1785 } 1786 break; 1787 default: 1788 break; 1789 } 1790 1791 return err; 1792 } 1793 1794 static int ocelot_netdevice_event(struct notifier_block *unused, 1795 unsigned long event, void *ptr) 1796 { 1797 struct netdev_notifier_changeupper_info *info = ptr; 1798 struct net_device *dev = netdev_notifier_info_to_dev(ptr); 1799 int ret = 0; 1800 1801 if (!ocelot_netdevice_dev_check(dev)) 1802 return 0; 1803 1804 if (event == NETDEV_PRECHANGEUPPER && 1805 netif_is_lag_master(info->upper_dev)) { 1806 struct netdev_lag_upper_info *lag_upper_info = info->upper_info; 1807 struct netlink_ext_ack *extack; 1808 1809 if (lag_upper_info && 1810 lag_upper_info->tx_type != NETDEV_LAG_TX_TYPE_HASH) { 1811 extack = netdev_notifier_info_to_extack(&info->info); 1812 NL_SET_ERR_MSG_MOD(extack, "LAG device using unsupported Tx type"); 1813 1814 ret = -EINVAL; 1815 goto notify; 1816 } 1817 } 1818 1819 if (netif_is_lag_master(dev)) { 1820 struct net_device *slave; 1821 struct list_head *iter; 1822 1823 netdev_for_each_lower_dev(dev, slave, iter) { 1824 ret = ocelot_netdevice_port_event(slave, event, info); 1825 if (ret) 1826 goto notify; 1827 } 1828 } else { 1829 ret = ocelot_netdevice_port_event(dev, event, info); 1830 } 1831 1832 notify: 1833 return notifier_from_errno(ret); 1834 } 1835 1836 struct notifier_block ocelot_netdevice_nb __read_mostly = { 1837 .notifier_call = ocelot_netdevice_event, 1838 }; 1839 EXPORT_SYMBOL(ocelot_netdevice_nb); 1840 1841 static int ocelot_switchdev_event(struct notifier_block *unused, 1842 unsigned long event, void *ptr) 1843 { 1844 struct net_device *dev = switchdev_notifier_info_to_dev(ptr); 1845 int err; 1846 1847 switch (event) { 1848 case SWITCHDEV_PORT_ATTR_SET: 1849 err = switchdev_handle_port_attr_set(dev, ptr, 1850 ocelot_netdevice_dev_check, 1851 ocelot_port_attr_set); 1852 return notifier_from_errno(err); 1853 } 1854 1855 return NOTIFY_DONE; 1856 } 1857 1858 struct notifier_block ocelot_switchdev_nb __read_mostly = { 1859 .notifier_call = ocelot_switchdev_event, 1860 }; 1861 EXPORT_SYMBOL(ocelot_switchdev_nb); 1862 1863 static int ocelot_switchdev_blocking_event(struct notifier_block *unused, 1864 unsigned long event, void *ptr) 1865 { 1866 struct net_device *dev = switchdev_notifier_info_to_dev(ptr); 1867 int err; 1868 1869 switch (event) { 1870 /* Blocking events. */ 1871 case SWITCHDEV_PORT_OBJ_ADD: 1872 err = switchdev_handle_port_obj_add(dev, ptr, 1873 ocelot_netdevice_dev_check, 1874 ocelot_port_obj_add); 1875 return notifier_from_errno(err); 1876 case SWITCHDEV_PORT_OBJ_DEL: 1877 err = switchdev_handle_port_obj_del(dev, ptr, 1878 ocelot_netdevice_dev_check, 1879 ocelot_port_obj_del); 1880 return notifier_from_errno(err); 1881 case SWITCHDEV_PORT_ATTR_SET: 1882 err = switchdev_handle_port_attr_set(dev, ptr, 1883 ocelot_netdevice_dev_check, 1884 ocelot_port_attr_set); 1885 return notifier_from_errno(err); 1886 } 1887 1888 return NOTIFY_DONE; 1889 } 1890 1891 struct notifier_block ocelot_switchdev_blocking_nb __read_mostly = { 1892 .notifier_call = ocelot_switchdev_blocking_event, 1893 }; 1894 EXPORT_SYMBOL(ocelot_switchdev_blocking_nb); 1895 1896 int ocelot_ptp_gettime64(struct ptp_clock_info *ptp, struct timespec64 *ts) 1897 { 1898 struct ocelot *ocelot = container_of(ptp, struct ocelot, ptp_info); 1899 unsigned long flags; 1900 time64_t s; 1901 u32 val; 1902 s64 ns; 1903 1904 spin_lock_irqsave(&ocelot->ptp_clock_lock, flags); 1905 1906 val = ocelot_read_rix(ocelot, PTP_PIN_CFG, TOD_ACC_PIN); 1907 val &= ~(PTP_PIN_CFG_SYNC | PTP_PIN_CFG_ACTION_MASK | PTP_PIN_CFG_DOM); 1908 val |= PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_SAVE); 1909 ocelot_write_rix(ocelot, val, PTP_PIN_CFG, TOD_ACC_PIN); 1910 1911 s = ocelot_read_rix(ocelot, PTP_PIN_TOD_SEC_MSB, TOD_ACC_PIN) & 0xffff; 1912 s <<= 32; 1913 s += ocelot_read_rix(ocelot, PTP_PIN_TOD_SEC_LSB, TOD_ACC_PIN); 1914 ns = ocelot_read_rix(ocelot, PTP_PIN_TOD_NSEC, TOD_ACC_PIN); 1915 1916 spin_unlock_irqrestore(&ocelot->ptp_clock_lock, flags); 1917 1918 /* Deal with negative values */ 1919 if (ns >= 0x3ffffff0 && ns <= 0x3fffffff) { 1920 s--; 1921 ns &= 0xf; 1922 ns += 999999984; 1923 } 1924 1925 set_normalized_timespec64(ts, s, ns); 1926 return 0; 1927 } 1928 EXPORT_SYMBOL(ocelot_ptp_gettime64); 1929 1930 static int ocelot_ptp_settime64(struct ptp_clock_info *ptp, 1931 const struct timespec64 *ts) 1932 { 1933 struct ocelot *ocelot = container_of(ptp, struct ocelot, ptp_info); 1934 unsigned long flags; 1935 u32 val; 1936 1937 spin_lock_irqsave(&ocelot->ptp_clock_lock, flags); 1938 1939 val = ocelot_read_rix(ocelot, PTP_PIN_CFG, TOD_ACC_PIN); 1940 val &= ~(PTP_PIN_CFG_SYNC | PTP_PIN_CFG_ACTION_MASK | PTP_PIN_CFG_DOM); 1941 val |= PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_IDLE); 1942 1943 ocelot_write_rix(ocelot, val, PTP_PIN_CFG, TOD_ACC_PIN); 1944 1945 ocelot_write_rix(ocelot, lower_32_bits(ts->tv_sec), PTP_PIN_TOD_SEC_LSB, 1946 TOD_ACC_PIN); 1947 ocelot_write_rix(ocelot, upper_32_bits(ts->tv_sec), PTP_PIN_TOD_SEC_MSB, 1948 TOD_ACC_PIN); 1949 ocelot_write_rix(ocelot, ts->tv_nsec, PTP_PIN_TOD_NSEC, TOD_ACC_PIN); 1950 1951 val = ocelot_read_rix(ocelot, PTP_PIN_CFG, TOD_ACC_PIN); 1952 val &= ~(PTP_PIN_CFG_SYNC | PTP_PIN_CFG_ACTION_MASK | PTP_PIN_CFG_DOM); 1953 val |= PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_LOAD); 1954 1955 ocelot_write_rix(ocelot, val, PTP_PIN_CFG, TOD_ACC_PIN); 1956 1957 spin_unlock_irqrestore(&ocelot->ptp_clock_lock, flags); 1958 return 0; 1959 } 1960 1961 static int ocelot_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta) 1962 { 1963 if (delta > -(NSEC_PER_SEC / 2) && delta < (NSEC_PER_SEC / 2)) { 1964 struct ocelot *ocelot = container_of(ptp, struct ocelot, ptp_info); 1965 unsigned long flags; 1966 u32 val; 1967 1968 spin_lock_irqsave(&ocelot->ptp_clock_lock, flags); 1969 1970 val = ocelot_read_rix(ocelot, PTP_PIN_CFG, TOD_ACC_PIN); 1971 val &= ~(PTP_PIN_CFG_SYNC | PTP_PIN_CFG_ACTION_MASK | PTP_PIN_CFG_DOM); 1972 val |= PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_IDLE); 1973 1974 ocelot_write_rix(ocelot, val, PTP_PIN_CFG, TOD_ACC_PIN); 1975 1976 ocelot_write_rix(ocelot, 0, PTP_PIN_TOD_SEC_LSB, TOD_ACC_PIN); 1977 ocelot_write_rix(ocelot, 0, PTP_PIN_TOD_SEC_MSB, TOD_ACC_PIN); 1978 ocelot_write_rix(ocelot, delta, PTP_PIN_TOD_NSEC, TOD_ACC_PIN); 1979 1980 val = ocelot_read_rix(ocelot, PTP_PIN_CFG, TOD_ACC_PIN); 1981 val &= ~(PTP_PIN_CFG_SYNC | PTP_PIN_CFG_ACTION_MASK | PTP_PIN_CFG_DOM); 1982 val |= PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_DELTA); 1983 1984 ocelot_write_rix(ocelot, val, PTP_PIN_CFG, TOD_ACC_PIN); 1985 1986 spin_unlock_irqrestore(&ocelot->ptp_clock_lock, flags); 1987 } else { 1988 /* Fall back using ocelot_ptp_settime64 which is not exact. */ 1989 struct timespec64 ts; 1990 u64 now; 1991 1992 ocelot_ptp_gettime64(ptp, &ts); 1993 1994 now = ktime_to_ns(timespec64_to_ktime(ts)); 1995 ts = ns_to_timespec64(now + delta); 1996 1997 ocelot_ptp_settime64(ptp, &ts); 1998 } 1999 return 0; 2000 } 2001 2002 static int ocelot_ptp_adjfine(struct ptp_clock_info *ptp, long scaled_ppm) 2003 { 2004 struct ocelot *ocelot = container_of(ptp, struct ocelot, ptp_info); 2005 u32 unit = 0, direction = 0; 2006 unsigned long flags; 2007 u64 adj = 0; 2008 2009 spin_lock_irqsave(&ocelot->ptp_clock_lock, flags); 2010 2011 if (!scaled_ppm) 2012 goto disable_adj; 2013 2014 if (scaled_ppm < 0) { 2015 direction = PTP_CFG_CLK_ADJ_CFG_DIR; 2016 scaled_ppm = -scaled_ppm; 2017 } 2018 2019 adj = PSEC_PER_SEC << 16; 2020 do_div(adj, scaled_ppm); 2021 do_div(adj, 1000); 2022 2023 /* If the adjustment value is too large, use ns instead */ 2024 if (adj >= (1L << 30)) { 2025 unit = PTP_CFG_CLK_ADJ_FREQ_NS; 2026 do_div(adj, 1000); 2027 } 2028 2029 /* Still too big */ 2030 if (adj >= (1L << 30)) 2031 goto disable_adj; 2032 2033 ocelot_write(ocelot, unit | adj, PTP_CLK_CFG_ADJ_FREQ); 2034 ocelot_write(ocelot, PTP_CFG_CLK_ADJ_CFG_ENA | direction, 2035 PTP_CLK_CFG_ADJ_CFG); 2036 2037 spin_unlock_irqrestore(&ocelot->ptp_clock_lock, flags); 2038 return 0; 2039 2040 disable_adj: 2041 ocelot_write(ocelot, 0, PTP_CLK_CFG_ADJ_CFG); 2042 2043 spin_unlock_irqrestore(&ocelot->ptp_clock_lock, flags); 2044 return 0; 2045 } 2046 2047 static struct ptp_clock_info ocelot_ptp_clock_info = { 2048 .owner = THIS_MODULE, 2049 .name = "ocelot ptp", 2050 .max_adj = 0x7fffffff, 2051 .n_alarm = 0, 2052 .n_ext_ts = 0, 2053 .n_per_out = 0, 2054 .n_pins = 0, 2055 .pps = 0, 2056 .gettime64 = ocelot_ptp_gettime64, 2057 .settime64 = ocelot_ptp_settime64, 2058 .adjtime = ocelot_ptp_adjtime, 2059 .adjfine = ocelot_ptp_adjfine, 2060 }; 2061 2062 static int ocelot_init_timestamp(struct ocelot *ocelot) 2063 { 2064 ocelot->ptp_info = ocelot_ptp_clock_info; 2065 ocelot->ptp_clock = ptp_clock_register(&ocelot->ptp_info, ocelot->dev); 2066 if (IS_ERR(ocelot->ptp_clock)) 2067 return PTR_ERR(ocelot->ptp_clock); 2068 /* Check if PHC support is missing at the configuration level */ 2069 if (!ocelot->ptp_clock) 2070 return 0; 2071 2072 ocelot_write(ocelot, SYS_PTP_CFG_PTP_STAMP_WID(30), SYS_PTP_CFG); 2073 ocelot_write(ocelot, 0xffffffff, ANA_TABLES_PTP_ID_LOW); 2074 ocelot_write(ocelot, 0xffffffff, ANA_TABLES_PTP_ID_HIGH); 2075 2076 ocelot_write(ocelot, PTP_CFG_MISC_PTP_EN, PTP_CFG_MISC); 2077 2078 /* There is no device reconfiguration, PTP Rx stamping is always 2079 * enabled. 2080 */ 2081 ocelot->hwtstamp_config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 2082 2083 return 0; 2084 } 2085 2086 int ocelot_probe_port(struct ocelot *ocelot, u8 port, 2087 void __iomem *regs, 2088 struct phy_device *phy) 2089 { 2090 struct ocelot_port *ocelot_port; 2091 struct net_device *dev; 2092 u32 val; 2093 int err; 2094 2095 dev = alloc_etherdev(sizeof(struct ocelot_port)); 2096 if (!dev) 2097 return -ENOMEM; 2098 SET_NETDEV_DEV(dev, ocelot->dev); 2099 ocelot_port = netdev_priv(dev); 2100 ocelot_port->dev = dev; 2101 ocelot_port->ocelot = ocelot; 2102 ocelot_port->regs = regs; 2103 ocelot_port->chip_port = port; 2104 ocelot_port->phy = phy; 2105 ocelot->ports[port] = ocelot_port; 2106 2107 dev->netdev_ops = &ocelot_port_netdev_ops; 2108 dev->ethtool_ops = &ocelot_ethtool_ops; 2109 2110 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_RXFCS | 2111 NETIF_F_HW_TC; 2112 dev->features |= NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_TC; 2113 2114 memcpy(dev->dev_addr, ocelot->base_mac, ETH_ALEN); 2115 dev->dev_addr[ETH_ALEN - 1] += port; 2116 ocelot_mact_learn(ocelot, PGID_CPU, dev->dev_addr, ocelot_port->pvid, 2117 ENTRYTYPE_LOCKED); 2118 2119 INIT_LIST_HEAD(&ocelot_port->skbs); 2120 2121 err = register_netdev(dev); 2122 if (err) { 2123 dev_err(ocelot->dev, "register_netdev failed\n"); 2124 goto err_register_netdev; 2125 } 2126 2127 /* Basic L2 initialization */ 2128 2129 /* Drop frames with multicast source address */ 2130 val = ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA; 2131 ocelot_rmw_gix(ocelot, val, val, ANA_PORT_DROP_CFG, port); 2132 2133 /* Set default VLAN and tag type to 8021Q. */ 2134 ocelot_rmw_gix(ocelot, REW_PORT_VLAN_CFG_PORT_TPID(ETH_P_8021Q), 2135 REW_PORT_VLAN_CFG_PORT_TPID_M, 2136 REW_PORT_VLAN_CFG, port); 2137 2138 /* Enable vcap lookups */ 2139 ocelot_vcap_enable(ocelot, ocelot_port); 2140 2141 return 0; 2142 2143 err_register_netdev: 2144 free_netdev(dev); 2145 return err; 2146 } 2147 EXPORT_SYMBOL(ocelot_probe_port); 2148 2149 int ocelot_init(struct ocelot *ocelot) 2150 { 2151 u32 port; 2152 int i, ret, cpu = ocelot->num_phys_ports; 2153 char queue_name[32]; 2154 2155 ocelot->lags = devm_kcalloc(ocelot->dev, ocelot->num_phys_ports, 2156 sizeof(u32), GFP_KERNEL); 2157 if (!ocelot->lags) 2158 return -ENOMEM; 2159 2160 ocelot->stats = devm_kcalloc(ocelot->dev, 2161 ocelot->num_phys_ports * ocelot->num_stats, 2162 sizeof(u64), GFP_KERNEL); 2163 if (!ocelot->stats) 2164 return -ENOMEM; 2165 2166 mutex_init(&ocelot->stats_lock); 2167 mutex_init(&ocelot->ptp_lock); 2168 spin_lock_init(&ocelot->ptp_clock_lock); 2169 snprintf(queue_name, sizeof(queue_name), "%s-stats", 2170 dev_name(ocelot->dev)); 2171 ocelot->stats_queue = create_singlethread_workqueue(queue_name); 2172 if (!ocelot->stats_queue) 2173 return -ENOMEM; 2174 2175 ocelot_mact_init(ocelot); 2176 ocelot_vlan_init(ocelot); 2177 ocelot_ace_init(ocelot); 2178 2179 for (port = 0; port < ocelot->num_phys_ports; port++) { 2180 /* Clear all counters (5 groups) */ 2181 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(port) | 2182 SYS_STAT_CFG_STAT_CLEAR_SHOT(0x7f), 2183 SYS_STAT_CFG); 2184 } 2185 2186 /* Only use S-Tag */ 2187 ocelot_write(ocelot, ETH_P_8021AD, SYS_VLAN_ETYPE_CFG); 2188 2189 /* Aggregation mode */ 2190 ocelot_write(ocelot, ANA_AGGR_CFG_AC_SMAC_ENA | 2191 ANA_AGGR_CFG_AC_DMAC_ENA | 2192 ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA | 2193 ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA, ANA_AGGR_CFG); 2194 2195 /* Set MAC age time to default value. The entry is aged after 2196 * 2*AGE_PERIOD 2197 */ 2198 ocelot_write(ocelot, 2199 ANA_AUTOAGE_AGE_PERIOD(BR_DEFAULT_AGEING_TIME / 2 / HZ), 2200 ANA_AUTOAGE); 2201 2202 /* Disable learning for frames discarded by VLAN ingress filtering */ 2203 regmap_field_write(ocelot->regfields[ANA_ADVLEARN_VLAN_CHK], 1); 2204 2205 /* Setup frame ageing - fixed value "2 sec" - in 6.5 us units */ 2206 ocelot_write(ocelot, SYS_FRM_AGING_AGE_TX_ENA | 2207 SYS_FRM_AGING_MAX_AGE(307692), SYS_FRM_AGING); 2208 2209 /* Setup flooding PGIDs */ 2210 ocelot_write_rix(ocelot, ANA_FLOODING_FLD_MULTICAST(PGID_MC) | 2211 ANA_FLOODING_FLD_BROADCAST(PGID_MC) | 2212 ANA_FLOODING_FLD_UNICAST(PGID_UC), 2213 ANA_FLOODING, 0); 2214 ocelot_write(ocelot, ANA_FLOODING_IPMC_FLD_MC6_DATA(PGID_MCIPV6) | 2215 ANA_FLOODING_IPMC_FLD_MC6_CTRL(PGID_MC) | 2216 ANA_FLOODING_IPMC_FLD_MC4_DATA(PGID_MCIPV4) | 2217 ANA_FLOODING_IPMC_FLD_MC4_CTRL(PGID_MC), 2218 ANA_FLOODING_IPMC); 2219 2220 for (port = 0; port < ocelot->num_phys_ports; port++) { 2221 /* Transmit the frame to the local port. */ 2222 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port); 2223 /* Do not forward BPDU frames to the front ports. */ 2224 ocelot_write_gix(ocelot, 2225 ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA(0xffff), 2226 ANA_PORT_CPU_FWD_BPDU_CFG, 2227 port); 2228 /* Ensure bridging is disabled */ 2229 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_SRC + port); 2230 } 2231 2232 /* Configure and enable the CPU port. */ 2233 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, cpu); 2234 ocelot_write_rix(ocelot, BIT(cpu), ANA_PGID_PGID, PGID_CPU); 2235 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_RECV_ENA | 2236 ANA_PORT_PORT_CFG_PORTID_VAL(cpu), 2237 ANA_PORT_PORT_CFG, cpu); 2238 2239 /* Allow broadcast MAC frames. */ 2240 for (i = ocelot->num_phys_ports + 1; i < PGID_CPU; i++) { 2241 u32 val = ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports - 1, 0)); 2242 2243 ocelot_write_rix(ocelot, val, ANA_PGID_PGID, i); 2244 } 2245 ocelot_write_rix(ocelot, 2246 ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports, 0)), 2247 ANA_PGID_PGID, PGID_MC); 2248 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV4); 2249 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV6); 2250 2251 /* CPU port Injection/Extraction configuration */ 2252 ocelot_write_rix(ocelot, QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE | 2253 QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG(1) | 2254 QSYS_SWITCH_PORT_MODE_PORT_ENA, 2255 QSYS_SWITCH_PORT_MODE, cpu); 2256 ocelot_write_rix(ocelot, SYS_PORT_MODE_INCL_XTR_HDR(1) | 2257 SYS_PORT_MODE_INCL_INJ_HDR(1), SYS_PORT_MODE, cpu); 2258 /* Allow manual injection via DEVCPU_QS registers, and byte swap these 2259 * registers endianness. 2260 */ 2261 ocelot_write_rix(ocelot, QS_INJ_GRP_CFG_BYTE_SWAP | 2262 QS_INJ_GRP_CFG_MODE(1), QS_INJ_GRP_CFG, 0); 2263 ocelot_write_rix(ocelot, QS_XTR_GRP_CFG_BYTE_SWAP | 2264 QS_XTR_GRP_CFG_MODE(1), QS_XTR_GRP_CFG, 0); 2265 ocelot_write(ocelot, ANA_CPUQ_CFG_CPUQ_MIRROR(2) | 2266 ANA_CPUQ_CFG_CPUQ_LRN(2) | 2267 ANA_CPUQ_CFG_CPUQ_MAC_COPY(2) | 2268 ANA_CPUQ_CFG_CPUQ_SRC_COPY(2) | 2269 ANA_CPUQ_CFG_CPUQ_LOCKED_PORTMOVE(2) | 2270 ANA_CPUQ_CFG_CPUQ_ALLBRIDGE(6) | 2271 ANA_CPUQ_CFG_CPUQ_IPMC_CTRL(6) | 2272 ANA_CPUQ_CFG_CPUQ_IGMP(6) | 2273 ANA_CPUQ_CFG_CPUQ_MLD(6), ANA_CPUQ_CFG); 2274 for (i = 0; i < 16; i++) 2275 ocelot_write_rix(ocelot, ANA_CPUQ_8021_CFG_CPUQ_GARP_VAL(6) | 2276 ANA_CPUQ_8021_CFG_CPUQ_BPDU_VAL(6), 2277 ANA_CPUQ_8021_CFG, i); 2278 2279 INIT_DELAYED_WORK(&ocelot->stats_work, ocelot_check_stats_work); 2280 queue_delayed_work(ocelot->stats_queue, &ocelot->stats_work, 2281 OCELOT_STATS_CHECK_DELAY); 2282 2283 if (ocelot->ptp) { 2284 ret = ocelot_init_timestamp(ocelot); 2285 if (ret) { 2286 dev_err(ocelot->dev, 2287 "Timestamp initialization failed\n"); 2288 return ret; 2289 } 2290 } 2291 2292 return 0; 2293 } 2294 EXPORT_SYMBOL(ocelot_init); 2295 2296 void ocelot_deinit(struct ocelot *ocelot) 2297 { 2298 struct list_head *pos, *tmp; 2299 struct ocelot_port *port; 2300 struct ocelot_skb *entry; 2301 int i; 2302 2303 cancel_delayed_work(&ocelot->stats_work); 2304 destroy_workqueue(ocelot->stats_queue); 2305 mutex_destroy(&ocelot->stats_lock); 2306 ocelot_ace_deinit(); 2307 2308 for (i = 0; i < ocelot->num_phys_ports; i++) { 2309 port = ocelot->ports[i]; 2310 2311 list_for_each_safe(pos, tmp, &port->skbs) { 2312 entry = list_entry(pos, struct ocelot_skb, head); 2313 2314 list_del(pos); 2315 dev_kfree_skb_any(entry->skb); 2316 kfree(entry); 2317 } 2318 } 2319 } 2320 EXPORT_SYMBOL(ocelot_deinit); 2321 2322 MODULE_LICENSE("Dual MIT/GPL"); 2323