1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* 3 * Microsemi Ocelot Switch driver 4 * 5 * Copyright (c) 2017 Microsemi Corporation 6 */ 7 #include <linux/dsa/ocelot.h> 8 #include <linux/if_bridge.h> 9 #include <linux/ptp_classify.h> 10 #include <soc/mscc/ocelot_vcap.h> 11 #include "ocelot.h" 12 #include "ocelot_vcap.h" 13 14 #define TABLE_UPDATE_SLEEP_US 10 15 #define TABLE_UPDATE_TIMEOUT_US 100000 16 17 struct ocelot_mact_entry { 18 u8 mac[ETH_ALEN]; 19 u16 vid; 20 enum macaccess_entry_type type; 21 }; 22 23 static inline u32 ocelot_mact_read_macaccess(struct ocelot *ocelot) 24 { 25 return ocelot_read(ocelot, ANA_TABLES_MACACCESS); 26 } 27 28 static inline int ocelot_mact_wait_for_completion(struct ocelot *ocelot) 29 { 30 u32 val; 31 32 return readx_poll_timeout(ocelot_mact_read_macaccess, 33 ocelot, val, 34 (val & ANA_TABLES_MACACCESS_MAC_TABLE_CMD_M) == 35 MACACCESS_CMD_IDLE, 36 TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US); 37 } 38 39 static void ocelot_mact_select(struct ocelot *ocelot, 40 const unsigned char mac[ETH_ALEN], 41 unsigned int vid) 42 { 43 u32 macl = 0, mach = 0; 44 45 /* Set the MAC address to handle and the vlan associated in a format 46 * understood by the hardware. 47 */ 48 mach |= vid << 16; 49 mach |= mac[0] << 8; 50 mach |= mac[1] << 0; 51 macl |= mac[2] << 24; 52 macl |= mac[3] << 16; 53 macl |= mac[4] << 8; 54 macl |= mac[5] << 0; 55 56 ocelot_write(ocelot, macl, ANA_TABLES_MACLDATA); 57 ocelot_write(ocelot, mach, ANA_TABLES_MACHDATA); 58 59 } 60 61 int ocelot_mact_learn(struct ocelot *ocelot, int port, 62 const unsigned char mac[ETH_ALEN], 63 unsigned int vid, enum macaccess_entry_type type) 64 { 65 u32 cmd = ANA_TABLES_MACACCESS_VALID | 66 ANA_TABLES_MACACCESS_DEST_IDX(port) | 67 ANA_TABLES_MACACCESS_ENTRYTYPE(type) | 68 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_LEARN); 69 unsigned int mc_ports; 70 71 /* Set MAC_CPU_COPY if the CPU port is used by a multicast entry */ 72 if (type == ENTRYTYPE_MACv4) 73 mc_ports = (mac[1] << 8) | mac[2]; 74 else if (type == ENTRYTYPE_MACv6) 75 mc_ports = (mac[0] << 8) | mac[1]; 76 else 77 mc_ports = 0; 78 79 if (mc_ports & BIT(ocelot->num_phys_ports)) 80 cmd |= ANA_TABLES_MACACCESS_MAC_CPU_COPY; 81 82 ocelot_mact_select(ocelot, mac, vid); 83 84 /* Issue a write command */ 85 ocelot_write(ocelot, cmd, ANA_TABLES_MACACCESS); 86 87 return ocelot_mact_wait_for_completion(ocelot); 88 } 89 EXPORT_SYMBOL(ocelot_mact_learn); 90 91 int ocelot_mact_forget(struct ocelot *ocelot, 92 const unsigned char mac[ETH_ALEN], unsigned int vid) 93 { 94 ocelot_mact_select(ocelot, mac, vid); 95 96 /* Issue a forget command */ 97 ocelot_write(ocelot, 98 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_FORGET), 99 ANA_TABLES_MACACCESS); 100 101 return ocelot_mact_wait_for_completion(ocelot); 102 } 103 EXPORT_SYMBOL(ocelot_mact_forget); 104 105 static void ocelot_mact_init(struct ocelot *ocelot) 106 { 107 /* Configure the learning mode entries attributes: 108 * - Do not copy the frame to the CPU extraction queues. 109 * - Use the vlan and mac_cpoy for dmac lookup. 110 */ 111 ocelot_rmw(ocelot, 0, 112 ANA_AGENCTRL_LEARN_CPU_COPY | ANA_AGENCTRL_IGNORE_DMAC_FLAGS 113 | ANA_AGENCTRL_LEARN_FWD_KILL 114 | ANA_AGENCTRL_LEARN_IGNORE_VLAN, 115 ANA_AGENCTRL); 116 117 /* Clear the MAC table */ 118 ocelot_write(ocelot, MACACCESS_CMD_INIT, ANA_TABLES_MACACCESS); 119 } 120 121 static void ocelot_vcap_enable(struct ocelot *ocelot, int port) 122 { 123 ocelot_write_gix(ocelot, ANA_PORT_VCAP_S2_CFG_S2_ENA | 124 ANA_PORT_VCAP_S2_CFG_S2_IP6_CFG(0xa), 125 ANA_PORT_VCAP_S2_CFG, port); 126 127 ocelot_write_gix(ocelot, ANA_PORT_VCAP_CFG_S1_ENA, 128 ANA_PORT_VCAP_CFG, port); 129 130 ocelot_rmw_gix(ocelot, REW_PORT_CFG_ES0_EN, 131 REW_PORT_CFG_ES0_EN, 132 REW_PORT_CFG, port); 133 } 134 135 static inline u32 ocelot_vlant_read_vlanaccess(struct ocelot *ocelot) 136 { 137 return ocelot_read(ocelot, ANA_TABLES_VLANACCESS); 138 } 139 140 static inline int ocelot_vlant_wait_for_completion(struct ocelot *ocelot) 141 { 142 u32 val; 143 144 return readx_poll_timeout(ocelot_vlant_read_vlanaccess, 145 ocelot, 146 val, 147 (val & ANA_TABLES_VLANACCESS_VLAN_TBL_CMD_M) == 148 ANA_TABLES_VLANACCESS_CMD_IDLE, 149 TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US); 150 } 151 152 static int ocelot_vlant_set_mask(struct ocelot *ocelot, u16 vid, u32 mask) 153 { 154 /* Select the VID to configure */ 155 ocelot_write(ocelot, ANA_TABLES_VLANTIDX_V_INDEX(vid), 156 ANA_TABLES_VLANTIDX); 157 /* Set the vlan port members mask and issue a write command */ 158 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_VLAN_PORT_MASK(mask) | 159 ANA_TABLES_VLANACCESS_CMD_WRITE, 160 ANA_TABLES_VLANACCESS); 161 162 return ocelot_vlant_wait_for_completion(ocelot); 163 } 164 165 static void ocelot_port_set_native_vlan(struct ocelot *ocelot, int port, 166 struct ocelot_vlan native_vlan) 167 { 168 struct ocelot_port *ocelot_port = ocelot->ports[port]; 169 u32 val = 0; 170 171 ocelot_port->native_vlan = native_vlan; 172 173 ocelot_rmw_gix(ocelot, REW_PORT_VLAN_CFG_PORT_VID(native_vlan.vid), 174 REW_PORT_VLAN_CFG_PORT_VID_M, 175 REW_PORT_VLAN_CFG, port); 176 177 if (ocelot_port->vlan_aware) { 178 if (native_vlan.valid) 179 /* Tag all frames except when VID == DEFAULT_VLAN */ 180 val = REW_TAG_CFG_TAG_CFG(1); 181 else 182 /* Tag all frames */ 183 val = REW_TAG_CFG_TAG_CFG(3); 184 } else { 185 /* Port tagging disabled. */ 186 val = REW_TAG_CFG_TAG_CFG(0); 187 } 188 ocelot_rmw_gix(ocelot, val, 189 REW_TAG_CFG_TAG_CFG_M, 190 REW_TAG_CFG, port); 191 } 192 193 /* Default vlan to clasify for untagged frames (may be zero) */ 194 static void ocelot_port_set_pvid(struct ocelot *ocelot, int port, 195 struct ocelot_vlan pvid_vlan) 196 { 197 struct ocelot_port *ocelot_port = ocelot->ports[port]; 198 u32 val = 0; 199 200 ocelot_port->pvid_vlan = pvid_vlan; 201 202 if (!ocelot_port->vlan_aware) 203 pvid_vlan.vid = 0; 204 205 ocelot_rmw_gix(ocelot, 206 ANA_PORT_VLAN_CFG_VLAN_VID(pvid_vlan.vid), 207 ANA_PORT_VLAN_CFG_VLAN_VID_M, 208 ANA_PORT_VLAN_CFG, port); 209 210 /* If there's no pvid, we should drop not only untagged traffic (which 211 * happens automatically), but also 802.1p traffic which gets 212 * classified to VLAN 0, but that is always in our RX filter, so it 213 * would get accepted were it not for this setting. 214 */ 215 if (!pvid_vlan.valid && ocelot_port->vlan_aware) 216 val = ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA | 217 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA; 218 219 ocelot_rmw_gix(ocelot, val, 220 ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA | 221 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA, 222 ANA_PORT_DROP_CFG, port); 223 } 224 225 static int ocelot_vlan_member_set(struct ocelot *ocelot, u32 vlan_mask, u16 vid) 226 { 227 int err; 228 229 err = ocelot_vlant_set_mask(ocelot, vid, vlan_mask); 230 if (err) 231 return err; 232 233 ocelot->vlan_mask[vid] = vlan_mask; 234 235 return 0; 236 } 237 238 static int ocelot_vlan_member_add(struct ocelot *ocelot, int port, u16 vid) 239 { 240 return ocelot_vlan_member_set(ocelot, 241 ocelot->vlan_mask[vid] | BIT(port), 242 vid); 243 } 244 245 static int ocelot_vlan_member_del(struct ocelot *ocelot, int port, u16 vid) 246 { 247 return ocelot_vlan_member_set(ocelot, 248 ocelot->vlan_mask[vid] & ~BIT(port), 249 vid); 250 } 251 252 int ocelot_port_vlan_filtering(struct ocelot *ocelot, int port, 253 bool vlan_aware, struct netlink_ext_ack *extack) 254 { 255 struct ocelot_vcap_block *block = &ocelot->block[VCAP_IS1]; 256 struct ocelot_port *ocelot_port = ocelot->ports[port]; 257 struct ocelot_vcap_filter *filter; 258 u32 val; 259 260 list_for_each_entry(filter, &block->rules, list) { 261 if (filter->ingress_port_mask & BIT(port) && 262 filter->action.vid_replace_ena) { 263 NL_SET_ERR_MSG_MOD(extack, 264 "Cannot change VLAN state with vlan modify rules active"); 265 return -EBUSY; 266 } 267 } 268 269 ocelot_port->vlan_aware = vlan_aware; 270 271 if (vlan_aware) 272 val = ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 273 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1); 274 else 275 val = 0; 276 ocelot_rmw_gix(ocelot, val, 277 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 278 ANA_PORT_VLAN_CFG_VLAN_POP_CNT_M, 279 ANA_PORT_VLAN_CFG, port); 280 281 ocelot_port_set_pvid(ocelot, port, ocelot_port->pvid_vlan); 282 ocelot_port_set_native_vlan(ocelot, port, ocelot_port->native_vlan); 283 284 return 0; 285 } 286 EXPORT_SYMBOL(ocelot_port_vlan_filtering); 287 288 int ocelot_vlan_prepare(struct ocelot *ocelot, int port, u16 vid, bool pvid, 289 bool untagged, struct netlink_ext_ack *extack) 290 { 291 struct ocelot_port *ocelot_port = ocelot->ports[port]; 292 293 /* Deny changing the native VLAN, but always permit deleting it */ 294 if (untagged && ocelot_port->native_vlan.vid != vid && 295 ocelot_port->native_vlan.valid) { 296 NL_SET_ERR_MSG_MOD(extack, 297 "Port already has a native VLAN"); 298 return -EBUSY; 299 } 300 301 return 0; 302 } 303 EXPORT_SYMBOL(ocelot_vlan_prepare); 304 305 int ocelot_vlan_add(struct ocelot *ocelot, int port, u16 vid, bool pvid, 306 bool untagged) 307 { 308 int err; 309 310 err = ocelot_vlan_member_add(ocelot, port, vid); 311 if (err) 312 return err; 313 314 /* Default ingress vlan classification */ 315 if (pvid) { 316 struct ocelot_vlan pvid_vlan; 317 318 pvid_vlan.vid = vid; 319 pvid_vlan.valid = true; 320 ocelot_port_set_pvid(ocelot, port, pvid_vlan); 321 } 322 323 /* Untagged egress vlan clasification */ 324 if (untagged) { 325 struct ocelot_vlan native_vlan; 326 327 native_vlan.vid = vid; 328 native_vlan.valid = true; 329 ocelot_port_set_native_vlan(ocelot, port, native_vlan); 330 } 331 332 return 0; 333 } 334 EXPORT_SYMBOL(ocelot_vlan_add); 335 336 int ocelot_vlan_del(struct ocelot *ocelot, int port, u16 vid) 337 { 338 struct ocelot_port *ocelot_port = ocelot->ports[port]; 339 int err; 340 341 err = ocelot_vlan_member_del(ocelot, port, vid); 342 if (err) 343 return err; 344 345 /* Ingress */ 346 if (ocelot_port->pvid_vlan.vid == vid) { 347 struct ocelot_vlan pvid_vlan = {0}; 348 349 ocelot_port_set_pvid(ocelot, port, pvid_vlan); 350 } 351 352 /* Egress */ 353 if (ocelot_port->native_vlan.vid == vid) { 354 struct ocelot_vlan native_vlan = {0}; 355 356 ocelot_port_set_native_vlan(ocelot, port, native_vlan); 357 } 358 359 return 0; 360 } 361 EXPORT_SYMBOL(ocelot_vlan_del); 362 363 static void ocelot_vlan_init(struct ocelot *ocelot) 364 { 365 unsigned long all_ports = GENMASK(ocelot->num_phys_ports - 1, 0); 366 u16 port, vid; 367 368 /* Clear VLAN table, by default all ports are members of all VLANs */ 369 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_CMD_INIT, 370 ANA_TABLES_VLANACCESS); 371 ocelot_vlant_wait_for_completion(ocelot); 372 373 /* Configure the port VLAN memberships */ 374 for (vid = 1; vid < VLAN_N_VID; vid++) 375 ocelot_vlan_member_set(ocelot, 0, vid); 376 377 /* Because VLAN filtering is enabled, we need VID 0 to get untagged 378 * traffic. It is added automatically if 8021q module is loaded, but 379 * we can't rely on it since module may be not loaded. 380 */ 381 ocelot_vlan_member_set(ocelot, all_ports, 0); 382 383 /* Set vlan ingress filter mask to all ports but the CPU port by 384 * default. 385 */ 386 ocelot_write(ocelot, all_ports, ANA_VLANMASK); 387 388 for (port = 0; port < ocelot->num_phys_ports; port++) { 389 ocelot_write_gix(ocelot, 0, REW_PORT_VLAN_CFG, port); 390 ocelot_write_gix(ocelot, 0, REW_TAG_CFG, port); 391 } 392 } 393 394 static u32 ocelot_read_eq_avail(struct ocelot *ocelot, int port) 395 { 396 return ocelot_read_rix(ocelot, QSYS_SW_STATUS, port); 397 } 398 399 static int ocelot_port_flush(struct ocelot *ocelot, int port) 400 { 401 unsigned int pause_ena; 402 int err, val; 403 404 /* Disable dequeuing from the egress queues */ 405 ocelot_rmw_rix(ocelot, QSYS_PORT_MODE_DEQUEUE_DIS, 406 QSYS_PORT_MODE_DEQUEUE_DIS, 407 QSYS_PORT_MODE, port); 408 409 /* Disable flow control */ 410 ocelot_fields_read(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, &pause_ena); 411 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, 0); 412 413 /* Disable priority flow control */ 414 ocelot_fields_write(ocelot, port, 415 QSYS_SWITCH_PORT_MODE_TX_PFC_ENA, 0); 416 417 /* Wait at least the time it takes to receive a frame of maximum length 418 * at the port. 419 * Worst-case delays for 10 kilobyte jumbo frames are: 420 * 8 ms on a 10M port 421 * 800 μs on a 100M port 422 * 80 μs on a 1G port 423 * 32 μs on a 2.5G port 424 */ 425 usleep_range(8000, 10000); 426 427 /* Disable half duplex backpressure. */ 428 ocelot_rmw_rix(ocelot, 0, SYS_FRONT_PORT_MODE_HDX_MODE, 429 SYS_FRONT_PORT_MODE, port); 430 431 /* Flush the queues associated with the port. */ 432 ocelot_rmw_gix(ocelot, REW_PORT_CFG_FLUSH_ENA, REW_PORT_CFG_FLUSH_ENA, 433 REW_PORT_CFG, port); 434 435 /* Enable dequeuing from the egress queues. */ 436 ocelot_rmw_rix(ocelot, 0, QSYS_PORT_MODE_DEQUEUE_DIS, QSYS_PORT_MODE, 437 port); 438 439 /* Wait until flushing is complete. */ 440 err = read_poll_timeout(ocelot_read_eq_avail, val, !val, 441 100, 2000000, false, ocelot, port); 442 443 /* Clear flushing again. */ 444 ocelot_rmw_gix(ocelot, 0, REW_PORT_CFG_FLUSH_ENA, REW_PORT_CFG, port); 445 446 /* Re-enable flow control */ 447 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, pause_ena); 448 449 return err; 450 } 451 452 void ocelot_phylink_mac_link_down(struct ocelot *ocelot, int port, 453 unsigned int link_an_mode, 454 phy_interface_t interface, 455 unsigned long quirks) 456 { 457 struct ocelot_port *ocelot_port = ocelot->ports[port]; 458 int err; 459 460 ocelot_port_rmwl(ocelot_port, 0, DEV_MAC_ENA_CFG_RX_ENA, 461 DEV_MAC_ENA_CFG); 462 463 ocelot_fields_write(ocelot, port, QSYS_SWITCH_PORT_MODE_PORT_ENA, 0); 464 465 err = ocelot_port_flush(ocelot, port); 466 if (err) 467 dev_err(ocelot->dev, "failed to flush port %d: %d\n", 468 port, err); 469 470 /* Put the port in reset. */ 471 if (interface != PHY_INTERFACE_MODE_QSGMII || 472 !(quirks & OCELOT_QUIRK_QSGMII_PORTS_MUST_BE_UP)) 473 ocelot_port_rmwl(ocelot_port, 474 DEV_CLOCK_CFG_MAC_TX_RST | 475 DEV_CLOCK_CFG_MAC_TX_RST, 476 DEV_CLOCK_CFG_MAC_TX_RST | 477 DEV_CLOCK_CFG_MAC_TX_RST, 478 DEV_CLOCK_CFG); 479 } 480 EXPORT_SYMBOL_GPL(ocelot_phylink_mac_link_down); 481 482 void ocelot_phylink_mac_link_up(struct ocelot *ocelot, int port, 483 struct phy_device *phydev, 484 unsigned int link_an_mode, 485 phy_interface_t interface, 486 int speed, int duplex, 487 bool tx_pause, bool rx_pause, 488 unsigned long quirks) 489 { 490 struct ocelot_port *ocelot_port = ocelot->ports[port]; 491 int mac_speed, mode = 0; 492 u32 mac_fc_cfg; 493 494 /* The MAC might be integrated in systems where the MAC speed is fixed 495 * and it's the PCS who is performing the rate adaptation, so we have 496 * to write "1000Mbps" into the LINK_SPEED field of DEV_CLOCK_CFG 497 * (which is also its default value). 498 */ 499 if ((quirks & OCELOT_QUIRK_PCS_PERFORMS_RATE_ADAPTATION) || 500 speed == SPEED_1000) { 501 mac_speed = OCELOT_SPEED_1000; 502 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA; 503 } else if (speed == SPEED_2500) { 504 mac_speed = OCELOT_SPEED_2500; 505 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA; 506 } else if (speed == SPEED_100) { 507 mac_speed = OCELOT_SPEED_100; 508 } else { 509 mac_speed = OCELOT_SPEED_10; 510 } 511 512 if (duplex == DUPLEX_FULL) 513 mode |= DEV_MAC_MODE_CFG_FDX_ENA; 514 515 ocelot_port_writel(ocelot_port, mode, DEV_MAC_MODE_CFG); 516 517 /* Take port out of reset by clearing the MAC_TX_RST, MAC_RX_RST and 518 * PORT_RST bits in DEV_CLOCK_CFG. 519 */ 520 ocelot_port_writel(ocelot_port, DEV_CLOCK_CFG_LINK_SPEED(mac_speed), 521 DEV_CLOCK_CFG); 522 523 switch (speed) { 524 case SPEED_10: 525 mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(OCELOT_SPEED_10); 526 break; 527 case SPEED_100: 528 mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(OCELOT_SPEED_100); 529 break; 530 case SPEED_1000: 531 case SPEED_2500: 532 mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(OCELOT_SPEED_1000); 533 break; 534 default: 535 dev_err(ocelot->dev, "Unsupported speed on port %d: %d\n", 536 port, speed); 537 return; 538 } 539 540 /* Handle RX pause in all cases, with 2500base-X this is used for rate 541 * adaptation. 542 */ 543 mac_fc_cfg |= SYS_MAC_FC_CFG_RX_FC_ENA; 544 545 if (tx_pause) 546 mac_fc_cfg |= SYS_MAC_FC_CFG_TX_FC_ENA | 547 SYS_MAC_FC_CFG_PAUSE_VAL_CFG(0xffff) | 548 SYS_MAC_FC_CFG_FC_LATENCY_CFG(0x7) | 549 SYS_MAC_FC_CFG_ZERO_PAUSE_ENA; 550 551 /* Flow control. Link speed is only used here to evaluate the time 552 * specification in incoming pause frames. 553 */ 554 ocelot_write_rix(ocelot, mac_fc_cfg, SYS_MAC_FC_CFG, port); 555 556 ocelot_write_rix(ocelot, 0, ANA_POL_FLOWC, port); 557 558 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, tx_pause); 559 560 /* Undo the effects of ocelot_phylink_mac_link_down: 561 * enable MAC module 562 */ 563 ocelot_port_writel(ocelot_port, DEV_MAC_ENA_CFG_RX_ENA | 564 DEV_MAC_ENA_CFG_TX_ENA, DEV_MAC_ENA_CFG); 565 566 /* Take MAC, Port, Phy (intern) and PCS (SGMII/Serdes) clock out of 567 * reset 568 */ 569 ocelot_port_writel(ocelot_port, DEV_CLOCK_CFG_LINK_SPEED(speed), 570 DEV_CLOCK_CFG); 571 572 /* Core: Enable port for frame transfer */ 573 ocelot_fields_write(ocelot, port, 574 QSYS_SWITCH_PORT_MODE_PORT_ENA, 1); 575 } 576 EXPORT_SYMBOL_GPL(ocelot_phylink_mac_link_up); 577 578 static void ocelot_port_add_txtstamp_skb(struct ocelot *ocelot, int port, 579 struct sk_buff *clone) 580 { 581 struct ocelot_port *ocelot_port = ocelot->ports[port]; 582 583 spin_lock(&ocelot_port->ts_id_lock); 584 585 skb_shinfo(clone)->tx_flags |= SKBTX_IN_PROGRESS; 586 /* Store timestamp ID in OCELOT_SKB_CB(clone)->ts_id */ 587 OCELOT_SKB_CB(clone)->ts_id = ocelot_port->ts_id; 588 ocelot_port->ts_id = (ocelot_port->ts_id + 1) % 4; 589 skb_queue_tail(&ocelot_port->tx_skbs, clone); 590 591 spin_unlock(&ocelot_port->ts_id_lock); 592 } 593 594 u32 ocelot_ptp_rew_op(struct sk_buff *skb) 595 { 596 struct sk_buff *clone = OCELOT_SKB_CB(skb)->clone; 597 u8 ptp_cmd = OCELOT_SKB_CB(skb)->ptp_cmd; 598 u32 rew_op = 0; 599 600 if (ptp_cmd == IFH_REW_OP_TWO_STEP_PTP && clone) { 601 rew_op = ptp_cmd; 602 rew_op |= OCELOT_SKB_CB(clone)->ts_id << 3; 603 } else if (ptp_cmd == IFH_REW_OP_ORIGIN_PTP) { 604 rew_op = ptp_cmd; 605 } 606 607 return rew_op; 608 } 609 EXPORT_SYMBOL(ocelot_ptp_rew_op); 610 611 static bool ocelot_ptp_is_onestep_sync(struct sk_buff *skb) 612 { 613 struct ptp_header *hdr; 614 unsigned int ptp_class; 615 u8 msgtype, twostep; 616 617 ptp_class = ptp_classify_raw(skb); 618 if (ptp_class == PTP_CLASS_NONE) 619 return false; 620 621 hdr = ptp_parse_header(skb, ptp_class); 622 if (!hdr) 623 return false; 624 625 msgtype = ptp_get_msgtype(hdr, ptp_class); 626 twostep = hdr->flag_field[0] & 0x2; 627 628 if (msgtype == PTP_MSGTYPE_SYNC && twostep == 0) 629 return true; 630 631 return false; 632 } 633 634 int ocelot_port_txtstamp_request(struct ocelot *ocelot, int port, 635 struct sk_buff *skb, 636 struct sk_buff **clone) 637 { 638 struct ocelot_port *ocelot_port = ocelot->ports[port]; 639 u8 ptp_cmd = ocelot_port->ptp_cmd; 640 641 /* Store ptp_cmd in OCELOT_SKB_CB(skb)->ptp_cmd */ 642 if (ptp_cmd == IFH_REW_OP_ORIGIN_PTP) { 643 if (ocelot_ptp_is_onestep_sync(skb)) { 644 OCELOT_SKB_CB(skb)->ptp_cmd = ptp_cmd; 645 return 0; 646 } 647 648 /* Fall back to two-step timestamping */ 649 ptp_cmd = IFH_REW_OP_TWO_STEP_PTP; 650 } 651 652 if (ptp_cmd == IFH_REW_OP_TWO_STEP_PTP) { 653 *clone = skb_clone_sk(skb); 654 if (!(*clone)) 655 return -ENOMEM; 656 657 ocelot_port_add_txtstamp_skb(ocelot, port, *clone); 658 OCELOT_SKB_CB(skb)->ptp_cmd = ptp_cmd; 659 } 660 661 return 0; 662 } 663 EXPORT_SYMBOL(ocelot_port_txtstamp_request); 664 665 static void ocelot_get_hwtimestamp(struct ocelot *ocelot, 666 struct timespec64 *ts) 667 { 668 unsigned long flags; 669 u32 val; 670 671 spin_lock_irqsave(&ocelot->ptp_clock_lock, flags); 672 673 /* Read current PTP time to get seconds */ 674 val = ocelot_read_rix(ocelot, PTP_PIN_CFG, TOD_ACC_PIN); 675 676 val &= ~(PTP_PIN_CFG_SYNC | PTP_PIN_CFG_ACTION_MASK | PTP_PIN_CFG_DOM); 677 val |= PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_SAVE); 678 ocelot_write_rix(ocelot, val, PTP_PIN_CFG, TOD_ACC_PIN); 679 ts->tv_sec = ocelot_read_rix(ocelot, PTP_PIN_TOD_SEC_LSB, TOD_ACC_PIN); 680 681 /* Read packet HW timestamp from FIFO */ 682 val = ocelot_read(ocelot, SYS_PTP_TXSTAMP); 683 ts->tv_nsec = SYS_PTP_TXSTAMP_PTP_TXSTAMP(val); 684 685 /* Sec has incremented since the ts was registered */ 686 if ((ts->tv_sec & 0x1) != !!(val & SYS_PTP_TXSTAMP_PTP_TXSTAMP_SEC)) 687 ts->tv_sec--; 688 689 spin_unlock_irqrestore(&ocelot->ptp_clock_lock, flags); 690 } 691 692 void ocelot_get_txtstamp(struct ocelot *ocelot) 693 { 694 int budget = OCELOT_PTP_QUEUE_SZ; 695 696 while (budget--) { 697 struct sk_buff *skb, *skb_tmp, *skb_match = NULL; 698 struct skb_shared_hwtstamps shhwtstamps; 699 struct ocelot_port *port; 700 struct timespec64 ts; 701 unsigned long flags; 702 u32 val, id, txport; 703 704 val = ocelot_read(ocelot, SYS_PTP_STATUS); 705 706 /* Check if a timestamp can be retrieved */ 707 if (!(val & SYS_PTP_STATUS_PTP_MESS_VLD)) 708 break; 709 710 WARN_ON(val & SYS_PTP_STATUS_PTP_OVFL); 711 712 /* Retrieve the ts ID and Tx port */ 713 id = SYS_PTP_STATUS_PTP_MESS_ID_X(val); 714 txport = SYS_PTP_STATUS_PTP_MESS_TXPORT_X(val); 715 716 /* Retrieve its associated skb */ 717 port = ocelot->ports[txport]; 718 719 spin_lock_irqsave(&port->tx_skbs.lock, flags); 720 721 skb_queue_walk_safe(&port->tx_skbs, skb, skb_tmp) { 722 if (OCELOT_SKB_CB(skb)->ts_id != id) 723 continue; 724 __skb_unlink(skb, &port->tx_skbs); 725 skb_match = skb; 726 break; 727 } 728 729 spin_unlock_irqrestore(&port->tx_skbs.lock, flags); 730 731 /* Get the h/w timestamp */ 732 ocelot_get_hwtimestamp(ocelot, &ts); 733 734 if (unlikely(!skb_match)) 735 continue; 736 737 /* Set the timestamp into the skb */ 738 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 739 shhwtstamps.hwtstamp = ktime_set(ts.tv_sec, ts.tv_nsec); 740 skb_complete_tx_timestamp(skb_match, &shhwtstamps); 741 742 /* Next ts */ 743 ocelot_write(ocelot, SYS_PTP_NXT_PTP_NXT, SYS_PTP_NXT); 744 } 745 } 746 EXPORT_SYMBOL(ocelot_get_txtstamp); 747 748 static int ocelot_rx_frame_word(struct ocelot *ocelot, u8 grp, bool ifh, 749 u32 *rval) 750 { 751 u32 bytes_valid, val; 752 753 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 754 if (val == XTR_NOT_READY) { 755 if (ifh) 756 return -EIO; 757 758 do { 759 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 760 } while (val == XTR_NOT_READY); 761 } 762 763 switch (val) { 764 case XTR_ABORT: 765 return -EIO; 766 case XTR_EOF_0: 767 case XTR_EOF_1: 768 case XTR_EOF_2: 769 case XTR_EOF_3: 770 case XTR_PRUNED: 771 bytes_valid = XTR_VALID_BYTES(val); 772 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 773 if (val == XTR_ESCAPE) 774 *rval = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 775 else 776 *rval = val; 777 778 return bytes_valid; 779 case XTR_ESCAPE: 780 *rval = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 781 782 return 4; 783 default: 784 *rval = val; 785 786 return 4; 787 } 788 } 789 790 static int ocelot_xtr_poll_xfh(struct ocelot *ocelot, int grp, u32 *xfh) 791 { 792 int i, err = 0; 793 794 for (i = 0; i < OCELOT_TAG_LEN / 4; i++) { 795 err = ocelot_rx_frame_word(ocelot, grp, true, &xfh[i]); 796 if (err != 4) 797 return (err < 0) ? err : -EIO; 798 } 799 800 return 0; 801 } 802 803 int ocelot_xtr_poll_frame(struct ocelot *ocelot, int grp, struct sk_buff **nskb) 804 { 805 struct skb_shared_hwtstamps *shhwtstamps; 806 u64 tod_in_ns, full_ts_in_ns; 807 u64 timestamp, src_port, len; 808 u32 xfh[OCELOT_TAG_LEN / 4]; 809 struct net_device *dev; 810 struct timespec64 ts; 811 struct sk_buff *skb; 812 int sz, buf_len; 813 u32 val, *buf; 814 int err; 815 816 err = ocelot_xtr_poll_xfh(ocelot, grp, xfh); 817 if (err) 818 return err; 819 820 ocelot_xfh_get_src_port(xfh, &src_port); 821 ocelot_xfh_get_len(xfh, &len); 822 ocelot_xfh_get_rew_val(xfh, ×tamp); 823 824 if (WARN_ON(src_port >= ocelot->num_phys_ports)) 825 return -EINVAL; 826 827 dev = ocelot->ops->port_to_netdev(ocelot, src_port); 828 if (!dev) 829 return -EINVAL; 830 831 skb = netdev_alloc_skb(dev, len); 832 if (unlikely(!skb)) { 833 netdev_err(dev, "Unable to allocate sk_buff\n"); 834 return -ENOMEM; 835 } 836 837 buf_len = len - ETH_FCS_LEN; 838 buf = (u32 *)skb_put(skb, buf_len); 839 840 len = 0; 841 do { 842 sz = ocelot_rx_frame_word(ocelot, grp, false, &val); 843 if (sz < 0) { 844 err = sz; 845 goto out_free_skb; 846 } 847 *buf++ = val; 848 len += sz; 849 } while (len < buf_len); 850 851 /* Read the FCS */ 852 sz = ocelot_rx_frame_word(ocelot, grp, false, &val); 853 if (sz < 0) { 854 err = sz; 855 goto out_free_skb; 856 } 857 858 /* Update the statistics if part of the FCS was read before */ 859 len -= ETH_FCS_LEN - sz; 860 861 if (unlikely(dev->features & NETIF_F_RXFCS)) { 862 buf = (u32 *)skb_put(skb, ETH_FCS_LEN); 863 *buf = val; 864 } 865 866 if (ocelot->ptp) { 867 ocelot_ptp_gettime64(&ocelot->ptp_info, &ts); 868 869 tod_in_ns = ktime_set(ts.tv_sec, ts.tv_nsec); 870 if ((tod_in_ns & 0xffffffff) < timestamp) 871 full_ts_in_ns = (((tod_in_ns >> 32) - 1) << 32) | 872 timestamp; 873 else 874 full_ts_in_ns = (tod_in_ns & GENMASK_ULL(63, 32)) | 875 timestamp; 876 877 shhwtstamps = skb_hwtstamps(skb); 878 memset(shhwtstamps, 0, sizeof(struct skb_shared_hwtstamps)); 879 shhwtstamps->hwtstamp = full_ts_in_ns; 880 } 881 882 /* Everything we see on an interface that is in the HW bridge 883 * has already been forwarded. 884 */ 885 if (ocelot->ports[src_port]->bridge) 886 skb->offload_fwd_mark = 1; 887 888 skb->protocol = eth_type_trans(skb, dev); 889 890 *nskb = skb; 891 892 return 0; 893 894 out_free_skb: 895 kfree_skb(skb); 896 return err; 897 } 898 EXPORT_SYMBOL(ocelot_xtr_poll_frame); 899 900 bool ocelot_can_inject(struct ocelot *ocelot, int grp) 901 { 902 u32 val = ocelot_read(ocelot, QS_INJ_STATUS); 903 904 if (!(val & QS_INJ_STATUS_FIFO_RDY(BIT(grp)))) 905 return false; 906 if (val & QS_INJ_STATUS_WMARK_REACHED(BIT(grp))) 907 return false; 908 909 return true; 910 } 911 EXPORT_SYMBOL(ocelot_can_inject); 912 913 void ocelot_port_inject_frame(struct ocelot *ocelot, int port, int grp, 914 u32 rew_op, struct sk_buff *skb) 915 { 916 u32 ifh[OCELOT_TAG_LEN / 4] = {0}; 917 unsigned int i, count, last; 918 919 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) | 920 QS_INJ_CTRL_SOF, QS_INJ_CTRL, grp); 921 922 ocelot_ifh_set_bypass(ifh, 1); 923 ocelot_ifh_set_dest(ifh, BIT_ULL(port)); 924 ocelot_ifh_set_tag_type(ifh, IFH_TAG_TYPE_C); 925 ocelot_ifh_set_vid(ifh, skb_vlan_tag_get(skb)); 926 ocelot_ifh_set_rew_op(ifh, rew_op); 927 928 for (i = 0; i < OCELOT_TAG_LEN / 4; i++) 929 ocelot_write_rix(ocelot, ifh[i], QS_INJ_WR, grp); 930 931 count = DIV_ROUND_UP(skb->len, 4); 932 last = skb->len % 4; 933 for (i = 0; i < count; i++) 934 ocelot_write_rix(ocelot, ((u32 *)skb->data)[i], QS_INJ_WR, grp); 935 936 /* Add padding */ 937 while (i < (OCELOT_BUFFER_CELL_SZ / 4)) { 938 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp); 939 i++; 940 } 941 942 /* Indicate EOF and valid bytes in last word */ 943 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) | 944 QS_INJ_CTRL_VLD_BYTES(skb->len < OCELOT_BUFFER_CELL_SZ ? 0 : last) | 945 QS_INJ_CTRL_EOF, 946 QS_INJ_CTRL, grp); 947 948 /* Add dummy CRC */ 949 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp); 950 skb_tx_timestamp(skb); 951 952 skb->dev->stats.tx_packets++; 953 skb->dev->stats.tx_bytes += skb->len; 954 } 955 EXPORT_SYMBOL(ocelot_port_inject_frame); 956 957 void ocelot_drain_cpu_queue(struct ocelot *ocelot, int grp) 958 { 959 while (ocelot_read(ocelot, QS_XTR_DATA_PRESENT) & BIT(grp)) 960 ocelot_read_rix(ocelot, QS_XTR_RD, grp); 961 } 962 EXPORT_SYMBOL(ocelot_drain_cpu_queue); 963 964 int ocelot_fdb_add(struct ocelot *ocelot, int port, 965 const unsigned char *addr, u16 vid) 966 { 967 int pgid = port; 968 969 if (port == ocelot->npi) 970 pgid = PGID_CPU; 971 972 return ocelot_mact_learn(ocelot, pgid, addr, vid, ENTRYTYPE_LOCKED); 973 } 974 EXPORT_SYMBOL(ocelot_fdb_add); 975 976 int ocelot_fdb_del(struct ocelot *ocelot, int port, 977 const unsigned char *addr, u16 vid) 978 { 979 return ocelot_mact_forget(ocelot, addr, vid); 980 } 981 EXPORT_SYMBOL(ocelot_fdb_del); 982 983 int ocelot_port_fdb_do_dump(const unsigned char *addr, u16 vid, 984 bool is_static, void *data) 985 { 986 struct ocelot_dump_ctx *dump = data; 987 u32 portid = NETLINK_CB(dump->cb->skb).portid; 988 u32 seq = dump->cb->nlh->nlmsg_seq; 989 struct nlmsghdr *nlh; 990 struct ndmsg *ndm; 991 992 if (dump->idx < dump->cb->args[2]) 993 goto skip; 994 995 nlh = nlmsg_put(dump->skb, portid, seq, RTM_NEWNEIGH, 996 sizeof(*ndm), NLM_F_MULTI); 997 if (!nlh) 998 return -EMSGSIZE; 999 1000 ndm = nlmsg_data(nlh); 1001 ndm->ndm_family = AF_BRIDGE; 1002 ndm->ndm_pad1 = 0; 1003 ndm->ndm_pad2 = 0; 1004 ndm->ndm_flags = NTF_SELF; 1005 ndm->ndm_type = 0; 1006 ndm->ndm_ifindex = dump->dev->ifindex; 1007 ndm->ndm_state = is_static ? NUD_NOARP : NUD_REACHABLE; 1008 1009 if (nla_put(dump->skb, NDA_LLADDR, ETH_ALEN, addr)) 1010 goto nla_put_failure; 1011 1012 if (vid && nla_put_u16(dump->skb, NDA_VLAN, vid)) 1013 goto nla_put_failure; 1014 1015 nlmsg_end(dump->skb, nlh); 1016 1017 skip: 1018 dump->idx++; 1019 return 0; 1020 1021 nla_put_failure: 1022 nlmsg_cancel(dump->skb, nlh); 1023 return -EMSGSIZE; 1024 } 1025 EXPORT_SYMBOL(ocelot_port_fdb_do_dump); 1026 1027 static int ocelot_mact_read(struct ocelot *ocelot, int port, int row, int col, 1028 struct ocelot_mact_entry *entry) 1029 { 1030 u32 val, dst, macl, mach; 1031 char mac[ETH_ALEN]; 1032 1033 /* Set row and column to read from */ 1034 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_M_INDEX, row); 1035 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_BUCKET, col); 1036 1037 /* Issue a read command */ 1038 ocelot_write(ocelot, 1039 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_READ), 1040 ANA_TABLES_MACACCESS); 1041 1042 if (ocelot_mact_wait_for_completion(ocelot)) 1043 return -ETIMEDOUT; 1044 1045 /* Read the entry flags */ 1046 val = ocelot_read(ocelot, ANA_TABLES_MACACCESS); 1047 if (!(val & ANA_TABLES_MACACCESS_VALID)) 1048 return -EINVAL; 1049 1050 /* If the entry read has another port configured as its destination, 1051 * do not report it. 1052 */ 1053 dst = (val & ANA_TABLES_MACACCESS_DEST_IDX_M) >> 3; 1054 if (dst != port) 1055 return -EINVAL; 1056 1057 /* Get the entry's MAC address and VLAN id */ 1058 macl = ocelot_read(ocelot, ANA_TABLES_MACLDATA); 1059 mach = ocelot_read(ocelot, ANA_TABLES_MACHDATA); 1060 1061 mac[0] = (mach >> 8) & 0xff; 1062 mac[1] = (mach >> 0) & 0xff; 1063 mac[2] = (macl >> 24) & 0xff; 1064 mac[3] = (macl >> 16) & 0xff; 1065 mac[4] = (macl >> 8) & 0xff; 1066 mac[5] = (macl >> 0) & 0xff; 1067 1068 entry->vid = (mach >> 16) & 0xfff; 1069 ether_addr_copy(entry->mac, mac); 1070 1071 return 0; 1072 } 1073 1074 int ocelot_fdb_dump(struct ocelot *ocelot, int port, 1075 dsa_fdb_dump_cb_t *cb, void *data) 1076 { 1077 int i, j; 1078 1079 /* Loop through all the mac tables entries. */ 1080 for (i = 0; i < ocelot->num_mact_rows; i++) { 1081 for (j = 0; j < 4; j++) { 1082 struct ocelot_mact_entry entry; 1083 bool is_static; 1084 int ret; 1085 1086 ret = ocelot_mact_read(ocelot, port, i, j, &entry); 1087 /* If the entry is invalid (wrong port, invalid...), 1088 * skip it. 1089 */ 1090 if (ret == -EINVAL) 1091 continue; 1092 else if (ret) 1093 return ret; 1094 1095 is_static = (entry.type == ENTRYTYPE_LOCKED); 1096 1097 ret = cb(entry.mac, entry.vid, is_static, data); 1098 if (ret) 1099 return ret; 1100 } 1101 } 1102 1103 return 0; 1104 } 1105 EXPORT_SYMBOL(ocelot_fdb_dump); 1106 1107 int ocelot_hwstamp_get(struct ocelot *ocelot, int port, struct ifreq *ifr) 1108 { 1109 return copy_to_user(ifr->ifr_data, &ocelot->hwtstamp_config, 1110 sizeof(ocelot->hwtstamp_config)) ? -EFAULT : 0; 1111 } 1112 EXPORT_SYMBOL(ocelot_hwstamp_get); 1113 1114 int ocelot_hwstamp_set(struct ocelot *ocelot, int port, struct ifreq *ifr) 1115 { 1116 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1117 struct hwtstamp_config cfg; 1118 1119 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg))) 1120 return -EFAULT; 1121 1122 /* reserved for future extensions */ 1123 if (cfg.flags) 1124 return -EINVAL; 1125 1126 /* Tx type sanity check */ 1127 switch (cfg.tx_type) { 1128 case HWTSTAMP_TX_ON: 1129 ocelot_port->ptp_cmd = IFH_REW_OP_TWO_STEP_PTP; 1130 break; 1131 case HWTSTAMP_TX_ONESTEP_SYNC: 1132 /* IFH_REW_OP_ONE_STEP_PTP updates the correctional field, we 1133 * need to update the origin time. 1134 */ 1135 ocelot_port->ptp_cmd = IFH_REW_OP_ORIGIN_PTP; 1136 break; 1137 case HWTSTAMP_TX_OFF: 1138 ocelot_port->ptp_cmd = 0; 1139 break; 1140 default: 1141 return -ERANGE; 1142 } 1143 1144 mutex_lock(&ocelot->ptp_lock); 1145 1146 switch (cfg.rx_filter) { 1147 case HWTSTAMP_FILTER_NONE: 1148 break; 1149 case HWTSTAMP_FILTER_ALL: 1150 case HWTSTAMP_FILTER_SOME: 1151 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 1152 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 1153 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 1154 case HWTSTAMP_FILTER_NTP_ALL: 1155 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 1156 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 1157 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 1158 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 1159 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 1160 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 1161 case HWTSTAMP_FILTER_PTP_V2_EVENT: 1162 case HWTSTAMP_FILTER_PTP_V2_SYNC: 1163 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 1164 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 1165 break; 1166 default: 1167 mutex_unlock(&ocelot->ptp_lock); 1168 return -ERANGE; 1169 } 1170 1171 /* Commit back the result & save it */ 1172 memcpy(&ocelot->hwtstamp_config, &cfg, sizeof(cfg)); 1173 mutex_unlock(&ocelot->ptp_lock); 1174 1175 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 1176 } 1177 EXPORT_SYMBOL(ocelot_hwstamp_set); 1178 1179 void ocelot_get_strings(struct ocelot *ocelot, int port, u32 sset, u8 *data) 1180 { 1181 int i; 1182 1183 if (sset != ETH_SS_STATS) 1184 return; 1185 1186 for (i = 0; i < ocelot->num_stats; i++) 1187 memcpy(data + i * ETH_GSTRING_LEN, ocelot->stats_layout[i].name, 1188 ETH_GSTRING_LEN); 1189 } 1190 EXPORT_SYMBOL(ocelot_get_strings); 1191 1192 static void ocelot_update_stats(struct ocelot *ocelot) 1193 { 1194 int i, j; 1195 1196 mutex_lock(&ocelot->stats_lock); 1197 1198 for (i = 0; i < ocelot->num_phys_ports; i++) { 1199 /* Configure the port to read the stats from */ 1200 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(i), SYS_STAT_CFG); 1201 1202 for (j = 0; j < ocelot->num_stats; j++) { 1203 u32 val; 1204 unsigned int idx = i * ocelot->num_stats + j; 1205 1206 val = ocelot_read_rix(ocelot, SYS_COUNT_RX_OCTETS, 1207 ocelot->stats_layout[j].offset); 1208 1209 if (val < (ocelot->stats[idx] & U32_MAX)) 1210 ocelot->stats[idx] += (u64)1 << 32; 1211 1212 ocelot->stats[idx] = (ocelot->stats[idx] & 1213 ~(u64)U32_MAX) + val; 1214 } 1215 } 1216 1217 mutex_unlock(&ocelot->stats_lock); 1218 } 1219 1220 static void ocelot_check_stats_work(struct work_struct *work) 1221 { 1222 struct delayed_work *del_work = to_delayed_work(work); 1223 struct ocelot *ocelot = container_of(del_work, struct ocelot, 1224 stats_work); 1225 1226 ocelot_update_stats(ocelot); 1227 1228 queue_delayed_work(ocelot->stats_queue, &ocelot->stats_work, 1229 OCELOT_STATS_CHECK_DELAY); 1230 } 1231 1232 void ocelot_get_ethtool_stats(struct ocelot *ocelot, int port, u64 *data) 1233 { 1234 int i; 1235 1236 /* check and update now */ 1237 ocelot_update_stats(ocelot); 1238 1239 /* Copy all counters */ 1240 for (i = 0; i < ocelot->num_stats; i++) 1241 *data++ = ocelot->stats[port * ocelot->num_stats + i]; 1242 } 1243 EXPORT_SYMBOL(ocelot_get_ethtool_stats); 1244 1245 int ocelot_get_sset_count(struct ocelot *ocelot, int port, int sset) 1246 { 1247 if (sset != ETH_SS_STATS) 1248 return -EOPNOTSUPP; 1249 1250 return ocelot->num_stats; 1251 } 1252 EXPORT_SYMBOL(ocelot_get_sset_count); 1253 1254 int ocelot_get_ts_info(struct ocelot *ocelot, int port, 1255 struct ethtool_ts_info *info) 1256 { 1257 info->phc_index = ocelot->ptp_clock ? 1258 ptp_clock_index(ocelot->ptp_clock) : -1; 1259 if (info->phc_index == -1) { 1260 info->so_timestamping |= SOF_TIMESTAMPING_TX_SOFTWARE | 1261 SOF_TIMESTAMPING_RX_SOFTWARE | 1262 SOF_TIMESTAMPING_SOFTWARE; 1263 return 0; 1264 } 1265 info->so_timestamping |= SOF_TIMESTAMPING_TX_SOFTWARE | 1266 SOF_TIMESTAMPING_RX_SOFTWARE | 1267 SOF_TIMESTAMPING_SOFTWARE | 1268 SOF_TIMESTAMPING_TX_HARDWARE | 1269 SOF_TIMESTAMPING_RX_HARDWARE | 1270 SOF_TIMESTAMPING_RAW_HARDWARE; 1271 info->tx_types = BIT(HWTSTAMP_TX_OFF) | BIT(HWTSTAMP_TX_ON) | 1272 BIT(HWTSTAMP_TX_ONESTEP_SYNC); 1273 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) | BIT(HWTSTAMP_FILTER_ALL); 1274 1275 return 0; 1276 } 1277 EXPORT_SYMBOL(ocelot_get_ts_info); 1278 1279 static u32 ocelot_get_bond_mask(struct ocelot *ocelot, struct net_device *bond, 1280 bool only_active_ports) 1281 { 1282 u32 mask = 0; 1283 int port; 1284 1285 for (port = 0; port < ocelot->num_phys_ports; port++) { 1286 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1287 1288 if (!ocelot_port) 1289 continue; 1290 1291 if (ocelot_port->bond == bond) { 1292 if (only_active_ports && !ocelot_port->lag_tx_active) 1293 continue; 1294 1295 mask |= BIT(port); 1296 } 1297 } 1298 1299 return mask; 1300 } 1301 1302 static u32 ocelot_get_bridge_fwd_mask(struct ocelot *ocelot, 1303 struct net_device *bridge) 1304 { 1305 u32 mask = 0; 1306 int port; 1307 1308 for (port = 0; port < ocelot->num_phys_ports; port++) { 1309 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1310 1311 if (!ocelot_port) 1312 continue; 1313 1314 if (ocelot_port->stp_state == BR_STATE_FORWARDING && 1315 ocelot_port->bridge == bridge) 1316 mask |= BIT(port); 1317 } 1318 1319 return mask; 1320 } 1321 1322 static u32 ocelot_get_dsa_8021q_cpu_mask(struct ocelot *ocelot) 1323 { 1324 u32 mask = 0; 1325 int port; 1326 1327 for (port = 0; port < ocelot->num_phys_ports; port++) { 1328 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1329 1330 if (!ocelot_port) 1331 continue; 1332 1333 if (ocelot_port->is_dsa_8021q_cpu) 1334 mask |= BIT(port); 1335 } 1336 1337 return mask; 1338 } 1339 1340 void ocelot_apply_bridge_fwd_mask(struct ocelot *ocelot) 1341 { 1342 unsigned long cpu_fwd_mask; 1343 int port; 1344 1345 /* If a DSA tag_8021q CPU exists, it needs to be included in the 1346 * regular forwarding path of the front ports regardless of whether 1347 * those are bridged or standalone. 1348 * If DSA tag_8021q is not used, this returns 0, which is fine because 1349 * the hardware-based CPU port module can be a destination for packets 1350 * even if it isn't part of PGID_SRC. 1351 */ 1352 cpu_fwd_mask = ocelot_get_dsa_8021q_cpu_mask(ocelot); 1353 1354 /* Apply FWD mask. The loop is needed to add/remove the current port as 1355 * a source for the other ports. 1356 */ 1357 for (port = 0; port < ocelot->num_phys_ports; port++) { 1358 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1359 unsigned long mask; 1360 1361 if (!ocelot_port) { 1362 /* Unused ports can't send anywhere */ 1363 mask = 0; 1364 } else if (ocelot_port->is_dsa_8021q_cpu) { 1365 /* The DSA tag_8021q CPU ports need to be able to 1366 * forward packets to all other ports except for 1367 * themselves 1368 */ 1369 mask = GENMASK(ocelot->num_phys_ports - 1, 0); 1370 mask &= ~cpu_fwd_mask; 1371 } else if (ocelot_port->bridge) { 1372 struct net_device *bridge = ocelot_port->bridge; 1373 struct net_device *bond = ocelot_port->bond; 1374 1375 mask = ocelot_get_bridge_fwd_mask(ocelot, bridge); 1376 mask |= cpu_fwd_mask; 1377 mask &= ~BIT(port); 1378 if (bond) { 1379 mask &= ~ocelot_get_bond_mask(ocelot, bond, 1380 false); 1381 } 1382 } else { 1383 /* Standalone ports forward only to DSA tag_8021q CPU 1384 * ports (if those exist), or to the hardware CPU port 1385 * module otherwise. 1386 */ 1387 mask = cpu_fwd_mask; 1388 } 1389 1390 ocelot_write_rix(ocelot, mask, ANA_PGID_PGID, PGID_SRC + port); 1391 } 1392 } 1393 EXPORT_SYMBOL(ocelot_apply_bridge_fwd_mask); 1394 1395 void ocelot_bridge_stp_state_set(struct ocelot *ocelot, int port, u8 state) 1396 { 1397 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1398 u32 learn_ena = 0; 1399 1400 ocelot_port->stp_state = state; 1401 1402 if ((state == BR_STATE_LEARNING || state == BR_STATE_FORWARDING) && 1403 ocelot_port->learn_ena) 1404 learn_ena = ANA_PORT_PORT_CFG_LEARN_ENA; 1405 1406 ocelot_rmw_gix(ocelot, learn_ena, ANA_PORT_PORT_CFG_LEARN_ENA, 1407 ANA_PORT_PORT_CFG, port); 1408 1409 ocelot_apply_bridge_fwd_mask(ocelot); 1410 } 1411 EXPORT_SYMBOL(ocelot_bridge_stp_state_set); 1412 1413 void ocelot_set_ageing_time(struct ocelot *ocelot, unsigned int msecs) 1414 { 1415 unsigned int age_period = ANA_AUTOAGE_AGE_PERIOD(msecs / 2000); 1416 1417 /* Setting AGE_PERIOD to zero effectively disables automatic aging, 1418 * which is clearly not what our intention is. So avoid that. 1419 */ 1420 if (!age_period) 1421 age_period = 1; 1422 1423 ocelot_rmw(ocelot, age_period, ANA_AUTOAGE_AGE_PERIOD_M, ANA_AUTOAGE); 1424 } 1425 EXPORT_SYMBOL(ocelot_set_ageing_time); 1426 1427 static struct ocelot_multicast *ocelot_multicast_get(struct ocelot *ocelot, 1428 const unsigned char *addr, 1429 u16 vid) 1430 { 1431 struct ocelot_multicast *mc; 1432 1433 list_for_each_entry(mc, &ocelot->multicast, list) { 1434 if (ether_addr_equal(mc->addr, addr) && mc->vid == vid) 1435 return mc; 1436 } 1437 1438 return NULL; 1439 } 1440 1441 static enum macaccess_entry_type ocelot_classify_mdb(const unsigned char *addr) 1442 { 1443 if (addr[0] == 0x01 && addr[1] == 0x00 && addr[2] == 0x5e) 1444 return ENTRYTYPE_MACv4; 1445 if (addr[0] == 0x33 && addr[1] == 0x33) 1446 return ENTRYTYPE_MACv6; 1447 return ENTRYTYPE_LOCKED; 1448 } 1449 1450 static struct ocelot_pgid *ocelot_pgid_alloc(struct ocelot *ocelot, int index, 1451 unsigned long ports) 1452 { 1453 struct ocelot_pgid *pgid; 1454 1455 pgid = kzalloc(sizeof(*pgid), GFP_KERNEL); 1456 if (!pgid) 1457 return ERR_PTR(-ENOMEM); 1458 1459 pgid->ports = ports; 1460 pgid->index = index; 1461 refcount_set(&pgid->refcount, 1); 1462 list_add_tail(&pgid->list, &ocelot->pgids); 1463 1464 return pgid; 1465 } 1466 1467 static void ocelot_pgid_free(struct ocelot *ocelot, struct ocelot_pgid *pgid) 1468 { 1469 if (!refcount_dec_and_test(&pgid->refcount)) 1470 return; 1471 1472 list_del(&pgid->list); 1473 kfree(pgid); 1474 } 1475 1476 static struct ocelot_pgid *ocelot_mdb_get_pgid(struct ocelot *ocelot, 1477 const struct ocelot_multicast *mc) 1478 { 1479 struct ocelot_pgid *pgid; 1480 int index; 1481 1482 /* According to VSC7514 datasheet 3.9.1.5 IPv4 Multicast Entries and 1483 * 3.9.1.6 IPv6 Multicast Entries, "Instead of a lookup in the 1484 * destination mask table (PGID), the destination set is programmed as 1485 * part of the entry MAC address.", and the DEST_IDX is set to 0. 1486 */ 1487 if (mc->entry_type == ENTRYTYPE_MACv4 || 1488 mc->entry_type == ENTRYTYPE_MACv6) 1489 return ocelot_pgid_alloc(ocelot, 0, mc->ports); 1490 1491 list_for_each_entry(pgid, &ocelot->pgids, list) { 1492 /* When searching for a nonreserved multicast PGID, ignore the 1493 * dummy PGID of zero that we have for MACv4/MACv6 entries 1494 */ 1495 if (pgid->index && pgid->ports == mc->ports) { 1496 refcount_inc(&pgid->refcount); 1497 return pgid; 1498 } 1499 } 1500 1501 /* Search for a free index in the nonreserved multicast PGID area */ 1502 for_each_nonreserved_multicast_dest_pgid(ocelot, index) { 1503 bool used = false; 1504 1505 list_for_each_entry(pgid, &ocelot->pgids, list) { 1506 if (pgid->index == index) { 1507 used = true; 1508 break; 1509 } 1510 } 1511 1512 if (!used) 1513 return ocelot_pgid_alloc(ocelot, index, mc->ports); 1514 } 1515 1516 return ERR_PTR(-ENOSPC); 1517 } 1518 1519 static void ocelot_encode_ports_to_mdb(unsigned char *addr, 1520 struct ocelot_multicast *mc) 1521 { 1522 ether_addr_copy(addr, mc->addr); 1523 1524 if (mc->entry_type == ENTRYTYPE_MACv4) { 1525 addr[0] = 0; 1526 addr[1] = mc->ports >> 8; 1527 addr[2] = mc->ports & 0xff; 1528 } else if (mc->entry_type == ENTRYTYPE_MACv6) { 1529 addr[0] = mc->ports >> 8; 1530 addr[1] = mc->ports & 0xff; 1531 } 1532 } 1533 1534 int ocelot_port_mdb_add(struct ocelot *ocelot, int port, 1535 const struct switchdev_obj_port_mdb *mdb) 1536 { 1537 unsigned char addr[ETH_ALEN]; 1538 struct ocelot_multicast *mc; 1539 struct ocelot_pgid *pgid; 1540 u16 vid = mdb->vid; 1541 1542 if (port == ocelot->npi) 1543 port = ocelot->num_phys_ports; 1544 1545 mc = ocelot_multicast_get(ocelot, mdb->addr, vid); 1546 if (!mc) { 1547 /* New entry */ 1548 mc = devm_kzalloc(ocelot->dev, sizeof(*mc), GFP_KERNEL); 1549 if (!mc) 1550 return -ENOMEM; 1551 1552 mc->entry_type = ocelot_classify_mdb(mdb->addr); 1553 ether_addr_copy(mc->addr, mdb->addr); 1554 mc->vid = vid; 1555 1556 list_add_tail(&mc->list, &ocelot->multicast); 1557 } else { 1558 /* Existing entry. Clean up the current port mask from 1559 * hardware now, because we'll be modifying it. 1560 */ 1561 ocelot_pgid_free(ocelot, mc->pgid); 1562 ocelot_encode_ports_to_mdb(addr, mc); 1563 ocelot_mact_forget(ocelot, addr, vid); 1564 } 1565 1566 mc->ports |= BIT(port); 1567 1568 pgid = ocelot_mdb_get_pgid(ocelot, mc); 1569 if (IS_ERR(pgid)) { 1570 dev_err(ocelot->dev, 1571 "Cannot allocate PGID for mdb %pM vid %d\n", 1572 mc->addr, mc->vid); 1573 devm_kfree(ocelot->dev, mc); 1574 return PTR_ERR(pgid); 1575 } 1576 mc->pgid = pgid; 1577 1578 ocelot_encode_ports_to_mdb(addr, mc); 1579 1580 if (mc->entry_type != ENTRYTYPE_MACv4 && 1581 mc->entry_type != ENTRYTYPE_MACv6) 1582 ocelot_write_rix(ocelot, pgid->ports, ANA_PGID_PGID, 1583 pgid->index); 1584 1585 return ocelot_mact_learn(ocelot, pgid->index, addr, vid, 1586 mc->entry_type); 1587 } 1588 EXPORT_SYMBOL(ocelot_port_mdb_add); 1589 1590 int ocelot_port_mdb_del(struct ocelot *ocelot, int port, 1591 const struct switchdev_obj_port_mdb *mdb) 1592 { 1593 unsigned char addr[ETH_ALEN]; 1594 struct ocelot_multicast *mc; 1595 struct ocelot_pgid *pgid; 1596 u16 vid = mdb->vid; 1597 1598 if (port == ocelot->npi) 1599 port = ocelot->num_phys_ports; 1600 1601 mc = ocelot_multicast_get(ocelot, mdb->addr, vid); 1602 if (!mc) 1603 return -ENOENT; 1604 1605 ocelot_encode_ports_to_mdb(addr, mc); 1606 ocelot_mact_forget(ocelot, addr, vid); 1607 1608 ocelot_pgid_free(ocelot, mc->pgid); 1609 mc->ports &= ~BIT(port); 1610 if (!mc->ports) { 1611 list_del(&mc->list); 1612 devm_kfree(ocelot->dev, mc); 1613 return 0; 1614 } 1615 1616 /* We have a PGID with fewer ports now */ 1617 pgid = ocelot_mdb_get_pgid(ocelot, mc); 1618 if (IS_ERR(pgid)) 1619 return PTR_ERR(pgid); 1620 mc->pgid = pgid; 1621 1622 ocelot_encode_ports_to_mdb(addr, mc); 1623 1624 if (mc->entry_type != ENTRYTYPE_MACv4 && 1625 mc->entry_type != ENTRYTYPE_MACv6) 1626 ocelot_write_rix(ocelot, pgid->ports, ANA_PGID_PGID, 1627 pgid->index); 1628 1629 return ocelot_mact_learn(ocelot, pgid->index, addr, vid, 1630 mc->entry_type); 1631 } 1632 EXPORT_SYMBOL(ocelot_port_mdb_del); 1633 1634 void ocelot_port_bridge_join(struct ocelot *ocelot, int port, 1635 struct net_device *bridge) 1636 { 1637 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1638 1639 ocelot_port->bridge = bridge; 1640 1641 ocelot_apply_bridge_fwd_mask(ocelot); 1642 } 1643 EXPORT_SYMBOL(ocelot_port_bridge_join); 1644 1645 void ocelot_port_bridge_leave(struct ocelot *ocelot, int port, 1646 struct net_device *bridge) 1647 { 1648 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1649 struct ocelot_vlan pvid = {0}, native_vlan = {0}; 1650 1651 ocelot_port->bridge = NULL; 1652 1653 ocelot_port_set_pvid(ocelot, port, pvid); 1654 ocelot_port_set_native_vlan(ocelot, port, native_vlan); 1655 ocelot_apply_bridge_fwd_mask(ocelot); 1656 } 1657 EXPORT_SYMBOL(ocelot_port_bridge_leave); 1658 1659 static void ocelot_set_aggr_pgids(struct ocelot *ocelot) 1660 { 1661 unsigned long visited = GENMASK(ocelot->num_phys_ports - 1, 0); 1662 int i, port, lag; 1663 1664 /* Reset destination and aggregation PGIDS */ 1665 for_each_unicast_dest_pgid(ocelot, port) 1666 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port); 1667 1668 for_each_aggr_pgid(ocelot, i) 1669 ocelot_write_rix(ocelot, GENMASK(ocelot->num_phys_ports - 1, 0), 1670 ANA_PGID_PGID, i); 1671 1672 /* The visited ports bitmask holds the list of ports offloading any 1673 * bonding interface. Initially we mark all these ports as unvisited, 1674 * then every time we visit a port in this bitmask, we know that it is 1675 * the lowest numbered port, i.e. the one whose logical ID == physical 1676 * port ID == LAG ID. So we mark as visited all further ports in the 1677 * bitmask that are offloading the same bonding interface. This way, 1678 * we set up the aggregation PGIDs only once per bonding interface. 1679 */ 1680 for (port = 0; port < ocelot->num_phys_ports; port++) { 1681 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1682 1683 if (!ocelot_port || !ocelot_port->bond) 1684 continue; 1685 1686 visited &= ~BIT(port); 1687 } 1688 1689 /* Now, set PGIDs for each active LAG */ 1690 for (lag = 0; lag < ocelot->num_phys_ports; lag++) { 1691 struct net_device *bond = ocelot->ports[lag]->bond; 1692 int num_active_ports = 0; 1693 unsigned long bond_mask; 1694 u8 aggr_idx[16]; 1695 1696 if (!bond || (visited & BIT(lag))) 1697 continue; 1698 1699 bond_mask = ocelot_get_bond_mask(ocelot, bond, true); 1700 1701 for_each_set_bit(port, &bond_mask, ocelot->num_phys_ports) { 1702 // Destination mask 1703 ocelot_write_rix(ocelot, bond_mask, 1704 ANA_PGID_PGID, port); 1705 aggr_idx[num_active_ports++] = port; 1706 } 1707 1708 for_each_aggr_pgid(ocelot, i) { 1709 u32 ac; 1710 1711 ac = ocelot_read_rix(ocelot, ANA_PGID_PGID, i); 1712 ac &= ~bond_mask; 1713 /* Don't do division by zero if there was no active 1714 * port. Just make all aggregation codes zero. 1715 */ 1716 if (num_active_ports) 1717 ac |= BIT(aggr_idx[i % num_active_ports]); 1718 ocelot_write_rix(ocelot, ac, ANA_PGID_PGID, i); 1719 } 1720 1721 /* Mark all ports in the same LAG as visited to avoid applying 1722 * the same config again. 1723 */ 1724 for (port = lag; port < ocelot->num_phys_ports; port++) { 1725 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1726 1727 if (!ocelot_port) 1728 continue; 1729 1730 if (ocelot_port->bond == bond) 1731 visited |= BIT(port); 1732 } 1733 } 1734 } 1735 1736 /* When offloading a bonding interface, the switch ports configured under the 1737 * same bond must have the same logical port ID, equal to the physical port ID 1738 * of the lowest numbered physical port in that bond. Otherwise, in standalone/ 1739 * bridged mode, each port has a logical port ID equal to its physical port ID. 1740 */ 1741 static void ocelot_setup_logical_port_ids(struct ocelot *ocelot) 1742 { 1743 int port; 1744 1745 for (port = 0; port < ocelot->num_phys_ports; port++) { 1746 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1747 struct net_device *bond; 1748 1749 if (!ocelot_port) 1750 continue; 1751 1752 bond = ocelot_port->bond; 1753 if (bond) { 1754 int lag = __ffs(ocelot_get_bond_mask(ocelot, bond, 1755 false)); 1756 1757 ocelot_rmw_gix(ocelot, 1758 ANA_PORT_PORT_CFG_PORTID_VAL(lag), 1759 ANA_PORT_PORT_CFG_PORTID_VAL_M, 1760 ANA_PORT_PORT_CFG, port); 1761 } else { 1762 ocelot_rmw_gix(ocelot, 1763 ANA_PORT_PORT_CFG_PORTID_VAL(port), 1764 ANA_PORT_PORT_CFG_PORTID_VAL_M, 1765 ANA_PORT_PORT_CFG, port); 1766 } 1767 } 1768 } 1769 1770 int ocelot_port_lag_join(struct ocelot *ocelot, int port, 1771 struct net_device *bond, 1772 struct netdev_lag_upper_info *info) 1773 { 1774 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) 1775 return -EOPNOTSUPP; 1776 1777 ocelot->ports[port]->bond = bond; 1778 1779 ocelot_setup_logical_port_ids(ocelot); 1780 ocelot_apply_bridge_fwd_mask(ocelot); 1781 ocelot_set_aggr_pgids(ocelot); 1782 1783 return 0; 1784 } 1785 EXPORT_SYMBOL(ocelot_port_lag_join); 1786 1787 void ocelot_port_lag_leave(struct ocelot *ocelot, int port, 1788 struct net_device *bond) 1789 { 1790 ocelot->ports[port]->bond = NULL; 1791 1792 ocelot_setup_logical_port_ids(ocelot); 1793 ocelot_apply_bridge_fwd_mask(ocelot); 1794 ocelot_set_aggr_pgids(ocelot); 1795 } 1796 EXPORT_SYMBOL(ocelot_port_lag_leave); 1797 1798 void ocelot_port_lag_change(struct ocelot *ocelot, int port, bool lag_tx_active) 1799 { 1800 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1801 1802 ocelot_port->lag_tx_active = lag_tx_active; 1803 1804 /* Rebalance the LAGs */ 1805 ocelot_set_aggr_pgids(ocelot); 1806 } 1807 EXPORT_SYMBOL(ocelot_port_lag_change); 1808 1809 /* Configure the maximum SDU (L2 payload) on RX to the value specified in @sdu. 1810 * The length of VLAN tags is accounted for automatically via DEV_MAC_TAGS_CFG. 1811 * In the special case that it's the NPI port that we're configuring, the 1812 * length of the tag and optional prefix needs to be accounted for privately, 1813 * in order to be able to sustain communication at the requested @sdu. 1814 */ 1815 void ocelot_port_set_maxlen(struct ocelot *ocelot, int port, size_t sdu) 1816 { 1817 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1818 int maxlen = sdu + ETH_HLEN + ETH_FCS_LEN; 1819 int pause_start, pause_stop; 1820 int atop, atop_tot; 1821 1822 if (port == ocelot->npi) { 1823 maxlen += OCELOT_TAG_LEN; 1824 1825 if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_SHORT) 1826 maxlen += OCELOT_SHORT_PREFIX_LEN; 1827 else if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_LONG) 1828 maxlen += OCELOT_LONG_PREFIX_LEN; 1829 } 1830 1831 ocelot_port_writel(ocelot_port, maxlen, DEV_MAC_MAXLEN_CFG); 1832 1833 /* Set Pause watermark hysteresis */ 1834 pause_start = 6 * maxlen / OCELOT_BUFFER_CELL_SZ; 1835 pause_stop = 4 * maxlen / OCELOT_BUFFER_CELL_SZ; 1836 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_START, 1837 pause_start); 1838 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_STOP, 1839 pause_stop); 1840 1841 /* Tail dropping watermarks */ 1842 atop_tot = (ocelot->packet_buffer_size - 9 * maxlen) / 1843 OCELOT_BUFFER_CELL_SZ; 1844 atop = (9 * maxlen) / OCELOT_BUFFER_CELL_SZ; 1845 ocelot_write_rix(ocelot, ocelot->ops->wm_enc(atop), SYS_ATOP, port); 1846 ocelot_write(ocelot, ocelot->ops->wm_enc(atop_tot), SYS_ATOP_TOT_CFG); 1847 } 1848 EXPORT_SYMBOL(ocelot_port_set_maxlen); 1849 1850 int ocelot_get_max_mtu(struct ocelot *ocelot, int port) 1851 { 1852 int max_mtu = 65535 - ETH_HLEN - ETH_FCS_LEN; 1853 1854 if (port == ocelot->npi) { 1855 max_mtu -= OCELOT_TAG_LEN; 1856 1857 if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_SHORT) 1858 max_mtu -= OCELOT_SHORT_PREFIX_LEN; 1859 else if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_LONG) 1860 max_mtu -= OCELOT_LONG_PREFIX_LEN; 1861 } 1862 1863 return max_mtu; 1864 } 1865 EXPORT_SYMBOL(ocelot_get_max_mtu); 1866 1867 static void ocelot_port_set_learning(struct ocelot *ocelot, int port, 1868 bool enabled) 1869 { 1870 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1871 u32 val = 0; 1872 1873 if (enabled) 1874 val = ANA_PORT_PORT_CFG_LEARN_ENA; 1875 1876 ocelot_rmw_gix(ocelot, val, ANA_PORT_PORT_CFG_LEARN_ENA, 1877 ANA_PORT_PORT_CFG, port); 1878 1879 ocelot_port->learn_ena = enabled; 1880 } 1881 1882 static void ocelot_port_set_ucast_flood(struct ocelot *ocelot, int port, 1883 bool enabled) 1884 { 1885 u32 val = 0; 1886 1887 if (enabled) 1888 val = BIT(port); 1889 1890 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_UC); 1891 } 1892 1893 static void ocelot_port_set_mcast_flood(struct ocelot *ocelot, int port, 1894 bool enabled) 1895 { 1896 u32 val = 0; 1897 1898 if (enabled) 1899 val = BIT(port); 1900 1901 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_MC); 1902 } 1903 1904 static void ocelot_port_set_bcast_flood(struct ocelot *ocelot, int port, 1905 bool enabled) 1906 { 1907 u32 val = 0; 1908 1909 if (enabled) 1910 val = BIT(port); 1911 1912 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_BC); 1913 } 1914 1915 int ocelot_port_pre_bridge_flags(struct ocelot *ocelot, int port, 1916 struct switchdev_brport_flags flags) 1917 { 1918 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | 1919 BR_BCAST_FLOOD)) 1920 return -EINVAL; 1921 1922 return 0; 1923 } 1924 EXPORT_SYMBOL(ocelot_port_pre_bridge_flags); 1925 1926 void ocelot_port_bridge_flags(struct ocelot *ocelot, int port, 1927 struct switchdev_brport_flags flags) 1928 { 1929 if (flags.mask & BR_LEARNING) 1930 ocelot_port_set_learning(ocelot, port, 1931 !!(flags.val & BR_LEARNING)); 1932 1933 if (flags.mask & BR_FLOOD) 1934 ocelot_port_set_ucast_flood(ocelot, port, 1935 !!(flags.val & BR_FLOOD)); 1936 1937 if (flags.mask & BR_MCAST_FLOOD) 1938 ocelot_port_set_mcast_flood(ocelot, port, 1939 !!(flags.val & BR_MCAST_FLOOD)); 1940 1941 if (flags.mask & BR_BCAST_FLOOD) 1942 ocelot_port_set_bcast_flood(ocelot, port, 1943 !!(flags.val & BR_BCAST_FLOOD)); 1944 } 1945 EXPORT_SYMBOL(ocelot_port_bridge_flags); 1946 1947 void ocelot_init_port(struct ocelot *ocelot, int port) 1948 { 1949 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1950 1951 skb_queue_head_init(&ocelot_port->tx_skbs); 1952 spin_lock_init(&ocelot_port->ts_id_lock); 1953 1954 /* Basic L2 initialization */ 1955 1956 /* Set MAC IFG Gaps 1957 * FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 0 1958 * !FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 5 1959 */ 1960 ocelot_port_writel(ocelot_port, DEV_MAC_IFG_CFG_TX_IFG(5), 1961 DEV_MAC_IFG_CFG); 1962 1963 /* Load seed (0) and set MAC HDX late collision */ 1964 ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67) | 1965 DEV_MAC_HDX_CFG_SEED_LOAD, 1966 DEV_MAC_HDX_CFG); 1967 mdelay(1); 1968 ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67), 1969 DEV_MAC_HDX_CFG); 1970 1971 /* Set Max Length and maximum tags allowed */ 1972 ocelot_port_set_maxlen(ocelot, port, ETH_DATA_LEN); 1973 ocelot_port_writel(ocelot_port, DEV_MAC_TAGS_CFG_TAG_ID(ETH_P_8021AD) | 1974 DEV_MAC_TAGS_CFG_VLAN_AWR_ENA | 1975 DEV_MAC_TAGS_CFG_VLAN_DBL_AWR_ENA | 1976 DEV_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA, 1977 DEV_MAC_TAGS_CFG); 1978 1979 /* Set SMAC of Pause frame (00:00:00:00:00:00) */ 1980 ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_HIGH_CFG); 1981 ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_LOW_CFG); 1982 1983 /* Enable transmission of pause frames */ 1984 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, 1); 1985 1986 /* Drop frames with multicast source address */ 1987 ocelot_rmw_gix(ocelot, ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA, 1988 ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA, 1989 ANA_PORT_DROP_CFG, port); 1990 1991 /* Set default VLAN and tag type to 8021Q. */ 1992 ocelot_rmw_gix(ocelot, REW_PORT_VLAN_CFG_PORT_TPID(ETH_P_8021Q), 1993 REW_PORT_VLAN_CFG_PORT_TPID_M, 1994 REW_PORT_VLAN_CFG, port); 1995 1996 /* Disable source address learning for standalone mode */ 1997 ocelot_port_set_learning(ocelot, port, false); 1998 1999 /* Set the port's initial logical port ID value, enable receiving 2000 * frames on it, and configure the MAC address learning type to 2001 * automatic. 2002 */ 2003 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_LEARNAUTO | 2004 ANA_PORT_PORT_CFG_RECV_ENA | 2005 ANA_PORT_PORT_CFG_PORTID_VAL(port), 2006 ANA_PORT_PORT_CFG, port); 2007 2008 /* Enable vcap lookups */ 2009 ocelot_vcap_enable(ocelot, port); 2010 } 2011 EXPORT_SYMBOL(ocelot_init_port); 2012 2013 /* Configure and enable the CPU port module, which is a set of queues 2014 * accessible through register MMIO, frame DMA or Ethernet (in case 2015 * NPI mode is used). 2016 */ 2017 static void ocelot_cpu_port_init(struct ocelot *ocelot) 2018 { 2019 int cpu = ocelot->num_phys_ports; 2020 2021 /* The unicast destination PGID for the CPU port module is unused */ 2022 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, cpu); 2023 /* Instead set up a multicast destination PGID for traffic copied to 2024 * the CPU. Whitelisted MAC addresses like the port netdevice MAC 2025 * addresses will be copied to the CPU via this PGID. 2026 */ 2027 ocelot_write_rix(ocelot, BIT(cpu), ANA_PGID_PGID, PGID_CPU); 2028 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_RECV_ENA | 2029 ANA_PORT_PORT_CFG_PORTID_VAL(cpu), 2030 ANA_PORT_PORT_CFG, cpu); 2031 2032 /* Enable CPU port module */ 2033 ocelot_fields_write(ocelot, cpu, QSYS_SWITCH_PORT_MODE_PORT_ENA, 1); 2034 /* CPU port Injection/Extraction configuration */ 2035 ocelot_fields_write(ocelot, cpu, SYS_PORT_MODE_INCL_XTR_HDR, 2036 OCELOT_TAG_PREFIX_NONE); 2037 ocelot_fields_write(ocelot, cpu, SYS_PORT_MODE_INCL_INJ_HDR, 2038 OCELOT_TAG_PREFIX_NONE); 2039 2040 /* Configure the CPU port to be VLAN aware */ 2041 ocelot_write_gix(ocelot, ANA_PORT_VLAN_CFG_VLAN_VID(0) | 2042 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 2043 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1), 2044 ANA_PORT_VLAN_CFG, cpu); 2045 } 2046 2047 static void ocelot_detect_features(struct ocelot *ocelot) 2048 { 2049 int mmgt, eq_ctrl; 2050 2051 /* For Ocelot, Felix, Seville, Serval etc, SYS:MMGT:MMGT:FREECNT holds 2052 * the number of 240-byte free memory words (aka 4-cell chunks) and not 2053 * 192 bytes as the documentation incorrectly says. 2054 */ 2055 mmgt = ocelot_read(ocelot, SYS_MMGT); 2056 ocelot->packet_buffer_size = 240 * SYS_MMGT_FREECNT(mmgt); 2057 2058 eq_ctrl = ocelot_read(ocelot, QSYS_EQ_CTRL); 2059 ocelot->num_frame_refs = QSYS_MMGT_EQ_CTRL_FP_FREE_CNT(eq_ctrl); 2060 } 2061 2062 int ocelot_init(struct ocelot *ocelot) 2063 { 2064 char queue_name[32]; 2065 int i, ret; 2066 u32 port; 2067 2068 if (ocelot->ops->reset) { 2069 ret = ocelot->ops->reset(ocelot); 2070 if (ret) { 2071 dev_err(ocelot->dev, "Switch reset failed\n"); 2072 return ret; 2073 } 2074 } 2075 2076 ocelot->stats = devm_kcalloc(ocelot->dev, 2077 ocelot->num_phys_ports * ocelot->num_stats, 2078 sizeof(u64), GFP_KERNEL); 2079 if (!ocelot->stats) 2080 return -ENOMEM; 2081 2082 mutex_init(&ocelot->stats_lock); 2083 mutex_init(&ocelot->ptp_lock); 2084 spin_lock_init(&ocelot->ptp_clock_lock); 2085 snprintf(queue_name, sizeof(queue_name), "%s-stats", 2086 dev_name(ocelot->dev)); 2087 ocelot->stats_queue = create_singlethread_workqueue(queue_name); 2088 if (!ocelot->stats_queue) 2089 return -ENOMEM; 2090 2091 ocelot->owq = alloc_ordered_workqueue("ocelot-owq", 0); 2092 if (!ocelot->owq) { 2093 destroy_workqueue(ocelot->stats_queue); 2094 return -ENOMEM; 2095 } 2096 2097 INIT_LIST_HEAD(&ocelot->multicast); 2098 INIT_LIST_HEAD(&ocelot->pgids); 2099 ocelot_detect_features(ocelot); 2100 ocelot_mact_init(ocelot); 2101 ocelot_vlan_init(ocelot); 2102 ocelot_vcap_init(ocelot); 2103 ocelot_cpu_port_init(ocelot); 2104 2105 for (port = 0; port < ocelot->num_phys_ports; port++) { 2106 /* Clear all counters (5 groups) */ 2107 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(port) | 2108 SYS_STAT_CFG_STAT_CLEAR_SHOT(0x7f), 2109 SYS_STAT_CFG); 2110 } 2111 2112 /* Only use S-Tag */ 2113 ocelot_write(ocelot, ETH_P_8021AD, SYS_VLAN_ETYPE_CFG); 2114 2115 /* Aggregation mode */ 2116 ocelot_write(ocelot, ANA_AGGR_CFG_AC_SMAC_ENA | 2117 ANA_AGGR_CFG_AC_DMAC_ENA | 2118 ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA | 2119 ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA | 2120 ANA_AGGR_CFG_AC_IP6_FLOW_LBL_ENA | 2121 ANA_AGGR_CFG_AC_IP6_TCPUDP_ENA, 2122 ANA_AGGR_CFG); 2123 2124 /* Set MAC age time to default value. The entry is aged after 2125 * 2*AGE_PERIOD 2126 */ 2127 ocelot_write(ocelot, 2128 ANA_AUTOAGE_AGE_PERIOD(BR_DEFAULT_AGEING_TIME / 2 / HZ), 2129 ANA_AUTOAGE); 2130 2131 /* Disable learning for frames discarded by VLAN ingress filtering */ 2132 regmap_field_write(ocelot->regfields[ANA_ADVLEARN_VLAN_CHK], 1); 2133 2134 /* Setup frame ageing - fixed value "2 sec" - in 6.5 us units */ 2135 ocelot_write(ocelot, SYS_FRM_AGING_AGE_TX_ENA | 2136 SYS_FRM_AGING_MAX_AGE(307692), SYS_FRM_AGING); 2137 2138 /* Setup flooding PGIDs */ 2139 for (i = 0; i < ocelot->num_flooding_pgids; i++) 2140 ocelot_write_rix(ocelot, ANA_FLOODING_FLD_MULTICAST(PGID_MC) | 2141 ANA_FLOODING_FLD_BROADCAST(PGID_BC) | 2142 ANA_FLOODING_FLD_UNICAST(PGID_UC), 2143 ANA_FLOODING, i); 2144 ocelot_write(ocelot, ANA_FLOODING_IPMC_FLD_MC6_DATA(PGID_MCIPV6) | 2145 ANA_FLOODING_IPMC_FLD_MC6_CTRL(PGID_MC) | 2146 ANA_FLOODING_IPMC_FLD_MC4_DATA(PGID_MCIPV4) | 2147 ANA_FLOODING_IPMC_FLD_MC4_CTRL(PGID_MC), 2148 ANA_FLOODING_IPMC); 2149 2150 for (port = 0; port < ocelot->num_phys_ports; port++) { 2151 /* Transmit the frame to the local port. */ 2152 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port); 2153 /* Do not forward BPDU frames to the front ports. */ 2154 ocelot_write_gix(ocelot, 2155 ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA(0xffff), 2156 ANA_PORT_CPU_FWD_BPDU_CFG, 2157 port); 2158 /* Ensure bridging is disabled */ 2159 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_SRC + port); 2160 } 2161 2162 for_each_nonreserved_multicast_dest_pgid(ocelot, i) { 2163 u32 val = ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports - 1, 0)); 2164 2165 ocelot_write_rix(ocelot, val, ANA_PGID_PGID, i); 2166 } 2167 2168 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_BLACKHOLE); 2169 2170 /* Allow broadcast and unknown L2 multicast to the CPU. */ 2171 ocelot_rmw_rix(ocelot, ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)), 2172 ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)), 2173 ANA_PGID_PGID, PGID_MC); 2174 ocelot_rmw_rix(ocelot, ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)), 2175 ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)), 2176 ANA_PGID_PGID, PGID_BC); 2177 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV4); 2178 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV6); 2179 2180 /* Allow manual injection via DEVCPU_QS registers, and byte swap these 2181 * registers endianness. 2182 */ 2183 ocelot_write_rix(ocelot, QS_INJ_GRP_CFG_BYTE_SWAP | 2184 QS_INJ_GRP_CFG_MODE(1), QS_INJ_GRP_CFG, 0); 2185 ocelot_write_rix(ocelot, QS_XTR_GRP_CFG_BYTE_SWAP | 2186 QS_XTR_GRP_CFG_MODE(1), QS_XTR_GRP_CFG, 0); 2187 ocelot_write(ocelot, ANA_CPUQ_CFG_CPUQ_MIRROR(2) | 2188 ANA_CPUQ_CFG_CPUQ_LRN(2) | 2189 ANA_CPUQ_CFG_CPUQ_MAC_COPY(2) | 2190 ANA_CPUQ_CFG_CPUQ_SRC_COPY(2) | 2191 ANA_CPUQ_CFG_CPUQ_LOCKED_PORTMOVE(2) | 2192 ANA_CPUQ_CFG_CPUQ_ALLBRIDGE(6) | 2193 ANA_CPUQ_CFG_CPUQ_IPMC_CTRL(6) | 2194 ANA_CPUQ_CFG_CPUQ_IGMP(6) | 2195 ANA_CPUQ_CFG_CPUQ_MLD(6), ANA_CPUQ_CFG); 2196 for (i = 0; i < 16; i++) 2197 ocelot_write_rix(ocelot, ANA_CPUQ_8021_CFG_CPUQ_GARP_VAL(6) | 2198 ANA_CPUQ_8021_CFG_CPUQ_BPDU_VAL(6), 2199 ANA_CPUQ_8021_CFG, i); 2200 2201 INIT_DELAYED_WORK(&ocelot->stats_work, ocelot_check_stats_work); 2202 queue_delayed_work(ocelot->stats_queue, &ocelot->stats_work, 2203 OCELOT_STATS_CHECK_DELAY); 2204 2205 return 0; 2206 } 2207 EXPORT_SYMBOL(ocelot_init); 2208 2209 void ocelot_deinit(struct ocelot *ocelot) 2210 { 2211 cancel_delayed_work(&ocelot->stats_work); 2212 destroy_workqueue(ocelot->stats_queue); 2213 destroy_workqueue(ocelot->owq); 2214 mutex_destroy(&ocelot->stats_lock); 2215 } 2216 EXPORT_SYMBOL(ocelot_deinit); 2217 2218 void ocelot_deinit_port(struct ocelot *ocelot, int port) 2219 { 2220 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2221 2222 skb_queue_purge(&ocelot_port->tx_skbs); 2223 } 2224 EXPORT_SYMBOL(ocelot_deinit_port); 2225 2226 MODULE_LICENSE("Dual MIT/GPL"); 2227