1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* 3 * Microsemi Ocelot Switch driver 4 * 5 * Copyright (c) 2017 Microsemi Corporation 6 */ 7 #include <linux/dsa/ocelot.h> 8 #include <linux/if_bridge.h> 9 #include <linux/ptp_classify.h> 10 #include <soc/mscc/ocelot_vcap.h> 11 #include "ocelot.h" 12 #include "ocelot_vcap.h" 13 14 #define TABLE_UPDATE_SLEEP_US 10 15 #define TABLE_UPDATE_TIMEOUT_US 100000 16 17 struct ocelot_mact_entry { 18 u8 mac[ETH_ALEN]; 19 u16 vid; 20 enum macaccess_entry_type type; 21 }; 22 23 static inline u32 ocelot_mact_read_macaccess(struct ocelot *ocelot) 24 { 25 return ocelot_read(ocelot, ANA_TABLES_MACACCESS); 26 } 27 28 static inline int ocelot_mact_wait_for_completion(struct ocelot *ocelot) 29 { 30 u32 val; 31 32 return readx_poll_timeout(ocelot_mact_read_macaccess, 33 ocelot, val, 34 (val & ANA_TABLES_MACACCESS_MAC_TABLE_CMD_M) == 35 MACACCESS_CMD_IDLE, 36 TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US); 37 } 38 39 static void ocelot_mact_select(struct ocelot *ocelot, 40 const unsigned char mac[ETH_ALEN], 41 unsigned int vid) 42 { 43 u32 macl = 0, mach = 0; 44 45 /* Set the MAC address to handle and the vlan associated in a format 46 * understood by the hardware. 47 */ 48 mach |= vid << 16; 49 mach |= mac[0] << 8; 50 mach |= mac[1] << 0; 51 macl |= mac[2] << 24; 52 macl |= mac[3] << 16; 53 macl |= mac[4] << 8; 54 macl |= mac[5] << 0; 55 56 ocelot_write(ocelot, macl, ANA_TABLES_MACLDATA); 57 ocelot_write(ocelot, mach, ANA_TABLES_MACHDATA); 58 59 } 60 61 int ocelot_mact_learn(struct ocelot *ocelot, int port, 62 const unsigned char mac[ETH_ALEN], 63 unsigned int vid, enum macaccess_entry_type type) 64 { 65 u32 cmd = ANA_TABLES_MACACCESS_VALID | 66 ANA_TABLES_MACACCESS_DEST_IDX(port) | 67 ANA_TABLES_MACACCESS_ENTRYTYPE(type) | 68 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_LEARN); 69 unsigned int mc_ports; 70 71 /* Set MAC_CPU_COPY if the CPU port is used by a multicast entry */ 72 if (type == ENTRYTYPE_MACv4) 73 mc_ports = (mac[1] << 8) | mac[2]; 74 else if (type == ENTRYTYPE_MACv6) 75 mc_ports = (mac[0] << 8) | mac[1]; 76 else 77 mc_ports = 0; 78 79 if (mc_ports & BIT(ocelot->num_phys_ports)) 80 cmd |= ANA_TABLES_MACACCESS_MAC_CPU_COPY; 81 82 ocelot_mact_select(ocelot, mac, vid); 83 84 /* Issue a write command */ 85 ocelot_write(ocelot, cmd, ANA_TABLES_MACACCESS); 86 87 return ocelot_mact_wait_for_completion(ocelot); 88 } 89 EXPORT_SYMBOL(ocelot_mact_learn); 90 91 int ocelot_mact_forget(struct ocelot *ocelot, 92 const unsigned char mac[ETH_ALEN], unsigned int vid) 93 { 94 ocelot_mact_select(ocelot, mac, vid); 95 96 /* Issue a forget command */ 97 ocelot_write(ocelot, 98 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_FORGET), 99 ANA_TABLES_MACACCESS); 100 101 return ocelot_mact_wait_for_completion(ocelot); 102 } 103 EXPORT_SYMBOL(ocelot_mact_forget); 104 105 static void ocelot_mact_init(struct ocelot *ocelot) 106 { 107 /* Configure the learning mode entries attributes: 108 * - Do not copy the frame to the CPU extraction queues. 109 * - Use the vlan and mac_cpoy for dmac lookup. 110 */ 111 ocelot_rmw(ocelot, 0, 112 ANA_AGENCTRL_LEARN_CPU_COPY | ANA_AGENCTRL_IGNORE_DMAC_FLAGS 113 | ANA_AGENCTRL_LEARN_FWD_KILL 114 | ANA_AGENCTRL_LEARN_IGNORE_VLAN, 115 ANA_AGENCTRL); 116 117 /* Clear the MAC table */ 118 ocelot_write(ocelot, MACACCESS_CMD_INIT, ANA_TABLES_MACACCESS); 119 } 120 121 static void ocelot_vcap_enable(struct ocelot *ocelot, int port) 122 { 123 ocelot_write_gix(ocelot, ANA_PORT_VCAP_S2_CFG_S2_ENA | 124 ANA_PORT_VCAP_S2_CFG_S2_IP6_CFG(0xa), 125 ANA_PORT_VCAP_S2_CFG, port); 126 127 ocelot_write_gix(ocelot, ANA_PORT_VCAP_CFG_S1_ENA, 128 ANA_PORT_VCAP_CFG, port); 129 130 ocelot_rmw_gix(ocelot, REW_PORT_CFG_ES0_EN, 131 REW_PORT_CFG_ES0_EN, 132 REW_PORT_CFG, port); 133 } 134 135 static inline u32 ocelot_vlant_read_vlanaccess(struct ocelot *ocelot) 136 { 137 return ocelot_read(ocelot, ANA_TABLES_VLANACCESS); 138 } 139 140 static inline int ocelot_vlant_wait_for_completion(struct ocelot *ocelot) 141 { 142 u32 val; 143 144 return readx_poll_timeout(ocelot_vlant_read_vlanaccess, 145 ocelot, 146 val, 147 (val & ANA_TABLES_VLANACCESS_VLAN_TBL_CMD_M) == 148 ANA_TABLES_VLANACCESS_CMD_IDLE, 149 TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US); 150 } 151 152 static int ocelot_vlant_set_mask(struct ocelot *ocelot, u16 vid, u32 mask) 153 { 154 /* Select the VID to configure */ 155 ocelot_write(ocelot, ANA_TABLES_VLANTIDX_V_INDEX(vid), 156 ANA_TABLES_VLANTIDX); 157 /* Set the vlan port members mask and issue a write command */ 158 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_VLAN_PORT_MASK(mask) | 159 ANA_TABLES_VLANACCESS_CMD_WRITE, 160 ANA_TABLES_VLANACCESS); 161 162 return ocelot_vlant_wait_for_completion(ocelot); 163 } 164 165 static void ocelot_port_set_native_vlan(struct ocelot *ocelot, int port, 166 struct ocelot_vlan native_vlan) 167 { 168 struct ocelot_port *ocelot_port = ocelot->ports[port]; 169 u32 val = 0; 170 171 ocelot_port->native_vlan = native_vlan; 172 173 ocelot_rmw_gix(ocelot, REW_PORT_VLAN_CFG_PORT_VID(native_vlan.vid), 174 REW_PORT_VLAN_CFG_PORT_VID_M, 175 REW_PORT_VLAN_CFG, port); 176 177 if (ocelot_port->vlan_aware) { 178 if (native_vlan.valid) 179 /* Tag all frames except when VID == DEFAULT_VLAN */ 180 val = REW_TAG_CFG_TAG_CFG(1); 181 else 182 /* Tag all frames */ 183 val = REW_TAG_CFG_TAG_CFG(3); 184 } else { 185 /* Port tagging disabled. */ 186 val = REW_TAG_CFG_TAG_CFG(0); 187 } 188 ocelot_rmw_gix(ocelot, val, 189 REW_TAG_CFG_TAG_CFG_M, 190 REW_TAG_CFG, port); 191 } 192 193 /* Default vlan to clasify for untagged frames (may be zero) */ 194 static void ocelot_port_set_pvid(struct ocelot *ocelot, int port, 195 struct ocelot_vlan pvid_vlan) 196 { 197 struct ocelot_port *ocelot_port = ocelot->ports[port]; 198 u32 val = 0; 199 200 ocelot_port->pvid_vlan = pvid_vlan; 201 202 if (!ocelot_port->vlan_aware) 203 pvid_vlan.vid = 0; 204 205 ocelot_rmw_gix(ocelot, 206 ANA_PORT_VLAN_CFG_VLAN_VID(pvid_vlan.vid), 207 ANA_PORT_VLAN_CFG_VLAN_VID_M, 208 ANA_PORT_VLAN_CFG, port); 209 210 /* If there's no pvid, we should drop not only untagged traffic (which 211 * happens automatically), but also 802.1p traffic which gets 212 * classified to VLAN 0, but that is always in our RX filter, so it 213 * would get accepted were it not for this setting. 214 */ 215 if (!pvid_vlan.valid && ocelot_port->vlan_aware) 216 val = ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA | 217 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA; 218 219 ocelot_rmw_gix(ocelot, val, 220 ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA | 221 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA, 222 ANA_PORT_DROP_CFG, port); 223 } 224 225 int ocelot_port_vlan_filtering(struct ocelot *ocelot, int port, 226 bool vlan_aware) 227 { 228 struct ocelot_vcap_block *block = &ocelot->block[VCAP_IS1]; 229 struct ocelot_port *ocelot_port = ocelot->ports[port]; 230 struct ocelot_vcap_filter *filter; 231 u32 val; 232 233 list_for_each_entry(filter, &block->rules, list) { 234 if (filter->ingress_port_mask & BIT(port) && 235 filter->action.vid_replace_ena) { 236 dev_err(ocelot->dev, 237 "Cannot change VLAN state with vlan modify rules active\n"); 238 return -EBUSY; 239 } 240 } 241 242 ocelot_port->vlan_aware = vlan_aware; 243 244 if (vlan_aware) 245 val = ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 246 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1); 247 else 248 val = 0; 249 ocelot_rmw_gix(ocelot, val, 250 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 251 ANA_PORT_VLAN_CFG_VLAN_POP_CNT_M, 252 ANA_PORT_VLAN_CFG, port); 253 254 ocelot_port_set_pvid(ocelot, port, ocelot_port->pvid_vlan); 255 ocelot_port_set_native_vlan(ocelot, port, ocelot_port->native_vlan); 256 257 return 0; 258 } 259 EXPORT_SYMBOL(ocelot_port_vlan_filtering); 260 261 int ocelot_vlan_prepare(struct ocelot *ocelot, int port, u16 vid, bool pvid, 262 bool untagged, struct netlink_ext_ack *extack) 263 { 264 struct ocelot_port *ocelot_port = ocelot->ports[port]; 265 266 /* Deny changing the native VLAN, but always permit deleting it */ 267 if (untagged && ocelot_port->native_vlan.vid != vid && 268 ocelot_port->native_vlan.valid) { 269 NL_SET_ERR_MSG_MOD(extack, 270 "Port already has a native VLAN"); 271 return -EBUSY; 272 } 273 274 return 0; 275 } 276 EXPORT_SYMBOL(ocelot_vlan_prepare); 277 278 int ocelot_vlan_add(struct ocelot *ocelot, int port, u16 vid, bool pvid, 279 bool untagged) 280 { 281 int ret; 282 283 /* Make the port a member of the VLAN */ 284 ocelot->vlan_mask[vid] |= BIT(port); 285 ret = ocelot_vlant_set_mask(ocelot, vid, ocelot->vlan_mask[vid]); 286 if (ret) 287 return ret; 288 289 /* Default ingress vlan classification */ 290 if (pvid) { 291 struct ocelot_vlan pvid_vlan; 292 293 pvid_vlan.vid = vid; 294 pvid_vlan.valid = true; 295 ocelot_port_set_pvid(ocelot, port, pvid_vlan); 296 } 297 298 /* Untagged egress vlan clasification */ 299 if (untagged) { 300 struct ocelot_vlan native_vlan; 301 302 native_vlan.vid = vid; 303 native_vlan.valid = true; 304 ocelot_port_set_native_vlan(ocelot, port, native_vlan); 305 } 306 307 return 0; 308 } 309 EXPORT_SYMBOL(ocelot_vlan_add); 310 311 int ocelot_vlan_del(struct ocelot *ocelot, int port, u16 vid) 312 { 313 struct ocelot_port *ocelot_port = ocelot->ports[port]; 314 int ret; 315 316 /* Stop the port from being a member of the vlan */ 317 ocelot->vlan_mask[vid] &= ~BIT(port); 318 ret = ocelot_vlant_set_mask(ocelot, vid, ocelot->vlan_mask[vid]); 319 if (ret) 320 return ret; 321 322 /* Ingress */ 323 if (ocelot_port->pvid_vlan.vid == vid) { 324 struct ocelot_vlan pvid_vlan = {0}; 325 326 ocelot_port_set_pvid(ocelot, port, pvid_vlan); 327 } 328 329 /* Egress */ 330 if (ocelot_port->native_vlan.vid == vid) { 331 struct ocelot_vlan native_vlan = {0}; 332 333 ocelot_port_set_native_vlan(ocelot, port, native_vlan); 334 } 335 336 return 0; 337 } 338 EXPORT_SYMBOL(ocelot_vlan_del); 339 340 static void ocelot_vlan_init(struct ocelot *ocelot) 341 { 342 u16 port, vid; 343 344 /* Clear VLAN table, by default all ports are members of all VLANs */ 345 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_CMD_INIT, 346 ANA_TABLES_VLANACCESS); 347 ocelot_vlant_wait_for_completion(ocelot); 348 349 /* Configure the port VLAN memberships */ 350 for (vid = 1; vid < VLAN_N_VID; vid++) { 351 ocelot->vlan_mask[vid] = 0; 352 ocelot_vlant_set_mask(ocelot, vid, ocelot->vlan_mask[vid]); 353 } 354 355 /* Because VLAN filtering is enabled, we need VID 0 to get untagged 356 * traffic. It is added automatically if 8021q module is loaded, but 357 * we can't rely on it since module may be not loaded. 358 */ 359 ocelot->vlan_mask[0] = GENMASK(ocelot->num_phys_ports - 1, 0); 360 ocelot_vlant_set_mask(ocelot, 0, ocelot->vlan_mask[0]); 361 362 /* Set vlan ingress filter mask to all ports but the CPU port by 363 * default. 364 */ 365 ocelot_write(ocelot, GENMASK(ocelot->num_phys_ports - 1, 0), 366 ANA_VLANMASK); 367 368 for (port = 0; port < ocelot->num_phys_ports; port++) { 369 ocelot_write_gix(ocelot, 0, REW_PORT_VLAN_CFG, port); 370 ocelot_write_gix(ocelot, 0, REW_TAG_CFG, port); 371 } 372 } 373 374 static u32 ocelot_read_eq_avail(struct ocelot *ocelot, int port) 375 { 376 return ocelot_read_rix(ocelot, QSYS_SW_STATUS, port); 377 } 378 379 static int ocelot_port_flush(struct ocelot *ocelot, int port) 380 { 381 unsigned int pause_ena; 382 int err, val; 383 384 /* Disable dequeuing from the egress queues */ 385 ocelot_rmw_rix(ocelot, QSYS_PORT_MODE_DEQUEUE_DIS, 386 QSYS_PORT_MODE_DEQUEUE_DIS, 387 QSYS_PORT_MODE, port); 388 389 /* Disable flow control */ 390 ocelot_fields_read(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, &pause_ena); 391 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, 0); 392 393 /* Disable priority flow control */ 394 ocelot_fields_write(ocelot, port, 395 QSYS_SWITCH_PORT_MODE_TX_PFC_ENA, 0); 396 397 /* Wait at least the time it takes to receive a frame of maximum length 398 * at the port. 399 * Worst-case delays for 10 kilobyte jumbo frames are: 400 * 8 ms on a 10M port 401 * 800 μs on a 100M port 402 * 80 μs on a 1G port 403 * 32 μs on a 2.5G port 404 */ 405 usleep_range(8000, 10000); 406 407 /* Disable half duplex backpressure. */ 408 ocelot_rmw_rix(ocelot, 0, SYS_FRONT_PORT_MODE_HDX_MODE, 409 SYS_FRONT_PORT_MODE, port); 410 411 /* Flush the queues associated with the port. */ 412 ocelot_rmw_gix(ocelot, REW_PORT_CFG_FLUSH_ENA, REW_PORT_CFG_FLUSH_ENA, 413 REW_PORT_CFG, port); 414 415 /* Enable dequeuing from the egress queues. */ 416 ocelot_rmw_rix(ocelot, 0, QSYS_PORT_MODE_DEQUEUE_DIS, QSYS_PORT_MODE, 417 port); 418 419 /* Wait until flushing is complete. */ 420 err = read_poll_timeout(ocelot_read_eq_avail, val, !val, 421 100, 2000000, false, ocelot, port); 422 423 /* Clear flushing again. */ 424 ocelot_rmw_gix(ocelot, 0, REW_PORT_CFG_FLUSH_ENA, REW_PORT_CFG, port); 425 426 /* Re-enable flow control */ 427 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, pause_ena); 428 429 return err; 430 } 431 432 void ocelot_phylink_mac_link_down(struct ocelot *ocelot, int port, 433 unsigned int link_an_mode, 434 phy_interface_t interface, 435 unsigned long quirks) 436 { 437 struct ocelot_port *ocelot_port = ocelot->ports[port]; 438 int err; 439 440 ocelot_port_rmwl(ocelot_port, 0, DEV_MAC_ENA_CFG_RX_ENA, 441 DEV_MAC_ENA_CFG); 442 443 ocelot_fields_write(ocelot, port, QSYS_SWITCH_PORT_MODE_PORT_ENA, 0); 444 445 err = ocelot_port_flush(ocelot, port); 446 if (err) 447 dev_err(ocelot->dev, "failed to flush port %d: %d\n", 448 port, err); 449 450 /* Put the port in reset. */ 451 if (interface != PHY_INTERFACE_MODE_QSGMII || 452 !(quirks & OCELOT_QUIRK_QSGMII_PORTS_MUST_BE_UP)) 453 ocelot_port_rmwl(ocelot_port, 454 DEV_CLOCK_CFG_MAC_TX_RST | 455 DEV_CLOCK_CFG_MAC_TX_RST, 456 DEV_CLOCK_CFG_MAC_TX_RST | 457 DEV_CLOCK_CFG_MAC_TX_RST, 458 DEV_CLOCK_CFG); 459 } 460 EXPORT_SYMBOL_GPL(ocelot_phylink_mac_link_down); 461 462 void ocelot_phylink_mac_link_up(struct ocelot *ocelot, int port, 463 struct phy_device *phydev, 464 unsigned int link_an_mode, 465 phy_interface_t interface, 466 int speed, int duplex, 467 bool tx_pause, bool rx_pause, 468 unsigned long quirks) 469 { 470 struct ocelot_port *ocelot_port = ocelot->ports[port]; 471 int mac_speed, mode = 0; 472 u32 mac_fc_cfg; 473 474 /* The MAC might be integrated in systems where the MAC speed is fixed 475 * and it's the PCS who is performing the rate adaptation, so we have 476 * to write "1000Mbps" into the LINK_SPEED field of DEV_CLOCK_CFG 477 * (which is also its default value). 478 */ 479 if ((quirks & OCELOT_QUIRK_PCS_PERFORMS_RATE_ADAPTATION) || 480 speed == SPEED_1000) { 481 mac_speed = OCELOT_SPEED_1000; 482 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA; 483 } else if (speed == SPEED_2500) { 484 mac_speed = OCELOT_SPEED_2500; 485 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA; 486 } else if (speed == SPEED_100) { 487 mac_speed = OCELOT_SPEED_100; 488 } else { 489 mac_speed = OCELOT_SPEED_10; 490 } 491 492 if (duplex == DUPLEX_FULL) 493 mode |= DEV_MAC_MODE_CFG_FDX_ENA; 494 495 ocelot_port_writel(ocelot_port, mode, DEV_MAC_MODE_CFG); 496 497 /* Take port out of reset by clearing the MAC_TX_RST, MAC_RX_RST and 498 * PORT_RST bits in DEV_CLOCK_CFG. 499 */ 500 ocelot_port_writel(ocelot_port, DEV_CLOCK_CFG_LINK_SPEED(mac_speed), 501 DEV_CLOCK_CFG); 502 503 switch (speed) { 504 case SPEED_10: 505 mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(OCELOT_SPEED_10); 506 break; 507 case SPEED_100: 508 mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(OCELOT_SPEED_100); 509 break; 510 case SPEED_1000: 511 case SPEED_2500: 512 mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(OCELOT_SPEED_1000); 513 break; 514 default: 515 dev_err(ocelot->dev, "Unsupported speed on port %d: %d\n", 516 port, speed); 517 return; 518 } 519 520 /* Handle RX pause in all cases, with 2500base-X this is used for rate 521 * adaptation. 522 */ 523 mac_fc_cfg |= SYS_MAC_FC_CFG_RX_FC_ENA; 524 525 if (tx_pause) 526 mac_fc_cfg |= SYS_MAC_FC_CFG_TX_FC_ENA | 527 SYS_MAC_FC_CFG_PAUSE_VAL_CFG(0xffff) | 528 SYS_MAC_FC_CFG_FC_LATENCY_CFG(0x7) | 529 SYS_MAC_FC_CFG_ZERO_PAUSE_ENA; 530 531 /* Flow control. Link speed is only used here to evaluate the time 532 * specification in incoming pause frames. 533 */ 534 ocelot_write_rix(ocelot, mac_fc_cfg, SYS_MAC_FC_CFG, port); 535 536 ocelot_write_rix(ocelot, 0, ANA_POL_FLOWC, port); 537 538 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, tx_pause); 539 540 /* Undo the effects of ocelot_phylink_mac_link_down: 541 * enable MAC module 542 */ 543 ocelot_port_writel(ocelot_port, DEV_MAC_ENA_CFG_RX_ENA | 544 DEV_MAC_ENA_CFG_TX_ENA, DEV_MAC_ENA_CFG); 545 546 /* Take MAC, Port, Phy (intern) and PCS (SGMII/Serdes) clock out of 547 * reset 548 */ 549 ocelot_port_writel(ocelot_port, DEV_CLOCK_CFG_LINK_SPEED(speed), 550 DEV_CLOCK_CFG); 551 552 /* No PFC */ 553 ocelot_write_gix(ocelot, ANA_PFC_PFC_CFG_FC_LINK_SPEED(speed), 554 ANA_PFC_PFC_CFG, port); 555 556 /* Core: Enable port for frame transfer */ 557 ocelot_fields_write(ocelot, port, 558 QSYS_SWITCH_PORT_MODE_PORT_ENA, 1); 559 } 560 EXPORT_SYMBOL_GPL(ocelot_phylink_mac_link_up); 561 562 static void ocelot_port_add_txtstamp_skb(struct ocelot *ocelot, int port, 563 struct sk_buff *clone) 564 { 565 struct ocelot_port *ocelot_port = ocelot->ports[port]; 566 567 spin_lock(&ocelot_port->ts_id_lock); 568 569 skb_shinfo(clone)->tx_flags |= SKBTX_IN_PROGRESS; 570 /* Store timestamp ID in OCELOT_SKB_CB(clone)->ts_id */ 571 OCELOT_SKB_CB(clone)->ts_id = ocelot_port->ts_id; 572 ocelot_port->ts_id = (ocelot_port->ts_id + 1) % 4; 573 skb_queue_tail(&ocelot_port->tx_skbs, clone); 574 575 spin_unlock(&ocelot_port->ts_id_lock); 576 } 577 578 u32 ocelot_ptp_rew_op(struct sk_buff *skb) 579 { 580 struct sk_buff *clone = OCELOT_SKB_CB(skb)->clone; 581 u8 ptp_cmd = OCELOT_SKB_CB(skb)->ptp_cmd; 582 u32 rew_op = 0; 583 584 if (ptp_cmd == IFH_REW_OP_TWO_STEP_PTP && clone) { 585 rew_op = ptp_cmd; 586 rew_op |= OCELOT_SKB_CB(clone)->ts_id << 3; 587 } else if (ptp_cmd == IFH_REW_OP_ORIGIN_PTP) { 588 rew_op = ptp_cmd; 589 } 590 591 return rew_op; 592 } 593 EXPORT_SYMBOL(ocelot_ptp_rew_op); 594 595 static bool ocelot_ptp_is_onestep_sync(struct sk_buff *skb) 596 { 597 struct ptp_header *hdr; 598 unsigned int ptp_class; 599 u8 msgtype, twostep; 600 601 ptp_class = ptp_classify_raw(skb); 602 if (ptp_class == PTP_CLASS_NONE) 603 return false; 604 605 hdr = ptp_parse_header(skb, ptp_class); 606 if (!hdr) 607 return false; 608 609 msgtype = ptp_get_msgtype(hdr, ptp_class); 610 twostep = hdr->flag_field[0] & 0x2; 611 612 if (msgtype == PTP_MSGTYPE_SYNC && twostep == 0) 613 return true; 614 615 return false; 616 } 617 618 int ocelot_port_txtstamp_request(struct ocelot *ocelot, int port, 619 struct sk_buff *skb, 620 struct sk_buff **clone) 621 { 622 struct ocelot_port *ocelot_port = ocelot->ports[port]; 623 u8 ptp_cmd = ocelot_port->ptp_cmd; 624 625 /* Store ptp_cmd in OCELOT_SKB_CB(skb)->ptp_cmd */ 626 if (ptp_cmd == IFH_REW_OP_ORIGIN_PTP) { 627 if (ocelot_ptp_is_onestep_sync(skb)) { 628 OCELOT_SKB_CB(skb)->ptp_cmd = ptp_cmd; 629 return 0; 630 } 631 632 /* Fall back to two-step timestamping */ 633 ptp_cmd = IFH_REW_OP_TWO_STEP_PTP; 634 } 635 636 if (ptp_cmd == IFH_REW_OP_TWO_STEP_PTP) { 637 *clone = skb_clone_sk(skb); 638 if (!(*clone)) 639 return -ENOMEM; 640 641 ocelot_port_add_txtstamp_skb(ocelot, port, *clone); 642 OCELOT_SKB_CB(skb)->ptp_cmd = ptp_cmd; 643 } 644 645 return 0; 646 } 647 EXPORT_SYMBOL(ocelot_port_txtstamp_request); 648 649 static void ocelot_get_hwtimestamp(struct ocelot *ocelot, 650 struct timespec64 *ts) 651 { 652 unsigned long flags; 653 u32 val; 654 655 spin_lock_irqsave(&ocelot->ptp_clock_lock, flags); 656 657 /* Read current PTP time to get seconds */ 658 val = ocelot_read_rix(ocelot, PTP_PIN_CFG, TOD_ACC_PIN); 659 660 val &= ~(PTP_PIN_CFG_SYNC | PTP_PIN_CFG_ACTION_MASK | PTP_PIN_CFG_DOM); 661 val |= PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_SAVE); 662 ocelot_write_rix(ocelot, val, PTP_PIN_CFG, TOD_ACC_PIN); 663 ts->tv_sec = ocelot_read_rix(ocelot, PTP_PIN_TOD_SEC_LSB, TOD_ACC_PIN); 664 665 /* Read packet HW timestamp from FIFO */ 666 val = ocelot_read(ocelot, SYS_PTP_TXSTAMP); 667 ts->tv_nsec = SYS_PTP_TXSTAMP_PTP_TXSTAMP(val); 668 669 /* Sec has incremented since the ts was registered */ 670 if ((ts->tv_sec & 0x1) != !!(val & SYS_PTP_TXSTAMP_PTP_TXSTAMP_SEC)) 671 ts->tv_sec--; 672 673 spin_unlock_irqrestore(&ocelot->ptp_clock_lock, flags); 674 } 675 676 void ocelot_get_txtstamp(struct ocelot *ocelot) 677 { 678 int budget = OCELOT_PTP_QUEUE_SZ; 679 680 while (budget--) { 681 struct sk_buff *skb, *skb_tmp, *skb_match = NULL; 682 struct skb_shared_hwtstamps shhwtstamps; 683 struct ocelot_port *port; 684 struct timespec64 ts; 685 unsigned long flags; 686 u32 val, id, txport; 687 688 val = ocelot_read(ocelot, SYS_PTP_STATUS); 689 690 /* Check if a timestamp can be retrieved */ 691 if (!(val & SYS_PTP_STATUS_PTP_MESS_VLD)) 692 break; 693 694 WARN_ON(val & SYS_PTP_STATUS_PTP_OVFL); 695 696 /* Retrieve the ts ID and Tx port */ 697 id = SYS_PTP_STATUS_PTP_MESS_ID_X(val); 698 txport = SYS_PTP_STATUS_PTP_MESS_TXPORT_X(val); 699 700 /* Retrieve its associated skb */ 701 port = ocelot->ports[txport]; 702 703 spin_lock_irqsave(&port->tx_skbs.lock, flags); 704 705 skb_queue_walk_safe(&port->tx_skbs, skb, skb_tmp) { 706 if (OCELOT_SKB_CB(skb)->ts_id != id) 707 continue; 708 __skb_unlink(skb, &port->tx_skbs); 709 skb_match = skb; 710 break; 711 } 712 713 spin_unlock_irqrestore(&port->tx_skbs.lock, flags); 714 715 /* Get the h/w timestamp */ 716 ocelot_get_hwtimestamp(ocelot, &ts); 717 718 if (unlikely(!skb_match)) 719 continue; 720 721 /* Set the timestamp into the skb */ 722 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 723 shhwtstamps.hwtstamp = ktime_set(ts.tv_sec, ts.tv_nsec); 724 skb_complete_tx_timestamp(skb_match, &shhwtstamps); 725 726 /* Next ts */ 727 ocelot_write(ocelot, SYS_PTP_NXT_PTP_NXT, SYS_PTP_NXT); 728 } 729 } 730 EXPORT_SYMBOL(ocelot_get_txtstamp); 731 732 static int ocelot_rx_frame_word(struct ocelot *ocelot, u8 grp, bool ifh, 733 u32 *rval) 734 { 735 u32 bytes_valid, val; 736 737 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 738 if (val == XTR_NOT_READY) { 739 if (ifh) 740 return -EIO; 741 742 do { 743 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 744 } while (val == XTR_NOT_READY); 745 } 746 747 switch (val) { 748 case XTR_ABORT: 749 return -EIO; 750 case XTR_EOF_0: 751 case XTR_EOF_1: 752 case XTR_EOF_2: 753 case XTR_EOF_3: 754 case XTR_PRUNED: 755 bytes_valid = XTR_VALID_BYTES(val); 756 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 757 if (val == XTR_ESCAPE) 758 *rval = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 759 else 760 *rval = val; 761 762 return bytes_valid; 763 case XTR_ESCAPE: 764 *rval = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 765 766 return 4; 767 default: 768 *rval = val; 769 770 return 4; 771 } 772 } 773 774 static int ocelot_xtr_poll_xfh(struct ocelot *ocelot, int grp, u32 *xfh) 775 { 776 int i, err = 0; 777 778 for (i = 0; i < OCELOT_TAG_LEN / 4; i++) { 779 err = ocelot_rx_frame_word(ocelot, grp, true, &xfh[i]); 780 if (err != 4) 781 return (err < 0) ? err : -EIO; 782 } 783 784 return 0; 785 } 786 787 int ocelot_xtr_poll_frame(struct ocelot *ocelot, int grp, struct sk_buff **nskb) 788 { 789 struct skb_shared_hwtstamps *shhwtstamps; 790 u64 tod_in_ns, full_ts_in_ns; 791 u64 timestamp, src_port, len; 792 u32 xfh[OCELOT_TAG_LEN / 4]; 793 struct net_device *dev; 794 struct timespec64 ts; 795 struct sk_buff *skb; 796 int sz, buf_len; 797 u32 val, *buf; 798 int err; 799 800 err = ocelot_xtr_poll_xfh(ocelot, grp, xfh); 801 if (err) 802 return err; 803 804 ocelot_xfh_get_src_port(xfh, &src_port); 805 ocelot_xfh_get_len(xfh, &len); 806 ocelot_xfh_get_rew_val(xfh, ×tamp); 807 808 if (WARN_ON(src_port >= ocelot->num_phys_ports)) 809 return -EINVAL; 810 811 dev = ocelot->ops->port_to_netdev(ocelot, src_port); 812 if (!dev) 813 return -EINVAL; 814 815 skb = netdev_alloc_skb(dev, len); 816 if (unlikely(!skb)) { 817 netdev_err(dev, "Unable to allocate sk_buff\n"); 818 return -ENOMEM; 819 } 820 821 buf_len = len - ETH_FCS_LEN; 822 buf = (u32 *)skb_put(skb, buf_len); 823 824 len = 0; 825 do { 826 sz = ocelot_rx_frame_word(ocelot, grp, false, &val); 827 if (sz < 0) { 828 err = sz; 829 goto out_free_skb; 830 } 831 *buf++ = val; 832 len += sz; 833 } while (len < buf_len); 834 835 /* Read the FCS */ 836 sz = ocelot_rx_frame_word(ocelot, grp, false, &val); 837 if (sz < 0) { 838 err = sz; 839 goto out_free_skb; 840 } 841 842 /* Update the statistics if part of the FCS was read before */ 843 len -= ETH_FCS_LEN - sz; 844 845 if (unlikely(dev->features & NETIF_F_RXFCS)) { 846 buf = (u32 *)skb_put(skb, ETH_FCS_LEN); 847 *buf = val; 848 } 849 850 if (ocelot->ptp) { 851 ocelot_ptp_gettime64(&ocelot->ptp_info, &ts); 852 853 tod_in_ns = ktime_set(ts.tv_sec, ts.tv_nsec); 854 if ((tod_in_ns & 0xffffffff) < timestamp) 855 full_ts_in_ns = (((tod_in_ns >> 32) - 1) << 32) | 856 timestamp; 857 else 858 full_ts_in_ns = (tod_in_ns & GENMASK_ULL(63, 32)) | 859 timestamp; 860 861 shhwtstamps = skb_hwtstamps(skb); 862 memset(shhwtstamps, 0, sizeof(struct skb_shared_hwtstamps)); 863 shhwtstamps->hwtstamp = full_ts_in_ns; 864 } 865 866 /* Everything we see on an interface that is in the HW bridge 867 * has already been forwarded. 868 */ 869 if (ocelot->ports[src_port]->bridge) 870 skb->offload_fwd_mark = 1; 871 872 skb->protocol = eth_type_trans(skb, dev); 873 874 *nskb = skb; 875 876 return 0; 877 878 out_free_skb: 879 kfree_skb(skb); 880 return err; 881 } 882 EXPORT_SYMBOL(ocelot_xtr_poll_frame); 883 884 bool ocelot_can_inject(struct ocelot *ocelot, int grp) 885 { 886 u32 val = ocelot_read(ocelot, QS_INJ_STATUS); 887 888 if (!(val & QS_INJ_STATUS_FIFO_RDY(BIT(grp)))) 889 return false; 890 if (val & QS_INJ_STATUS_WMARK_REACHED(BIT(grp))) 891 return false; 892 893 return true; 894 } 895 EXPORT_SYMBOL(ocelot_can_inject); 896 897 void ocelot_port_inject_frame(struct ocelot *ocelot, int port, int grp, 898 u32 rew_op, struct sk_buff *skb) 899 { 900 u32 ifh[OCELOT_TAG_LEN / 4] = {0}; 901 unsigned int i, count, last; 902 903 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) | 904 QS_INJ_CTRL_SOF, QS_INJ_CTRL, grp); 905 906 ocelot_ifh_set_bypass(ifh, 1); 907 ocelot_ifh_set_dest(ifh, BIT_ULL(port)); 908 ocelot_ifh_set_tag_type(ifh, IFH_TAG_TYPE_C); 909 ocelot_ifh_set_vid(ifh, skb_vlan_tag_get(skb)); 910 ocelot_ifh_set_rew_op(ifh, rew_op); 911 912 for (i = 0; i < OCELOT_TAG_LEN / 4; i++) 913 ocelot_write_rix(ocelot, ifh[i], QS_INJ_WR, grp); 914 915 count = DIV_ROUND_UP(skb->len, 4); 916 last = skb->len % 4; 917 for (i = 0; i < count; i++) 918 ocelot_write_rix(ocelot, ((u32 *)skb->data)[i], QS_INJ_WR, grp); 919 920 /* Add padding */ 921 while (i < (OCELOT_BUFFER_CELL_SZ / 4)) { 922 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp); 923 i++; 924 } 925 926 /* Indicate EOF and valid bytes in last word */ 927 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) | 928 QS_INJ_CTRL_VLD_BYTES(skb->len < OCELOT_BUFFER_CELL_SZ ? 0 : last) | 929 QS_INJ_CTRL_EOF, 930 QS_INJ_CTRL, grp); 931 932 /* Add dummy CRC */ 933 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp); 934 skb_tx_timestamp(skb); 935 936 skb->dev->stats.tx_packets++; 937 skb->dev->stats.tx_bytes += skb->len; 938 } 939 EXPORT_SYMBOL(ocelot_port_inject_frame); 940 941 void ocelot_drain_cpu_queue(struct ocelot *ocelot, int grp) 942 { 943 while (ocelot_read(ocelot, QS_XTR_DATA_PRESENT) & BIT(grp)) 944 ocelot_read_rix(ocelot, QS_XTR_RD, grp); 945 } 946 EXPORT_SYMBOL(ocelot_drain_cpu_queue); 947 948 int ocelot_fdb_add(struct ocelot *ocelot, int port, 949 const unsigned char *addr, u16 vid) 950 { 951 int pgid = port; 952 953 if (port == ocelot->npi) 954 pgid = PGID_CPU; 955 956 return ocelot_mact_learn(ocelot, pgid, addr, vid, ENTRYTYPE_LOCKED); 957 } 958 EXPORT_SYMBOL(ocelot_fdb_add); 959 960 int ocelot_fdb_del(struct ocelot *ocelot, int port, 961 const unsigned char *addr, u16 vid) 962 { 963 return ocelot_mact_forget(ocelot, addr, vid); 964 } 965 EXPORT_SYMBOL(ocelot_fdb_del); 966 967 int ocelot_port_fdb_do_dump(const unsigned char *addr, u16 vid, 968 bool is_static, void *data) 969 { 970 struct ocelot_dump_ctx *dump = data; 971 u32 portid = NETLINK_CB(dump->cb->skb).portid; 972 u32 seq = dump->cb->nlh->nlmsg_seq; 973 struct nlmsghdr *nlh; 974 struct ndmsg *ndm; 975 976 if (dump->idx < dump->cb->args[2]) 977 goto skip; 978 979 nlh = nlmsg_put(dump->skb, portid, seq, RTM_NEWNEIGH, 980 sizeof(*ndm), NLM_F_MULTI); 981 if (!nlh) 982 return -EMSGSIZE; 983 984 ndm = nlmsg_data(nlh); 985 ndm->ndm_family = AF_BRIDGE; 986 ndm->ndm_pad1 = 0; 987 ndm->ndm_pad2 = 0; 988 ndm->ndm_flags = NTF_SELF; 989 ndm->ndm_type = 0; 990 ndm->ndm_ifindex = dump->dev->ifindex; 991 ndm->ndm_state = is_static ? NUD_NOARP : NUD_REACHABLE; 992 993 if (nla_put(dump->skb, NDA_LLADDR, ETH_ALEN, addr)) 994 goto nla_put_failure; 995 996 if (vid && nla_put_u16(dump->skb, NDA_VLAN, vid)) 997 goto nla_put_failure; 998 999 nlmsg_end(dump->skb, nlh); 1000 1001 skip: 1002 dump->idx++; 1003 return 0; 1004 1005 nla_put_failure: 1006 nlmsg_cancel(dump->skb, nlh); 1007 return -EMSGSIZE; 1008 } 1009 EXPORT_SYMBOL(ocelot_port_fdb_do_dump); 1010 1011 static int ocelot_mact_read(struct ocelot *ocelot, int port, int row, int col, 1012 struct ocelot_mact_entry *entry) 1013 { 1014 u32 val, dst, macl, mach; 1015 char mac[ETH_ALEN]; 1016 1017 /* Set row and column to read from */ 1018 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_M_INDEX, row); 1019 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_BUCKET, col); 1020 1021 /* Issue a read command */ 1022 ocelot_write(ocelot, 1023 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_READ), 1024 ANA_TABLES_MACACCESS); 1025 1026 if (ocelot_mact_wait_for_completion(ocelot)) 1027 return -ETIMEDOUT; 1028 1029 /* Read the entry flags */ 1030 val = ocelot_read(ocelot, ANA_TABLES_MACACCESS); 1031 if (!(val & ANA_TABLES_MACACCESS_VALID)) 1032 return -EINVAL; 1033 1034 /* If the entry read has another port configured as its destination, 1035 * do not report it. 1036 */ 1037 dst = (val & ANA_TABLES_MACACCESS_DEST_IDX_M) >> 3; 1038 if (dst != port) 1039 return -EINVAL; 1040 1041 /* Get the entry's MAC address and VLAN id */ 1042 macl = ocelot_read(ocelot, ANA_TABLES_MACLDATA); 1043 mach = ocelot_read(ocelot, ANA_TABLES_MACHDATA); 1044 1045 mac[0] = (mach >> 8) & 0xff; 1046 mac[1] = (mach >> 0) & 0xff; 1047 mac[2] = (macl >> 24) & 0xff; 1048 mac[3] = (macl >> 16) & 0xff; 1049 mac[4] = (macl >> 8) & 0xff; 1050 mac[5] = (macl >> 0) & 0xff; 1051 1052 entry->vid = (mach >> 16) & 0xfff; 1053 ether_addr_copy(entry->mac, mac); 1054 1055 return 0; 1056 } 1057 1058 int ocelot_fdb_dump(struct ocelot *ocelot, int port, 1059 dsa_fdb_dump_cb_t *cb, void *data) 1060 { 1061 int i, j; 1062 1063 /* Loop through all the mac tables entries. */ 1064 for (i = 0; i < ocelot->num_mact_rows; i++) { 1065 for (j = 0; j < 4; j++) { 1066 struct ocelot_mact_entry entry; 1067 bool is_static; 1068 int ret; 1069 1070 ret = ocelot_mact_read(ocelot, port, i, j, &entry); 1071 /* If the entry is invalid (wrong port, invalid...), 1072 * skip it. 1073 */ 1074 if (ret == -EINVAL) 1075 continue; 1076 else if (ret) 1077 return ret; 1078 1079 is_static = (entry.type == ENTRYTYPE_LOCKED); 1080 1081 ret = cb(entry.mac, entry.vid, is_static, data); 1082 if (ret) 1083 return ret; 1084 } 1085 } 1086 1087 return 0; 1088 } 1089 EXPORT_SYMBOL(ocelot_fdb_dump); 1090 1091 int ocelot_hwstamp_get(struct ocelot *ocelot, int port, struct ifreq *ifr) 1092 { 1093 return copy_to_user(ifr->ifr_data, &ocelot->hwtstamp_config, 1094 sizeof(ocelot->hwtstamp_config)) ? -EFAULT : 0; 1095 } 1096 EXPORT_SYMBOL(ocelot_hwstamp_get); 1097 1098 int ocelot_hwstamp_set(struct ocelot *ocelot, int port, struct ifreq *ifr) 1099 { 1100 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1101 struct hwtstamp_config cfg; 1102 1103 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg))) 1104 return -EFAULT; 1105 1106 /* reserved for future extensions */ 1107 if (cfg.flags) 1108 return -EINVAL; 1109 1110 /* Tx type sanity check */ 1111 switch (cfg.tx_type) { 1112 case HWTSTAMP_TX_ON: 1113 ocelot_port->ptp_cmd = IFH_REW_OP_TWO_STEP_PTP; 1114 break; 1115 case HWTSTAMP_TX_ONESTEP_SYNC: 1116 /* IFH_REW_OP_ONE_STEP_PTP updates the correctional field, we 1117 * need to update the origin time. 1118 */ 1119 ocelot_port->ptp_cmd = IFH_REW_OP_ORIGIN_PTP; 1120 break; 1121 case HWTSTAMP_TX_OFF: 1122 ocelot_port->ptp_cmd = 0; 1123 break; 1124 default: 1125 return -ERANGE; 1126 } 1127 1128 mutex_lock(&ocelot->ptp_lock); 1129 1130 switch (cfg.rx_filter) { 1131 case HWTSTAMP_FILTER_NONE: 1132 break; 1133 case HWTSTAMP_FILTER_ALL: 1134 case HWTSTAMP_FILTER_SOME: 1135 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 1136 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 1137 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 1138 case HWTSTAMP_FILTER_NTP_ALL: 1139 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 1140 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 1141 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 1142 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 1143 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 1144 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 1145 case HWTSTAMP_FILTER_PTP_V2_EVENT: 1146 case HWTSTAMP_FILTER_PTP_V2_SYNC: 1147 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 1148 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 1149 break; 1150 default: 1151 mutex_unlock(&ocelot->ptp_lock); 1152 return -ERANGE; 1153 } 1154 1155 /* Commit back the result & save it */ 1156 memcpy(&ocelot->hwtstamp_config, &cfg, sizeof(cfg)); 1157 mutex_unlock(&ocelot->ptp_lock); 1158 1159 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 1160 } 1161 EXPORT_SYMBOL(ocelot_hwstamp_set); 1162 1163 void ocelot_get_strings(struct ocelot *ocelot, int port, u32 sset, u8 *data) 1164 { 1165 int i; 1166 1167 if (sset != ETH_SS_STATS) 1168 return; 1169 1170 for (i = 0; i < ocelot->num_stats; i++) 1171 memcpy(data + i * ETH_GSTRING_LEN, ocelot->stats_layout[i].name, 1172 ETH_GSTRING_LEN); 1173 } 1174 EXPORT_SYMBOL(ocelot_get_strings); 1175 1176 static void ocelot_update_stats(struct ocelot *ocelot) 1177 { 1178 int i, j; 1179 1180 mutex_lock(&ocelot->stats_lock); 1181 1182 for (i = 0; i < ocelot->num_phys_ports; i++) { 1183 /* Configure the port to read the stats from */ 1184 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(i), SYS_STAT_CFG); 1185 1186 for (j = 0; j < ocelot->num_stats; j++) { 1187 u32 val; 1188 unsigned int idx = i * ocelot->num_stats + j; 1189 1190 val = ocelot_read_rix(ocelot, SYS_COUNT_RX_OCTETS, 1191 ocelot->stats_layout[j].offset); 1192 1193 if (val < (ocelot->stats[idx] & U32_MAX)) 1194 ocelot->stats[idx] += (u64)1 << 32; 1195 1196 ocelot->stats[idx] = (ocelot->stats[idx] & 1197 ~(u64)U32_MAX) + val; 1198 } 1199 } 1200 1201 mutex_unlock(&ocelot->stats_lock); 1202 } 1203 1204 static void ocelot_check_stats_work(struct work_struct *work) 1205 { 1206 struct delayed_work *del_work = to_delayed_work(work); 1207 struct ocelot *ocelot = container_of(del_work, struct ocelot, 1208 stats_work); 1209 1210 ocelot_update_stats(ocelot); 1211 1212 queue_delayed_work(ocelot->stats_queue, &ocelot->stats_work, 1213 OCELOT_STATS_CHECK_DELAY); 1214 } 1215 1216 void ocelot_get_ethtool_stats(struct ocelot *ocelot, int port, u64 *data) 1217 { 1218 int i; 1219 1220 /* check and update now */ 1221 ocelot_update_stats(ocelot); 1222 1223 /* Copy all counters */ 1224 for (i = 0; i < ocelot->num_stats; i++) 1225 *data++ = ocelot->stats[port * ocelot->num_stats + i]; 1226 } 1227 EXPORT_SYMBOL(ocelot_get_ethtool_stats); 1228 1229 int ocelot_get_sset_count(struct ocelot *ocelot, int port, int sset) 1230 { 1231 if (sset != ETH_SS_STATS) 1232 return -EOPNOTSUPP; 1233 1234 return ocelot->num_stats; 1235 } 1236 EXPORT_SYMBOL(ocelot_get_sset_count); 1237 1238 int ocelot_get_ts_info(struct ocelot *ocelot, int port, 1239 struct ethtool_ts_info *info) 1240 { 1241 info->phc_index = ocelot->ptp_clock ? 1242 ptp_clock_index(ocelot->ptp_clock) : -1; 1243 if (info->phc_index == -1) { 1244 info->so_timestamping |= SOF_TIMESTAMPING_TX_SOFTWARE | 1245 SOF_TIMESTAMPING_RX_SOFTWARE | 1246 SOF_TIMESTAMPING_SOFTWARE; 1247 return 0; 1248 } 1249 info->so_timestamping |= SOF_TIMESTAMPING_TX_SOFTWARE | 1250 SOF_TIMESTAMPING_RX_SOFTWARE | 1251 SOF_TIMESTAMPING_SOFTWARE | 1252 SOF_TIMESTAMPING_TX_HARDWARE | 1253 SOF_TIMESTAMPING_RX_HARDWARE | 1254 SOF_TIMESTAMPING_RAW_HARDWARE; 1255 info->tx_types = BIT(HWTSTAMP_TX_OFF) | BIT(HWTSTAMP_TX_ON) | 1256 BIT(HWTSTAMP_TX_ONESTEP_SYNC); 1257 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) | BIT(HWTSTAMP_FILTER_ALL); 1258 1259 return 0; 1260 } 1261 EXPORT_SYMBOL(ocelot_get_ts_info); 1262 1263 static u32 ocelot_get_bond_mask(struct ocelot *ocelot, struct net_device *bond, 1264 bool only_active_ports) 1265 { 1266 u32 mask = 0; 1267 int port; 1268 1269 for (port = 0; port < ocelot->num_phys_ports; port++) { 1270 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1271 1272 if (!ocelot_port) 1273 continue; 1274 1275 if (ocelot_port->bond == bond) { 1276 if (only_active_ports && !ocelot_port->lag_tx_active) 1277 continue; 1278 1279 mask |= BIT(port); 1280 } 1281 } 1282 1283 return mask; 1284 } 1285 1286 static u32 ocelot_get_bridge_fwd_mask(struct ocelot *ocelot, 1287 struct net_device *bridge) 1288 { 1289 u32 mask = 0; 1290 int port; 1291 1292 for (port = 0; port < ocelot->num_phys_ports; port++) { 1293 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1294 1295 if (!ocelot_port) 1296 continue; 1297 1298 if (ocelot_port->stp_state == BR_STATE_FORWARDING && 1299 ocelot_port->bridge == bridge) 1300 mask |= BIT(port); 1301 } 1302 1303 return mask; 1304 } 1305 1306 static u32 ocelot_get_dsa_8021q_cpu_mask(struct ocelot *ocelot) 1307 { 1308 u32 mask = 0; 1309 int port; 1310 1311 for (port = 0; port < ocelot->num_phys_ports; port++) { 1312 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1313 1314 if (!ocelot_port) 1315 continue; 1316 1317 if (ocelot_port->is_dsa_8021q_cpu) 1318 mask |= BIT(port); 1319 } 1320 1321 return mask; 1322 } 1323 1324 void ocelot_apply_bridge_fwd_mask(struct ocelot *ocelot) 1325 { 1326 unsigned long cpu_fwd_mask; 1327 int port; 1328 1329 /* If a DSA tag_8021q CPU exists, it needs to be included in the 1330 * regular forwarding path of the front ports regardless of whether 1331 * those are bridged or standalone. 1332 * If DSA tag_8021q is not used, this returns 0, which is fine because 1333 * the hardware-based CPU port module can be a destination for packets 1334 * even if it isn't part of PGID_SRC. 1335 */ 1336 cpu_fwd_mask = ocelot_get_dsa_8021q_cpu_mask(ocelot); 1337 1338 /* Apply FWD mask. The loop is needed to add/remove the current port as 1339 * a source for the other ports. 1340 */ 1341 for (port = 0; port < ocelot->num_phys_ports; port++) { 1342 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1343 unsigned long mask; 1344 1345 if (!ocelot_port) { 1346 /* Unused ports can't send anywhere */ 1347 mask = 0; 1348 } else if (ocelot_port->is_dsa_8021q_cpu) { 1349 /* The DSA tag_8021q CPU ports need to be able to 1350 * forward packets to all other ports except for 1351 * themselves 1352 */ 1353 mask = GENMASK(ocelot->num_phys_ports - 1, 0); 1354 mask &= ~cpu_fwd_mask; 1355 } else if (ocelot_port->bridge) { 1356 struct net_device *bridge = ocelot_port->bridge; 1357 struct net_device *bond = ocelot_port->bond; 1358 1359 mask = ocelot_get_bridge_fwd_mask(ocelot, bridge); 1360 mask |= cpu_fwd_mask; 1361 mask &= ~BIT(port); 1362 if (bond) { 1363 mask &= ~ocelot_get_bond_mask(ocelot, bond, 1364 false); 1365 } 1366 } else { 1367 /* Standalone ports forward only to DSA tag_8021q CPU 1368 * ports (if those exist), or to the hardware CPU port 1369 * module otherwise. 1370 */ 1371 mask = cpu_fwd_mask; 1372 } 1373 1374 ocelot_write_rix(ocelot, mask, ANA_PGID_PGID, PGID_SRC + port); 1375 } 1376 } 1377 EXPORT_SYMBOL(ocelot_apply_bridge_fwd_mask); 1378 1379 void ocelot_bridge_stp_state_set(struct ocelot *ocelot, int port, u8 state) 1380 { 1381 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1382 u32 learn_ena = 0; 1383 1384 ocelot_port->stp_state = state; 1385 1386 if ((state == BR_STATE_LEARNING || state == BR_STATE_FORWARDING) && 1387 ocelot_port->learn_ena) 1388 learn_ena = ANA_PORT_PORT_CFG_LEARN_ENA; 1389 1390 ocelot_rmw_gix(ocelot, learn_ena, ANA_PORT_PORT_CFG_LEARN_ENA, 1391 ANA_PORT_PORT_CFG, port); 1392 1393 ocelot_apply_bridge_fwd_mask(ocelot); 1394 } 1395 EXPORT_SYMBOL(ocelot_bridge_stp_state_set); 1396 1397 void ocelot_set_ageing_time(struct ocelot *ocelot, unsigned int msecs) 1398 { 1399 unsigned int age_period = ANA_AUTOAGE_AGE_PERIOD(msecs / 2000); 1400 1401 /* Setting AGE_PERIOD to zero effectively disables automatic aging, 1402 * which is clearly not what our intention is. So avoid that. 1403 */ 1404 if (!age_period) 1405 age_period = 1; 1406 1407 ocelot_rmw(ocelot, age_period, ANA_AUTOAGE_AGE_PERIOD_M, ANA_AUTOAGE); 1408 } 1409 EXPORT_SYMBOL(ocelot_set_ageing_time); 1410 1411 static struct ocelot_multicast *ocelot_multicast_get(struct ocelot *ocelot, 1412 const unsigned char *addr, 1413 u16 vid) 1414 { 1415 struct ocelot_multicast *mc; 1416 1417 list_for_each_entry(mc, &ocelot->multicast, list) { 1418 if (ether_addr_equal(mc->addr, addr) && mc->vid == vid) 1419 return mc; 1420 } 1421 1422 return NULL; 1423 } 1424 1425 static enum macaccess_entry_type ocelot_classify_mdb(const unsigned char *addr) 1426 { 1427 if (addr[0] == 0x01 && addr[1] == 0x00 && addr[2] == 0x5e) 1428 return ENTRYTYPE_MACv4; 1429 if (addr[0] == 0x33 && addr[1] == 0x33) 1430 return ENTRYTYPE_MACv6; 1431 return ENTRYTYPE_LOCKED; 1432 } 1433 1434 static struct ocelot_pgid *ocelot_pgid_alloc(struct ocelot *ocelot, int index, 1435 unsigned long ports) 1436 { 1437 struct ocelot_pgid *pgid; 1438 1439 pgid = kzalloc(sizeof(*pgid), GFP_KERNEL); 1440 if (!pgid) 1441 return ERR_PTR(-ENOMEM); 1442 1443 pgid->ports = ports; 1444 pgid->index = index; 1445 refcount_set(&pgid->refcount, 1); 1446 list_add_tail(&pgid->list, &ocelot->pgids); 1447 1448 return pgid; 1449 } 1450 1451 static void ocelot_pgid_free(struct ocelot *ocelot, struct ocelot_pgid *pgid) 1452 { 1453 if (!refcount_dec_and_test(&pgid->refcount)) 1454 return; 1455 1456 list_del(&pgid->list); 1457 kfree(pgid); 1458 } 1459 1460 static struct ocelot_pgid *ocelot_mdb_get_pgid(struct ocelot *ocelot, 1461 const struct ocelot_multicast *mc) 1462 { 1463 struct ocelot_pgid *pgid; 1464 int index; 1465 1466 /* According to VSC7514 datasheet 3.9.1.5 IPv4 Multicast Entries and 1467 * 3.9.1.6 IPv6 Multicast Entries, "Instead of a lookup in the 1468 * destination mask table (PGID), the destination set is programmed as 1469 * part of the entry MAC address.", and the DEST_IDX is set to 0. 1470 */ 1471 if (mc->entry_type == ENTRYTYPE_MACv4 || 1472 mc->entry_type == ENTRYTYPE_MACv6) 1473 return ocelot_pgid_alloc(ocelot, 0, mc->ports); 1474 1475 list_for_each_entry(pgid, &ocelot->pgids, list) { 1476 /* When searching for a nonreserved multicast PGID, ignore the 1477 * dummy PGID of zero that we have for MACv4/MACv6 entries 1478 */ 1479 if (pgid->index && pgid->ports == mc->ports) { 1480 refcount_inc(&pgid->refcount); 1481 return pgid; 1482 } 1483 } 1484 1485 /* Search for a free index in the nonreserved multicast PGID area */ 1486 for_each_nonreserved_multicast_dest_pgid(ocelot, index) { 1487 bool used = false; 1488 1489 list_for_each_entry(pgid, &ocelot->pgids, list) { 1490 if (pgid->index == index) { 1491 used = true; 1492 break; 1493 } 1494 } 1495 1496 if (!used) 1497 return ocelot_pgid_alloc(ocelot, index, mc->ports); 1498 } 1499 1500 return ERR_PTR(-ENOSPC); 1501 } 1502 1503 static void ocelot_encode_ports_to_mdb(unsigned char *addr, 1504 struct ocelot_multicast *mc) 1505 { 1506 ether_addr_copy(addr, mc->addr); 1507 1508 if (mc->entry_type == ENTRYTYPE_MACv4) { 1509 addr[0] = 0; 1510 addr[1] = mc->ports >> 8; 1511 addr[2] = mc->ports & 0xff; 1512 } else if (mc->entry_type == ENTRYTYPE_MACv6) { 1513 addr[0] = mc->ports >> 8; 1514 addr[1] = mc->ports & 0xff; 1515 } 1516 } 1517 1518 int ocelot_port_mdb_add(struct ocelot *ocelot, int port, 1519 const struct switchdev_obj_port_mdb *mdb) 1520 { 1521 unsigned char addr[ETH_ALEN]; 1522 struct ocelot_multicast *mc; 1523 struct ocelot_pgid *pgid; 1524 u16 vid = mdb->vid; 1525 1526 if (port == ocelot->npi) 1527 port = ocelot->num_phys_ports; 1528 1529 mc = ocelot_multicast_get(ocelot, mdb->addr, vid); 1530 if (!mc) { 1531 /* New entry */ 1532 mc = devm_kzalloc(ocelot->dev, sizeof(*mc), GFP_KERNEL); 1533 if (!mc) 1534 return -ENOMEM; 1535 1536 mc->entry_type = ocelot_classify_mdb(mdb->addr); 1537 ether_addr_copy(mc->addr, mdb->addr); 1538 mc->vid = vid; 1539 1540 list_add_tail(&mc->list, &ocelot->multicast); 1541 } else { 1542 /* Existing entry. Clean up the current port mask from 1543 * hardware now, because we'll be modifying it. 1544 */ 1545 ocelot_pgid_free(ocelot, mc->pgid); 1546 ocelot_encode_ports_to_mdb(addr, mc); 1547 ocelot_mact_forget(ocelot, addr, vid); 1548 } 1549 1550 mc->ports |= BIT(port); 1551 1552 pgid = ocelot_mdb_get_pgid(ocelot, mc); 1553 if (IS_ERR(pgid)) { 1554 dev_err(ocelot->dev, 1555 "Cannot allocate PGID for mdb %pM vid %d\n", 1556 mc->addr, mc->vid); 1557 devm_kfree(ocelot->dev, mc); 1558 return PTR_ERR(pgid); 1559 } 1560 mc->pgid = pgid; 1561 1562 ocelot_encode_ports_to_mdb(addr, mc); 1563 1564 if (mc->entry_type != ENTRYTYPE_MACv4 && 1565 mc->entry_type != ENTRYTYPE_MACv6) 1566 ocelot_write_rix(ocelot, pgid->ports, ANA_PGID_PGID, 1567 pgid->index); 1568 1569 return ocelot_mact_learn(ocelot, pgid->index, addr, vid, 1570 mc->entry_type); 1571 } 1572 EXPORT_SYMBOL(ocelot_port_mdb_add); 1573 1574 int ocelot_port_mdb_del(struct ocelot *ocelot, int port, 1575 const struct switchdev_obj_port_mdb *mdb) 1576 { 1577 unsigned char addr[ETH_ALEN]; 1578 struct ocelot_multicast *mc; 1579 struct ocelot_pgid *pgid; 1580 u16 vid = mdb->vid; 1581 1582 if (port == ocelot->npi) 1583 port = ocelot->num_phys_ports; 1584 1585 mc = ocelot_multicast_get(ocelot, mdb->addr, vid); 1586 if (!mc) 1587 return -ENOENT; 1588 1589 ocelot_encode_ports_to_mdb(addr, mc); 1590 ocelot_mact_forget(ocelot, addr, vid); 1591 1592 ocelot_pgid_free(ocelot, mc->pgid); 1593 mc->ports &= ~BIT(port); 1594 if (!mc->ports) { 1595 list_del(&mc->list); 1596 devm_kfree(ocelot->dev, mc); 1597 return 0; 1598 } 1599 1600 /* We have a PGID with fewer ports now */ 1601 pgid = ocelot_mdb_get_pgid(ocelot, mc); 1602 if (IS_ERR(pgid)) 1603 return PTR_ERR(pgid); 1604 mc->pgid = pgid; 1605 1606 ocelot_encode_ports_to_mdb(addr, mc); 1607 1608 if (mc->entry_type != ENTRYTYPE_MACv4 && 1609 mc->entry_type != ENTRYTYPE_MACv6) 1610 ocelot_write_rix(ocelot, pgid->ports, ANA_PGID_PGID, 1611 pgid->index); 1612 1613 return ocelot_mact_learn(ocelot, pgid->index, addr, vid, 1614 mc->entry_type); 1615 } 1616 EXPORT_SYMBOL(ocelot_port_mdb_del); 1617 1618 void ocelot_port_bridge_join(struct ocelot *ocelot, int port, 1619 struct net_device *bridge) 1620 { 1621 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1622 1623 ocelot_port->bridge = bridge; 1624 1625 ocelot_apply_bridge_fwd_mask(ocelot); 1626 } 1627 EXPORT_SYMBOL(ocelot_port_bridge_join); 1628 1629 void ocelot_port_bridge_leave(struct ocelot *ocelot, int port, 1630 struct net_device *bridge) 1631 { 1632 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1633 struct ocelot_vlan pvid = {0}, native_vlan = {0}; 1634 1635 ocelot_port->bridge = NULL; 1636 1637 ocelot_port_set_pvid(ocelot, port, pvid); 1638 ocelot_port_set_native_vlan(ocelot, port, native_vlan); 1639 ocelot_apply_bridge_fwd_mask(ocelot); 1640 } 1641 EXPORT_SYMBOL(ocelot_port_bridge_leave); 1642 1643 static void ocelot_set_aggr_pgids(struct ocelot *ocelot) 1644 { 1645 unsigned long visited = GENMASK(ocelot->num_phys_ports - 1, 0); 1646 int i, port, lag; 1647 1648 /* Reset destination and aggregation PGIDS */ 1649 for_each_unicast_dest_pgid(ocelot, port) 1650 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port); 1651 1652 for_each_aggr_pgid(ocelot, i) 1653 ocelot_write_rix(ocelot, GENMASK(ocelot->num_phys_ports - 1, 0), 1654 ANA_PGID_PGID, i); 1655 1656 /* The visited ports bitmask holds the list of ports offloading any 1657 * bonding interface. Initially we mark all these ports as unvisited, 1658 * then every time we visit a port in this bitmask, we know that it is 1659 * the lowest numbered port, i.e. the one whose logical ID == physical 1660 * port ID == LAG ID. So we mark as visited all further ports in the 1661 * bitmask that are offloading the same bonding interface. This way, 1662 * we set up the aggregation PGIDs only once per bonding interface. 1663 */ 1664 for (port = 0; port < ocelot->num_phys_ports; port++) { 1665 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1666 1667 if (!ocelot_port || !ocelot_port->bond) 1668 continue; 1669 1670 visited &= ~BIT(port); 1671 } 1672 1673 /* Now, set PGIDs for each active LAG */ 1674 for (lag = 0; lag < ocelot->num_phys_ports; lag++) { 1675 struct net_device *bond = ocelot->ports[lag]->bond; 1676 int num_active_ports = 0; 1677 unsigned long bond_mask; 1678 u8 aggr_idx[16]; 1679 1680 if (!bond || (visited & BIT(lag))) 1681 continue; 1682 1683 bond_mask = ocelot_get_bond_mask(ocelot, bond, true); 1684 1685 for_each_set_bit(port, &bond_mask, ocelot->num_phys_ports) { 1686 // Destination mask 1687 ocelot_write_rix(ocelot, bond_mask, 1688 ANA_PGID_PGID, port); 1689 aggr_idx[num_active_ports++] = port; 1690 } 1691 1692 for_each_aggr_pgid(ocelot, i) { 1693 u32 ac; 1694 1695 ac = ocelot_read_rix(ocelot, ANA_PGID_PGID, i); 1696 ac &= ~bond_mask; 1697 /* Don't do division by zero if there was no active 1698 * port. Just make all aggregation codes zero. 1699 */ 1700 if (num_active_ports) 1701 ac |= BIT(aggr_idx[i % num_active_ports]); 1702 ocelot_write_rix(ocelot, ac, ANA_PGID_PGID, i); 1703 } 1704 1705 /* Mark all ports in the same LAG as visited to avoid applying 1706 * the same config again. 1707 */ 1708 for (port = lag; port < ocelot->num_phys_ports; port++) { 1709 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1710 1711 if (!ocelot_port) 1712 continue; 1713 1714 if (ocelot_port->bond == bond) 1715 visited |= BIT(port); 1716 } 1717 } 1718 } 1719 1720 /* When offloading a bonding interface, the switch ports configured under the 1721 * same bond must have the same logical port ID, equal to the physical port ID 1722 * of the lowest numbered physical port in that bond. Otherwise, in standalone/ 1723 * bridged mode, each port has a logical port ID equal to its physical port ID. 1724 */ 1725 static void ocelot_setup_logical_port_ids(struct ocelot *ocelot) 1726 { 1727 int port; 1728 1729 for (port = 0; port < ocelot->num_phys_ports; port++) { 1730 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1731 struct net_device *bond; 1732 1733 if (!ocelot_port) 1734 continue; 1735 1736 bond = ocelot_port->bond; 1737 if (bond) { 1738 int lag = __ffs(ocelot_get_bond_mask(ocelot, bond, 1739 false)); 1740 1741 ocelot_rmw_gix(ocelot, 1742 ANA_PORT_PORT_CFG_PORTID_VAL(lag), 1743 ANA_PORT_PORT_CFG_PORTID_VAL_M, 1744 ANA_PORT_PORT_CFG, port); 1745 } else { 1746 ocelot_rmw_gix(ocelot, 1747 ANA_PORT_PORT_CFG_PORTID_VAL(port), 1748 ANA_PORT_PORT_CFG_PORTID_VAL_M, 1749 ANA_PORT_PORT_CFG, port); 1750 } 1751 } 1752 } 1753 1754 int ocelot_port_lag_join(struct ocelot *ocelot, int port, 1755 struct net_device *bond, 1756 struct netdev_lag_upper_info *info) 1757 { 1758 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) 1759 return -EOPNOTSUPP; 1760 1761 ocelot->ports[port]->bond = bond; 1762 1763 ocelot_setup_logical_port_ids(ocelot); 1764 ocelot_apply_bridge_fwd_mask(ocelot); 1765 ocelot_set_aggr_pgids(ocelot); 1766 1767 return 0; 1768 } 1769 EXPORT_SYMBOL(ocelot_port_lag_join); 1770 1771 void ocelot_port_lag_leave(struct ocelot *ocelot, int port, 1772 struct net_device *bond) 1773 { 1774 ocelot->ports[port]->bond = NULL; 1775 1776 ocelot_setup_logical_port_ids(ocelot); 1777 ocelot_apply_bridge_fwd_mask(ocelot); 1778 ocelot_set_aggr_pgids(ocelot); 1779 } 1780 EXPORT_SYMBOL(ocelot_port_lag_leave); 1781 1782 void ocelot_port_lag_change(struct ocelot *ocelot, int port, bool lag_tx_active) 1783 { 1784 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1785 1786 ocelot_port->lag_tx_active = lag_tx_active; 1787 1788 /* Rebalance the LAGs */ 1789 ocelot_set_aggr_pgids(ocelot); 1790 } 1791 EXPORT_SYMBOL(ocelot_port_lag_change); 1792 1793 /* Configure the maximum SDU (L2 payload) on RX to the value specified in @sdu. 1794 * The length of VLAN tags is accounted for automatically via DEV_MAC_TAGS_CFG. 1795 * In the special case that it's the NPI port that we're configuring, the 1796 * length of the tag and optional prefix needs to be accounted for privately, 1797 * in order to be able to sustain communication at the requested @sdu. 1798 */ 1799 void ocelot_port_set_maxlen(struct ocelot *ocelot, int port, size_t sdu) 1800 { 1801 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1802 int maxlen = sdu + ETH_HLEN + ETH_FCS_LEN; 1803 int pause_start, pause_stop; 1804 int atop, atop_tot; 1805 1806 if (port == ocelot->npi) { 1807 maxlen += OCELOT_TAG_LEN; 1808 1809 if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_SHORT) 1810 maxlen += OCELOT_SHORT_PREFIX_LEN; 1811 else if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_LONG) 1812 maxlen += OCELOT_LONG_PREFIX_LEN; 1813 } 1814 1815 ocelot_port_writel(ocelot_port, maxlen, DEV_MAC_MAXLEN_CFG); 1816 1817 /* Set Pause watermark hysteresis */ 1818 pause_start = 6 * maxlen / OCELOT_BUFFER_CELL_SZ; 1819 pause_stop = 4 * maxlen / OCELOT_BUFFER_CELL_SZ; 1820 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_START, 1821 pause_start); 1822 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_STOP, 1823 pause_stop); 1824 1825 /* Tail dropping watermarks */ 1826 atop_tot = (ocelot->packet_buffer_size - 9 * maxlen) / 1827 OCELOT_BUFFER_CELL_SZ; 1828 atop = (9 * maxlen) / OCELOT_BUFFER_CELL_SZ; 1829 ocelot_write_rix(ocelot, ocelot->ops->wm_enc(atop), SYS_ATOP, port); 1830 ocelot_write(ocelot, ocelot->ops->wm_enc(atop_tot), SYS_ATOP_TOT_CFG); 1831 } 1832 EXPORT_SYMBOL(ocelot_port_set_maxlen); 1833 1834 int ocelot_get_max_mtu(struct ocelot *ocelot, int port) 1835 { 1836 int max_mtu = 65535 - ETH_HLEN - ETH_FCS_LEN; 1837 1838 if (port == ocelot->npi) { 1839 max_mtu -= OCELOT_TAG_LEN; 1840 1841 if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_SHORT) 1842 max_mtu -= OCELOT_SHORT_PREFIX_LEN; 1843 else if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_LONG) 1844 max_mtu -= OCELOT_LONG_PREFIX_LEN; 1845 } 1846 1847 return max_mtu; 1848 } 1849 EXPORT_SYMBOL(ocelot_get_max_mtu); 1850 1851 static void ocelot_port_set_learning(struct ocelot *ocelot, int port, 1852 bool enabled) 1853 { 1854 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1855 u32 val = 0; 1856 1857 if (enabled) 1858 val = ANA_PORT_PORT_CFG_LEARN_ENA; 1859 1860 ocelot_rmw_gix(ocelot, val, ANA_PORT_PORT_CFG_LEARN_ENA, 1861 ANA_PORT_PORT_CFG, port); 1862 1863 ocelot_port->learn_ena = enabled; 1864 } 1865 1866 static void ocelot_port_set_ucast_flood(struct ocelot *ocelot, int port, 1867 bool enabled) 1868 { 1869 u32 val = 0; 1870 1871 if (enabled) 1872 val = BIT(port); 1873 1874 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_UC); 1875 } 1876 1877 static void ocelot_port_set_mcast_flood(struct ocelot *ocelot, int port, 1878 bool enabled) 1879 { 1880 u32 val = 0; 1881 1882 if (enabled) 1883 val = BIT(port); 1884 1885 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_MC); 1886 } 1887 1888 static void ocelot_port_set_bcast_flood(struct ocelot *ocelot, int port, 1889 bool enabled) 1890 { 1891 u32 val = 0; 1892 1893 if (enabled) 1894 val = BIT(port); 1895 1896 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_BC); 1897 } 1898 1899 int ocelot_port_pre_bridge_flags(struct ocelot *ocelot, int port, 1900 struct switchdev_brport_flags flags) 1901 { 1902 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | 1903 BR_BCAST_FLOOD)) 1904 return -EINVAL; 1905 1906 return 0; 1907 } 1908 EXPORT_SYMBOL(ocelot_port_pre_bridge_flags); 1909 1910 void ocelot_port_bridge_flags(struct ocelot *ocelot, int port, 1911 struct switchdev_brport_flags flags) 1912 { 1913 if (flags.mask & BR_LEARNING) 1914 ocelot_port_set_learning(ocelot, port, 1915 !!(flags.val & BR_LEARNING)); 1916 1917 if (flags.mask & BR_FLOOD) 1918 ocelot_port_set_ucast_flood(ocelot, port, 1919 !!(flags.val & BR_FLOOD)); 1920 1921 if (flags.mask & BR_MCAST_FLOOD) 1922 ocelot_port_set_mcast_flood(ocelot, port, 1923 !!(flags.val & BR_MCAST_FLOOD)); 1924 1925 if (flags.mask & BR_BCAST_FLOOD) 1926 ocelot_port_set_bcast_flood(ocelot, port, 1927 !!(flags.val & BR_BCAST_FLOOD)); 1928 } 1929 EXPORT_SYMBOL(ocelot_port_bridge_flags); 1930 1931 void ocelot_init_port(struct ocelot *ocelot, int port) 1932 { 1933 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1934 1935 skb_queue_head_init(&ocelot_port->tx_skbs); 1936 spin_lock_init(&ocelot_port->ts_id_lock); 1937 1938 /* Basic L2 initialization */ 1939 1940 /* Set MAC IFG Gaps 1941 * FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 0 1942 * !FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 5 1943 */ 1944 ocelot_port_writel(ocelot_port, DEV_MAC_IFG_CFG_TX_IFG(5), 1945 DEV_MAC_IFG_CFG); 1946 1947 /* Load seed (0) and set MAC HDX late collision */ 1948 ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67) | 1949 DEV_MAC_HDX_CFG_SEED_LOAD, 1950 DEV_MAC_HDX_CFG); 1951 mdelay(1); 1952 ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67), 1953 DEV_MAC_HDX_CFG); 1954 1955 /* Set Max Length and maximum tags allowed */ 1956 ocelot_port_set_maxlen(ocelot, port, ETH_DATA_LEN); 1957 ocelot_port_writel(ocelot_port, DEV_MAC_TAGS_CFG_TAG_ID(ETH_P_8021AD) | 1958 DEV_MAC_TAGS_CFG_VLAN_AWR_ENA | 1959 DEV_MAC_TAGS_CFG_VLAN_DBL_AWR_ENA | 1960 DEV_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA, 1961 DEV_MAC_TAGS_CFG); 1962 1963 /* Set SMAC of Pause frame (00:00:00:00:00:00) */ 1964 ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_HIGH_CFG); 1965 ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_LOW_CFG); 1966 1967 /* Enable transmission of pause frames */ 1968 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, 1); 1969 1970 /* Drop frames with multicast source address */ 1971 ocelot_rmw_gix(ocelot, ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA, 1972 ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA, 1973 ANA_PORT_DROP_CFG, port); 1974 1975 /* Set default VLAN and tag type to 8021Q. */ 1976 ocelot_rmw_gix(ocelot, REW_PORT_VLAN_CFG_PORT_TPID(ETH_P_8021Q), 1977 REW_PORT_VLAN_CFG_PORT_TPID_M, 1978 REW_PORT_VLAN_CFG, port); 1979 1980 /* Disable source address learning for standalone mode */ 1981 ocelot_port_set_learning(ocelot, port, false); 1982 1983 /* Set the port's initial logical port ID value, enable receiving 1984 * frames on it, and configure the MAC address learning type to 1985 * automatic. 1986 */ 1987 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_LEARNAUTO | 1988 ANA_PORT_PORT_CFG_RECV_ENA | 1989 ANA_PORT_PORT_CFG_PORTID_VAL(port), 1990 ANA_PORT_PORT_CFG, port); 1991 1992 /* Enable vcap lookups */ 1993 ocelot_vcap_enable(ocelot, port); 1994 } 1995 EXPORT_SYMBOL(ocelot_init_port); 1996 1997 /* Configure and enable the CPU port module, which is a set of queues 1998 * accessible through register MMIO, frame DMA or Ethernet (in case 1999 * NPI mode is used). 2000 */ 2001 static void ocelot_cpu_port_init(struct ocelot *ocelot) 2002 { 2003 int cpu = ocelot->num_phys_ports; 2004 2005 /* The unicast destination PGID for the CPU port module is unused */ 2006 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, cpu); 2007 /* Instead set up a multicast destination PGID for traffic copied to 2008 * the CPU. Whitelisted MAC addresses like the port netdevice MAC 2009 * addresses will be copied to the CPU via this PGID. 2010 */ 2011 ocelot_write_rix(ocelot, BIT(cpu), ANA_PGID_PGID, PGID_CPU); 2012 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_RECV_ENA | 2013 ANA_PORT_PORT_CFG_PORTID_VAL(cpu), 2014 ANA_PORT_PORT_CFG, cpu); 2015 2016 /* Enable CPU port module */ 2017 ocelot_fields_write(ocelot, cpu, QSYS_SWITCH_PORT_MODE_PORT_ENA, 1); 2018 /* CPU port Injection/Extraction configuration */ 2019 ocelot_fields_write(ocelot, cpu, SYS_PORT_MODE_INCL_XTR_HDR, 2020 OCELOT_TAG_PREFIX_NONE); 2021 ocelot_fields_write(ocelot, cpu, SYS_PORT_MODE_INCL_INJ_HDR, 2022 OCELOT_TAG_PREFIX_NONE); 2023 2024 /* Configure the CPU port to be VLAN aware */ 2025 ocelot_write_gix(ocelot, ANA_PORT_VLAN_CFG_VLAN_VID(0) | 2026 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 2027 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1), 2028 ANA_PORT_VLAN_CFG, cpu); 2029 } 2030 2031 static void ocelot_detect_features(struct ocelot *ocelot) 2032 { 2033 int mmgt, eq_ctrl; 2034 2035 /* For Ocelot, Felix, Seville, Serval etc, SYS:MMGT:MMGT:FREECNT holds 2036 * the number of 240-byte free memory words (aka 4-cell chunks) and not 2037 * 192 bytes as the documentation incorrectly says. 2038 */ 2039 mmgt = ocelot_read(ocelot, SYS_MMGT); 2040 ocelot->packet_buffer_size = 240 * SYS_MMGT_FREECNT(mmgt); 2041 2042 eq_ctrl = ocelot_read(ocelot, QSYS_EQ_CTRL); 2043 ocelot->num_frame_refs = QSYS_MMGT_EQ_CTRL_FP_FREE_CNT(eq_ctrl); 2044 } 2045 2046 int ocelot_init(struct ocelot *ocelot) 2047 { 2048 char queue_name[32]; 2049 int i, ret; 2050 u32 port; 2051 2052 if (ocelot->ops->reset) { 2053 ret = ocelot->ops->reset(ocelot); 2054 if (ret) { 2055 dev_err(ocelot->dev, "Switch reset failed\n"); 2056 return ret; 2057 } 2058 } 2059 2060 ocelot->stats = devm_kcalloc(ocelot->dev, 2061 ocelot->num_phys_ports * ocelot->num_stats, 2062 sizeof(u64), GFP_KERNEL); 2063 if (!ocelot->stats) 2064 return -ENOMEM; 2065 2066 mutex_init(&ocelot->stats_lock); 2067 mutex_init(&ocelot->ptp_lock); 2068 spin_lock_init(&ocelot->ptp_clock_lock); 2069 snprintf(queue_name, sizeof(queue_name), "%s-stats", 2070 dev_name(ocelot->dev)); 2071 ocelot->stats_queue = create_singlethread_workqueue(queue_name); 2072 if (!ocelot->stats_queue) 2073 return -ENOMEM; 2074 2075 ocelot->owq = alloc_ordered_workqueue("ocelot-owq", 0); 2076 if (!ocelot->owq) { 2077 destroy_workqueue(ocelot->stats_queue); 2078 return -ENOMEM; 2079 } 2080 2081 INIT_LIST_HEAD(&ocelot->multicast); 2082 INIT_LIST_HEAD(&ocelot->pgids); 2083 ocelot_detect_features(ocelot); 2084 ocelot_mact_init(ocelot); 2085 ocelot_vlan_init(ocelot); 2086 ocelot_vcap_init(ocelot); 2087 ocelot_cpu_port_init(ocelot); 2088 2089 for (port = 0; port < ocelot->num_phys_ports; port++) { 2090 /* Clear all counters (5 groups) */ 2091 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(port) | 2092 SYS_STAT_CFG_STAT_CLEAR_SHOT(0x7f), 2093 SYS_STAT_CFG); 2094 } 2095 2096 /* Only use S-Tag */ 2097 ocelot_write(ocelot, ETH_P_8021AD, SYS_VLAN_ETYPE_CFG); 2098 2099 /* Aggregation mode */ 2100 ocelot_write(ocelot, ANA_AGGR_CFG_AC_SMAC_ENA | 2101 ANA_AGGR_CFG_AC_DMAC_ENA | 2102 ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA | 2103 ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA | 2104 ANA_AGGR_CFG_AC_IP6_FLOW_LBL_ENA | 2105 ANA_AGGR_CFG_AC_IP6_TCPUDP_ENA, 2106 ANA_AGGR_CFG); 2107 2108 /* Set MAC age time to default value. The entry is aged after 2109 * 2*AGE_PERIOD 2110 */ 2111 ocelot_write(ocelot, 2112 ANA_AUTOAGE_AGE_PERIOD(BR_DEFAULT_AGEING_TIME / 2 / HZ), 2113 ANA_AUTOAGE); 2114 2115 /* Disable learning for frames discarded by VLAN ingress filtering */ 2116 regmap_field_write(ocelot->regfields[ANA_ADVLEARN_VLAN_CHK], 1); 2117 2118 /* Setup frame ageing - fixed value "2 sec" - in 6.5 us units */ 2119 ocelot_write(ocelot, SYS_FRM_AGING_AGE_TX_ENA | 2120 SYS_FRM_AGING_MAX_AGE(307692), SYS_FRM_AGING); 2121 2122 /* Setup flooding PGIDs */ 2123 for (i = 0; i < ocelot->num_flooding_pgids; i++) 2124 ocelot_write_rix(ocelot, ANA_FLOODING_FLD_MULTICAST(PGID_MC) | 2125 ANA_FLOODING_FLD_BROADCAST(PGID_BC) | 2126 ANA_FLOODING_FLD_UNICAST(PGID_UC), 2127 ANA_FLOODING, i); 2128 ocelot_write(ocelot, ANA_FLOODING_IPMC_FLD_MC6_DATA(PGID_MCIPV6) | 2129 ANA_FLOODING_IPMC_FLD_MC6_CTRL(PGID_MC) | 2130 ANA_FLOODING_IPMC_FLD_MC4_DATA(PGID_MCIPV4) | 2131 ANA_FLOODING_IPMC_FLD_MC4_CTRL(PGID_MC), 2132 ANA_FLOODING_IPMC); 2133 2134 for (port = 0; port < ocelot->num_phys_ports; port++) { 2135 /* Transmit the frame to the local port. */ 2136 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port); 2137 /* Do not forward BPDU frames to the front ports. */ 2138 ocelot_write_gix(ocelot, 2139 ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA(0xffff), 2140 ANA_PORT_CPU_FWD_BPDU_CFG, 2141 port); 2142 /* Ensure bridging is disabled */ 2143 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_SRC + port); 2144 } 2145 2146 for_each_nonreserved_multicast_dest_pgid(ocelot, i) { 2147 u32 val = ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports - 1, 0)); 2148 2149 ocelot_write_rix(ocelot, val, ANA_PGID_PGID, i); 2150 } 2151 2152 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_BLACKHOLE); 2153 2154 /* Allow broadcast and unknown L2 multicast to the CPU. */ 2155 ocelot_rmw_rix(ocelot, ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)), 2156 ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)), 2157 ANA_PGID_PGID, PGID_MC); 2158 ocelot_rmw_rix(ocelot, ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)), 2159 ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)), 2160 ANA_PGID_PGID, PGID_BC); 2161 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV4); 2162 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV6); 2163 2164 /* Allow manual injection via DEVCPU_QS registers, and byte swap these 2165 * registers endianness. 2166 */ 2167 ocelot_write_rix(ocelot, QS_INJ_GRP_CFG_BYTE_SWAP | 2168 QS_INJ_GRP_CFG_MODE(1), QS_INJ_GRP_CFG, 0); 2169 ocelot_write_rix(ocelot, QS_XTR_GRP_CFG_BYTE_SWAP | 2170 QS_XTR_GRP_CFG_MODE(1), QS_XTR_GRP_CFG, 0); 2171 ocelot_write(ocelot, ANA_CPUQ_CFG_CPUQ_MIRROR(2) | 2172 ANA_CPUQ_CFG_CPUQ_LRN(2) | 2173 ANA_CPUQ_CFG_CPUQ_MAC_COPY(2) | 2174 ANA_CPUQ_CFG_CPUQ_SRC_COPY(2) | 2175 ANA_CPUQ_CFG_CPUQ_LOCKED_PORTMOVE(2) | 2176 ANA_CPUQ_CFG_CPUQ_ALLBRIDGE(6) | 2177 ANA_CPUQ_CFG_CPUQ_IPMC_CTRL(6) | 2178 ANA_CPUQ_CFG_CPUQ_IGMP(6) | 2179 ANA_CPUQ_CFG_CPUQ_MLD(6), ANA_CPUQ_CFG); 2180 for (i = 0; i < 16; i++) 2181 ocelot_write_rix(ocelot, ANA_CPUQ_8021_CFG_CPUQ_GARP_VAL(6) | 2182 ANA_CPUQ_8021_CFG_CPUQ_BPDU_VAL(6), 2183 ANA_CPUQ_8021_CFG, i); 2184 2185 INIT_DELAYED_WORK(&ocelot->stats_work, ocelot_check_stats_work); 2186 queue_delayed_work(ocelot->stats_queue, &ocelot->stats_work, 2187 OCELOT_STATS_CHECK_DELAY); 2188 2189 return 0; 2190 } 2191 EXPORT_SYMBOL(ocelot_init); 2192 2193 void ocelot_deinit(struct ocelot *ocelot) 2194 { 2195 cancel_delayed_work(&ocelot->stats_work); 2196 destroy_workqueue(ocelot->stats_queue); 2197 destroy_workqueue(ocelot->owq); 2198 mutex_destroy(&ocelot->stats_lock); 2199 } 2200 EXPORT_SYMBOL(ocelot_deinit); 2201 2202 void ocelot_deinit_port(struct ocelot *ocelot, int port) 2203 { 2204 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2205 2206 skb_queue_purge(&ocelot_port->tx_skbs); 2207 } 2208 EXPORT_SYMBOL(ocelot_deinit_port); 2209 2210 MODULE_LICENSE("Dual MIT/GPL"); 2211