1ab0e493eSDaniel Machon /* SPDX-License-Identifier: GPL-2.0+ */ 2ab0e493eSDaniel Machon /* Microchip Sparx5 Switch driver 3ab0e493eSDaniel Machon * 4ab0e493eSDaniel Machon * Copyright (c) 2022 Microchip Technology Inc. and its subsidiaries. 5ab0e493eSDaniel Machon */ 6ab0e493eSDaniel Machon 7ab0e493eSDaniel Machon #ifndef __SPARX5_QOS_H__ 8ab0e493eSDaniel Machon #define __SPARX5_QOS_H__ 9ab0e493eSDaniel Machon 10ab0e493eSDaniel Machon #include <linux/netdevice.h> 11ab0e493eSDaniel Machon 12e02a5ac6SDaniel Machon /* Number of Layers */ 13e02a5ac6SDaniel Machon #define SPX5_HSCH_LAYER_CNT 3 14e02a5ac6SDaniel Machon 15e02a5ac6SDaniel Machon /* Scheduling elements per layer */ 16e02a5ac6SDaniel Machon #define SPX5_HSCH_L0_SE_CNT 5040 17e02a5ac6SDaniel Machon #define SPX5_HSCH_L1_SE_CNT 64 18e02a5ac6SDaniel Machon #define SPX5_HSCH_L2_SE_CNT 64 19e02a5ac6SDaniel Machon 20e02a5ac6SDaniel Machon /* Calculate Layer 0 Scheduler Element when using normal hierarchy */ 21e02a5ac6SDaniel Machon #define SPX5_HSCH_L0_GET_IDX(port, queue) ((64 * (port)) + (8 * (queue))) 22e02a5ac6SDaniel Machon 23e02a5ac6SDaniel Machon /* Number of leak groups */ 24e02a5ac6SDaniel Machon #define SPX5_HSCH_LEAK_GRP_CNT 4 25e02a5ac6SDaniel Machon 26e02a5ac6SDaniel Machon /* Scheduler modes */ 27e02a5ac6SDaniel Machon #define SPX5_SE_MODE_LINERATE 0 28e02a5ac6SDaniel Machon #define SPX5_SE_MODE_DATARATE 1 29e02a5ac6SDaniel Machon 30e02a5ac6SDaniel Machon /* Rate and burst */ 31e02a5ac6SDaniel Machon #define SPX5_SE_RATE_MAX 262143 32e02a5ac6SDaniel Machon #define SPX5_SE_BURST_MAX 127 33e02a5ac6SDaniel Machon #define SPX5_SE_RATE_MIN 1 34e02a5ac6SDaniel Machon #define SPX5_SE_BURST_MIN 1 35e02a5ac6SDaniel Machon #define SPX5_SE_BURST_UNIT 4096 36e02a5ac6SDaniel Machon 37*21122542SDaniel Machon /* Dwrr */ 38*21122542SDaniel Machon #define SPX5_DWRR_COST_MAX 63 39*21122542SDaniel Machon 40e02a5ac6SDaniel Machon struct sparx5_shaper { 41e02a5ac6SDaniel Machon u32 mode; 42e02a5ac6SDaniel Machon u32 rate; 43e02a5ac6SDaniel Machon u32 burst; 44e02a5ac6SDaniel Machon }; 45e02a5ac6SDaniel Machon 46e02a5ac6SDaniel Machon struct sparx5_lg { 47e02a5ac6SDaniel Machon u32 max_rate; 48e02a5ac6SDaniel Machon u32 resolution; 49e02a5ac6SDaniel Machon u32 leak_time; 50e02a5ac6SDaniel Machon u32 max_ses; 51e02a5ac6SDaniel Machon }; 52e02a5ac6SDaniel Machon 53e02a5ac6SDaniel Machon struct sparx5_layer { 54e02a5ac6SDaniel Machon struct sparx5_lg leak_groups[SPX5_HSCH_LEAK_GRP_CNT]; 55e02a5ac6SDaniel Machon }; 56e02a5ac6SDaniel Machon 57*21122542SDaniel Machon struct sparx5_dwrr { 58*21122542SDaniel Machon u32 count; /* Number of inputs running dwrr */ 59*21122542SDaniel Machon u8 cost[SPX5_PRIOS]; 60*21122542SDaniel Machon }; 61*21122542SDaniel Machon 62e02a5ac6SDaniel Machon int sparx5_qos_init(struct sparx5 *sparx5); 63e02a5ac6SDaniel Machon 64ab0e493eSDaniel Machon /* Multi-Queue Priority */ 65ab0e493eSDaniel Machon int sparx5_tc_mqprio_add(struct net_device *ndev, u8 num_tc); 66ab0e493eSDaniel Machon int sparx5_tc_mqprio_del(struct net_device *ndev); 67ab0e493eSDaniel Machon 68e02a5ac6SDaniel Machon /* Token Bucket Filter */ 69e02a5ac6SDaniel Machon struct tc_tbf_qopt_offload_replace_params; 70e02a5ac6SDaniel Machon int sparx5_tc_tbf_add(struct sparx5_port *port, 71e02a5ac6SDaniel Machon struct tc_tbf_qopt_offload_replace_params *params, 72e02a5ac6SDaniel Machon u32 layer, u32 idx); 73e02a5ac6SDaniel Machon int sparx5_tc_tbf_del(struct sparx5_port *port, u32 layer, u32 idx); 74e02a5ac6SDaniel Machon 75*21122542SDaniel Machon /* Enhanced Transmission Selection */ 76*21122542SDaniel Machon struct tc_ets_qopt_offload_replace_params; 77*21122542SDaniel Machon int sparx5_tc_ets_add(struct sparx5_port *port, 78*21122542SDaniel Machon struct tc_ets_qopt_offload_replace_params *params); 79*21122542SDaniel Machon 80*21122542SDaniel Machon int sparx5_tc_ets_del(struct sparx5_port *port); 81*21122542SDaniel Machon 82ab0e493eSDaniel Machon #endif /* __SPARX5_QOS_H__ */ 83