xref: /openbmc/linux/drivers/net/ethernet/microchip/sparx5/sparx5_port.h (revision 9a87ffc99ec8eb8d35eed7c4f816d75f5cc9662e)
1946e7fd5SSteen Hegelund /* SPDX-License-Identifier: GPL-2.0+ */
2946e7fd5SSteen Hegelund /* Microchip Sparx5 Switch driver
3946e7fd5SSteen Hegelund  *
4946e7fd5SSteen Hegelund  * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries.
5946e7fd5SSteen Hegelund  */
6946e7fd5SSteen Hegelund 
7946e7fd5SSteen Hegelund #ifndef __SPARX5_PORT_H__
8946e7fd5SSteen Hegelund #define __SPARX5_PORT_H__
9946e7fd5SSteen Hegelund 
10946e7fd5SSteen Hegelund #include "sparx5_main.h"
11946e7fd5SSteen Hegelund 
122234879fSDaniel Machon /* Port PCP rewrite mode */
132234879fSDaniel Machon #define SPARX5_PORT_REW_TAG_CTRL_CLASSIFIED 0
142234879fSDaniel Machon #define SPARX5_PORT_REW_TAG_CTRL_DEFAULT 1
152234879fSDaniel Machon #define SPARX5_PORT_REW_TAG_CTRL_MAPPED  2
162234879fSDaniel Machon 
17*246c77f6SDaniel Machon /* Port DSCP rewrite mode */
18*246c77f6SDaniel Machon #define SPARX5_PORT_REW_DSCP_NONE 0
19*246c77f6SDaniel Machon #define SPARX5_PORT_REW_DSCP_IF_ZERO 1
20*246c77f6SDaniel Machon #define SPARX5_PORT_REW_DSCP_SELECTED  2
21*246c77f6SDaniel Machon #define SPARX5_PORT_REW_DSCP_ALL 3
22*246c77f6SDaniel Machon 
sparx5_port_is_2g5(int portno)23946e7fd5SSteen Hegelund static inline bool sparx5_port_is_2g5(int portno)
24946e7fd5SSteen Hegelund {
25946e7fd5SSteen Hegelund 	return portno >= 16 && portno <= 47;
26946e7fd5SSteen Hegelund }
27946e7fd5SSteen Hegelund 
sparx5_port_is_5g(int portno)28946e7fd5SSteen Hegelund static inline bool sparx5_port_is_5g(int portno)
29946e7fd5SSteen Hegelund {
30946e7fd5SSteen Hegelund 	return portno <= 11 || portno == 64;
31946e7fd5SSteen Hegelund }
32946e7fd5SSteen Hegelund 
sparx5_port_is_10g(int portno)33946e7fd5SSteen Hegelund static inline bool sparx5_port_is_10g(int portno)
34946e7fd5SSteen Hegelund {
35946e7fd5SSteen Hegelund 	return (portno >= 12 && portno <= 15) || (portno >= 48 && portno <= 55);
36946e7fd5SSteen Hegelund }
37946e7fd5SSteen Hegelund 
sparx5_port_is_25g(int portno)38946e7fd5SSteen Hegelund static inline bool sparx5_port_is_25g(int portno)
39946e7fd5SSteen Hegelund {
40946e7fd5SSteen Hegelund 	return portno >= 56 && portno <= 63;
41946e7fd5SSteen Hegelund }
42946e7fd5SSteen Hegelund 
sparx5_to_high_dev(int port)43946e7fd5SSteen Hegelund static inline u32 sparx5_to_high_dev(int port)
44946e7fd5SSteen Hegelund {
45946e7fd5SSteen Hegelund 	if (sparx5_port_is_5g(port))
46946e7fd5SSteen Hegelund 		return TARGET_DEV5G;
47946e7fd5SSteen Hegelund 	if (sparx5_port_is_10g(port))
48946e7fd5SSteen Hegelund 		return TARGET_DEV10G;
49946e7fd5SSteen Hegelund 	return TARGET_DEV25G;
50946e7fd5SSteen Hegelund }
51946e7fd5SSteen Hegelund 
sparx5_to_pcs_dev(int port)52946e7fd5SSteen Hegelund static inline u32 sparx5_to_pcs_dev(int port)
53946e7fd5SSteen Hegelund {
54946e7fd5SSteen Hegelund 	if (sparx5_port_is_5g(port))
55946e7fd5SSteen Hegelund 		return TARGET_PCS5G_BR;
56946e7fd5SSteen Hegelund 	if (sparx5_port_is_10g(port))
57946e7fd5SSteen Hegelund 		return TARGET_PCS10G_BR;
58946e7fd5SSteen Hegelund 	return TARGET_PCS25G_BR;
59946e7fd5SSteen Hegelund }
60946e7fd5SSteen Hegelund 
sparx5_port_dev_index(int port)61946e7fd5SSteen Hegelund static inline int sparx5_port_dev_index(int port)
62946e7fd5SSteen Hegelund {
63946e7fd5SSteen Hegelund 	if (sparx5_port_is_2g5(port))
64946e7fd5SSteen Hegelund 		return port;
65946e7fd5SSteen Hegelund 	if (sparx5_port_is_5g(port))
66946e7fd5SSteen Hegelund 		return (port <= 11 ? port : 12);
67946e7fd5SSteen Hegelund 	if (sparx5_port_is_10g(port))
68946e7fd5SSteen Hegelund 		return (port >= 12 && port <= 15) ?
69946e7fd5SSteen Hegelund 			port - 12 : port - 44;
70946e7fd5SSteen Hegelund 	return (port - 56);
71946e7fd5SSteen Hegelund }
72946e7fd5SSteen Hegelund 
73946e7fd5SSteen Hegelund int sparx5_port_init(struct sparx5 *sparx5,
74946e7fd5SSteen Hegelund 		     struct sparx5_port *spx5_port,
75946e7fd5SSteen Hegelund 		     struct sparx5_port_config *conf);
76946e7fd5SSteen Hegelund 
77946e7fd5SSteen Hegelund int sparx5_port_config(struct sparx5 *sparx5,
78946e7fd5SSteen Hegelund 		       struct sparx5_port *spx5_port,
79946e7fd5SSteen Hegelund 		       struct sparx5_port_config *conf);
80946e7fd5SSteen Hegelund 
81946e7fd5SSteen Hegelund int sparx5_port_pcs_set(struct sparx5 *sparx5,
82946e7fd5SSteen Hegelund 			struct sparx5_port *port,
83946e7fd5SSteen Hegelund 			struct sparx5_port_config *conf);
84946e7fd5SSteen Hegelund 
85946e7fd5SSteen Hegelund int sparx5_serdes_set(struct sparx5 *sparx5,
86946e7fd5SSteen Hegelund 		      struct sparx5_port *spx5_port,
87946e7fd5SSteen Hegelund 		      struct sparx5_port_config *conf);
88946e7fd5SSteen Hegelund 
89946e7fd5SSteen Hegelund struct sparx5_port_status {
90946e7fd5SSteen Hegelund 	bool link;
91946e7fd5SSteen Hegelund 	bool link_down;
92946e7fd5SSteen Hegelund 	int  speed;
93946e7fd5SSteen Hegelund 	bool an_complete;
94946e7fd5SSteen Hegelund 	int  duplex;
95946e7fd5SSteen Hegelund 	int  pause;
96946e7fd5SSteen Hegelund };
97946e7fd5SSteen Hegelund 
98946e7fd5SSteen Hegelund int sparx5_get_port_status(struct sparx5 *sparx5,
99946e7fd5SSteen Hegelund 			   struct sparx5_port *port,
100946e7fd5SSteen Hegelund 			   struct sparx5_port_status *status);
101946e7fd5SSteen Hegelund 
102946e7fd5SSteen Hegelund void sparx5_port_enable(struct sparx5_port *port, bool enable);
10310615907SSteen Hegelund int sparx5_port_fwd_urg(struct sparx5 *sparx5, u32 speed);
104946e7fd5SSteen Hegelund 
10592ef3d01SDaniel Machon #define SPARX5_PORT_QOS_PCP_COUNT 8
10692ef3d01SDaniel Machon #define SPARX5_PORT_QOS_DEI_COUNT 8
10792ef3d01SDaniel Machon #define SPARX5_PORT_QOS_PCP_DEI_COUNT \
10892ef3d01SDaniel Machon 	(SPARX5_PORT_QOS_PCP_COUNT + SPARX5_PORT_QOS_DEI_COUNT)
10992ef3d01SDaniel Machon struct sparx5_port_qos_pcp_map {
11092ef3d01SDaniel Machon 	u8 map[SPARX5_PORT_QOS_PCP_DEI_COUNT];
11192ef3d01SDaniel Machon };
11292ef3d01SDaniel Machon 
1132234879fSDaniel Machon struct sparx5_port_qos_pcp_rewr_map {
1142234879fSDaniel Machon 	u16 map[SPX5_PRIOS];
1152234879fSDaniel Machon };
1162234879fSDaniel Machon 
117*246c77f6SDaniel Machon #define SPARX5_PORT_QOS_DP_NUM 4
118*246c77f6SDaniel Machon struct sparx5_port_qos_dscp_rewr_map {
119*246c77f6SDaniel Machon 	u16 map[SPX5_PRIOS * SPARX5_PORT_QOS_DP_NUM];
120*246c77f6SDaniel Machon };
121*246c77f6SDaniel Machon 
1228dcf69a6SDaniel Machon #define SPARX5_PORT_QOS_DSCP_COUNT 64
1238dcf69a6SDaniel Machon struct sparx5_port_qos_dscp_map {
1248dcf69a6SDaniel Machon 	u8 map[SPARX5_PORT_QOS_DSCP_COUNT];
1258dcf69a6SDaniel Machon };
1268dcf69a6SDaniel Machon 
12792ef3d01SDaniel Machon struct sparx5_port_qos_pcp {
12892ef3d01SDaniel Machon 	struct sparx5_port_qos_pcp_map map;
12923f8382cSDaniel Machon 	bool qos_enable;
13023f8382cSDaniel Machon 	bool dp_enable;
13192ef3d01SDaniel Machon };
13292ef3d01SDaniel Machon 
1332234879fSDaniel Machon struct sparx5_port_qos_pcp_rewr {
1342234879fSDaniel Machon 	struct sparx5_port_qos_pcp_rewr_map map;
1352234879fSDaniel Machon 	bool enable;
1362234879fSDaniel Machon };
1372234879fSDaniel Machon 
1388dcf69a6SDaniel Machon struct sparx5_port_qos_dscp {
1398dcf69a6SDaniel Machon 	struct sparx5_port_qos_dscp_map map;
1408dcf69a6SDaniel Machon 	bool qos_enable;
1418dcf69a6SDaniel Machon 	bool dp_enable;
1428dcf69a6SDaniel Machon };
1438dcf69a6SDaniel Machon 
144*246c77f6SDaniel Machon struct sparx5_port_qos_dscp_rewr {
145*246c77f6SDaniel Machon 	struct sparx5_port_qos_dscp_rewr_map map;
146*246c77f6SDaniel Machon 	bool enable;
147*246c77f6SDaniel Machon };
148*246c77f6SDaniel Machon 
14992ef3d01SDaniel Machon struct sparx5_port_qos {
15092ef3d01SDaniel Machon 	struct sparx5_port_qos_pcp pcp;
1512234879fSDaniel Machon 	struct sparx5_port_qos_pcp_rewr pcp_rewr;
1528dcf69a6SDaniel Machon 	struct sparx5_port_qos_dscp dscp;
153*246c77f6SDaniel Machon 	struct sparx5_port_qos_dscp_rewr dscp_rewr;
154c58ff3edSDaniel Machon 	u8 default_prio;
15592ef3d01SDaniel Machon };
15692ef3d01SDaniel Machon 
15792ef3d01SDaniel Machon int sparx5_port_qos_set(struct sparx5_port *port, struct sparx5_port_qos *qos);
15892ef3d01SDaniel Machon 
15992ef3d01SDaniel Machon int sparx5_port_qos_pcp_set(const struct sparx5_port *port,
16092ef3d01SDaniel Machon 			    struct sparx5_port_qos_pcp *qos);
16192ef3d01SDaniel Machon 
1622234879fSDaniel Machon int sparx5_port_qos_pcp_rewr_set(const struct sparx5_port *port,
1632234879fSDaniel Machon 				 struct sparx5_port_qos_pcp_rewr *qos);
1642234879fSDaniel Machon 
1658dcf69a6SDaniel Machon int sparx5_port_qos_dscp_set(const struct sparx5_port *port,
1668dcf69a6SDaniel Machon 			     struct sparx5_port_qos_dscp *qos);
167c58ff3edSDaniel Machon 
168*246c77f6SDaniel Machon void sparx5_port_qos_dscp_rewr_mode_set(const struct sparx5_port *port,
169*246c77f6SDaniel Machon 					int mode);
170*246c77f6SDaniel Machon 
171*246c77f6SDaniel Machon int sparx5_port_qos_dscp_rewr_set(const struct sparx5_port *port,
172*246c77f6SDaniel Machon 				  struct sparx5_port_qos_dscp_rewr *qos);
173*246c77f6SDaniel Machon 
174c58ff3edSDaniel Machon int sparx5_port_qos_default_set(const struct sparx5_port *port,
175c58ff3edSDaniel Machon 				const struct sparx5_port_qos *qos);
176c58ff3edSDaniel Machon 
177946e7fd5SSteen Hegelund #endif	/* __SPARX5_PORT_H__ */
178