1*9948a064SJiri Pirko /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */ 2*9948a064SJiri Pirko /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */ 3*9948a064SJiri Pirko 493c1edb2SJiri Pirko #ifndef _MLXSW_PORT_H 593c1edb2SJiri Pirko #define _MLXSW_PORT_H 693c1edb2SJiri Pirko 793c1edb2SJiri Pirko #include <linux/types.h> 893c1edb2SJiri Pirko 993c1edb2SJiri Pirko #define MLXSW_PORT_MAX_MTU 10000 1093c1edb2SJiri Pirko 1193c1edb2SJiri Pirko #define MLXSW_PORT_DEFAULT_VID 1 1293c1edb2SJiri Pirko 134ec14b76SIdo Schimmel #define MLXSW_PORT_SWID_DISABLED_PORT 255 144ec14b76SIdo Schimmel #define MLXSW_PORT_SWID_ALL_SWIDS 254 15c68b71cbSElad Raz #define MLXSW_PORT_SWID_TYPE_IB 1 164ec14b76SIdo Schimmel #define MLXSW_PORT_SWID_TYPE_ETH 2 174ec14b76SIdo Schimmel 18d1ba5263SElad Raz #define MLXSW_PORT_MAX_IB_PHY_PORTS 36 19d1ba5263SElad Raz #define MLXSW_PORT_MAX_IB_PORTS (MLXSW_PORT_MAX_IB_PHY_PORTS + 1) 20d1ba5263SElad Raz 2193c1edb2SJiri Pirko #define MLXSW_PORT_CPU_PORT 0x0 2293c1edb2SJiri Pirko 235ec2ee7dSIdo Schimmel #define MLXSW_PORT_DONT_CARE 0xFF 2493c1edb2SJiri Pirko 254ec14b76SIdo Schimmel enum mlxsw_port_admin_status { 264ec14b76SIdo Schimmel MLXSW_PORT_ADMIN_STATUS_UP = 1, 274ec14b76SIdo Schimmel MLXSW_PORT_ADMIN_STATUS_DOWN = 2, 284ec14b76SIdo Schimmel MLXSW_PORT_ADMIN_STATUS_UP_ONCE = 3, 294ec14b76SIdo Schimmel MLXSW_PORT_ADMIN_STATUS_DISABLED = 4, 304ec14b76SIdo Schimmel }; 314ec14b76SIdo Schimmel 324ec14b76SIdo Schimmel enum mlxsw_reg_pude_oper_status { 334ec14b76SIdo Schimmel MLXSW_PORT_OPER_STATUS_UP = 1, 344ec14b76SIdo Schimmel MLXSW_PORT_OPER_STATUS_DOWN = 2, 354ec14b76SIdo Schimmel MLXSW_PORT_OPER_STATUS_FAILURE = 4, /* Can be set to up again. */ 364ec14b76SIdo Schimmel }; 374ec14b76SIdo Schimmel 3893c1edb2SJiri Pirko #endif /* _MLXSW_PORT_H */ 39