1 /* 2 * drivers/net/ethernet/mellanox/mlxsw/cmd.h 3 * Copyright (c) 2015 Mellanox Technologies. All rights reserved. 4 * Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com> 5 * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com> 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. Neither the names of the copyright holders nor the names of its 16 * contributors may be used to endorse or promote products derived from 17 * this software without specific prior written permission. 18 * 19 * Alternatively, this software may be distributed under the terms of the 20 * GNU General Public License ("GPL") version 2 as published by the Free 21 * Software Foundation. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 #ifndef _MLXSW_CMD_H 37 #define _MLXSW_CMD_H 38 39 #include "item.h" 40 41 #define MLXSW_CMD_MBOX_SIZE 4096 42 43 static inline char *mlxsw_cmd_mbox_alloc(void) 44 { 45 return kzalloc(MLXSW_CMD_MBOX_SIZE, GFP_KERNEL); 46 } 47 48 static inline void mlxsw_cmd_mbox_free(char *mbox) 49 { 50 kfree(mbox); 51 } 52 53 static inline void mlxsw_cmd_mbox_zero(char *mbox) 54 { 55 memset(mbox, 0, MLXSW_CMD_MBOX_SIZE); 56 } 57 58 struct mlxsw_core; 59 60 int mlxsw_cmd_exec(struct mlxsw_core *mlxsw_core, u16 opcode, u8 opcode_mod, 61 u32 in_mod, bool out_mbox_direct, 62 char *in_mbox, size_t in_mbox_size, 63 char *out_mbox, size_t out_mbox_size); 64 65 static inline int mlxsw_cmd_exec_in(struct mlxsw_core *mlxsw_core, u16 opcode, 66 u8 opcode_mod, u32 in_mod, char *in_mbox, 67 size_t in_mbox_size) 68 { 69 return mlxsw_cmd_exec(mlxsw_core, opcode, opcode_mod, in_mod, false, 70 in_mbox, in_mbox_size, NULL, 0); 71 } 72 73 static inline int mlxsw_cmd_exec_out(struct mlxsw_core *mlxsw_core, u16 opcode, 74 u8 opcode_mod, u32 in_mod, 75 bool out_mbox_direct, 76 char *out_mbox, size_t out_mbox_size) 77 { 78 return mlxsw_cmd_exec(mlxsw_core, opcode, opcode_mod, in_mod, 79 out_mbox_direct, NULL, 0, 80 out_mbox, out_mbox_size); 81 } 82 83 static inline int mlxsw_cmd_exec_none(struct mlxsw_core *mlxsw_core, u16 opcode, 84 u8 opcode_mod, u32 in_mod) 85 { 86 return mlxsw_cmd_exec(mlxsw_core, opcode, opcode_mod, in_mod, false, 87 NULL, 0, NULL, 0); 88 } 89 90 enum mlxsw_cmd_opcode { 91 MLXSW_CMD_OPCODE_QUERY_FW = 0x004, 92 MLXSW_CMD_OPCODE_QUERY_BOARDINFO = 0x006, 93 MLXSW_CMD_OPCODE_QUERY_AQ_CAP = 0x003, 94 MLXSW_CMD_OPCODE_MAP_FA = 0xFFF, 95 MLXSW_CMD_OPCODE_UNMAP_FA = 0xFFE, 96 MLXSW_CMD_OPCODE_CONFIG_PROFILE = 0x100, 97 MLXSW_CMD_OPCODE_ACCESS_REG = 0x040, 98 MLXSW_CMD_OPCODE_SW2HW_DQ = 0x201, 99 MLXSW_CMD_OPCODE_HW2SW_DQ = 0x202, 100 MLXSW_CMD_OPCODE_2ERR_DQ = 0x01E, 101 MLXSW_CMD_OPCODE_QUERY_DQ = 0x022, 102 MLXSW_CMD_OPCODE_SW2HW_CQ = 0x016, 103 MLXSW_CMD_OPCODE_HW2SW_CQ = 0x017, 104 MLXSW_CMD_OPCODE_QUERY_CQ = 0x018, 105 MLXSW_CMD_OPCODE_SW2HW_EQ = 0x013, 106 MLXSW_CMD_OPCODE_HW2SW_EQ = 0x014, 107 MLXSW_CMD_OPCODE_QUERY_EQ = 0x015, 108 }; 109 110 static inline const char *mlxsw_cmd_opcode_str(u16 opcode) 111 { 112 switch (opcode) { 113 case MLXSW_CMD_OPCODE_QUERY_FW: 114 return "QUERY_FW"; 115 case MLXSW_CMD_OPCODE_QUERY_BOARDINFO: 116 return "QUERY_BOARDINFO"; 117 case MLXSW_CMD_OPCODE_QUERY_AQ_CAP: 118 return "QUERY_AQ_CAP"; 119 case MLXSW_CMD_OPCODE_MAP_FA: 120 return "MAP_FA"; 121 case MLXSW_CMD_OPCODE_UNMAP_FA: 122 return "UNMAP_FA"; 123 case MLXSW_CMD_OPCODE_CONFIG_PROFILE: 124 return "CONFIG_PROFILE"; 125 case MLXSW_CMD_OPCODE_ACCESS_REG: 126 return "ACCESS_REG"; 127 case MLXSW_CMD_OPCODE_SW2HW_DQ: 128 return "SW2HW_DQ"; 129 case MLXSW_CMD_OPCODE_HW2SW_DQ: 130 return "HW2SW_DQ"; 131 case MLXSW_CMD_OPCODE_2ERR_DQ: 132 return "2ERR_DQ"; 133 case MLXSW_CMD_OPCODE_QUERY_DQ: 134 return "QUERY_DQ"; 135 case MLXSW_CMD_OPCODE_SW2HW_CQ: 136 return "SW2HW_CQ"; 137 case MLXSW_CMD_OPCODE_HW2SW_CQ: 138 return "HW2SW_CQ"; 139 case MLXSW_CMD_OPCODE_QUERY_CQ: 140 return "QUERY_CQ"; 141 case MLXSW_CMD_OPCODE_SW2HW_EQ: 142 return "SW2HW_EQ"; 143 case MLXSW_CMD_OPCODE_HW2SW_EQ: 144 return "HW2SW_EQ"; 145 case MLXSW_CMD_OPCODE_QUERY_EQ: 146 return "QUERY_EQ"; 147 default: 148 return "*UNKNOWN*"; 149 } 150 } 151 152 enum mlxsw_cmd_status { 153 /* Command execution succeeded. */ 154 MLXSW_CMD_STATUS_OK = 0x00, 155 /* Internal error (e.g. bus error) occurred while processing command. */ 156 MLXSW_CMD_STATUS_INTERNAL_ERR = 0x01, 157 /* Operation/command not supported or opcode modifier not supported. */ 158 MLXSW_CMD_STATUS_BAD_OP = 0x02, 159 /* Parameter not supported, parameter out of range. */ 160 MLXSW_CMD_STATUS_BAD_PARAM = 0x03, 161 /* System was not enabled or bad system state. */ 162 MLXSW_CMD_STATUS_BAD_SYS_STATE = 0x04, 163 /* Attempt to access reserved or unallocated resource, or resource in 164 * inappropriate ownership. 165 */ 166 MLXSW_CMD_STATUS_BAD_RESOURCE = 0x05, 167 /* Requested resource is currently executing a command. */ 168 MLXSW_CMD_STATUS_RESOURCE_BUSY = 0x06, 169 /* Required capability exceeds device limits. */ 170 MLXSW_CMD_STATUS_EXCEED_LIM = 0x08, 171 /* Resource is not in the appropriate state or ownership. */ 172 MLXSW_CMD_STATUS_BAD_RES_STATE = 0x09, 173 /* Index out of range (might be beyond table size or attempt to 174 * access a reserved resource). 175 */ 176 MLXSW_CMD_STATUS_BAD_INDEX = 0x0A, 177 /* NVMEM checksum/CRC failed. */ 178 MLXSW_CMD_STATUS_BAD_NVMEM = 0x0B, 179 /* Bad management packet (silently discarded). */ 180 MLXSW_CMD_STATUS_BAD_PKT = 0x30, 181 }; 182 183 static inline const char *mlxsw_cmd_status_str(u8 status) 184 { 185 switch (status) { 186 case MLXSW_CMD_STATUS_OK: 187 return "OK"; 188 case MLXSW_CMD_STATUS_INTERNAL_ERR: 189 return "INTERNAL_ERR"; 190 case MLXSW_CMD_STATUS_BAD_OP: 191 return "BAD_OP"; 192 case MLXSW_CMD_STATUS_BAD_PARAM: 193 return "BAD_PARAM"; 194 case MLXSW_CMD_STATUS_BAD_SYS_STATE: 195 return "BAD_SYS_STATE"; 196 case MLXSW_CMD_STATUS_BAD_RESOURCE: 197 return "BAD_RESOURCE"; 198 case MLXSW_CMD_STATUS_RESOURCE_BUSY: 199 return "RESOURCE_BUSY"; 200 case MLXSW_CMD_STATUS_EXCEED_LIM: 201 return "EXCEED_LIM"; 202 case MLXSW_CMD_STATUS_BAD_RES_STATE: 203 return "BAD_RES_STATE"; 204 case MLXSW_CMD_STATUS_BAD_INDEX: 205 return "BAD_INDEX"; 206 case MLXSW_CMD_STATUS_BAD_NVMEM: 207 return "BAD_NVMEM"; 208 case MLXSW_CMD_STATUS_BAD_PKT: 209 return "BAD_PKT"; 210 default: 211 return "*UNKNOWN*"; 212 } 213 } 214 215 /* QUERY_FW - Query Firmware 216 * ------------------------- 217 * OpMod == 0, INMmod == 0 218 * ----------------------- 219 * The QUERY_FW command retrieves information related to firmware, command 220 * interface version and the amount of resources that should be allocated to 221 * the firmware. 222 */ 223 224 static inline int mlxsw_cmd_query_fw(struct mlxsw_core *mlxsw_core, 225 char *out_mbox) 226 { 227 return mlxsw_cmd_exec_out(mlxsw_core, MLXSW_CMD_OPCODE_QUERY_FW, 228 0, 0, false, out_mbox, MLXSW_CMD_MBOX_SIZE); 229 } 230 231 /* cmd_mbox_query_fw_fw_pages 232 * Amount of physical memory to be allocatedfor firmware usage in 4KB pages. 233 */ 234 MLXSW_ITEM32(cmd_mbox, query_fw, fw_pages, 0x00, 16, 16); 235 236 /* cmd_mbox_query_fw_fw_rev_major 237 * Firmware Revision - Major 238 */ 239 MLXSW_ITEM32(cmd_mbox, query_fw, fw_rev_major, 0x00, 0, 16); 240 241 /* cmd_mbox_query_fw_fw_rev_subminor 242 * Firmware Sub-minor version (Patch level) 243 */ 244 MLXSW_ITEM32(cmd_mbox, query_fw, fw_rev_subminor, 0x04, 16, 16); 245 246 /* cmd_mbox_query_fw_fw_rev_minor 247 * Firmware Revision - Minor 248 */ 249 MLXSW_ITEM32(cmd_mbox, query_fw, fw_rev_minor, 0x04, 0, 16); 250 251 /* cmd_mbox_query_fw_core_clk 252 * Internal Clock Frequency (in MHz) 253 */ 254 MLXSW_ITEM32(cmd_mbox, query_fw, core_clk, 0x08, 16, 16); 255 256 /* cmd_mbox_query_fw_cmd_interface_rev 257 * Command Interface Interpreter Revision ID. This number is bumped up 258 * every time a non-backward-compatible change is done for the command 259 * interface. The current cmd_interface_rev is 1. 260 */ 261 MLXSW_ITEM32(cmd_mbox, query_fw, cmd_interface_rev, 0x08, 0, 16); 262 263 /* cmd_mbox_query_fw_dt 264 * If set, Debug Trace is supported 265 */ 266 MLXSW_ITEM32(cmd_mbox, query_fw, dt, 0x0C, 31, 1); 267 268 /* cmd_mbox_query_fw_api_version 269 * Indicates the version of the API, to enable software querying 270 * for compatibility. The current api_version is 1. 271 */ 272 MLXSW_ITEM32(cmd_mbox, query_fw, api_version, 0x0C, 0, 16); 273 274 /* cmd_mbox_query_fw_fw_hour 275 * Firmware timestamp - hour 276 */ 277 MLXSW_ITEM32(cmd_mbox, query_fw, fw_hour, 0x10, 24, 8); 278 279 /* cmd_mbox_query_fw_fw_minutes 280 * Firmware timestamp - minutes 281 */ 282 MLXSW_ITEM32(cmd_mbox, query_fw, fw_minutes, 0x10, 16, 8); 283 284 /* cmd_mbox_query_fw_fw_seconds 285 * Firmware timestamp - seconds 286 */ 287 MLXSW_ITEM32(cmd_mbox, query_fw, fw_seconds, 0x10, 8, 8); 288 289 /* cmd_mbox_query_fw_fw_year 290 * Firmware timestamp - year 291 */ 292 MLXSW_ITEM32(cmd_mbox, query_fw, fw_year, 0x14, 16, 16); 293 294 /* cmd_mbox_query_fw_fw_month 295 * Firmware timestamp - month 296 */ 297 MLXSW_ITEM32(cmd_mbox, query_fw, fw_month, 0x14, 8, 8); 298 299 /* cmd_mbox_query_fw_fw_day 300 * Firmware timestamp - day 301 */ 302 MLXSW_ITEM32(cmd_mbox, query_fw, fw_day, 0x14, 0, 8); 303 304 /* cmd_mbox_query_fw_clr_int_base_offset 305 * Clear Interrupt register's offset from clr_int_bar register 306 * in PCI address space. 307 */ 308 MLXSW_ITEM64(cmd_mbox, query_fw, clr_int_base_offset, 0x20, 0, 64); 309 310 /* cmd_mbox_query_fw_clr_int_bar 311 * PCI base address register (BAR) where clr_int register is located. 312 * 00 - BAR 0-1 (64 bit BAR) 313 */ 314 MLXSW_ITEM32(cmd_mbox, query_fw, clr_int_bar, 0x28, 30, 2); 315 316 /* cmd_mbox_query_fw_error_buf_offset 317 * Read Only buffer for internal error reports of offset 318 * from error_buf_bar register in PCI address space). 319 */ 320 MLXSW_ITEM64(cmd_mbox, query_fw, error_buf_offset, 0x30, 0, 64); 321 322 /* cmd_mbox_query_fw_error_buf_size 323 * Internal error buffer size in DWORDs 324 */ 325 MLXSW_ITEM32(cmd_mbox, query_fw, error_buf_size, 0x38, 0, 32); 326 327 /* cmd_mbox_query_fw_error_int_bar 328 * PCI base address register (BAR) where error buffer 329 * register is located. 330 * 00 - BAR 0-1 (64 bit BAR) 331 */ 332 MLXSW_ITEM32(cmd_mbox, query_fw, error_int_bar, 0x3C, 30, 2); 333 334 /* cmd_mbox_query_fw_doorbell_page_offset 335 * Offset of the doorbell page 336 */ 337 MLXSW_ITEM64(cmd_mbox, query_fw, doorbell_page_offset, 0x40, 0, 64); 338 339 /* cmd_mbox_query_fw_doorbell_page_bar 340 * PCI base address register (BAR) of the doorbell page 341 * 00 - BAR 0-1 (64 bit BAR) 342 */ 343 MLXSW_ITEM32(cmd_mbox, query_fw, doorbell_page_bar, 0x48, 30, 2); 344 345 /* QUERY_BOARDINFO - Query Board Information 346 * ----------------------------------------- 347 * OpMod == 0 (N/A), INMmod == 0 (N/A) 348 * ----------------------------------- 349 * The QUERY_BOARDINFO command retrieves adapter specific parameters. 350 */ 351 352 static inline int mlxsw_cmd_boardinfo(struct mlxsw_core *mlxsw_core, 353 char *out_mbox) 354 { 355 return mlxsw_cmd_exec_out(mlxsw_core, MLXSW_CMD_OPCODE_QUERY_BOARDINFO, 356 0, 0, false, out_mbox, MLXSW_CMD_MBOX_SIZE); 357 } 358 359 /* cmd_mbox_boardinfo_intapin 360 * When PCIe interrupt messages are being used, this value is used for clearing 361 * an interrupt. When using MSI-X, this register is not used. 362 */ 363 MLXSW_ITEM32(cmd_mbox, boardinfo, intapin, 0x10, 24, 8); 364 365 /* cmd_mbox_boardinfo_vsd_vendor_id 366 * PCISIG Vendor ID (www.pcisig.com/membership/vid_search) of the vendor 367 * specifying/formatting the VSD. The vsd_vendor_id identifies the management 368 * domain of the VSD/PSID data. Different vendors may choose different VSD/PSID 369 * format and encoding as long as they use their assigned vsd_vendor_id. 370 */ 371 MLXSW_ITEM32(cmd_mbox, boardinfo, vsd_vendor_id, 0x1C, 0, 16); 372 373 /* cmd_mbox_boardinfo_vsd 374 * Vendor Specific Data. The VSD string that is burnt to the Flash 375 * with the firmware. 376 */ 377 #define MLXSW_CMD_BOARDINFO_VSD_LEN 208 378 MLXSW_ITEM_BUF(cmd_mbox, boardinfo, vsd, 0x20, MLXSW_CMD_BOARDINFO_VSD_LEN); 379 380 /* cmd_mbox_boardinfo_psid 381 * The PSID field is a 16-ascii (byte) character string which acts as 382 * the board ID. The PSID format is used in conjunction with 383 * Mellanox vsd_vendor_id (15B3h). 384 */ 385 #define MLXSW_CMD_BOARDINFO_PSID_LEN 16 386 MLXSW_ITEM_BUF(cmd_mbox, boardinfo, psid, 0xF0, MLXSW_CMD_BOARDINFO_PSID_LEN); 387 388 /* QUERY_AQ_CAP - Query Asynchronous Queues Capabilities 389 * ----------------------------------------------------- 390 * OpMod == 0 (N/A), INMmod == 0 (N/A) 391 * ----------------------------------- 392 * The QUERY_AQ_CAP command returns the device asynchronous queues 393 * capabilities supported. 394 */ 395 396 static inline int mlxsw_cmd_query_aq_cap(struct mlxsw_core *mlxsw_core, 397 char *out_mbox) 398 { 399 return mlxsw_cmd_exec_out(mlxsw_core, MLXSW_CMD_OPCODE_QUERY_AQ_CAP, 400 0, 0, false, out_mbox, MLXSW_CMD_MBOX_SIZE); 401 } 402 403 /* cmd_mbox_query_aq_cap_log_max_sdq_sz 404 * Log (base 2) of max WQEs allowed on SDQ. 405 */ 406 MLXSW_ITEM32(cmd_mbox, query_aq_cap, log_max_sdq_sz, 0x00, 24, 8); 407 408 /* cmd_mbox_query_aq_cap_max_num_sdqs 409 * Maximum number of SDQs. 410 */ 411 MLXSW_ITEM32(cmd_mbox, query_aq_cap, max_num_sdqs, 0x00, 0, 8); 412 413 /* cmd_mbox_query_aq_cap_log_max_rdq_sz 414 * Log (base 2) of max WQEs allowed on RDQ. 415 */ 416 MLXSW_ITEM32(cmd_mbox, query_aq_cap, log_max_rdq_sz, 0x04, 24, 8); 417 418 /* cmd_mbox_query_aq_cap_max_num_rdqs 419 * Maximum number of RDQs. 420 */ 421 MLXSW_ITEM32(cmd_mbox, query_aq_cap, max_num_rdqs, 0x04, 0, 8); 422 423 /* cmd_mbox_query_aq_cap_log_max_cq_sz 424 * Log (base 2) of max CQEs allowed on CQ. 425 */ 426 MLXSW_ITEM32(cmd_mbox, query_aq_cap, log_max_cq_sz, 0x08, 24, 8); 427 428 /* cmd_mbox_query_aq_cap_max_num_cqs 429 * Maximum number of CQs. 430 */ 431 MLXSW_ITEM32(cmd_mbox, query_aq_cap, max_num_cqs, 0x08, 0, 8); 432 433 /* cmd_mbox_query_aq_cap_log_max_eq_sz 434 * Log (base 2) of max EQEs allowed on EQ. 435 */ 436 MLXSW_ITEM32(cmd_mbox, query_aq_cap, log_max_eq_sz, 0x0C, 24, 8); 437 438 /* cmd_mbox_query_aq_cap_max_num_eqs 439 * Maximum number of EQs. 440 */ 441 MLXSW_ITEM32(cmd_mbox, query_aq_cap, max_num_eqs, 0x0C, 0, 8); 442 443 /* cmd_mbox_query_aq_cap_max_sg_sq 444 * The maximum S/G list elements in an DSQ. DSQ must not contain 445 * more S/G entries than indicated here. 446 */ 447 MLXSW_ITEM32(cmd_mbox, query_aq_cap, max_sg_sq, 0x10, 8, 8); 448 449 /* cmd_mbox_query_aq_cap_ 450 * The maximum S/G list elements in an DRQ. DRQ must not contain 451 * more S/G entries than indicated here. 452 */ 453 MLXSW_ITEM32(cmd_mbox, query_aq_cap, max_sg_rq, 0x10, 0, 8); 454 455 /* MAP_FA - Map Firmware Area 456 * -------------------------- 457 * OpMod == 0 (N/A), INMmod == Number of VPM entries 458 * ------------------------------------------------- 459 * The MAP_FA command passes physical pages to the switch. These pages 460 * are used to store the device firmware. MAP_FA can be executed multiple 461 * times until all the firmware area is mapped (the size that should be 462 * mapped is retrieved through the QUERY_FW command). All required pages 463 * must be mapped to finish the initialization phase. Physical memory 464 * passed in this command must be pinned. 465 */ 466 467 static inline int mlxsw_cmd_map_fa(struct mlxsw_core *mlxsw_core, 468 char *in_mbox, u32 vpm_entries_count) 469 { 470 return mlxsw_cmd_exec_in(mlxsw_core, MLXSW_CMD_OPCODE_MAP_FA, 471 0, vpm_entries_count, 472 in_mbox, MLXSW_CMD_MBOX_SIZE); 473 } 474 475 /* cmd_mbox_map_fa_pa 476 * Physical Address. 477 */ 478 MLXSW_ITEM64_INDEXED(cmd_mbox, map_fa, pa, 0x00, 12, 52, 0x08, 0x00, true); 479 480 /* cmd_mbox_map_fa_log2size 481 * Log (base 2) of the size in 4KB pages of the physical and contiguous memory 482 * that starts at PA_L/H. 483 */ 484 MLXSW_ITEM32_INDEXED(cmd_mbox, map_fa, log2size, 0x00, 0, 5, 0x08, 0x04, false); 485 486 /* UNMAP_FA - Unmap Firmware Area 487 * ------------------------------ 488 * OpMod == 0 (N/A), INMmod == 0 (N/A) 489 * ----------------------------------- 490 * The UNMAP_FA command unload the firmware and unmaps all the 491 * firmware area. After this command is completed the device will not access 492 * the pages that were mapped to the firmware area. After executing UNMAP_FA 493 * command, software reset must be done prior to execution of MAP_FW command. 494 */ 495 496 static inline int mlxsw_cmd_unmap_fa(struct mlxsw_core *mlxsw_core) 497 { 498 return mlxsw_cmd_exec_none(mlxsw_core, MLXSW_CMD_OPCODE_UNMAP_FA, 0, 0); 499 } 500 501 /* CONFIG_PROFILE (Set) - Configure Switch Profile 502 * ------------------------------ 503 * OpMod == 1 (Set), INMmod == 0 (N/A) 504 * ----------------------------------- 505 * The CONFIG_PROFILE command sets the switch profile. The command can be 506 * executed on the device only once at startup in order to allocate and 507 * configure all switch resources and prepare it for operational mode. 508 * It is not possible to change the device profile after the chip is 509 * in operational mode. 510 * Failure of the CONFIG_PROFILE command leaves the hardware in an indeterminate 511 * state therefore it is required to perform software reset to the device 512 * following an unsuccessful completion of the command. It is required 513 * to perform software reset to the device to change an existing profile. 514 */ 515 516 static inline int mlxsw_cmd_config_profile_set(struct mlxsw_core *mlxsw_core, 517 char *in_mbox) 518 { 519 return mlxsw_cmd_exec_in(mlxsw_core, MLXSW_CMD_OPCODE_CONFIG_PROFILE, 520 1, 0, in_mbox, MLXSW_CMD_MBOX_SIZE); 521 } 522 523 /* cmd_mbox_config_profile_set_max_vepa_channels 524 * Capability bit. Setting a bit to 1 configures the profile 525 * according to the mailbox contents. 526 */ 527 MLXSW_ITEM32(cmd_mbox, config_profile, set_max_vepa_channels, 0x0C, 0, 1); 528 529 /* cmd_mbox_config_profile_set_max_lag 530 * Capability bit. Setting a bit to 1 configures the profile 531 * according to the mailbox contents. 532 */ 533 MLXSW_ITEM32(cmd_mbox, config_profile, set_max_lag, 0x0C, 1, 1); 534 535 /* cmd_mbox_config_profile_set_max_port_per_lag 536 * Capability bit. Setting a bit to 1 configures the profile 537 * according to the mailbox contents. 538 */ 539 MLXSW_ITEM32(cmd_mbox, config_profile, set_max_port_per_lag, 0x0C, 2, 1); 540 541 /* cmd_mbox_config_profile_set_max_mid 542 * Capability bit. Setting a bit to 1 configures the profile 543 * according to the mailbox contents. 544 */ 545 MLXSW_ITEM32(cmd_mbox, config_profile, set_max_mid, 0x0C, 3, 1); 546 547 /* cmd_mbox_config_profile_set_max_pgt 548 * Capability bit. Setting a bit to 1 configures the profile 549 * according to the mailbox contents. 550 */ 551 MLXSW_ITEM32(cmd_mbox, config_profile, set_max_pgt, 0x0C, 4, 1); 552 553 /* cmd_mbox_config_profile_set_max_system_port 554 * Capability bit. Setting a bit to 1 configures the profile 555 * according to the mailbox contents. 556 */ 557 MLXSW_ITEM32(cmd_mbox, config_profile, set_max_system_port, 0x0C, 5, 1); 558 559 /* cmd_mbox_config_profile_set_max_vlan_groups 560 * Capability bit. Setting a bit to 1 configures the profile 561 * according to the mailbox contents. 562 */ 563 MLXSW_ITEM32(cmd_mbox, config_profile, set_max_vlan_groups, 0x0C, 6, 1); 564 565 /* cmd_mbox_config_profile_set_max_regions 566 * Capability bit. Setting a bit to 1 configures the profile 567 * according to the mailbox contents. 568 */ 569 MLXSW_ITEM32(cmd_mbox, config_profile, set_max_regions, 0x0C, 7, 1); 570 571 /* cmd_mbox_config_profile_set_fid_based 572 * Capability bit. Setting a bit to 1 configures the profile 573 * according to the mailbox contents. 574 */ 575 MLXSW_ITEM32(cmd_mbox, config_profile, set_flood_mode, 0x0C, 8, 1); 576 577 /* cmd_mbox_config_profile_set_max_flood_tables 578 * Capability bit. Setting a bit to 1 configures the profile 579 * according to the mailbox contents. 580 */ 581 MLXSW_ITEM32(cmd_mbox, config_profile, set_flood_tables, 0x0C, 9, 1); 582 583 /* cmd_mbox_config_profile_set_max_ib_mc 584 * Capability bit. Setting a bit to 1 configures the profile 585 * according to the mailbox contents. 586 */ 587 MLXSW_ITEM32(cmd_mbox, config_profile, set_max_ib_mc, 0x0C, 12, 1); 588 589 /* cmd_mbox_config_profile_set_max_pkey 590 * Capability bit. Setting a bit to 1 configures the profile 591 * according to the mailbox contents. 592 */ 593 MLXSW_ITEM32(cmd_mbox, config_profile, set_max_pkey, 0x0C, 13, 1); 594 595 /* cmd_mbox_config_profile_set_adaptive_routing_group_cap 596 * Capability bit. Setting a bit to 1 configures the profile 597 * according to the mailbox contents. 598 */ 599 MLXSW_ITEM32(cmd_mbox, config_profile, 600 set_adaptive_routing_group_cap, 0x0C, 14, 1); 601 602 /* cmd_mbox_config_profile_set_ar_sec 603 * Capability bit. Setting a bit to 1 configures the profile 604 * according to the mailbox contents. 605 */ 606 MLXSW_ITEM32(cmd_mbox, config_profile, set_ar_sec, 0x0C, 15, 1); 607 608 /* cmd_mbox_config_profile_max_vepa_channels 609 * Maximum number of VEPA channels per port (0 through 16) 610 * 0 - multi-channel VEPA is disabled 611 */ 612 MLXSW_ITEM32(cmd_mbox, config_profile, max_vepa_channels, 0x10, 0, 8); 613 614 /* cmd_mbox_config_profile_max_lag 615 * Maximum number of LAG IDs requested. 616 */ 617 MLXSW_ITEM32(cmd_mbox, config_profile, max_lag, 0x14, 0, 16); 618 619 /* cmd_mbox_config_profile_max_port_per_lag 620 * Maximum number of ports per LAG requested. 621 */ 622 MLXSW_ITEM32(cmd_mbox, config_profile, max_port_per_lag, 0x18, 0, 16); 623 624 /* cmd_mbox_config_profile_max_mid 625 * Maximum Multicast IDs. 626 * Multicast IDs are allocated from 0 to max_mid-1 627 */ 628 MLXSW_ITEM32(cmd_mbox, config_profile, max_mid, 0x1C, 0, 16); 629 630 /* cmd_mbox_config_profile_max_pgt 631 * Maximum records in the Port Group Table per Switch Partition. 632 * Port Group Table indexes are from 0 to max_pgt-1 633 */ 634 MLXSW_ITEM32(cmd_mbox, config_profile, max_pgt, 0x20, 0, 16); 635 636 /* cmd_mbox_config_profile_max_system_port 637 * The maximum number of system ports that can be allocated. 638 */ 639 MLXSW_ITEM32(cmd_mbox, config_profile, max_system_port, 0x24, 0, 16); 640 641 /* cmd_mbox_config_profile_max_vlan_groups 642 * Maximum number VLAN Groups for VLAN binding. 643 */ 644 MLXSW_ITEM32(cmd_mbox, config_profile, max_vlan_groups, 0x28, 0, 12); 645 646 /* cmd_mbox_config_profile_max_regions 647 * Maximum number of TCAM Regions. 648 */ 649 MLXSW_ITEM32(cmd_mbox, config_profile, max_regions, 0x2C, 0, 16); 650 651 /* cmd_mbox_config_profile_max_flood_tables 652 * Maximum number of Flooding Tables. Flooding Tables are associated to 653 * the different packet types for the different switch partitions. 654 * Note that the table size depends on the fid_based mode. 655 * In SwitchX silicon, tables are split equally between the switch 656 * partitions. e.g. for 2 swids and 8 tables, the first 4 are associated 657 * with swid-1 and the last 4 are associated with swid-2. 658 */ 659 MLXSW_ITEM32(cmd_mbox, config_profile, max_flood_tables, 0x30, 16, 4); 660 661 /* cmd_mbox_config_profile_max_vid_flood_tables 662 * Maximum number of per-vid flooding tables. Flooding tables are associated 663 * to the different packet types for the different switch partitions. 664 * Table size is 4K entries covering all VID space. 665 */ 666 MLXSW_ITEM32(cmd_mbox, config_profile, max_vid_flood_tables, 0x30, 8, 4); 667 668 /* cmd_mbox_config_profile_fid_based 669 * FID Based Flood Mode 670 * 00 Do not use FID to offset the index into the Port Group Table/Multicast ID 671 * 01 Use FID to offset the index to the Port Group Table (pgi) 672 * 10 Use FID to offset the index to the Port Group Table (pgi) and 673 * the Multicast ID 674 */ 675 MLXSW_ITEM32(cmd_mbox, config_profile, flood_mode, 0x30, 0, 2); 676 677 /* cmd_mbox_config_profile_max_ib_mc 678 * Maximum number of multicast FDB records for InfiniBand 679 * FDB (in 512 chunks) per InfiniBand switch partition. 680 */ 681 MLXSW_ITEM32(cmd_mbox, config_profile, max_ib_mc, 0x40, 0, 15); 682 683 /* cmd_mbox_config_profile_max_pkey 684 * Maximum per port PKEY table size (for PKEY enforcement) 685 */ 686 MLXSW_ITEM32(cmd_mbox, config_profile, max_pkey, 0x44, 0, 15); 687 688 /* cmd_mbox_config_profile_ar_sec 689 * Primary/secondary capability 690 * Describes the number of adaptive routing sub-groups 691 * 0 - disable primary/secondary (single group) 692 * 1 - enable primary/secondary (2 sub-groups) 693 * 2 - 3 sub-groups: Not supported in SwitchX, SwitchX-2 694 * 3 - 4 sub-groups: Not supported in SwitchX, SwitchX-2 695 */ 696 MLXSW_ITEM32(cmd_mbox, config_profile, ar_sec, 0x4C, 24, 2); 697 698 /* cmd_mbox_config_profile_adaptive_routing_group_cap 699 * Adaptive Routing Group Capability. Indicates the number of AR groups 700 * supported. Note that when Primary/secondary is enabled, each 701 * primary/secondary couple consumes 2 adaptive routing entries. 702 */ 703 MLXSW_ITEM32(cmd_mbox, config_profile, adaptive_routing_group_cap, 0x4C, 0, 16); 704 705 /* cmd_mbox_config_profile_arn 706 * Adaptive Routing Notification Enable 707 * Not supported in SwitchX, SwitchX-2 708 */ 709 MLXSW_ITEM32(cmd_mbox, config_profile, arn, 0x50, 31, 1); 710 711 /* cmd_mbox_config_profile_swid_config_mask 712 * Modify Switch Partition Configuration mask. When set, the configu- 713 * ration value for the Switch Partition are taken from the mailbox. 714 * When clear, the current configuration values are used. 715 * Bit 0 - set type 716 * Bit 1 - properties 717 * Other - reserved 718 */ 719 MLXSW_ITEM32_INDEXED(cmd_mbox, config_profile, swid_config_mask, 720 0x60, 24, 8, 0x08, 0x00, false); 721 722 /* cmd_mbox_config_profile_swid_config_type 723 * Switch Partition type. 724 * 0000 - disabled (Switch Partition does not exist) 725 * 0001 - InfiniBand 726 * 0010 - Ethernet 727 * 1000 - router port (SwitchX-2 only) 728 * Other - reserved 729 */ 730 MLXSW_ITEM32_INDEXED(cmd_mbox, config_profile, swid_config_type, 731 0x60, 20, 4, 0x08, 0x00, false); 732 733 /* cmd_mbox_config_profile_swid_config_properties 734 * Switch Partition properties. 735 */ 736 MLXSW_ITEM32_INDEXED(cmd_mbox, config_profile, swid_config_properties, 737 0x60, 0, 8, 0x08, 0x00, false); 738 739 /* ACCESS_REG - Access EMAD Supported Register 740 * ---------------------------------- 741 * OpMod == 0 (N/A), INMmod == 0 (N/A) 742 * ------------------------------------- 743 * The ACCESS_REG command supports accessing device registers. This access 744 * is mainly used for bootstrapping. 745 */ 746 747 static inline int mlxsw_cmd_access_reg(struct mlxsw_core *mlxsw_core, 748 char *in_mbox, char *out_mbox) 749 { 750 return mlxsw_cmd_exec(mlxsw_core, MLXSW_CMD_OPCODE_ACCESS_REG, 751 0, 0, false, in_mbox, MLXSW_CMD_MBOX_SIZE, 752 out_mbox, MLXSW_CMD_MBOX_SIZE); 753 } 754 755 /* SW2HW_DQ - Software to Hardware DQ 756 * ---------------------------------- 757 * OpMod == 0 (send DQ) / OpMod == 1 (receive DQ) 758 * INMmod == DQ number 759 * ---------------------------------------------- 760 * The SW2HW_DQ command transitions a descriptor queue from software to 761 * hardware ownership. The command enables posting WQEs and ringing DoorBells 762 * on the descriptor queue. 763 */ 764 765 static inline int __mlxsw_cmd_sw2hw_dq(struct mlxsw_core *mlxsw_core, 766 char *in_mbox, u32 dq_number, 767 u8 opcode_mod) 768 { 769 return mlxsw_cmd_exec_in(mlxsw_core, MLXSW_CMD_OPCODE_SW2HW_DQ, 770 opcode_mod, dq_number, 771 in_mbox, MLXSW_CMD_MBOX_SIZE); 772 } 773 774 enum { 775 MLXSW_CMD_OPCODE_MOD_SDQ = 0, 776 MLXSW_CMD_OPCODE_MOD_RDQ = 1, 777 }; 778 779 static inline int mlxsw_cmd_sw2hw_sdq(struct mlxsw_core *mlxsw_core, 780 char *in_mbox, u32 dq_number) 781 { 782 return __mlxsw_cmd_sw2hw_dq(mlxsw_core, in_mbox, dq_number, 783 MLXSW_CMD_OPCODE_MOD_SDQ); 784 } 785 786 static inline int mlxsw_cmd_sw2hw_rdq(struct mlxsw_core *mlxsw_core, 787 char *in_mbox, u32 dq_number) 788 { 789 return __mlxsw_cmd_sw2hw_dq(mlxsw_core, in_mbox, dq_number, 790 MLXSW_CMD_OPCODE_MOD_RDQ); 791 } 792 793 /* cmd_mbox_sw2hw_dq_cq 794 * Number of the CQ that this Descriptor Queue reports completions to. 795 */ 796 MLXSW_ITEM32(cmd_mbox, sw2hw_dq, cq, 0x00, 24, 8); 797 798 /* cmd_mbox_sw2hw_dq_sdq_tclass 799 * SDQ: CPU Egress TClass 800 * RDQ: Reserved 801 */ 802 MLXSW_ITEM32(cmd_mbox, sw2hw_dq, sdq_tclass, 0x00, 16, 6); 803 804 /* cmd_mbox_sw2hw_dq_log2_dq_sz 805 * Log (base 2) of the Descriptor Queue size in 4KB pages. 806 */ 807 MLXSW_ITEM32(cmd_mbox, sw2hw_dq, log2_dq_sz, 0x00, 0, 6); 808 809 /* cmd_mbox_sw2hw_dq_pa 810 * Physical Address. 811 */ 812 MLXSW_ITEM64_INDEXED(cmd_mbox, sw2hw_dq, pa, 0x10, 12, 52, 0x08, 0x00, true); 813 814 /* HW2SW_DQ - Hardware to Software DQ 815 * ---------------------------------- 816 * OpMod == 0 (send DQ) / OpMod == 1 (receive DQ) 817 * INMmod == DQ number 818 * ---------------------------------------------- 819 * The HW2SW_DQ command transitions a descriptor queue from hardware to 820 * software ownership. Incoming packets on the DQ are silently discarded, 821 * SW should not post descriptors on nonoperational DQs. 822 */ 823 824 static inline int __mlxsw_cmd_hw2sw_dq(struct mlxsw_core *mlxsw_core, 825 u32 dq_number, u8 opcode_mod) 826 { 827 return mlxsw_cmd_exec_none(mlxsw_core, MLXSW_CMD_OPCODE_HW2SW_DQ, 828 opcode_mod, dq_number); 829 } 830 831 static inline int mlxsw_cmd_hw2sw_sdq(struct mlxsw_core *mlxsw_core, 832 u32 dq_number) 833 { 834 return __mlxsw_cmd_hw2sw_dq(mlxsw_core, dq_number, 835 MLXSW_CMD_OPCODE_MOD_SDQ); 836 } 837 838 static inline int mlxsw_cmd_hw2sw_rdq(struct mlxsw_core *mlxsw_core, 839 u32 dq_number) 840 { 841 return __mlxsw_cmd_hw2sw_dq(mlxsw_core, dq_number, 842 MLXSW_CMD_OPCODE_MOD_RDQ); 843 } 844 845 /* 2ERR_DQ - To Error DQ 846 * --------------------- 847 * OpMod == 0 (send DQ) / OpMod == 1 (receive DQ) 848 * INMmod == DQ number 849 * ---------------------------------------------- 850 * The 2ERR_DQ command transitions the DQ into the error state from the state 851 * in which it has been. While the command is executed, some in-process 852 * descriptors may complete. Once the DQ transitions into the error state, 853 * if there are posted descriptors on the RDQ/SDQ, the hardware writes 854 * a completion with error (flushed) for all descriptors posted in the RDQ/SDQ. 855 * When the command is completed successfully, the DQ is already in 856 * the error state. 857 */ 858 859 static inline int __mlxsw_cmd_2err_dq(struct mlxsw_core *mlxsw_core, 860 u32 dq_number, u8 opcode_mod) 861 { 862 return mlxsw_cmd_exec_none(mlxsw_core, MLXSW_CMD_OPCODE_2ERR_DQ, 863 opcode_mod, dq_number); 864 } 865 866 static inline int mlxsw_cmd_2err_sdq(struct mlxsw_core *mlxsw_core, 867 u32 dq_number) 868 { 869 return __mlxsw_cmd_2err_dq(mlxsw_core, dq_number, 870 MLXSW_CMD_OPCODE_MOD_SDQ); 871 } 872 873 static inline int mlxsw_cmd_2err_rdq(struct mlxsw_core *mlxsw_core, 874 u32 dq_number) 875 { 876 return __mlxsw_cmd_2err_dq(mlxsw_core, dq_number, 877 MLXSW_CMD_OPCODE_MOD_RDQ); 878 } 879 880 /* QUERY_DQ - Query DQ 881 * --------------------- 882 * OpMod == 0 (send DQ) / OpMod == 1 (receive DQ) 883 * INMmod == DQ number 884 * ---------------------------------------------- 885 * The QUERY_DQ command retrieves a snapshot of DQ parameters from the hardware. 886 * 887 * Note: Output mailbox has the same format as SW2HW_DQ. 888 */ 889 890 static inline int __mlxsw_cmd_query_dq(struct mlxsw_core *mlxsw_core, 891 char *out_mbox, u32 dq_number, 892 u8 opcode_mod) 893 { 894 return mlxsw_cmd_exec_out(mlxsw_core, MLXSW_CMD_OPCODE_2ERR_DQ, 895 opcode_mod, dq_number, false, 896 out_mbox, MLXSW_CMD_MBOX_SIZE); 897 } 898 899 static inline int mlxsw_cmd_query_sdq(struct mlxsw_core *mlxsw_core, 900 char *out_mbox, u32 dq_number) 901 { 902 return __mlxsw_cmd_query_dq(mlxsw_core, out_mbox, dq_number, 903 MLXSW_CMD_OPCODE_MOD_SDQ); 904 } 905 906 static inline int mlxsw_cmd_query_rdq(struct mlxsw_core *mlxsw_core, 907 char *out_mbox, u32 dq_number) 908 { 909 return __mlxsw_cmd_query_dq(mlxsw_core, out_mbox, dq_number, 910 MLXSW_CMD_OPCODE_MOD_RDQ); 911 } 912 913 /* SW2HW_CQ - Software to Hardware CQ 914 * ---------------------------------- 915 * OpMod == 0 (N/A), INMmod == CQ number 916 * ------------------------------------- 917 * The SW2HW_CQ command transfers ownership of a CQ context entry from software 918 * to hardware. The command takes the CQ context entry from the input mailbox 919 * and stores it in the CQC in the ownership of the hardware. The command fails 920 * if the requested CQC entry is already in the ownership of the hardware. 921 */ 922 923 static inline int mlxsw_cmd_sw2hw_cq(struct mlxsw_core *mlxsw_core, 924 char *in_mbox, u32 cq_number) 925 { 926 return mlxsw_cmd_exec_in(mlxsw_core, MLXSW_CMD_OPCODE_SW2HW_CQ, 927 0, cq_number, in_mbox, MLXSW_CMD_MBOX_SIZE); 928 } 929 930 /* cmd_mbox_sw2hw_cq_cv 931 * CQE Version. 932 * 0 - CQE Version 0, 1 - CQE Version 1 933 */ 934 MLXSW_ITEM32(cmd_mbox, sw2hw_cq, cv, 0x00, 28, 4); 935 936 /* cmd_mbox_sw2hw_cq_c_eqn 937 * Event Queue this CQ reports completion events to. 938 */ 939 MLXSW_ITEM32(cmd_mbox, sw2hw_cq, c_eqn, 0x00, 24, 1); 940 941 /* cmd_mbox_sw2hw_cq_oi 942 * When set, overrun ignore is enabled. When set, updates of 943 * CQ consumer counter (poll for completion) or Request completion 944 * notifications (Arm CQ) DoorBells should not be rung on that CQ. 945 */ 946 MLXSW_ITEM32(cmd_mbox, sw2hw_cq, oi, 0x00, 12, 1); 947 948 /* cmd_mbox_sw2hw_cq_st 949 * Event delivery state machine 950 * 0x0 - FIRED 951 * 0x1 - ARMED (Request for Notification) 952 */ 953 MLXSW_ITEM32(cmd_mbox, sw2hw_cq, st, 0x00, 8, 1); 954 955 /* cmd_mbox_sw2hw_cq_log_cq_size 956 * Log (base 2) of the CQ size (in entries). 957 */ 958 MLXSW_ITEM32(cmd_mbox, sw2hw_cq, log_cq_size, 0x00, 0, 4); 959 960 /* cmd_mbox_sw2hw_cq_producer_counter 961 * Producer Counter. The counter is incremented for each CQE that is 962 * written by the HW to the CQ. 963 * Maintained by HW (valid for the QUERY_CQ command only) 964 */ 965 MLXSW_ITEM32(cmd_mbox, sw2hw_cq, producer_counter, 0x04, 0, 16); 966 967 /* cmd_mbox_sw2hw_cq_pa 968 * Physical Address. 969 */ 970 MLXSW_ITEM64_INDEXED(cmd_mbox, sw2hw_cq, pa, 0x10, 11, 53, 0x08, 0x00, true); 971 972 /* HW2SW_CQ - Hardware to Software CQ 973 * ---------------------------------- 974 * OpMod == 0 (N/A), INMmod == CQ number 975 * ------------------------------------- 976 * The HW2SW_CQ command transfers ownership of a CQ context entry from hardware 977 * to software. The CQC entry is invalidated as a result of this command. 978 */ 979 980 static inline int mlxsw_cmd_hw2sw_cq(struct mlxsw_core *mlxsw_core, 981 u32 cq_number) 982 { 983 return mlxsw_cmd_exec_none(mlxsw_core, MLXSW_CMD_OPCODE_HW2SW_CQ, 984 0, cq_number); 985 } 986 987 /* QUERY_CQ - Query CQ 988 * ---------------------------------- 989 * OpMod == 0 (N/A), INMmod == CQ number 990 * ------------------------------------- 991 * The QUERY_CQ command retrieves a snapshot of the current CQ context entry. 992 * The command stores the snapshot in the output mailbox in the software format. 993 * Note that the CQ context state and values are not affected by the QUERY_CQ 994 * command. The QUERY_CQ command is for debug purposes only. 995 * 996 * Note: Output mailbox has the same format as SW2HW_CQ. 997 */ 998 999 static inline int mlxsw_cmd_query_cq(struct mlxsw_core *mlxsw_core, 1000 char *out_mbox, u32 cq_number) 1001 { 1002 return mlxsw_cmd_exec_out(mlxsw_core, MLXSW_CMD_OPCODE_QUERY_CQ, 1003 0, cq_number, false, 1004 out_mbox, MLXSW_CMD_MBOX_SIZE); 1005 } 1006 1007 /* SW2HW_EQ - Software to Hardware EQ 1008 * ---------------------------------- 1009 * OpMod == 0 (N/A), INMmod == EQ number 1010 * ------------------------------------- 1011 * The SW2HW_EQ command transfers ownership of an EQ context entry from software 1012 * to hardware. The command takes the EQ context entry from the input mailbox 1013 * and stores it in the EQC in the ownership of the hardware. The command fails 1014 * if the requested EQC entry is already in the ownership of the hardware. 1015 */ 1016 1017 static inline int mlxsw_cmd_sw2hw_eq(struct mlxsw_core *mlxsw_core, 1018 char *in_mbox, u32 eq_number) 1019 { 1020 return mlxsw_cmd_exec_in(mlxsw_core, MLXSW_CMD_OPCODE_SW2HW_EQ, 1021 0, eq_number, in_mbox, MLXSW_CMD_MBOX_SIZE); 1022 } 1023 1024 /* cmd_mbox_sw2hw_eq_int_msix 1025 * When set, MSI-X cycles will be generated by this EQ. 1026 * When cleared, an interrupt will be generated by this EQ. 1027 */ 1028 MLXSW_ITEM32(cmd_mbox, sw2hw_eq, int_msix, 0x00, 24, 1); 1029 1030 /* cmd_mbox_sw2hw_eq_int_oi 1031 * When set, overrun ignore is enabled. 1032 */ 1033 MLXSW_ITEM32(cmd_mbox, sw2hw_eq, oi, 0x00, 12, 1); 1034 1035 /* cmd_mbox_sw2hw_eq_int_st 1036 * Event delivery state machine 1037 * 0x0 - FIRED 1038 * 0x1 - ARMED (Request for Notification) 1039 * 0x11 - Always ARMED 1040 * other - reserved 1041 */ 1042 MLXSW_ITEM32(cmd_mbox, sw2hw_eq, st, 0x00, 8, 2); 1043 1044 /* cmd_mbox_sw2hw_eq_int_log_eq_size 1045 * Log (base 2) of the EQ size (in entries). 1046 */ 1047 MLXSW_ITEM32(cmd_mbox, sw2hw_eq, log_eq_size, 0x00, 0, 4); 1048 1049 /* cmd_mbox_sw2hw_eq_int_producer_counter 1050 * Producer Counter. The counter is incremented for each EQE that is written 1051 * by the HW to the EQ. 1052 * Maintained by HW (valid for the QUERY_EQ command only) 1053 */ 1054 MLXSW_ITEM32(cmd_mbox, sw2hw_eq, producer_counter, 0x04, 0, 16); 1055 1056 /* cmd_mbox_sw2hw_eq_int_pa 1057 * Physical Address. 1058 */ 1059 MLXSW_ITEM64_INDEXED(cmd_mbox, sw2hw_eq, pa, 0x10, 11, 53, 0x08, 0x00, true); 1060 1061 /* HW2SW_EQ - Hardware to Software EQ 1062 * ---------------------------------- 1063 * OpMod == 0 (N/A), INMmod == EQ number 1064 * ------------------------------------- 1065 */ 1066 1067 static inline int mlxsw_cmd_hw2sw_eq(struct mlxsw_core *mlxsw_core, 1068 u32 eq_number) 1069 { 1070 return mlxsw_cmd_exec_none(mlxsw_core, MLXSW_CMD_OPCODE_HW2SW_EQ, 1071 0, eq_number); 1072 } 1073 1074 /* QUERY_EQ - Query EQ 1075 * ---------------------------------- 1076 * OpMod == 0 (N/A), INMmod == EQ number 1077 * ------------------------------------- 1078 * 1079 * Note: Output mailbox has the same format as SW2HW_EQ. 1080 */ 1081 1082 static inline int mlxsw_cmd_query_eq(struct mlxsw_core *mlxsw_core, 1083 char *out_mbox, u32 eq_number) 1084 { 1085 return mlxsw_cmd_exec_out(mlxsw_core, MLXSW_CMD_OPCODE_QUERY_EQ, 1086 0, eq_number, false, 1087 out_mbox, MLXSW_CMD_MBOX_SIZE); 1088 } 1089 1090 #endif 1091