1 /* 2 * New driver for Marvell Yukon 2 chipset. 3 * Based on earlier sk98lin, and skge driver. 4 * 5 * This driver intentionally does not support all the features 6 * of the original driver such as link fail-over and link management because 7 * those should be done at higher levels. 8 * 9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org> 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 23 */ 24 25 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 26 27 #include <linux/crc32.h> 28 #include <linux/kernel.h> 29 #include <linux/module.h> 30 #include <linux/netdevice.h> 31 #include <linux/dma-mapping.h> 32 #include <linux/etherdevice.h> 33 #include <linux/ethtool.h> 34 #include <linux/pci.h> 35 #include <linux/interrupt.h> 36 #include <linux/ip.h> 37 #include <linux/slab.h> 38 #include <net/ip.h> 39 #include <linux/tcp.h> 40 #include <linux/in.h> 41 #include <linux/delay.h> 42 #include <linux/workqueue.h> 43 #include <linux/if_vlan.h> 44 #include <linux/prefetch.h> 45 #include <linux/debugfs.h> 46 #include <linux/mii.h> 47 48 #include <asm/irq.h> 49 50 #include "sky2.h" 51 52 #define DRV_NAME "sky2" 53 #define DRV_VERSION "1.30" 54 55 /* 56 * The Yukon II chipset takes 64 bit command blocks (called list elements) 57 * that are organized into three (receive, transmit, status) different rings 58 * similar to Tigon3. 59 */ 60 61 #define RX_LE_SIZE 1024 62 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le)) 63 #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2) 64 #define RX_DEF_PENDING RX_MAX_PENDING 65 66 /* This is the worst case number of transmit list elements for a single skb: 67 VLAN:GSO + CKSUM + Data + skb_frags * DMA */ 68 #define MAX_SKB_TX_LE (2 + (sizeof(dma_addr_t)/sizeof(u32))*(MAX_SKB_FRAGS+1)) 69 #define TX_MIN_PENDING (MAX_SKB_TX_LE+1) 70 #define TX_MAX_PENDING 1024 71 #define TX_DEF_PENDING 63 72 73 #define TX_WATCHDOG (5 * HZ) 74 #define NAPI_WEIGHT 64 75 #define PHY_RETRIES 1000 76 77 #define SKY2_EEPROM_MAGIC 0x9955aabb 78 79 #define RING_NEXT(x, s) (((x)+1) & ((s)-1)) 80 81 static const u32 default_msg = 82 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK 83 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR 84 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN; 85 86 static int debug = -1; /* defaults above */ 87 module_param(debug, int, 0); 88 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 89 90 static int copybreak __read_mostly = 128; 91 module_param(copybreak, int, 0); 92 MODULE_PARM_DESC(copybreak, "Receive copy threshold"); 93 94 static int disable_msi = 0; 95 module_param(disable_msi, int, 0); 96 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)"); 97 98 static DEFINE_PCI_DEVICE_TABLE(sky2_id_table) = { 99 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */ 100 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */ 101 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E01) }, /* SK-9E21M */ 102 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */ 103 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */ 104 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */ 105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */ 106 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */ 107 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */ 108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */ 109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */ 110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */ 111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */ 112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */ 113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */ 114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */ 115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */ 116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */ 117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */ 118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */ 119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4355) }, /* 88E8040T */ 120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */ 121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */ 122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */ 123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */ 124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */ 125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */ 126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */ 127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */ 128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */ 129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */ 130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */ 131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */ 132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */ 133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */ 134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */ 135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */ 136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */ 137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */ 138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4380) }, /* 88E8057 */ 139 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4381) }, /* 88E8059 */ 140 { 0 } 141 }; 142 143 MODULE_DEVICE_TABLE(pci, sky2_id_table); 144 145 /* Avoid conditionals by using array */ 146 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 }; 147 static const unsigned rxqaddr[] = { Q_R1, Q_R2 }; 148 static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 }; 149 150 static void sky2_set_multicast(struct net_device *dev); 151 static irqreturn_t sky2_intr(int irq, void *dev_id); 152 153 /* Access to PHY via serial interconnect */ 154 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val) 155 { 156 int i; 157 158 gma_write16(hw, port, GM_SMI_DATA, val); 159 gma_write16(hw, port, GM_SMI_CTRL, 160 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg)); 161 162 for (i = 0; i < PHY_RETRIES; i++) { 163 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL); 164 if (ctrl == 0xffff) 165 goto io_error; 166 167 if (!(ctrl & GM_SMI_CT_BUSY)) 168 return 0; 169 170 udelay(10); 171 } 172 173 dev_warn(&hw->pdev->dev, "%s: phy write timeout\n", hw->dev[port]->name); 174 return -ETIMEDOUT; 175 176 io_error: 177 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name); 178 return -EIO; 179 } 180 181 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val) 182 { 183 int i; 184 185 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) 186 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD); 187 188 for (i = 0; i < PHY_RETRIES; i++) { 189 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL); 190 if (ctrl == 0xffff) 191 goto io_error; 192 193 if (ctrl & GM_SMI_CT_RD_VAL) { 194 *val = gma_read16(hw, port, GM_SMI_DATA); 195 return 0; 196 } 197 198 udelay(10); 199 } 200 201 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name); 202 return -ETIMEDOUT; 203 io_error: 204 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name); 205 return -EIO; 206 } 207 208 static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg) 209 { 210 u16 v; 211 __gm_phy_read(hw, port, reg, &v); 212 return v; 213 } 214 215 216 static void sky2_power_on(struct sky2_hw *hw) 217 { 218 /* switch power to VCC (WA for VAUX problem) */ 219 sky2_write8(hw, B0_POWER_CTRL, 220 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON); 221 222 /* disable Core Clock Division, */ 223 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS); 224 225 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1) 226 /* enable bits are inverted */ 227 sky2_write8(hw, B2_Y2_CLK_GATE, 228 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | 229 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | 230 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS); 231 else 232 sky2_write8(hw, B2_Y2_CLK_GATE, 0); 233 234 if (hw->flags & SKY2_HW_ADV_POWER_CTL) { 235 u32 reg; 236 237 sky2_pci_write32(hw, PCI_DEV_REG3, 0); 238 239 reg = sky2_pci_read32(hw, PCI_DEV_REG4); 240 /* set all bits to 0 except bits 15..12 and 8 */ 241 reg &= P_ASPM_CONTROL_MSK; 242 sky2_pci_write32(hw, PCI_DEV_REG4, reg); 243 244 reg = sky2_pci_read32(hw, PCI_DEV_REG5); 245 /* set all bits to 0 except bits 28 & 27 */ 246 reg &= P_CTL_TIM_VMAIN_AV_MSK; 247 sky2_pci_write32(hw, PCI_DEV_REG5, reg); 248 249 sky2_pci_write32(hw, PCI_CFG_REG_1, 0); 250 251 sky2_write16(hw, B0_CTST, Y2_HW_WOL_ON); 252 253 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */ 254 reg = sky2_read32(hw, B2_GP_IO); 255 reg |= GLB_GPIO_STAT_RACE_DIS; 256 sky2_write32(hw, B2_GP_IO, reg); 257 258 sky2_read32(hw, B2_GP_IO); 259 } 260 261 /* Turn on "driver loaded" LED */ 262 sky2_write16(hw, B0_CTST, Y2_LED_STAT_ON); 263 } 264 265 static void sky2_power_aux(struct sky2_hw *hw) 266 { 267 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1) 268 sky2_write8(hw, B2_Y2_CLK_GATE, 0); 269 else 270 /* enable bits are inverted */ 271 sky2_write8(hw, B2_Y2_CLK_GATE, 272 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | 273 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | 274 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS); 275 276 /* switch power to VAUX if supported and PME from D3cold */ 277 if ( (sky2_read32(hw, B0_CTST) & Y2_VAUX_AVAIL) && 278 pci_pme_capable(hw->pdev, PCI_D3cold)) 279 sky2_write8(hw, B0_POWER_CTRL, 280 (PC_VAUX_ENA | PC_VCC_ENA | 281 PC_VAUX_ON | PC_VCC_OFF)); 282 283 /* turn off "driver loaded LED" */ 284 sky2_write16(hw, B0_CTST, Y2_LED_STAT_OFF); 285 } 286 287 static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port) 288 { 289 u16 reg; 290 291 /* disable all GMAC IRQ's */ 292 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0); 293 294 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */ 295 gma_write16(hw, port, GM_MC_ADDR_H2, 0); 296 gma_write16(hw, port, GM_MC_ADDR_H3, 0); 297 gma_write16(hw, port, GM_MC_ADDR_H4, 0); 298 299 reg = gma_read16(hw, port, GM_RX_CTRL); 300 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA; 301 gma_write16(hw, port, GM_RX_CTRL, reg); 302 } 303 304 /* flow control to advertise bits */ 305 static const u16 copper_fc_adv[] = { 306 [FC_NONE] = 0, 307 [FC_TX] = PHY_M_AN_ASP, 308 [FC_RX] = PHY_M_AN_PC, 309 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP, 310 }; 311 312 /* flow control to advertise bits when using 1000BaseX */ 313 static const u16 fiber_fc_adv[] = { 314 [FC_NONE] = PHY_M_P_NO_PAUSE_X, 315 [FC_TX] = PHY_M_P_ASYM_MD_X, 316 [FC_RX] = PHY_M_P_SYM_MD_X, 317 [FC_BOTH] = PHY_M_P_BOTH_MD_X, 318 }; 319 320 /* flow control to GMA disable bits */ 321 static const u16 gm_fc_disable[] = { 322 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS, 323 [FC_TX] = GM_GPCR_FC_RX_DIS, 324 [FC_RX] = GM_GPCR_FC_TX_DIS, 325 [FC_BOTH] = 0, 326 }; 327 328 329 static void sky2_phy_init(struct sky2_hw *hw, unsigned port) 330 { 331 struct sky2_port *sky2 = netdev_priv(hw->dev[port]); 332 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg; 333 334 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) && 335 !(hw->flags & SKY2_HW_NEWER_PHY)) { 336 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL); 337 338 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK | 339 PHY_M_EC_MAC_S_MSK); 340 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ); 341 342 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */ 343 if (hw->chip_id == CHIP_ID_YUKON_EC) 344 /* set downshift counter to 3x and enable downshift */ 345 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA; 346 else 347 /* set master & slave downshift counter to 1x */ 348 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1); 349 350 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl); 351 } 352 353 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); 354 if (sky2_is_copper(hw)) { 355 if (!(hw->flags & SKY2_HW_GIGABIT)) { 356 /* enable automatic crossover */ 357 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1; 358 359 if (hw->chip_id == CHIP_ID_YUKON_FE_P && 360 hw->chip_rev == CHIP_REV_YU_FE2_A0) { 361 u16 spec; 362 363 /* Enable Class A driver for FE+ A0 */ 364 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2); 365 spec |= PHY_M_FESC_SEL_CL_A; 366 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec); 367 } 368 } else { 369 /* disable energy detect */ 370 ctrl &= ~PHY_M_PC_EN_DET_MSK; 371 372 /* enable automatic crossover */ 373 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO); 374 375 /* downshift on PHY 88E1112 and 88E1149 is changed */ 376 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) && 377 (hw->flags & SKY2_HW_NEWER_PHY)) { 378 /* set downshift counter to 3x and enable downshift */ 379 ctrl &= ~PHY_M_PC_DSC_MSK; 380 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA; 381 } 382 } 383 } else { 384 /* workaround for deviation #4.88 (CRC errors) */ 385 /* disable Automatic Crossover */ 386 387 ctrl &= ~PHY_M_PC_MDIX_MSK; 388 } 389 390 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); 391 392 /* special setup for PHY 88E1112 Fiber */ 393 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) { 394 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); 395 396 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */ 397 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2); 398 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); 399 ctrl &= ~PHY_M_MAC_MD_MSK; 400 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX); 401 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); 402 403 if (hw->pmd_type == 'P') { 404 /* select page 1 to access Fiber registers */ 405 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1); 406 407 /* for SFP-module set SIGDET polarity to low */ 408 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); 409 ctrl |= PHY_M_FIB_SIGD_POL; 410 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); 411 } 412 413 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); 414 } 415 416 ctrl = PHY_CT_RESET; 417 ct1000 = 0; 418 adv = PHY_AN_CSMA; 419 reg = 0; 420 421 if (sky2->flags & SKY2_FLAG_AUTO_SPEED) { 422 if (sky2_is_copper(hw)) { 423 if (sky2->advertising & ADVERTISED_1000baseT_Full) 424 ct1000 |= PHY_M_1000C_AFD; 425 if (sky2->advertising & ADVERTISED_1000baseT_Half) 426 ct1000 |= PHY_M_1000C_AHD; 427 if (sky2->advertising & ADVERTISED_100baseT_Full) 428 adv |= PHY_M_AN_100_FD; 429 if (sky2->advertising & ADVERTISED_100baseT_Half) 430 adv |= PHY_M_AN_100_HD; 431 if (sky2->advertising & ADVERTISED_10baseT_Full) 432 adv |= PHY_M_AN_10_FD; 433 if (sky2->advertising & ADVERTISED_10baseT_Half) 434 adv |= PHY_M_AN_10_HD; 435 436 } else { /* special defines for FIBER (88E1040S only) */ 437 if (sky2->advertising & ADVERTISED_1000baseT_Full) 438 adv |= PHY_M_AN_1000X_AFD; 439 if (sky2->advertising & ADVERTISED_1000baseT_Half) 440 adv |= PHY_M_AN_1000X_AHD; 441 } 442 443 /* Restart Auto-negotiation */ 444 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG; 445 } else { 446 /* forced speed/duplex settings */ 447 ct1000 = PHY_M_1000C_MSE; 448 449 /* Disable auto update for duplex flow control and duplex */ 450 reg |= GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_SPD_DIS; 451 452 switch (sky2->speed) { 453 case SPEED_1000: 454 ctrl |= PHY_CT_SP1000; 455 reg |= GM_GPCR_SPEED_1000; 456 break; 457 case SPEED_100: 458 ctrl |= PHY_CT_SP100; 459 reg |= GM_GPCR_SPEED_100; 460 break; 461 } 462 463 if (sky2->duplex == DUPLEX_FULL) { 464 reg |= GM_GPCR_DUP_FULL; 465 ctrl |= PHY_CT_DUP_MD; 466 } else if (sky2->speed < SPEED_1000) 467 sky2->flow_mode = FC_NONE; 468 } 469 470 if (sky2->flags & SKY2_FLAG_AUTO_PAUSE) { 471 if (sky2_is_copper(hw)) 472 adv |= copper_fc_adv[sky2->flow_mode]; 473 else 474 adv |= fiber_fc_adv[sky2->flow_mode]; 475 } else { 476 reg |= GM_GPCR_AU_FCT_DIS; 477 reg |= gm_fc_disable[sky2->flow_mode]; 478 479 /* Forward pause packets to GMAC? */ 480 if (sky2->flow_mode & FC_RX) 481 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON); 482 else 483 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); 484 } 485 486 gma_write16(hw, port, GM_GP_CTRL, reg); 487 488 if (hw->flags & SKY2_HW_GIGABIT) 489 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000); 490 491 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv); 492 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl); 493 494 /* Setup Phy LED's */ 495 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS); 496 ledover = 0; 497 498 switch (hw->chip_id) { 499 case CHIP_ID_YUKON_FE: 500 /* on 88E3082 these bits are at 11..9 (shifted left) */ 501 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1; 502 503 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR); 504 505 /* delete ACT LED control bits */ 506 ctrl &= ~PHY_M_FELP_LED1_MSK; 507 /* change ACT LED control to blink mode */ 508 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL); 509 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl); 510 break; 511 512 case CHIP_ID_YUKON_FE_P: 513 /* Enable Link Partner Next Page */ 514 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); 515 ctrl |= PHY_M_PC_ENA_LIP_NP; 516 517 /* disable Energy Detect and enable scrambler */ 518 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB); 519 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); 520 521 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */ 522 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) | 523 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) | 524 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED); 525 526 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl); 527 break; 528 529 case CHIP_ID_YUKON_XL: 530 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); 531 532 /* select page 3 to access LED control register */ 533 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); 534 535 /* set LED Function Control register */ 536 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, 537 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */ 538 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */ 539 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */ 540 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */ 541 542 /* set Polarity Control register */ 543 gm_phy_write(hw, port, PHY_MARV_PHY_STAT, 544 (PHY_M_POLC_LS1_P_MIX(4) | 545 PHY_M_POLC_IS0_P_MIX(4) | 546 PHY_M_POLC_LOS_CTRL(2) | 547 PHY_M_POLC_INIT_CTRL(2) | 548 PHY_M_POLC_STA1_CTRL(2) | 549 PHY_M_POLC_STA0_CTRL(2))); 550 551 /* restore page register */ 552 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); 553 break; 554 555 case CHIP_ID_YUKON_EC_U: 556 case CHIP_ID_YUKON_EX: 557 case CHIP_ID_YUKON_SUPR: 558 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); 559 560 /* select page 3 to access LED control register */ 561 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); 562 563 /* set LED Function Control register */ 564 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, 565 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */ 566 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */ 567 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */ 568 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */ 569 570 /* set Blink Rate in LED Timer Control Register */ 571 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 572 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS)); 573 /* restore page register */ 574 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); 575 break; 576 577 default: 578 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */ 579 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL; 580 581 /* turn off the Rx LED (LED_RX) */ 582 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF); 583 } 584 585 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_UL_2) { 586 /* apply fixes in PHY AFE */ 587 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255); 588 589 /* increase differential signal amplitude in 10BASE-T */ 590 gm_phy_write(hw, port, 0x18, 0xaa99); 591 gm_phy_write(hw, port, 0x17, 0x2011); 592 593 if (hw->chip_id == CHIP_ID_YUKON_EC_U) { 594 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */ 595 gm_phy_write(hw, port, 0x18, 0xa204); 596 gm_phy_write(hw, port, 0x17, 0x2002); 597 } 598 599 /* set page register to 0 */ 600 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0); 601 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P && 602 hw->chip_rev == CHIP_REV_YU_FE2_A0) { 603 /* apply workaround for integrated resistors calibration */ 604 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17); 605 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60); 606 } else if (hw->chip_id == CHIP_ID_YUKON_OPT && hw->chip_rev == 0) { 607 /* apply fixes in PHY AFE */ 608 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00ff); 609 610 /* apply RDAC termination workaround */ 611 gm_phy_write(hw, port, 24, 0x2800); 612 gm_phy_write(hw, port, 23, 0x2001); 613 614 /* set page register back to 0 */ 615 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0); 616 } else if (hw->chip_id != CHIP_ID_YUKON_EX && 617 hw->chip_id < CHIP_ID_YUKON_SUPR) { 618 /* no effect on Yukon-XL */ 619 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl); 620 621 if (!(sky2->flags & SKY2_FLAG_AUTO_SPEED) || 622 sky2->speed == SPEED_100) { 623 /* turn on 100 Mbps LED (LED_LINK100) */ 624 ledover |= PHY_M_LED_MO_100(MO_LED_ON); 625 } 626 627 if (ledover) 628 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover); 629 630 } else if (hw->chip_id == CHIP_ID_YUKON_PRM && 631 (sky2_read8(hw, B2_MAC_CFG) & 0xf) == 0x7) { 632 int i; 633 /* This a phy register setup workaround copied from vendor driver. */ 634 static const struct { 635 u16 reg, val; 636 } eee_afe[] = { 637 { 0x156, 0x58ce }, 638 { 0x153, 0x99eb }, 639 { 0x141, 0x8064 }, 640 /* { 0x155, 0x130b },*/ 641 { 0x000, 0x0000 }, 642 { 0x151, 0x8433 }, 643 { 0x14b, 0x8c44 }, 644 { 0x14c, 0x0f90 }, 645 { 0x14f, 0x39aa }, 646 /* { 0x154, 0x2f39 },*/ 647 { 0x14d, 0xba33 }, 648 { 0x144, 0x0048 }, 649 { 0x152, 0x2010 }, 650 /* { 0x158, 0x1223 },*/ 651 { 0x140, 0x4444 }, 652 { 0x154, 0x2f3b }, 653 { 0x158, 0xb203 }, 654 { 0x157, 0x2029 }, 655 }; 656 657 /* Start Workaround for OptimaEEE Rev.Z0 */ 658 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00fb); 659 660 gm_phy_write(hw, port, 1, 0x4099); 661 gm_phy_write(hw, port, 3, 0x1120); 662 gm_phy_write(hw, port, 11, 0x113c); 663 gm_phy_write(hw, port, 14, 0x8100); 664 gm_phy_write(hw, port, 15, 0x112a); 665 gm_phy_write(hw, port, 17, 0x1008); 666 667 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00fc); 668 gm_phy_write(hw, port, 1, 0x20b0); 669 670 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00ff); 671 672 for (i = 0; i < ARRAY_SIZE(eee_afe); i++) { 673 /* apply AFE settings */ 674 gm_phy_write(hw, port, 17, eee_afe[i].val); 675 gm_phy_write(hw, port, 16, eee_afe[i].reg | 1u<<13); 676 } 677 678 /* End Workaround for OptimaEEE */ 679 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0); 680 681 /* Enable 10Base-Te (EEE) */ 682 if (hw->chip_id >= CHIP_ID_YUKON_PRM) { 683 reg = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL); 684 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, 685 reg | PHY_M_10B_TE_ENABLE); 686 } 687 } 688 689 /* Enable phy interrupt on auto-negotiation complete (or link up) */ 690 if (sky2->flags & SKY2_FLAG_AUTO_SPEED) 691 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL); 692 else 693 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK); 694 } 695 696 static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD }; 697 static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA }; 698 699 static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port) 700 { 701 u32 reg1; 702 703 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); 704 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1); 705 reg1 &= ~phy_power[port]; 706 707 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1) 708 reg1 |= coma_mode[port]; 709 710 sky2_pci_write32(hw, PCI_DEV_REG1, reg1); 711 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 712 sky2_pci_read32(hw, PCI_DEV_REG1); 713 714 if (hw->chip_id == CHIP_ID_YUKON_FE) 715 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_ANE); 716 else if (hw->flags & SKY2_HW_ADV_POWER_CTL) 717 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR); 718 } 719 720 static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port) 721 { 722 u32 reg1; 723 u16 ctrl; 724 725 /* release GPHY Control reset */ 726 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR); 727 728 /* release GMAC reset */ 729 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR); 730 731 if (hw->flags & SKY2_HW_NEWER_PHY) { 732 /* select page 2 to access MAC control register */ 733 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2); 734 735 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); 736 /* allow GMII Power Down */ 737 ctrl &= ~PHY_M_MAC_GMIF_PUP; 738 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); 739 740 /* set page register back to 0 */ 741 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0); 742 } 743 744 /* setup General Purpose Control Register */ 745 gma_write16(hw, port, GM_GP_CTRL, 746 GM_GPCR_FL_PASS | GM_GPCR_SPEED_100 | 747 GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS | 748 GM_GPCR_AU_SPD_DIS); 749 750 if (hw->chip_id != CHIP_ID_YUKON_EC) { 751 if (hw->chip_id == CHIP_ID_YUKON_EC_U) { 752 /* select page 2 to access MAC control register */ 753 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2); 754 755 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); 756 /* enable Power Down */ 757 ctrl |= PHY_M_PC_POW_D_ENA; 758 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); 759 760 /* set page register back to 0 */ 761 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0); 762 } 763 764 /* set IEEE compatible Power Down Mode (dev. #4.99) */ 765 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_PDOWN); 766 } 767 768 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); 769 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1); 770 reg1 |= phy_power[port]; /* set PHY to PowerDown/COMA Mode */ 771 sky2_pci_write32(hw, PCI_DEV_REG1, reg1); 772 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 773 } 774 775 /* configure IPG according to used link speed */ 776 static void sky2_set_ipg(struct sky2_port *sky2) 777 { 778 u16 reg; 779 780 reg = gma_read16(sky2->hw, sky2->port, GM_SERIAL_MODE); 781 reg &= ~GM_SMOD_IPG_MSK; 782 if (sky2->speed > SPEED_100) 783 reg |= IPG_DATA_VAL(IPG_DATA_DEF_1000); 784 else 785 reg |= IPG_DATA_VAL(IPG_DATA_DEF_10_100); 786 gma_write16(sky2->hw, sky2->port, GM_SERIAL_MODE, reg); 787 } 788 789 /* Enable Rx/Tx */ 790 static void sky2_enable_rx_tx(struct sky2_port *sky2) 791 { 792 struct sky2_hw *hw = sky2->hw; 793 unsigned port = sky2->port; 794 u16 reg; 795 796 reg = gma_read16(hw, port, GM_GP_CTRL); 797 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA; 798 gma_write16(hw, port, GM_GP_CTRL, reg); 799 } 800 801 /* Force a renegotiation */ 802 static void sky2_phy_reinit(struct sky2_port *sky2) 803 { 804 spin_lock_bh(&sky2->phy_lock); 805 sky2_phy_init(sky2->hw, sky2->port); 806 sky2_enable_rx_tx(sky2); 807 spin_unlock_bh(&sky2->phy_lock); 808 } 809 810 /* Put device in state to listen for Wake On Lan */ 811 static void sky2_wol_init(struct sky2_port *sky2) 812 { 813 struct sky2_hw *hw = sky2->hw; 814 unsigned port = sky2->port; 815 enum flow_control save_mode; 816 u16 ctrl; 817 818 /* Bring hardware out of reset */ 819 sky2_write16(hw, B0_CTST, CS_RST_CLR); 820 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR); 821 822 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR); 823 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR); 824 825 /* Force to 10/100 826 * sky2_reset will re-enable on resume 827 */ 828 save_mode = sky2->flow_mode; 829 ctrl = sky2->advertising; 830 831 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full); 832 sky2->flow_mode = FC_NONE; 833 834 spin_lock_bh(&sky2->phy_lock); 835 sky2_phy_power_up(hw, port); 836 sky2_phy_init(hw, port); 837 spin_unlock_bh(&sky2->phy_lock); 838 839 sky2->flow_mode = save_mode; 840 sky2->advertising = ctrl; 841 842 /* Set GMAC to no flow control and auto update for speed/duplex */ 843 gma_write16(hw, port, GM_GP_CTRL, 844 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA| 845 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS); 846 847 /* Set WOL address */ 848 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR), 849 sky2->netdev->dev_addr, ETH_ALEN); 850 851 /* Turn on appropriate WOL control bits */ 852 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT); 853 ctrl = 0; 854 if (sky2->wol & WAKE_PHY) 855 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT; 856 else 857 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT; 858 859 if (sky2->wol & WAKE_MAGIC) 860 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT; 861 else 862 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT; 863 864 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT; 865 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl); 866 867 /* Disable PiG firmware */ 868 sky2_write16(hw, B0_CTST, Y2_HW_WOL_OFF); 869 870 /* block receiver */ 871 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET); 872 sky2_read32(hw, B0_CTST); 873 } 874 875 static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port) 876 { 877 struct net_device *dev = hw->dev[port]; 878 879 if ( (hw->chip_id == CHIP_ID_YUKON_EX && 880 hw->chip_rev != CHIP_REV_YU_EX_A0) || 881 hw->chip_id >= CHIP_ID_YUKON_FE_P) { 882 /* Yukon-Extreme B0 and further Extreme devices */ 883 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA); 884 } else if (dev->mtu > ETH_DATA_LEN) { 885 /* set Tx GMAC FIFO Almost Empty Threshold */ 886 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 887 (ECU_JUMBO_WM << 16) | ECU_AE_THR); 888 889 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS); 890 } else 891 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA); 892 } 893 894 static void sky2_mac_init(struct sky2_hw *hw, unsigned port) 895 { 896 struct sky2_port *sky2 = netdev_priv(hw->dev[port]); 897 u16 reg; 898 u32 rx_reg; 899 int i; 900 const u8 *addr = hw->dev[port]->dev_addr; 901 902 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET); 903 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR); 904 905 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR); 906 907 if (hw->chip_id == CHIP_ID_YUKON_XL && 908 hw->chip_rev == CHIP_REV_YU_XL_A0 && 909 port == 1) { 910 /* WA DEV_472 -- looks like crossed wires on port 2 */ 911 /* clear GMAC 1 Control reset */ 912 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR); 913 do { 914 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET); 915 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR); 916 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL || 917 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 || 918 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0); 919 } 920 921 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC)); 922 923 /* Enable Transmit FIFO Underrun */ 924 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK); 925 926 spin_lock_bh(&sky2->phy_lock); 927 sky2_phy_power_up(hw, port); 928 sky2_phy_init(hw, port); 929 spin_unlock_bh(&sky2->phy_lock); 930 931 /* MIB clear */ 932 reg = gma_read16(hw, port, GM_PHY_ADDR); 933 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR); 934 935 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4) 936 gma_read16(hw, port, i); 937 gma_write16(hw, port, GM_PHY_ADDR, reg); 938 939 /* transmit control */ 940 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF)); 941 942 /* receive control reg: unicast + multicast + no FCS */ 943 gma_write16(hw, port, GM_RX_CTRL, 944 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA); 945 946 /* transmit flow control */ 947 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff); 948 949 /* transmit parameter */ 950 gma_write16(hw, port, GM_TX_PARAM, 951 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) | 952 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) | 953 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) | 954 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF)); 955 956 /* serial mode register */ 957 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) | 958 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF_1000); 959 960 if (hw->dev[port]->mtu > ETH_DATA_LEN) 961 reg |= GM_SMOD_JUMBO_ENA; 962 963 if (hw->chip_id == CHIP_ID_YUKON_EC_U && 964 hw->chip_rev == CHIP_REV_YU_EC_U_B1) 965 reg |= GM_NEW_FLOW_CTRL; 966 967 gma_write16(hw, port, GM_SERIAL_MODE, reg); 968 969 /* virtual address for data */ 970 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr); 971 972 /* physical address: used for pause frames */ 973 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr); 974 975 /* ignore counter overflows */ 976 gma_write16(hw, port, GM_TX_IRQ_MSK, 0); 977 gma_write16(hw, port, GM_RX_IRQ_MSK, 0); 978 gma_write16(hw, port, GM_TR_IRQ_MSK, 0); 979 980 /* Configure Rx MAC FIFO */ 981 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR); 982 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON; 983 if (hw->chip_id == CHIP_ID_YUKON_EX || 984 hw->chip_id == CHIP_ID_YUKON_FE_P) 985 rx_reg |= GMF_RX_OVER_ON; 986 987 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg); 988 989 if (hw->chip_id == CHIP_ID_YUKON_XL) { 990 /* Hardware errata - clear flush mask */ 991 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0); 992 } else { 993 /* Flush Rx MAC FIFO on any flow control or error */ 994 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR); 995 } 996 997 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */ 998 reg = RX_GMF_FL_THR_DEF + 1; 999 /* Another magic mystery workaround from sk98lin */ 1000 if (hw->chip_id == CHIP_ID_YUKON_FE_P && 1001 hw->chip_rev == CHIP_REV_YU_FE2_A0) 1002 reg = 0x178; 1003 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg); 1004 1005 /* Configure Tx MAC FIFO */ 1006 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR); 1007 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON); 1008 1009 /* On chips without ram buffer, pause is controlled by MAC level */ 1010 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) { 1011 /* Pause threshold is scaled by 8 in bytes */ 1012 if (hw->chip_id == CHIP_ID_YUKON_FE_P && 1013 hw->chip_rev == CHIP_REV_YU_FE2_A0) 1014 reg = 1568 / 8; 1015 else 1016 reg = 1024 / 8; 1017 sky2_write16(hw, SK_REG(port, RX_GMF_UP_THR), reg); 1018 sky2_write16(hw, SK_REG(port, RX_GMF_LP_THR), 768 / 8); 1019 1020 sky2_set_tx_stfwd(hw, port); 1021 } 1022 1023 if (hw->chip_id == CHIP_ID_YUKON_FE_P && 1024 hw->chip_rev == CHIP_REV_YU_FE2_A0) { 1025 /* disable dynamic watermark */ 1026 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA)); 1027 reg &= ~TX_DYN_WM_ENA; 1028 sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg); 1029 } 1030 } 1031 1032 /* Assign Ram Buffer allocation to queue */ 1033 static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space) 1034 { 1035 u32 end; 1036 1037 /* convert from K bytes to qwords used for hw register */ 1038 start *= 1024/8; 1039 space *= 1024/8; 1040 end = start + space - 1; 1041 1042 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR); 1043 sky2_write32(hw, RB_ADDR(q, RB_START), start); 1044 sky2_write32(hw, RB_ADDR(q, RB_END), end); 1045 sky2_write32(hw, RB_ADDR(q, RB_WP), start); 1046 sky2_write32(hw, RB_ADDR(q, RB_RP), start); 1047 1048 if (q == Q_R1 || q == Q_R2) { 1049 u32 tp = space - space/4; 1050 1051 /* On receive queue's set the thresholds 1052 * give receiver priority when > 3/4 full 1053 * send pause when down to 2K 1054 */ 1055 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp); 1056 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2); 1057 1058 tp = space - 2048/8; 1059 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp); 1060 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4); 1061 } else { 1062 /* Enable store & forward on Tx queue's because 1063 * Tx FIFO is only 1K on Yukon 1064 */ 1065 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD); 1066 } 1067 1068 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD); 1069 sky2_read8(hw, RB_ADDR(q, RB_CTRL)); 1070 } 1071 1072 /* Setup Bus Memory Interface */ 1073 static void sky2_qset(struct sky2_hw *hw, u16 q) 1074 { 1075 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET); 1076 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT); 1077 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON); 1078 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT); 1079 } 1080 1081 /* Setup prefetch unit registers. This is the interface between 1082 * hardware and driver list elements 1083 */ 1084 static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr, 1085 dma_addr_t addr, u32 last) 1086 { 1087 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET); 1088 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR); 1089 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), upper_32_bits(addr)); 1090 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), lower_32_bits(addr)); 1091 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last); 1092 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON); 1093 1094 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL)); 1095 } 1096 1097 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2, u16 *slot) 1098 { 1099 struct sky2_tx_le *le = sky2->tx_le + *slot; 1100 1101 *slot = RING_NEXT(*slot, sky2->tx_ring_size); 1102 le->ctrl = 0; 1103 return le; 1104 } 1105 1106 static void tx_init(struct sky2_port *sky2) 1107 { 1108 struct sky2_tx_le *le; 1109 1110 sky2->tx_prod = sky2->tx_cons = 0; 1111 sky2->tx_tcpsum = 0; 1112 sky2->tx_last_mss = 0; 1113 netdev_reset_queue(sky2->netdev); 1114 1115 le = get_tx_le(sky2, &sky2->tx_prod); 1116 le->addr = 0; 1117 le->opcode = OP_ADDR64 | HW_OWNER; 1118 sky2->tx_last_upper = 0; 1119 } 1120 1121 /* Update chip's next pointer */ 1122 static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx) 1123 { 1124 /* Make sure write' to descriptors are complete before we tell hardware */ 1125 wmb(); 1126 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx); 1127 1128 /* Synchronize I/O on since next processor may write to tail */ 1129 mmiowb(); 1130 } 1131 1132 1133 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2) 1134 { 1135 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put; 1136 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE); 1137 le->ctrl = 0; 1138 return le; 1139 } 1140 1141 static unsigned sky2_get_rx_threshold(struct sky2_port *sky2) 1142 { 1143 unsigned size; 1144 1145 /* Space needed for frame data + headers rounded up */ 1146 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8); 1147 1148 /* Stopping point for hardware truncation */ 1149 return (size - 8) / sizeof(u32); 1150 } 1151 1152 static unsigned sky2_get_rx_data_size(struct sky2_port *sky2) 1153 { 1154 struct rx_ring_info *re; 1155 unsigned size; 1156 1157 /* Space needed for frame data + headers rounded up */ 1158 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8); 1159 1160 sky2->rx_nfrags = size >> PAGE_SHIFT; 1161 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr)); 1162 1163 /* Compute residue after pages */ 1164 size -= sky2->rx_nfrags << PAGE_SHIFT; 1165 1166 /* Optimize to handle small packets and headers */ 1167 if (size < copybreak) 1168 size = copybreak; 1169 if (size < ETH_HLEN) 1170 size = ETH_HLEN; 1171 1172 return size; 1173 } 1174 1175 /* Build description to hardware for one receive segment */ 1176 static void sky2_rx_add(struct sky2_port *sky2, u8 op, 1177 dma_addr_t map, unsigned len) 1178 { 1179 struct sky2_rx_le *le; 1180 1181 if (sizeof(dma_addr_t) > sizeof(u32)) { 1182 le = sky2_next_rx(sky2); 1183 le->addr = cpu_to_le32(upper_32_bits(map)); 1184 le->opcode = OP_ADDR64 | HW_OWNER; 1185 } 1186 1187 le = sky2_next_rx(sky2); 1188 le->addr = cpu_to_le32(lower_32_bits(map)); 1189 le->length = cpu_to_le16(len); 1190 le->opcode = op | HW_OWNER; 1191 } 1192 1193 /* Build description to hardware for one possibly fragmented skb */ 1194 static void sky2_rx_submit(struct sky2_port *sky2, 1195 const struct rx_ring_info *re) 1196 { 1197 int i; 1198 1199 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size); 1200 1201 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++) 1202 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE); 1203 } 1204 1205 1206 static int sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re, 1207 unsigned size) 1208 { 1209 struct sk_buff *skb = re->skb; 1210 int i; 1211 1212 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE); 1213 if (pci_dma_mapping_error(pdev, re->data_addr)) 1214 goto mapping_error; 1215 1216 dma_unmap_len_set(re, data_size, size); 1217 1218 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1219 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1220 1221 re->frag_addr[i] = skb_frag_dma_map(&pdev->dev, frag, 0, 1222 skb_frag_size(frag), 1223 DMA_FROM_DEVICE); 1224 1225 if (dma_mapping_error(&pdev->dev, re->frag_addr[i])) 1226 goto map_page_error; 1227 } 1228 return 0; 1229 1230 map_page_error: 1231 while (--i >= 0) { 1232 pci_unmap_page(pdev, re->frag_addr[i], 1233 skb_frag_size(&skb_shinfo(skb)->frags[i]), 1234 PCI_DMA_FROMDEVICE); 1235 } 1236 1237 pci_unmap_single(pdev, re->data_addr, dma_unmap_len(re, data_size), 1238 PCI_DMA_FROMDEVICE); 1239 1240 mapping_error: 1241 if (net_ratelimit()) 1242 dev_warn(&pdev->dev, "%s: rx mapping error\n", 1243 skb->dev->name); 1244 return -EIO; 1245 } 1246 1247 static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re) 1248 { 1249 struct sk_buff *skb = re->skb; 1250 int i; 1251 1252 pci_unmap_single(pdev, re->data_addr, dma_unmap_len(re, data_size), 1253 PCI_DMA_FROMDEVICE); 1254 1255 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) 1256 pci_unmap_page(pdev, re->frag_addr[i], 1257 skb_frag_size(&skb_shinfo(skb)->frags[i]), 1258 PCI_DMA_FROMDEVICE); 1259 } 1260 1261 /* Tell chip where to start receive checksum. 1262 * Actually has two checksums, but set both same to avoid possible byte 1263 * order problems. 1264 */ 1265 static void rx_set_checksum(struct sky2_port *sky2) 1266 { 1267 struct sky2_rx_le *le = sky2_next_rx(sky2); 1268 1269 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN); 1270 le->ctrl = 0; 1271 le->opcode = OP_TCPSTART | HW_OWNER; 1272 1273 sky2_write32(sky2->hw, 1274 Q_ADDR(rxqaddr[sky2->port], Q_CSR), 1275 (sky2->netdev->features & NETIF_F_RXCSUM) 1276 ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM); 1277 } 1278 1279 /* 1280 * Fixed initial key as seed to RSS. 1281 */ 1282 static const uint32_t rss_init_key[10] = { 1283 0x7c3351da, 0x51c5cf4e, 0x44adbdd1, 0xe8d38d18, 0x48897c43, 1284 0xb1d60e7e, 0x6a3dd760, 0x01a2e453, 0x16f46f13, 0x1a0e7b30 1285 }; 1286 1287 /* Enable/disable receive hash calculation (RSS) */ 1288 static void rx_set_rss(struct net_device *dev, netdev_features_t features) 1289 { 1290 struct sky2_port *sky2 = netdev_priv(dev); 1291 struct sky2_hw *hw = sky2->hw; 1292 int i, nkeys = 4; 1293 1294 /* Supports IPv6 and other modes */ 1295 if (hw->flags & SKY2_HW_NEW_LE) { 1296 nkeys = 10; 1297 sky2_write32(hw, SK_REG(sky2->port, RSS_CFG), HASH_ALL); 1298 } 1299 1300 /* Program RSS initial values */ 1301 if (features & NETIF_F_RXHASH) { 1302 for (i = 0; i < nkeys; i++) 1303 sky2_write32(hw, SK_REG(sky2->port, RSS_KEY + i * 4), 1304 rss_init_key[i]); 1305 1306 /* Need to turn on (undocumented) flag to make hashing work */ 1307 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), 1308 RX_STFW_ENA); 1309 1310 sky2_write32(hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR), 1311 BMU_ENA_RX_RSS_HASH); 1312 } else 1313 sky2_write32(hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR), 1314 BMU_DIS_RX_RSS_HASH); 1315 } 1316 1317 /* 1318 * The RX Stop command will not work for Yukon-2 if the BMU does not 1319 * reach the end of packet and since we can't make sure that we have 1320 * incoming data, we must reset the BMU while it is not doing a DMA 1321 * transfer. Since it is possible that the RX path is still active, 1322 * the RX RAM buffer will be stopped first, so any possible incoming 1323 * data will not trigger a DMA. After the RAM buffer is stopped, the 1324 * BMU is polled until any DMA in progress is ended and only then it 1325 * will be reset. 1326 */ 1327 static void sky2_rx_stop(struct sky2_port *sky2) 1328 { 1329 struct sky2_hw *hw = sky2->hw; 1330 unsigned rxq = rxqaddr[sky2->port]; 1331 int i; 1332 1333 /* disable the RAM Buffer receive queue */ 1334 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD); 1335 1336 for (i = 0; i < 0xffff; i++) 1337 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL)) 1338 == sky2_read8(hw, RB_ADDR(rxq, Q_RL))) 1339 goto stopped; 1340 1341 netdev_warn(sky2->netdev, "receiver stop failed\n"); 1342 stopped: 1343 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST); 1344 1345 /* reset the Rx prefetch unit */ 1346 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET); 1347 mmiowb(); 1348 } 1349 1350 /* Clean out receive buffer area, assumes receiver hardware stopped */ 1351 static void sky2_rx_clean(struct sky2_port *sky2) 1352 { 1353 unsigned i; 1354 1355 memset(sky2->rx_le, 0, RX_LE_BYTES); 1356 for (i = 0; i < sky2->rx_pending; i++) { 1357 struct rx_ring_info *re = sky2->rx_ring + i; 1358 1359 if (re->skb) { 1360 sky2_rx_unmap_skb(sky2->hw->pdev, re); 1361 kfree_skb(re->skb); 1362 re->skb = NULL; 1363 } 1364 } 1365 } 1366 1367 /* Basic MII support */ 1368 static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 1369 { 1370 struct mii_ioctl_data *data = if_mii(ifr); 1371 struct sky2_port *sky2 = netdev_priv(dev); 1372 struct sky2_hw *hw = sky2->hw; 1373 int err = -EOPNOTSUPP; 1374 1375 if (!netif_running(dev)) 1376 return -ENODEV; /* Phy still in reset */ 1377 1378 switch (cmd) { 1379 case SIOCGMIIPHY: 1380 data->phy_id = PHY_ADDR_MARV; 1381 1382 /* fallthru */ 1383 case SIOCGMIIREG: { 1384 u16 val = 0; 1385 1386 spin_lock_bh(&sky2->phy_lock); 1387 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val); 1388 spin_unlock_bh(&sky2->phy_lock); 1389 1390 data->val_out = val; 1391 break; 1392 } 1393 1394 case SIOCSMIIREG: 1395 spin_lock_bh(&sky2->phy_lock); 1396 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f, 1397 data->val_in); 1398 spin_unlock_bh(&sky2->phy_lock); 1399 break; 1400 } 1401 return err; 1402 } 1403 1404 #define SKY2_VLAN_OFFLOADS (NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_TSO) 1405 1406 static void sky2_vlan_mode(struct net_device *dev, netdev_features_t features) 1407 { 1408 struct sky2_port *sky2 = netdev_priv(dev); 1409 struct sky2_hw *hw = sky2->hw; 1410 u16 port = sky2->port; 1411 1412 if (features & NETIF_F_HW_VLAN_RX) 1413 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), 1414 RX_VLAN_STRIP_ON); 1415 else 1416 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), 1417 RX_VLAN_STRIP_OFF); 1418 1419 if (features & NETIF_F_HW_VLAN_TX) { 1420 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), 1421 TX_VLAN_TAG_ON); 1422 1423 dev->vlan_features |= SKY2_VLAN_OFFLOADS; 1424 } else { 1425 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), 1426 TX_VLAN_TAG_OFF); 1427 1428 /* Can't do transmit offload of vlan without hw vlan */ 1429 dev->vlan_features &= ~SKY2_VLAN_OFFLOADS; 1430 } 1431 } 1432 1433 /* Amount of required worst case padding in rx buffer */ 1434 static inline unsigned sky2_rx_pad(const struct sky2_hw *hw) 1435 { 1436 return (hw->flags & SKY2_HW_RAM_BUFFER) ? 8 : 2; 1437 } 1438 1439 /* 1440 * Allocate an skb for receiving. If the MTU is large enough 1441 * make the skb non-linear with a fragment list of pages. 1442 */ 1443 static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2, gfp_t gfp) 1444 { 1445 struct sk_buff *skb; 1446 int i; 1447 1448 skb = __netdev_alloc_skb(sky2->netdev, 1449 sky2->rx_data_size + sky2_rx_pad(sky2->hw), 1450 gfp); 1451 if (!skb) 1452 goto nomem; 1453 1454 if (sky2->hw->flags & SKY2_HW_RAM_BUFFER) { 1455 unsigned char *start; 1456 /* 1457 * Workaround for a bug in FIFO that cause hang 1458 * if the FIFO if the receive buffer is not 64 byte aligned. 1459 * The buffer returned from netdev_alloc_skb is 1460 * aligned except if slab debugging is enabled. 1461 */ 1462 start = PTR_ALIGN(skb->data, 8); 1463 skb_reserve(skb, start - skb->data); 1464 } else 1465 skb_reserve(skb, NET_IP_ALIGN); 1466 1467 for (i = 0; i < sky2->rx_nfrags; i++) { 1468 struct page *page = alloc_page(gfp); 1469 1470 if (!page) 1471 goto free_partial; 1472 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE); 1473 } 1474 1475 return skb; 1476 free_partial: 1477 kfree_skb(skb); 1478 nomem: 1479 return NULL; 1480 } 1481 1482 static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq) 1483 { 1484 sky2_put_idx(sky2->hw, rxq, sky2->rx_put); 1485 } 1486 1487 static int sky2_alloc_rx_skbs(struct sky2_port *sky2) 1488 { 1489 struct sky2_hw *hw = sky2->hw; 1490 unsigned i; 1491 1492 sky2->rx_data_size = sky2_get_rx_data_size(sky2); 1493 1494 /* Fill Rx ring */ 1495 for (i = 0; i < sky2->rx_pending; i++) { 1496 struct rx_ring_info *re = sky2->rx_ring + i; 1497 1498 re->skb = sky2_rx_alloc(sky2, GFP_KERNEL); 1499 if (!re->skb) 1500 return -ENOMEM; 1501 1502 if (sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size)) { 1503 dev_kfree_skb(re->skb); 1504 re->skb = NULL; 1505 return -ENOMEM; 1506 } 1507 } 1508 return 0; 1509 } 1510 1511 /* 1512 * Setup receiver buffer pool. 1513 * Normal case this ends up creating one list element for skb 1514 * in the receive ring. Worst case if using large MTU and each 1515 * allocation falls on a different 64 bit region, that results 1516 * in 6 list elements per ring entry. 1517 * One element is used for checksum enable/disable, and one 1518 * extra to avoid wrap. 1519 */ 1520 static void sky2_rx_start(struct sky2_port *sky2) 1521 { 1522 struct sky2_hw *hw = sky2->hw; 1523 struct rx_ring_info *re; 1524 unsigned rxq = rxqaddr[sky2->port]; 1525 unsigned i, thresh; 1526 1527 sky2->rx_put = sky2->rx_next = 0; 1528 sky2_qset(hw, rxq); 1529 1530 /* On PCI express lowering the watermark gives better performance */ 1531 if (pci_is_pcie(hw->pdev)) 1532 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX); 1533 1534 /* These chips have no ram buffer? 1535 * MAC Rx RAM Read is controlled by hardware */ 1536 if (hw->chip_id == CHIP_ID_YUKON_EC_U && 1537 hw->chip_rev > CHIP_REV_YU_EC_U_A0) 1538 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS); 1539 1540 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1); 1541 1542 if (!(hw->flags & SKY2_HW_NEW_LE)) 1543 rx_set_checksum(sky2); 1544 1545 if (!(hw->flags & SKY2_HW_RSS_BROKEN)) 1546 rx_set_rss(sky2->netdev, sky2->netdev->features); 1547 1548 /* submit Rx ring */ 1549 for (i = 0; i < sky2->rx_pending; i++) { 1550 re = sky2->rx_ring + i; 1551 sky2_rx_submit(sky2, re); 1552 } 1553 1554 /* 1555 * The receiver hangs if it receives frames larger than the 1556 * packet buffer. As a workaround, truncate oversize frames, but 1557 * the register is limited to 9 bits, so if you do frames > 2052 1558 * you better get the MTU right! 1559 */ 1560 thresh = sky2_get_rx_threshold(sky2); 1561 if (thresh > 0x1ff) 1562 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF); 1563 else { 1564 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh); 1565 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON); 1566 } 1567 1568 /* Tell chip about available buffers */ 1569 sky2_rx_update(sky2, rxq); 1570 1571 if (hw->chip_id == CHIP_ID_YUKON_EX || 1572 hw->chip_id == CHIP_ID_YUKON_SUPR) { 1573 /* 1574 * Disable flushing of non ASF packets; 1575 * must be done after initializing the BMUs; 1576 * drivers without ASF support should do this too, otherwise 1577 * it may happen that they cannot run on ASF devices; 1578 * remember that the MAC FIFO isn't reset during initialization. 1579 */ 1580 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_MACSEC_FLUSH_OFF); 1581 } 1582 1583 if (hw->chip_id >= CHIP_ID_YUKON_SUPR) { 1584 /* Enable RX Home Address & Routing Header checksum fix */ 1585 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_FL_CTRL), 1586 RX_IPV6_SA_MOB_ENA | RX_IPV6_DA_MOB_ENA); 1587 1588 /* Enable TX Home Address & Routing Header checksum fix */ 1589 sky2_write32(hw, Q_ADDR(txqaddr[sky2->port], Q_TEST), 1590 TBMU_TEST_HOME_ADD_FIX_EN | TBMU_TEST_ROUTING_ADD_FIX_EN); 1591 } 1592 } 1593 1594 static int sky2_alloc_buffers(struct sky2_port *sky2) 1595 { 1596 struct sky2_hw *hw = sky2->hw; 1597 1598 /* must be power of 2 */ 1599 sky2->tx_le = pci_alloc_consistent(hw->pdev, 1600 sky2->tx_ring_size * 1601 sizeof(struct sky2_tx_le), 1602 &sky2->tx_le_map); 1603 if (!sky2->tx_le) 1604 goto nomem; 1605 1606 sky2->tx_ring = kcalloc(sky2->tx_ring_size, sizeof(struct tx_ring_info), 1607 GFP_KERNEL); 1608 if (!sky2->tx_ring) 1609 goto nomem; 1610 1611 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES, 1612 &sky2->rx_le_map); 1613 if (!sky2->rx_le) 1614 goto nomem; 1615 memset(sky2->rx_le, 0, RX_LE_BYTES); 1616 1617 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info), 1618 GFP_KERNEL); 1619 if (!sky2->rx_ring) 1620 goto nomem; 1621 1622 return sky2_alloc_rx_skbs(sky2); 1623 nomem: 1624 return -ENOMEM; 1625 } 1626 1627 static void sky2_free_buffers(struct sky2_port *sky2) 1628 { 1629 struct sky2_hw *hw = sky2->hw; 1630 1631 sky2_rx_clean(sky2); 1632 1633 if (sky2->rx_le) { 1634 pci_free_consistent(hw->pdev, RX_LE_BYTES, 1635 sky2->rx_le, sky2->rx_le_map); 1636 sky2->rx_le = NULL; 1637 } 1638 if (sky2->tx_le) { 1639 pci_free_consistent(hw->pdev, 1640 sky2->tx_ring_size * sizeof(struct sky2_tx_le), 1641 sky2->tx_le, sky2->tx_le_map); 1642 sky2->tx_le = NULL; 1643 } 1644 kfree(sky2->tx_ring); 1645 kfree(sky2->rx_ring); 1646 1647 sky2->tx_ring = NULL; 1648 sky2->rx_ring = NULL; 1649 } 1650 1651 static void sky2_hw_up(struct sky2_port *sky2) 1652 { 1653 struct sky2_hw *hw = sky2->hw; 1654 unsigned port = sky2->port; 1655 u32 ramsize; 1656 int cap; 1657 struct net_device *otherdev = hw->dev[sky2->port^1]; 1658 1659 tx_init(sky2); 1660 1661 /* 1662 * On dual port PCI-X card, there is an problem where status 1663 * can be received out of order due to split transactions 1664 */ 1665 if (otherdev && netif_running(otherdev) && 1666 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) { 1667 u16 cmd; 1668 1669 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD); 1670 cmd &= ~PCI_X_CMD_MAX_SPLIT; 1671 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd); 1672 } 1673 1674 sky2_mac_init(hw, port); 1675 1676 /* Register is number of 4K blocks on internal RAM buffer. */ 1677 ramsize = sky2_read8(hw, B2_E_0) * 4; 1678 if (ramsize > 0) { 1679 u32 rxspace; 1680 1681 netdev_dbg(sky2->netdev, "ram buffer %dK\n", ramsize); 1682 if (ramsize < 16) 1683 rxspace = ramsize / 2; 1684 else 1685 rxspace = 8 + (2*(ramsize - 16))/3; 1686 1687 sky2_ramset(hw, rxqaddr[port], 0, rxspace); 1688 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace); 1689 1690 /* Make sure SyncQ is disabled */ 1691 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL), 1692 RB_RST_SET); 1693 } 1694 1695 sky2_qset(hw, txqaddr[port]); 1696 1697 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */ 1698 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0) 1699 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF); 1700 1701 /* Set almost empty threshold */ 1702 if (hw->chip_id == CHIP_ID_YUKON_EC_U && 1703 hw->chip_rev == CHIP_REV_YU_EC_U_A0) 1704 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV); 1705 1706 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map, 1707 sky2->tx_ring_size - 1); 1708 1709 sky2_vlan_mode(sky2->netdev, sky2->netdev->features); 1710 netdev_update_features(sky2->netdev); 1711 1712 sky2_rx_start(sky2); 1713 } 1714 1715 /* Setup device IRQ and enable napi to process */ 1716 static int sky2_setup_irq(struct sky2_hw *hw, const char *name) 1717 { 1718 struct pci_dev *pdev = hw->pdev; 1719 int err; 1720 1721 err = request_irq(pdev->irq, sky2_intr, 1722 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED, 1723 name, hw); 1724 if (err) 1725 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq); 1726 else { 1727 hw->flags |= SKY2_HW_IRQ_SETUP; 1728 1729 napi_enable(&hw->napi); 1730 sky2_write32(hw, B0_IMSK, Y2_IS_BASE); 1731 sky2_read32(hw, B0_IMSK); 1732 } 1733 1734 return err; 1735 } 1736 1737 1738 /* Bring up network interface. */ 1739 static int sky2_open(struct net_device *dev) 1740 { 1741 struct sky2_port *sky2 = netdev_priv(dev); 1742 struct sky2_hw *hw = sky2->hw; 1743 unsigned port = sky2->port; 1744 u32 imask; 1745 int err; 1746 1747 netif_carrier_off(dev); 1748 1749 err = sky2_alloc_buffers(sky2); 1750 if (err) 1751 goto err_out; 1752 1753 /* With single port, IRQ is setup when device is brought up */ 1754 if (hw->ports == 1 && (err = sky2_setup_irq(hw, dev->name))) 1755 goto err_out; 1756 1757 sky2_hw_up(sky2); 1758 1759 if (hw->chip_id == CHIP_ID_YUKON_OPT || 1760 hw->chip_id == CHIP_ID_YUKON_PRM || 1761 hw->chip_id == CHIP_ID_YUKON_OP_2) 1762 imask |= Y2_IS_PHY_QLNK; /* enable PHY Quick Link */ 1763 1764 /* Enable interrupts from phy/mac for port */ 1765 imask = sky2_read32(hw, B0_IMSK); 1766 imask |= portirq_msk[port]; 1767 sky2_write32(hw, B0_IMSK, imask); 1768 sky2_read32(hw, B0_IMSK); 1769 1770 netif_info(sky2, ifup, dev, "enabling interface\n"); 1771 1772 return 0; 1773 1774 err_out: 1775 sky2_free_buffers(sky2); 1776 return err; 1777 } 1778 1779 /* Modular subtraction in ring */ 1780 static inline int tx_inuse(const struct sky2_port *sky2) 1781 { 1782 return (sky2->tx_prod - sky2->tx_cons) & (sky2->tx_ring_size - 1); 1783 } 1784 1785 /* Number of list elements available for next tx */ 1786 static inline int tx_avail(const struct sky2_port *sky2) 1787 { 1788 return sky2->tx_pending - tx_inuse(sky2); 1789 } 1790 1791 /* Estimate of number of transmit list elements required */ 1792 static unsigned tx_le_req(const struct sk_buff *skb) 1793 { 1794 unsigned count; 1795 1796 count = (skb_shinfo(skb)->nr_frags + 1) 1797 * (sizeof(dma_addr_t) / sizeof(u32)); 1798 1799 if (skb_is_gso(skb)) 1800 ++count; 1801 else if (sizeof(dma_addr_t) == sizeof(u32)) 1802 ++count; /* possible vlan */ 1803 1804 if (skb->ip_summed == CHECKSUM_PARTIAL) 1805 ++count; 1806 1807 return count; 1808 } 1809 1810 static void sky2_tx_unmap(struct pci_dev *pdev, struct tx_ring_info *re) 1811 { 1812 if (re->flags & TX_MAP_SINGLE) 1813 pci_unmap_single(pdev, dma_unmap_addr(re, mapaddr), 1814 dma_unmap_len(re, maplen), 1815 PCI_DMA_TODEVICE); 1816 else if (re->flags & TX_MAP_PAGE) 1817 pci_unmap_page(pdev, dma_unmap_addr(re, mapaddr), 1818 dma_unmap_len(re, maplen), 1819 PCI_DMA_TODEVICE); 1820 re->flags = 0; 1821 } 1822 1823 /* 1824 * Put one packet in ring for transmit. 1825 * A single packet can generate multiple list elements, and 1826 * the number of ring elements will probably be less than the number 1827 * of list elements used. 1828 */ 1829 static netdev_tx_t sky2_xmit_frame(struct sk_buff *skb, 1830 struct net_device *dev) 1831 { 1832 struct sky2_port *sky2 = netdev_priv(dev); 1833 struct sky2_hw *hw = sky2->hw; 1834 struct sky2_tx_le *le = NULL; 1835 struct tx_ring_info *re; 1836 unsigned i, len; 1837 dma_addr_t mapping; 1838 u32 upper; 1839 u16 slot; 1840 u16 mss; 1841 u8 ctrl; 1842 1843 if (unlikely(tx_avail(sky2) < tx_le_req(skb))) 1844 return NETDEV_TX_BUSY; 1845 1846 len = skb_headlen(skb); 1847 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE); 1848 1849 if (pci_dma_mapping_error(hw->pdev, mapping)) 1850 goto mapping_error; 1851 1852 slot = sky2->tx_prod; 1853 netif_printk(sky2, tx_queued, KERN_DEBUG, dev, 1854 "tx queued, slot %u, len %d\n", slot, skb->len); 1855 1856 /* Send high bits if needed */ 1857 upper = upper_32_bits(mapping); 1858 if (upper != sky2->tx_last_upper) { 1859 le = get_tx_le(sky2, &slot); 1860 le->addr = cpu_to_le32(upper); 1861 sky2->tx_last_upper = upper; 1862 le->opcode = OP_ADDR64 | HW_OWNER; 1863 } 1864 1865 /* Check for TCP Segmentation Offload */ 1866 mss = skb_shinfo(skb)->gso_size; 1867 if (mss != 0) { 1868 1869 if (!(hw->flags & SKY2_HW_NEW_LE)) 1870 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb); 1871 1872 if (mss != sky2->tx_last_mss) { 1873 le = get_tx_le(sky2, &slot); 1874 le->addr = cpu_to_le32(mss); 1875 1876 if (hw->flags & SKY2_HW_NEW_LE) 1877 le->opcode = OP_MSS | HW_OWNER; 1878 else 1879 le->opcode = OP_LRGLEN | HW_OWNER; 1880 sky2->tx_last_mss = mss; 1881 } 1882 } 1883 1884 ctrl = 0; 1885 1886 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */ 1887 if (vlan_tx_tag_present(skb)) { 1888 if (!le) { 1889 le = get_tx_le(sky2, &slot); 1890 le->addr = 0; 1891 le->opcode = OP_VLAN|HW_OWNER; 1892 } else 1893 le->opcode |= OP_VLAN; 1894 le->length = cpu_to_be16(vlan_tx_tag_get(skb)); 1895 ctrl |= INS_VLAN; 1896 } 1897 1898 /* Handle TCP checksum offload */ 1899 if (skb->ip_summed == CHECKSUM_PARTIAL) { 1900 /* On Yukon EX (some versions) encoding change. */ 1901 if (hw->flags & SKY2_HW_AUTO_TX_SUM) 1902 ctrl |= CALSUM; /* auto checksum */ 1903 else { 1904 const unsigned offset = skb_transport_offset(skb); 1905 u32 tcpsum; 1906 1907 tcpsum = offset << 16; /* sum start */ 1908 tcpsum |= offset + skb->csum_offset; /* sum write */ 1909 1910 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM; 1911 if (ip_hdr(skb)->protocol == IPPROTO_UDP) 1912 ctrl |= UDPTCP; 1913 1914 if (tcpsum != sky2->tx_tcpsum) { 1915 sky2->tx_tcpsum = tcpsum; 1916 1917 le = get_tx_le(sky2, &slot); 1918 le->addr = cpu_to_le32(tcpsum); 1919 le->length = 0; /* initial checksum value */ 1920 le->ctrl = 1; /* one packet */ 1921 le->opcode = OP_TCPLISW | HW_OWNER; 1922 } 1923 } 1924 } 1925 1926 re = sky2->tx_ring + slot; 1927 re->flags = TX_MAP_SINGLE; 1928 dma_unmap_addr_set(re, mapaddr, mapping); 1929 dma_unmap_len_set(re, maplen, len); 1930 1931 le = get_tx_le(sky2, &slot); 1932 le->addr = cpu_to_le32(lower_32_bits(mapping)); 1933 le->length = cpu_to_le16(len); 1934 le->ctrl = ctrl; 1935 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER); 1936 1937 1938 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1939 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1940 1941 mapping = skb_frag_dma_map(&hw->pdev->dev, frag, 0, 1942 skb_frag_size(frag), DMA_TO_DEVICE); 1943 1944 if (dma_mapping_error(&hw->pdev->dev, mapping)) 1945 goto mapping_unwind; 1946 1947 upper = upper_32_bits(mapping); 1948 if (upper != sky2->tx_last_upper) { 1949 le = get_tx_le(sky2, &slot); 1950 le->addr = cpu_to_le32(upper); 1951 sky2->tx_last_upper = upper; 1952 le->opcode = OP_ADDR64 | HW_OWNER; 1953 } 1954 1955 re = sky2->tx_ring + slot; 1956 re->flags = TX_MAP_PAGE; 1957 dma_unmap_addr_set(re, mapaddr, mapping); 1958 dma_unmap_len_set(re, maplen, skb_frag_size(frag)); 1959 1960 le = get_tx_le(sky2, &slot); 1961 le->addr = cpu_to_le32(lower_32_bits(mapping)); 1962 le->length = cpu_to_le16(skb_frag_size(frag)); 1963 le->ctrl = ctrl; 1964 le->opcode = OP_BUFFER | HW_OWNER; 1965 } 1966 1967 re->skb = skb; 1968 le->ctrl |= EOP; 1969 1970 sky2->tx_prod = slot; 1971 1972 if (tx_avail(sky2) <= MAX_SKB_TX_LE) 1973 netif_stop_queue(dev); 1974 1975 netdev_sent_queue(dev, skb->len); 1976 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod); 1977 1978 return NETDEV_TX_OK; 1979 1980 mapping_unwind: 1981 for (i = sky2->tx_prod; i != slot; i = RING_NEXT(i, sky2->tx_ring_size)) { 1982 re = sky2->tx_ring + i; 1983 1984 sky2_tx_unmap(hw->pdev, re); 1985 } 1986 1987 mapping_error: 1988 if (net_ratelimit()) 1989 dev_warn(&hw->pdev->dev, "%s: tx mapping error\n", dev->name); 1990 dev_kfree_skb(skb); 1991 return NETDEV_TX_OK; 1992 } 1993 1994 /* 1995 * Free ring elements from starting at tx_cons until "done" 1996 * 1997 * NB: 1998 * 1. The hardware will tell us about partial completion of multi-part 1999 * buffers so make sure not to free skb to early. 2000 * 2. This may run in parallel start_xmit because the it only 2001 * looks at the tail of the queue of FIFO (tx_cons), not 2002 * the head (tx_prod) 2003 */ 2004 static void sky2_tx_complete(struct sky2_port *sky2, u16 done) 2005 { 2006 struct net_device *dev = sky2->netdev; 2007 u16 idx; 2008 unsigned int bytes_compl = 0, pkts_compl = 0; 2009 2010 BUG_ON(done >= sky2->tx_ring_size); 2011 2012 for (idx = sky2->tx_cons; idx != done; 2013 idx = RING_NEXT(idx, sky2->tx_ring_size)) { 2014 struct tx_ring_info *re = sky2->tx_ring + idx; 2015 struct sk_buff *skb = re->skb; 2016 2017 sky2_tx_unmap(sky2->hw->pdev, re); 2018 2019 if (skb) { 2020 netif_printk(sky2, tx_done, KERN_DEBUG, dev, 2021 "tx done %u\n", idx); 2022 2023 pkts_compl++; 2024 bytes_compl += skb->len; 2025 2026 re->skb = NULL; 2027 dev_kfree_skb_any(skb); 2028 2029 sky2->tx_next = RING_NEXT(idx, sky2->tx_ring_size); 2030 } 2031 } 2032 2033 sky2->tx_cons = idx; 2034 smp_mb(); 2035 2036 netdev_completed_queue(dev, pkts_compl, bytes_compl); 2037 2038 u64_stats_update_begin(&sky2->tx_stats.syncp); 2039 sky2->tx_stats.packets += pkts_compl; 2040 sky2->tx_stats.bytes += bytes_compl; 2041 u64_stats_update_end(&sky2->tx_stats.syncp); 2042 } 2043 2044 static void sky2_tx_reset(struct sky2_hw *hw, unsigned port) 2045 { 2046 /* Disable Force Sync bit and Enable Alloc bit */ 2047 sky2_write8(hw, SK_REG(port, TXA_CTRL), 2048 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC); 2049 2050 /* Stop Interval Timer and Limit Counter of Tx Arbiter */ 2051 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L); 2052 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L); 2053 2054 /* Reset the PCI FIFO of the async Tx queue */ 2055 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), 2056 BMU_RST_SET | BMU_FIFO_RST); 2057 2058 /* Reset the Tx prefetch units */ 2059 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL), 2060 PREF_UNIT_RST_SET); 2061 2062 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET); 2063 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET); 2064 2065 sky2_read32(hw, B0_CTST); 2066 } 2067 2068 static void sky2_hw_down(struct sky2_port *sky2) 2069 { 2070 struct sky2_hw *hw = sky2->hw; 2071 unsigned port = sky2->port; 2072 u16 ctrl; 2073 2074 /* Force flow control off */ 2075 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); 2076 2077 /* Stop transmitter */ 2078 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP); 2079 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR)); 2080 2081 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), 2082 RB_RST_SET | RB_DIS_OP_MD); 2083 2084 ctrl = gma_read16(hw, port, GM_GP_CTRL); 2085 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA); 2086 gma_write16(hw, port, GM_GP_CTRL, ctrl); 2087 2088 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET); 2089 2090 /* Workaround shared GMAC reset */ 2091 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && 2092 port == 0 && hw->dev[1] && netif_running(hw->dev[1]))) 2093 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET); 2094 2095 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET); 2096 2097 /* Force any delayed status interrupt and NAPI */ 2098 sky2_write32(hw, STAT_LEV_TIMER_CNT, 0); 2099 sky2_write32(hw, STAT_TX_TIMER_CNT, 0); 2100 sky2_write32(hw, STAT_ISR_TIMER_CNT, 0); 2101 sky2_read8(hw, STAT_ISR_TIMER_CTRL); 2102 2103 sky2_rx_stop(sky2); 2104 2105 spin_lock_bh(&sky2->phy_lock); 2106 sky2_phy_power_down(hw, port); 2107 spin_unlock_bh(&sky2->phy_lock); 2108 2109 sky2_tx_reset(hw, port); 2110 2111 /* Free any pending frames stuck in HW queue */ 2112 sky2_tx_complete(sky2, sky2->tx_prod); 2113 } 2114 2115 /* Network shutdown */ 2116 static int sky2_close(struct net_device *dev) 2117 { 2118 struct sky2_port *sky2 = netdev_priv(dev); 2119 struct sky2_hw *hw = sky2->hw; 2120 2121 /* Never really got started! */ 2122 if (!sky2->tx_le) 2123 return 0; 2124 2125 netif_info(sky2, ifdown, dev, "disabling interface\n"); 2126 2127 if (hw->ports == 1) { 2128 sky2_write32(hw, B0_IMSK, 0); 2129 sky2_read32(hw, B0_IMSK); 2130 2131 napi_disable(&hw->napi); 2132 free_irq(hw->pdev->irq, hw); 2133 hw->flags &= ~SKY2_HW_IRQ_SETUP; 2134 } else { 2135 u32 imask; 2136 2137 /* Disable port IRQ */ 2138 imask = sky2_read32(hw, B0_IMSK); 2139 imask &= ~portirq_msk[sky2->port]; 2140 sky2_write32(hw, B0_IMSK, imask); 2141 sky2_read32(hw, B0_IMSK); 2142 2143 synchronize_irq(hw->pdev->irq); 2144 napi_synchronize(&hw->napi); 2145 } 2146 2147 sky2_hw_down(sky2); 2148 2149 sky2_free_buffers(sky2); 2150 2151 return 0; 2152 } 2153 2154 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux) 2155 { 2156 if (hw->flags & SKY2_HW_FIBRE_PHY) 2157 return SPEED_1000; 2158 2159 if (!(hw->flags & SKY2_HW_GIGABIT)) { 2160 if (aux & PHY_M_PS_SPEED_100) 2161 return SPEED_100; 2162 else 2163 return SPEED_10; 2164 } 2165 2166 switch (aux & PHY_M_PS_SPEED_MSK) { 2167 case PHY_M_PS_SPEED_1000: 2168 return SPEED_1000; 2169 case PHY_M_PS_SPEED_100: 2170 return SPEED_100; 2171 default: 2172 return SPEED_10; 2173 } 2174 } 2175 2176 static void sky2_link_up(struct sky2_port *sky2) 2177 { 2178 struct sky2_hw *hw = sky2->hw; 2179 unsigned port = sky2->port; 2180 static const char *fc_name[] = { 2181 [FC_NONE] = "none", 2182 [FC_TX] = "tx", 2183 [FC_RX] = "rx", 2184 [FC_BOTH] = "both", 2185 }; 2186 2187 sky2_set_ipg(sky2); 2188 2189 sky2_enable_rx_tx(sky2); 2190 2191 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK); 2192 2193 netif_carrier_on(sky2->netdev); 2194 2195 mod_timer(&hw->watchdog_timer, jiffies + 1); 2196 2197 /* Turn on link LED */ 2198 sky2_write8(hw, SK_REG(port, LNK_LED_REG), 2199 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF); 2200 2201 netif_info(sky2, link, sky2->netdev, 2202 "Link is up at %d Mbps, %s duplex, flow control %s\n", 2203 sky2->speed, 2204 sky2->duplex == DUPLEX_FULL ? "full" : "half", 2205 fc_name[sky2->flow_status]); 2206 } 2207 2208 static void sky2_link_down(struct sky2_port *sky2) 2209 { 2210 struct sky2_hw *hw = sky2->hw; 2211 unsigned port = sky2->port; 2212 u16 reg; 2213 2214 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0); 2215 2216 reg = gma_read16(hw, port, GM_GP_CTRL); 2217 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); 2218 gma_write16(hw, port, GM_GP_CTRL, reg); 2219 2220 netif_carrier_off(sky2->netdev); 2221 2222 /* Turn off link LED */ 2223 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF); 2224 2225 netif_info(sky2, link, sky2->netdev, "Link is down\n"); 2226 2227 sky2_phy_init(hw, port); 2228 } 2229 2230 static enum flow_control sky2_flow(int rx, int tx) 2231 { 2232 if (rx) 2233 return tx ? FC_BOTH : FC_RX; 2234 else 2235 return tx ? FC_TX : FC_NONE; 2236 } 2237 2238 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux) 2239 { 2240 struct sky2_hw *hw = sky2->hw; 2241 unsigned port = sky2->port; 2242 u16 advert, lpa; 2243 2244 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV); 2245 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP); 2246 if (lpa & PHY_M_AN_RF) { 2247 netdev_err(sky2->netdev, "remote fault\n"); 2248 return -1; 2249 } 2250 2251 if (!(aux & PHY_M_PS_SPDUP_RES)) { 2252 netdev_err(sky2->netdev, "speed/duplex mismatch\n"); 2253 return -1; 2254 } 2255 2256 sky2->speed = sky2_phy_speed(hw, aux); 2257 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF; 2258 2259 /* Since the pause result bits seem to in different positions on 2260 * different chips. look at registers. 2261 */ 2262 if (hw->flags & SKY2_HW_FIBRE_PHY) { 2263 /* Shift for bits in fiber PHY */ 2264 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM); 2265 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM); 2266 2267 if (advert & ADVERTISE_1000XPAUSE) 2268 advert |= ADVERTISE_PAUSE_CAP; 2269 if (advert & ADVERTISE_1000XPSE_ASYM) 2270 advert |= ADVERTISE_PAUSE_ASYM; 2271 if (lpa & LPA_1000XPAUSE) 2272 lpa |= LPA_PAUSE_CAP; 2273 if (lpa & LPA_1000XPAUSE_ASYM) 2274 lpa |= LPA_PAUSE_ASYM; 2275 } 2276 2277 sky2->flow_status = FC_NONE; 2278 if (advert & ADVERTISE_PAUSE_CAP) { 2279 if (lpa & LPA_PAUSE_CAP) 2280 sky2->flow_status = FC_BOTH; 2281 else if (advert & ADVERTISE_PAUSE_ASYM) 2282 sky2->flow_status = FC_RX; 2283 } else if (advert & ADVERTISE_PAUSE_ASYM) { 2284 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM)) 2285 sky2->flow_status = FC_TX; 2286 } 2287 2288 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000 && 2289 !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX)) 2290 sky2->flow_status = FC_NONE; 2291 2292 if (sky2->flow_status & FC_TX) 2293 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON); 2294 else 2295 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); 2296 2297 return 0; 2298 } 2299 2300 /* Interrupt from PHY */ 2301 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port) 2302 { 2303 struct net_device *dev = hw->dev[port]; 2304 struct sky2_port *sky2 = netdev_priv(dev); 2305 u16 istatus, phystat; 2306 2307 if (!netif_running(dev)) 2308 return; 2309 2310 spin_lock(&sky2->phy_lock); 2311 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT); 2312 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT); 2313 2314 netif_info(sky2, intr, sky2->netdev, "phy interrupt status 0x%x 0x%x\n", 2315 istatus, phystat); 2316 2317 if (istatus & PHY_M_IS_AN_COMPL) { 2318 if (sky2_autoneg_done(sky2, phystat) == 0 && 2319 !netif_carrier_ok(dev)) 2320 sky2_link_up(sky2); 2321 goto out; 2322 } 2323 2324 if (istatus & PHY_M_IS_LSP_CHANGE) 2325 sky2->speed = sky2_phy_speed(hw, phystat); 2326 2327 if (istatus & PHY_M_IS_DUP_CHANGE) 2328 sky2->duplex = 2329 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF; 2330 2331 if (istatus & PHY_M_IS_LST_CHANGE) { 2332 if (phystat & PHY_M_PS_LINK_UP) 2333 sky2_link_up(sky2); 2334 else 2335 sky2_link_down(sky2); 2336 } 2337 out: 2338 spin_unlock(&sky2->phy_lock); 2339 } 2340 2341 /* Special quick link interrupt (Yukon-2 Optima only) */ 2342 static void sky2_qlink_intr(struct sky2_hw *hw) 2343 { 2344 struct sky2_port *sky2 = netdev_priv(hw->dev[0]); 2345 u32 imask; 2346 u16 phy; 2347 2348 /* disable irq */ 2349 imask = sky2_read32(hw, B0_IMSK); 2350 imask &= ~Y2_IS_PHY_QLNK; 2351 sky2_write32(hw, B0_IMSK, imask); 2352 2353 /* reset PHY Link Detect */ 2354 phy = sky2_pci_read16(hw, PSM_CONFIG_REG4); 2355 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); 2356 sky2_pci_write16(hw, PSM_CONFIG_REG4, phy | 1); 2357 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 2358 2359 sky2_link_up(sky2); 2360 } 2361 2362 /* Transmit timeout is only called if we are running, carrier is up 2363 * and tx queue is full (stopped). 2364 */ 2365 static void sky2_tx_timeout(struct net_device *dev) 2366 { 2367 struct sky2_port *sky2 = netdev_priv(dev); 2368 struct sky2_hw *hw = sky2->hw; 2369 2370 netif_err(sky2, timer, dev, "tx timeout\n"); 2371 2372 netdev_printk(KERN_DEBUG, dev, "transmit ring %u .. %u report=%u done=%u\n", 2373 sky2->tx_cons, sky2->tx_prod, 2374 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX), 2375 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE))); 2376 2377 /* can't restart safely under softirq */ 2378 schedule_work(&hw->restart_work); 2379 } 2380 2381 static int sky2_change_mtu(struct net_device *dev, int new_mtu) 2382 { 2383 struct sky2_port *sky2 = netdev_priv(dev); 2384 struct sky2_hw *hw = sky2->hw; 2385 unsigned port = sky2->port; 2386 int err; 2387 u16 ctl, mode; 2388 u32 imask; 2389 2390 /* MTU size outside the spec */ 2391 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU) 2392 return -EINVAL; 2393 2394 /* MTU > 1500 on yukon FE and FE+ not allowed */ 2395 if (new_mtu > ETH_DATA_LEN && 2396 (hw->chip_id == CHIP_ID_YUKON_FE || 2397 hw->chip_id == CHIP_ID_YUKON_FE_P)) 2398 return -EINVAL; 2399 2400 if (!netif_running(dev)) { 2401 dev->mtu = new_mtu; 2402 netdev_update_features(dev); 2403 return 0; 2404 } 2405 2406 imask = sky2_read32(hw, B0_IMSK); 2407 sky2_write32(hw, B0_IMSK, 0); 2408 2409 dev->trans_start = jiffies; /* prevent tx timeout */ 2410 napi_disable(&hw->napi); 2411 netif_tx_disable(dev); 2412 2413 synchronize_irq(hw->pdev->irq); 2414 2415 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) 2416 sky2_set_tx_stfwd(hw, port); 2417 2418 ctl = gma_read16(hw, port, GM_GP_CTRL); 2419 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA); 2420 sky2_rx_stop(sky2); 2421 sky2_rx_clean(sky2); 2422 2423 dev->mtu = new_mtu; 2424 netdev_update_features(dev); 2425 2426 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) | GM_SMOD_VLAN_ENA; 2427 if (sky2->speed > SPEED_100) 2428 mode |= IPG_DATA_VAL(IPG_DATA_DEF_1000); 2429 else 2430 mode |= IPG_DATA_VAL(IPG_DATA_DEF_10_100); 2431 2432 if (dev->mtu > ETH_DATA_LEN) 2433 mode |= GM_SMOD_JUMBO_ENA; 2434 2435 gma_write16(hw, port, GM_SERIAL_MODE, mode); 2436 2437 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD); 2438 2439 err = sky2_alloc_rx_skbs(sky2); 2440 if (!err) 2441 sky2_rx_start(sky2); 2442 else 2443 sky2_rx_clean(sky2); 2444 sky2_write32(hw, B0_IMSK, imask); 2445 2446 sky2_read32(hw, B0_Y2_SP_LISR); 2447 napi_enable(&hw->napi); 2448 2449 if (err) 2450 dev_close(dev); 2451 else { 2452 gma_write16(hw, port, GM_GP_CTRL, ctl); 2453 2454 netif_wake_queue(dev); 2455 } 2456 2457 return err; 2458 } 2459 2460 /* For small just reuse existing skb for next receive */ 2461 static struct sk_buff *receive_copy(struct sky2_port *sky2, 2462 const struct rx_ring_info *re, 2463 unsigned length) 2464 { 2465 struct sk_buff *skb; 2466 2467 skb = netdev_alloc_skb_ip_align(sky2->netdev, length); 2468 if (likely(skb)) { 2469 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr, 2470 length, PCI_DMA_FROMDEVICE); 2471 skb_copy_from_linear_data(re->skb, skb->data, length); 2472 skb->ip_summed = re->skb->ip_summed; 2473 skb->csum = re->skb->csum; 2474 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr, 2475 length, PCI_DMA_FROMDEVICE); 2476 re->skb->ip_summed = CHECKSUM_NONE; 2477 skb_put(skb, length); 2478 } 2479 return skb; 2480 } 2481 2482 /* Adjust length of skb with fragments to match received data */ 2483 static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space, 2484 unsigned int length) 2485 { 2486 int i, num_frags; 2487 unsigned int size; 2488 2489 /* put header into skb */ 2490 size = min(length, hdr_space); 2491 skb->tail += size; 2492 skb->len += size; 2493 length -= size; 2494 2495 num_frags = skb_shinfo(skb)->nr_frags; 2496 for (i = 0; i < num_frags; i++) { 2497 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 2498 2499 if (length == 0) { 2500 /* don't need this page */ 2501 __skb_frag_unref(frag); 2502 --skb_shinfo(skb)->nr_frags; 2503 } else { 2504 size = min(length, (unsigned) PAGE_SIZE); 2505 2506 skb_frag_size_set(frag, size); 2507 skb->data_len += size; 2508 skb->truesize += PAGE_SIZE; 2509 skb->len += size; 2510 length -= size; 2511 } 2512 } 2513 } 2514 2515 /* Normal packet - take skb from ring element and put in a new one */ 2516 static struct sk_buff *receive_new(struct sky2_port *sky2, 2517 struct rx_ring_info *re, 2518 unsigned int length) 2519 { 2520 struct sk_buff *skb; 2521 struct rx_ring_info nre; 2522 unsigned hdr_space = sky2->rx_data_size; 2523 2524 nre.skb = sky2_rx_alloc(sky2, GFP_ATOMIC); 2525 if (unlikely(!nre.skb)) 2526 goto nobuf; 2527 2528 if (sky2_rx_map_skb(sky2->hw->pdev, &nre, hdr_space)) 2529 goto nomap; 2530 2531 skb = re->skb; 2532 sky2_rx_unmap_skb(sky2->hw->pdev, re); 2533 prefetch(skb->data); 2534 *re = nre; 2535 2536 if (skb_shinfo(skb)->nr_frags) 2537 skb_put_frags(skb, hdr_space, length); 2538 else 2539 skb_put(skb, length); 2540 return skb; 2541 2542 nomap: 2543 dev_kfree_skb(nre.skb); 2544 nobuf: 2545 return NULL; 2546 } 2547 2548 /* 2549 * Receive one packet. 2550 * For larger packets, get new buffer. 2551 */ 2552 static struct sk_buff *sky2_receive(struct net_device *dev, 2553 u16 length, u32 status) 2554 { 2555 struct sky2_port *sky2 = netdev_priv(dev); 2556 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next; 2557 struct sk_buff *skb = NULL; 2558 u16 count = (status & GMR_FS_LEN) >> 16; 2559 2560 if (status & GMR_FS_VLAN) 2561 count -= VLAN_HLEN; /* Account for vlan tag */ 2562 2563 netif_printk(sky2, rx_status, KERN_DEBUG, dev, 2564 "rx slot %u status 0x%x len %d\n", 2565 sky2->rx_next, status, length); 2566 2567 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending; 2568 prefetch(sky2->rx_ring + sky2->rx_next); 2569 2570 /* This chip has hardware problems that generates bogus status. 2571 * So do only marginal checking and expect higher level protocols 2572 * to handle crap frames. 2573 */ 2574 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P && 2575 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 && 2576 length != count) 2577 goto okay; 2578 2579 if (status & GMR_FS_ANY_ERR) 2580 goto error; 2581 2582 if (!(status & GMR_FS_RX_OK)) 2583 goto resubmit; 2584 2585 /* if length reported by DMA does not match PHY, packet was truncated */ 2586 if (length != count) 2587 goto error; 2588 2589 okay: 2590 if (length < copybreak) 2591 skb = receive_copy(sky2, re, length); 2592 else 2593 skb = receive_new(sky2, re, length); 2594 2595 dev->stats.rx_dropped += (skb == NULL); 2596 2597 resubmit: 2598 sky2_rx_submit(sky2, re); 2599 2600 return skb; 2601 2602 error: 2603 ++dev->stats.rx_errors; 2604 2605 if (net_ratelimit()) 2606 netif_info(sky2, rx_err, dev, 2607 "rx error, status 0x%x length %d\n", status, length); 2608 2609 goto resubmit; 2610 } 2611 2612 /* Transmit complete */ 2613 static inline void sky2_tx_done(struct net_device *dev, u16 last) 2614 { 2615 struct sky2_port *sky2 = netdev_priv(dev); 2616 2617 if (netif_running(dev)) { 2618 sky2_tx_complete(sky2, last); 2619 2620 /* Wake unless it's detached, and called e.g. from sky2_close() */ 2621 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4) 2622 netif_wake_queue(dev); 2623 } 2624 } 2625 2626 static inline void sky2_skb_rx(const struct sky2_port *sky2, 2627 u32 status, struct sk_buff *skb) 2628 { 2629 if (status & GMR_FS_VLAN) 2630 __vlan_hwaccel_put_tag(skb, be16_to_cpu(sky2->rx_tag)); 2631 2632 if (skb->ip_summed == CHECKSUM_NONE) 2633 netif_receive_skb(skb); 2634 else 2635 napi_gro_receive(&sky2->hw->napi, skb); 2636 } 2637 2638 static inline void sky2_rx_done(struct sky2_hw *hw, unsigned port, 2639 unsigned packets, unsigned bytes) 2640 { 2641 struct net_device *dev = hw->dev[port]; 2642 struct sky2_port *sky2 = netdev_priv(dev); 2643 2644 if (packets == 0) 2645 return; 2646 2647 u64_stats_update_begin(&sky2->rx_stats.syncp); 2648 sky2->rx_stats.packets += packets; 2649 sky2->rx_stats.bytes += bytes; 2650 u64_stats_update_end(&sky2->rx_stats.syncp); 2651 2652 dev->last_rx = jiffies; 2653 sky2_rx_update(netdev_priv(dev), rxqaddr[port]); 2654 } 2655 2656 static void sky2_rx_checksum(struct sky2_port *sky2, u32 status) 2657 { 2658 /* If this happens then driver assuming wrong format for chip type */ 2659 BUG_ON(sky2->hw->flags & SKY2_HW_NEW_LE); 2660 2661 /* Both checksum counters are programmed to start at 2662 * the same offset, so unless there is a problem they 2663 * should match. This failure is an early indication that 2664 * hardware receive checksumming won't work. 2665 */ 2666 if (likely((u16)(status >> 16) == (u16)status)) { 2667 struct sk_buff *skb = sky2->rx_ring[sky2->rx_next].skb; 2668 skb->ip_summed = CHECKSUM_COMPLETE; 2669 skb->csum = le16_to_cpu(status); 2670 } else { 2671 dev_notice(&sky2->hw->pdev->dev, 2672 "%s: receive checksum problem (status = %#x)\n", 2673 sky2->netdev->name, status); 2674 2675 /* Disable checksum offload 2676 * It will be reenabled on next ndo_set_features, but if it's 2677 * really broken, will get disabled again 2678 */ 2679 sky2->netdev->features &= ~NETIF_F_RXCSUM; 2680 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR), 2681 BMU_DIS_RX_CHKSUM); 2682 } 2683 } 2684 2685 static void sky2_rx_hash(struct sky2_port *sky2, u32 status) 2686 { 2687 struct sk_buff *skb; 2688 2689 skb = sky2->rx_ring[sky2->rx_next].skb; 2690 skb->rxhash = le32_to_cpu(status); 2691 } 2692 2693 /* Process status response ring */ 2694 static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx) 2695 { 2696 int work_done = 0; 2697 unsigned int total_bytes[2] = { 0 }; 2698 unsigned int total_packets[2] = { 0 }; 2699 2700 rmb(); 2701 do { 2702 struct sky2_port *sky2; 2703 struct sky2_status_le *le = hw->st_le + hw->st_idx; 2704 unsigned port; 2705 struct net_device *dev; 2706 struct sk_buff *skb; 2707 u32 status; 2708 u16 length; 2709 u8 opcode = le->opcode; 2710 2711 if (!(opcode & HW_OWNER)) 2712 break; 2713 2714 hw->st_idx = RING_NEXT(hw->st_idx, hw->st_size); 2715 2716 port = le->css & CSS_LINK_BIT; 2717 dev = hw->dev[port]; 2718 sky2 = netdev_priv(dev); 2719 length = le16_to_cpu(le->length); 2720 status = le32_to_cpu(le->status); 2721 2722 le->opcode = 0; 2723 switch (opcode & ~HW_OWNER) { 2724 case OP_RXSTAT: 2725 total_packets[port]++; 2726 total_bytes[port] += length; 2727 2728 skb = sky2_receive(dev, length, status); 2729 if (!skb) 2730 break; 2731 2732 /* This chip reports checksum status differently */ 2733 if (hw->flags & SKY2_HW_NEW_LE) { 2734 if ((dev->features & NETIF_F_RXCSUM) && 2735 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) && 2736 (le->css & CSS_TCPUDPCSOK)) 2737 skb->ip_summed = CHECKSUM_UNNECESSARY; 2738 else 2739 skb->ip_summed = CHECKSUM_NONE; 2740 } 2741 2742 skb->protocol = eth_type_trans(skb, dev); 2743 2744 sky2_skb_rx(sky2, status, skb); 2745 2746 /* Stop after net poll weight */ 2747 if (++work_done >= to_do) 2748 goto exit_loop; 2749 break; 2750 2751 case OP_RXVLAN: 2752 sky2->rx_tag = length; 2753 break; 2754 2755 case OP_RXCHKSVLAN: 2756 sky2->rx_tag = length; 2757 /* fall through */ 2758 case OP_RXCHKS: 2759 if (likely(dev->features & NETIF_F_RXCSUM)) 2760 sky2_rx_checksum(sky2, status); 2761 break; 2762 2763 case OP_RSS_HASH: 2764 sky2_rx_hash(sky2, status); 2765 break; 2766 2767 case OP_TXINDEXLE: 2768 /* TX index reports status for both ports */ 2769 sky2_tx_done(hw->dev[0], status & 0xfff); 2770 if (hw->dev[1]) 2771 sky2_tx_done(hw->dev[1], 2772 ((status >> 24) & 0xff) 2773 | (u16)(length & 0xf) << 8); 2774 break; 2775 2776 default: 2777 if (net_ratelimit()) 2778 pr_warning("unknown status opcode 0x%x\n", opcode); 2779 } 2780 } while (hw->st_idx != idx); 2781 2782 /* Fully processed status ring so clear irq */ 2783 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ); 2784 2785 exit_loop: 2786 sky2_rx_done(hw, 0, total_packets[0], total_bytes[0]); 2787 sky2_rx_done(hw, 1, total_packets[1], total_bytes[1]); 2788 2789 return work_done; 2790 } 2791 2792 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status) 2793 { 2794 struct net_device *dev = hw->dev[port]; 2795 2796 if (net_ratelimit()) 2797 netdev_info(dev, "hw error interrupt status 0x%x\n", status); 2798 2799 if (status & Y2_IS_PAR_RD1) { 2800 if (net_ratelimit()) 2801 netdev_err(dev, "ram data read parity error\n"); 2802 /* Clear IRQ */ 2803 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR); 2804 } 2805 2806 if (status & Y2_IS_PAR_WR1) { 2807 if (net_ratelimit()) 2808 netdev_err(dev, "ram data write parity error\n"); 2809 2810 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR); 2811 } 2812 2813 if (status & Y2_IS_PAR_MAC1) { 2814 if (net_ratelimit()) 2815 netdev_err(dev, "MAC parity error\n"); 2816 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE); 2817 } 2818 2819 if (status & Y2_IS_PAR_RX1) { 2820 if (net_ratelimit()) 2821 netdev_err(dev, "RX parity error\n"); 2822 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR); 2823 } 2824 2825 if (status & Y2_IS_TCP_TXA1) { 2826 if (net_ratelimit()) 2827 netdev_err(dev, "TCP segmentation error\n"); 2828 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP); 2829 } 2830 } 2831 2832 static void sky2_hw_intr(struct sky2_hw *hw) 2833 { 2834 struct pci_dev *pdev = hw->pdev; 2835 u32 status = sky2_read32(hw, B0_HWE_ISRC); 2836 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK); 2837 2838 status &= hwmsk; 2839 2840 if (status & Y2_IS_TIST_OV) 2841 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); 2842 2843 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) { 2844 u16 pci_err; 2845 2846 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); 2847 pci_err = sky2_pci_read16(hw, PCI_STATUS); 2848 if (net_ratelimit()) 2849 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n", 2850 pci_err); 2851 2852 sky2_pci_write16(hw, PCI_STATUS, 2853 pci_err | PCI_STATUS_ERROR_BITS); 2854 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 2855 } 2856 2857 if (status & Y2_IS_PCI_EXP) { 2858 /* PCI-Express uncorrectable Error occurred */ 2859 u32 err; 2860 2861 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); 2862 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS); 2863 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS, 2864 0xfffffffful); 2865 if (net_ratelimit()) 2866 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err); 2867 2868 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS); 2869 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 2870 } 2871 2872 if (status & Y2_HWE_L1_MASK) 2873 sky2_hw_error(hw, 0, status); 2874 status >>= 8; 2875 if (status & Y2_HWE_L1_MASK) 2876 sky2_hw_error(hw, 1, status); 2877 } 2878 2879 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port) 2880 { 2881 struct net_device *dev = hw->dev[port]; 2882 struct sky2_port *sky2 = netdev_priv(dev); 2883 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC)); 2884 2885 netif_info(sky2, intr, dev, "mac interrupt status 0x%x\n", status); 2886 2887 if (status & GM_IS_RX_CO_OV) 2888 gma_read16(hw, port, GM_RX_IRQ_SRC); 2889 2890 if (status & GM_IS_TX_CO_OV) 2891 gma_read16(hw, port, GM_TX_IRQ_SRC); 2892 2893 if (status & GM_IS_RX_FF_OR) { 2894 ++dev->stats.rx_fifo_errors; 2895 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO); 2896 } 2897 2898 if (status & GM_IS_TX_FF_UR) { 2899 ++dev->stats.tx_fifo_errors; 2900 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU); 2901 } 2902 } 2903 2904 /* This should never happen it is a bug. */ 2905 static void sky2_le_error(struct sky2_hw *hw, unsigned port, u16 q) 2906 { 2907 struct net_device *dev = hw->dev[port]; 2908 u16 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX)); 2909 2910 dev_err(&hw->pdev->dev, "%s: descriptor error q=%#x get=%u put=%u\n", 2911 dev->name, (unsigned) q, (unsigned) idx, 2912 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX))); 2913 2914 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK); 2915 } 2916 2917 static int sky2_rx_hung(struct net_device *dev) 2918 { 2919 struct sky2_port *sky2 = netdev_priv(dev); 2920 struct sky2_hw *hw = sky2->hw; 2921 unsigned port = sky2->port; 2922 unsigned rxq = rxqaddr[port]; 2923 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP)); 2924 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV)); 2925 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP)); 2926 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL)); 2927 2928 /* If idle and MAC or PCI is stuck */ 2929 if (sky2->check.last == dev->last_rx && 2930 ((mac_rp == sky2->check.mac_rp && 2931 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) || 2932 /* Check if the PCI RX hang */ 2933 (fifo_rp == sky2->check.fifo_rp && 2934 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) { 2935 netdev_printk(KERN_DEBUG, dev, 2936 "hung mac %d:%d fifo %d (%d:%d)\n", 2937 mac_lev, mac_rp, fifo_lev, 2938 fifo_rp, sky2_read8(hw, Q_ADDR(rxq, Q_WP))); 2939 return 1; 2940 } else { 2941 sky2->check.last = dev->last_rx; 2942 sky2->check.mac_rp = mac_rp; 2943 sky2->check.mac_lev = mac_lev; 2944 sky2->check.fifo_rp = fifo_rp; 2945 sky2->check.fifo_lev = fifo_lev; 2946 return 0; 2947 } 2948 } 2949 2950 static void sky2_watchdog(unsigned long arg) 2951 { 2952 struct sky2_hw *hw = (struct sky2_hw *) arg; 2953 2954 /* Check for lost IRQ once a second */ 2955 if (sky2_read32(hw, B0_ISRC)) { 2956 napi_schedule(&hw->napi); 2957 } else { 2958 int i, active = 0; 2959 2960 for (i = 0; i < hw->ports; i++) { 2961 struct net_device *dev = hw->dev[i]; 2962 if (!netif_running(dev)) 2963 continue; 2964 ++active; 2965 2966 /* For chips with Rx FIFO, check if stuck */ 2967 if ((hw->flags & SKY2_HW_RAM_BUFFER) && 2968 sky2_rx_hung(dev)) { 2969 netdev_info(dev, "receiver hang detected\n"); 2970 schedule_work(&hw->restart_work); 2971 return; 2972 } 2973 } 2974 2975 if (active == 0) 2976 return; 2977 } 2978 2979 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ)); 2980 } 2981 2982 /* Hardware/software error handling */ 2983 static void sky2_err_intr(struct sky2_hw *hw, u32 status) 2984 { 2985 if (net_ratelimit()) 2986 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status); 2987 2988 if (status & Y2_IS_HW_ERR) 2989 sky2_hw_intr(hw); 2990 2991 if (status & Y2_IS_IRQ_MAC1) 2992 sky2_mac_intr(hw, 0); 2993 2994 if (status & Y2_IS_IRQ_MAC2) 2995 sky2_mac_intr(hw, 1); 2996 2997 if (status & Y2_IS_CHK_RX1) 2998 sky2_le_error(hw, 0, Q_R1); 2999 3000 if (status & Y2_IS_CHK_RX2) 3001 sky2_le_error(hw, 1, Q_R2); 3002 3003 if (status & Y2_IS_CHK_TXA1) 3004 sky2_le_error(hw, 0, Q_XA1); 3005 3006 if (status & Y2_IS_CHK_TXA2) 3007 sky2_le_error(hw, 1, Q_XA2); 3008 } 3009 3010 static int sky2_poll(struct napi_struct *napi, int work_limit) 3011 { 3012 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi); 3013 u32 status = sky2_read32(hw, B0_Y2_SP_EISR); 3014 int work_done = 0; 3015 u16 idx; 3016 3017 if (unlikely(status & Y2_IS_ERROR)) 3018 sky2_err_intr(hw, status); 3019 3020 if (status & Y2_IS_IRQ_PHY1) 3021 sky2_phy_intr(hw, 0); 3022 3023 if (status & Y2_IS_IRQ_PHY2) 3024 sky2_phy_intr(hw, 1); 3025 3026 if (status & Y2_IS_PHY_QLNK) 3027 sky2_qlink_intr(hw); 3028 3029 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) { 3030 work_done += sky2_status_intr(hw, work_limit - work_done, idx); 3031 3032 if (work_done >= work_limit) 3033 goto done; 3034 } 3035 3036 napi_complete(napi); 3037 sky2_read32(hw, B0_Y2_SP_LISR); 3038 done: 3039 3040 return work_done; 3041 } 3042 3043 static irqreturn_t sky2_intr(int irq, void *dev_id) 3044 { 3045 struct sky2_hw *hw = dev_id; 3046 u32 status; 3047 3048 /* Reading this mask interrupts as side effect */ 3049 status = sky2_read32(hw, B0_Y2_SP_ISRC2); 3050 if (status == 0 || status == ~0) 3051 return IRQ_NONE; 3052 3053 prefetch(&hw->st_le[hw->st_idx]); 3054 3055 napi_schedule(&hw->napi); 3056 3057 return IRQ_HANDLED; 3058 } 3059 3060 #ifdef CONFIG_NET_POLL_CONTROLLER 3061 static void sky2_netpoll(struct net_device *dev) 3062 { 3063 struct sky2_port *sky2 = netdev_priv(dev); 3064 3065 napi_schedule(&sky2->hw->napi); 3066 } 3067 #endif 3068 3069 /* Chip internal frequency for clock calculations */ 3070 static u32 sky2_mhz(const struct sky2_hw *hw) 3071 { 3072 switch (hw->chip_id) { 3073 case CHIP_ID_YUKON_EC: 3074 case CHIP_ID_YUKON_EC_U: 3075 case CHIP_ID_YUKON_EX: 3076 case CHIP_ID_YUKON_SUPR: 3077 case CHIP_ID_YUKON_UL_2: 3078 case CHIP_ID_YUKON_OPT: 3079 case CHIP_ID_YUKON_PRM: 3080 case CHIP_ID_YUKON_OP_2: 3081 return 125; 3082 3083 case CHIP_ID_YUKON_FE: 3084 return 100; 3085 3086 case CHIP_ID_YUKON_FE_P: 3087 return 50; 3088 3089 case CHIP_ID_YUKON_XL: 3090 return 156; 3091 3092 default: 3093 BUG(); 3094 } 3095 } 3096 3097 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us) 3098 { 3099 return sky2_mhz(hw) * us; 3100 } 3101 3102 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk) 3103 { 3104 return clk / sky2_mhz(hw); 3105 } 3106 3107 3108 static int __devinit sky2_init(struct sky2_hw *hw) 3109 { 3110 u8 t8; 3111 3112 /* Enable all clocks and check for bad PCI access */ 3113 sky2_pci_write32(hw, PCI_DEV_REG3, 0); 3114 3115 sky2_write8(hw, B0_CTST, CS_RST_CLR); 3116 3117 hw->chip_id = sky2_read8(hw, B2_CHIP_ID); 3118 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4; 3119 3120 switch (hw->chip_id) { 3121 case CHIP_ID_YUKON_XL: 3122 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY; 3123 if (hw->chip_rev < CHIP_REV_YU_XL_A2) 3124 hw->flags |= SKY2_HW_RSS_BROKEN; 3125 break; 3126 3127 case CHIP_ID_YUKON_EC_U: 3128 hw->flags = SKY2_HW_GIGABIT 3129 | SKY2_HW_NEWER_PHY 3130 | SKY2_HW_ADV_POWER_CTL; 3131 break; 3132 3133 case CHIP_ID_YUKON_EX: 3134 hw->flags = SKY2_HW_GIGABIT 3135 | SKY2_HW_NEWER_PHY 3136 | SKY2_HW_NEW_LE 3137 | SKY2_HW_ADV_POWER_CTL 3138 | SKY2_HW_RSS_CHKSUM; 3139 3140 /* New transmit checksum */ 3141 if (hw->chip_rev != CHIP_REV_YU_EX_B0) 3142 hw->flags |= SKY2_HW_AUTO_TX_SUM; 3143 break; 3144 3145 case CHIP_ID_YUKON_EC: 3146 /* This rev is really old, and requires untested workarounds */ 3147 if (hw->chip_rev == CHIP_REV_YU_EC_A1) { 3148 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n"); 3149 return -EOPNOTSUPP; 3150 } 3151 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_RSS_BROKEN; 3152 break; 3153 3154 case CHIP_ID_YUKON_FE: 3155 hw->flags = SKY2_HW_RSS_BROKEN; 3156 break; 3157 3158 case CHIP_ID_YUKON_FE_P: 3159 hw->flags = SKY2_HW_NEWER_PHY 3160 | SKY2_HW_NEW_LE 3161 | SKY2_HW_AUTO_TX_SUM 3162 | SKY2_HW_ADV_POWER_CTL; 3163 3164 /* The workaround for status conflicts VLAN tag detection. */ 3165 if (hw->chip_rev == CHIP_REV_YU_FE2_A0) 3166 hw->flags |= SKY2_HW_VLAN_BROKEN | SKY2_HW_RSS_CHKSUM; 3167 break; 3168 3169 case CHIP_ID_YUKON_SUPR: 3170 hw->flags = SKY2_HW_GIGABIT 3171 | SKY2_HW_NEWER_PHY 3172 | SKY2_HW_NEW_LE 3173 | SKY2_HW_AUTO_TX_SUM 3174 | SKY2_HW_ADV_POWER_CTL; 3175 3176 if (hw->chip_rev == CHIP_REV_YU_SU_A0) 3177 hw->flags |= SKY2_HW_RSS_CHKSUM; 3178 break; 3179 3180 case CHIP_ID_YUKON_UL_2: 3181 hw->flags = SKY2_HW_GIGABIT 3182 | SKY2_HW_ADV_POWER_CTL; 3183 break; 3184 3185 case CHIP_ID_YUKON_OPT: 3186 case CHIP_ID_YUKON_PRM: 3187 case CHIP_ID_YUKON_OP_2: 3188 hw->flags = SKY2_HW_GIGABIT 3189 | SKY2_HW_NEW_LE 3190 | SKY2_HW_ADV_POWER_CTL; 3191 break; 3192 3193 default: 3194 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n", 3195 hw->chip_id); 3196 return -EOPNOTSUPP; 3197 } 3198 3199 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP); 3200 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P') 3201 hw->flags |= SKY2_HW_FIBRE_PHY; 3202 3203 hw->ports = 1; 3204 t8 = sky2_read8(hw, B2_Y2_HW_RES); 3205 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) { 3206 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC)) 3207 ++hw->ports; 3208 } 3209 3210 if (sky2_read8(hw, B2_E_0)) 3211 hw->flags |= SKY2_HW_RAM_BUFFER; 3212 3213 return 0; 3214 } 3215 3216 static void sky2_reset(struct sky2_hw *hw) 3217 { 3218 struct pci_dev *pdev = hw->pdev; 3219 u16 status; 3220 int i; 3221 u32 hwe_mask = Y2_HWE_ALL_MASK; 3222 3223 /* disable ASF */ 3224 if (hw->chip_id == CHIP_ID_YUKON_EX 3225 || hw->chip_id == CHIP_ID_YUKON_SUPR) { 3226 sky2_write32(hw, CPU_WDOG, 0); 3227 status = sky2_read16(hw, HCU_CCSR); 3228 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE | 3229 HCU_CCSR_UC_STATE_MSK); 3230 /* 3231 * CPU clock divider shouldn't be used because 3232 * - ASF firmware may malfunction 3233 * - Yukon-Supreme: Parallel FLASH doesn't support divided clocks 3234 */ 3235 status &= ~HCU_CCSR_CPU_CLK_DIVIDE_MSK; 3236 sky2_write16(hw, HCU_CCSR, status); 3237 sky2_write32(hw, CPU_WDOG, 0); 3238 } else 3239 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET); 3240 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE); 3241 3242 /* do a SW reset */ 3243 sky2_write8(hw, B0_CTST, CS_RST_SET); 3244 sky2_write8(hw, B0_CTST, CS_RST_CLR); 3245 3246 /* allow writes to PCI config */ 3247 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); 3248 3249 /* clear PCI errors, if any */ 3250 status = sky2_pci_read16(hw, PCI_STATUS); 3251 status |= PCI_STATUS_ERROR_BITS; 3252 sky2_pci_write16(hw, PCI_STATUS, status); 3253 3254 sky2_write8(hw, B0_CTST, CS_MRST_CLR); 3255 3256 if (pci_is_pcie(pdev)) { 3257 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS, 3258 0xfffffffful); 3259 3260 /* If error bit is stuck on ignore it */ 3261 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP) 3262 dev_info(&pdev->dev, "ignoring stuck error report bit\n"); 3263 else 3264 hwe_mask |= Y2_IS_PCI_EXP; 3265 } 3266 3267 sky2_power_on(hw); 3268 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 3269 3270 for (i = 0; i < hw->ports; i++) { 3271 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET); 3272 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR); 3273 3274 if (hw->chip_id == CHIP_ID_YUKON_EX || 3275 hw->chip_id == CHIP_ID_YUKON_SUPR) 3276 sky2_write16(hw, SK_REG(i, GMAC_CTRL), 3277 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON 3278 | GMC_BYP_RETR_ON); 3279 3280 } 3281 3282 if (hw->chip_id == CHIP_ID_YUKON_SUPR && hw->chip_rev > CHIP_REV_YU_SU_B0) { 3283 /* enable MACSec clock gating */ 3284 sky2_pci_write32(hw, PCI_DEV_REG3, P_CLK_MACSEC_DIS); 3285 } 3286 3287 if (hw->chip_id == CHIP_ID_YUKON_OPT || 3288 hw->chip_id == CHIP_ID_YUKON_PRM || 3289 hw->chip_id == CHIP_ID_YUKON_OP_2) { 3290 u16 reg; 3291 3292 if (hw->chip_id == CHIP_ID_YUKON_OPT && hw->chip_rev == 0) { 3293 /* disable PCI-E PHY power down (set PHY reg 0x80, bit 7 */ 3294 sky2_write32(hw, Y2_PEX_PHY_DATA, (0x80UL << 16) | (1 << 7)); 3295 3296 /* set PHY Link Detect Timer to 1.1 second (11x 100ms) */ 3297 reg = 10; 3298 3299 /* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */ 3300 sky2_write32(hw, Y2_PEX_PHY_DATA, PEX_DB_ACCESS | (0x08UL << 16)); 3301 } else { 3302 /* set PHY Link Detect Timer to 0.4 second (4x 100ms) */ 3303 reg = 3; 3304 } 3305 3306 reg <<= PSM_CONFIG_REG4_TIMER_PHY_LINK_DETECT_BASE; 3307 reg |= PSM_CONFIG_REG4_RST_PHY_LINK_DETECT; 3308 3309 /* reset PHY Link Detect */ 3310 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); 3311 sky2_pci_write16(hw, PSM_CONFIG_REG4, reg); 3312 3313 /* check if PSMv2 was running before */ 3314 reg = sky2_pci_read16(hw, PSM_CONFIG_REG3); 3315 if (reg & PCI_EXP_LNKCTL_ASPMC) 3316 /* restore the PCIe Link Control register */ 3317 sky2_pci_write16(hw, pdev->pcie_cap + PCI_EXP_LNKCTL, 3318 reg); 3319 3320 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 3321 3322 /* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */ 3323 sky2_write32(hw, Y2_PEX_PHY_DATA, PEX_DB_ACCESS | (0x08UL << 16)); 3324 } 3325 3326 /* Clear I2C IRQ noise */ 3327 sky2_write32(hw, B2_I2C_IRQ, 1); 3328 3329 /* turn off hardware timer (unused) */ 3330 sky2_write8(hw, B2_TI_CTRL, TIM_STOP); 3331 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ); 3332 3333 /* Turn off descriptor polling */ 3334 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP); 3335 3336 /* Turn off receive timestamp */ 3337 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP); 3338 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); 3339 3340 /* enable the Tx Arbiters */ 3341 for (i = 0; i < hw->ports; i++) 3342 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB); 3343 3344 /* Initialize ram interface */ 3345 for (i = 0; i < hw->ports; i++) { 3346 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR); 3347 3348 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53); 3349 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53); 3350 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53); 3351 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53); 3352 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53); 3353 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53); 3354 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53); 3355 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53); 3356 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53); 3357 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53); 3358 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53); 3359 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53); 3360 } 3361 3362 sky2_write32(hw, B0_HWE_IMSK, hwe_mask); 3363 3364 for (i = 0; i < hw->ports; i++) 3365 sky2_gmac_reset(hw, i); 3366 3367 memset(hw->st_le, 0, hw->st_size * sizeof(struct sky2_status_le)); 3368 hw->st_idx = 0; 3369 3370 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET); 3371 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR); 3372 3373 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma); 3374 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32); 3375 3376 /* Set the list last index */ 3377 sky2_write16(hw, STAT_LAST_IDX, hw->st_size - 1); 3378 3379 sky2_write16(hw, STAT_TX_IDX_TH, 10); 3380 sky2_write8(hw, STAT_FIFO_WM, 16); 3381 3382 /* set Status-FIFO ISR watermark */ 3383 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0) 3384 sky2_write8(hw, STAT_FIFO_ISR_WM, 4); 3385 else 3386 sky2_write8(hw, STAT_FIFO_ISR_WM, 16); 3387 3388 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000)); 3389 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20)); 3390 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100)); 3391 3392 /* enable status unit */ 3393 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON); 3394 3395 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START); 3396 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START); 3397 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START); 3398 } 3399 3400 /* Take device down (offline). 3401 * Equivalent to doing dev_stop() but this does not 3402 * inform upper layers of the transition. 3403 */ 3404 static void sky2_detach(struct net_device *dev) 3405 { 3406 if (netif_running(dev)) { 3407 netif_tx_lock(dev); 3408 netif_device_detach(dev); /* stop txq */ 3409 netif_tx_unlock(dev); 3410 sky2_close(dev); 3411 } 3412 } 3413 3414 /* Bring device back after doing sky2_detach */ 3415 static int sky2_reattach(struct net_device *dev) 3416 { 3417 int err = 0; 3418 3419 if (netif_running(dev)) { 3420 err = sky2_open(dev); 3421 if (err) { 3422 netdev_info(dev, "could not restart %d\n", err); 3423 dev_close(dev); 3424 } else { 3425 netif_device_attach(dev); 3426 sky2_set_multicast(dev); 3427 } 3428 } 3429 3430 return err; 3431 } 3432 3433 static void sky2_all_down(struct sky2_hw *hw) 3434 { 3435 int i; 3436 3437 if (hw->flags & SKY2_HW_IRQ_SETUP) { 3438 sky2_read32(hw, B0_IMSK); 3439 sky2_write32(hw, B0_IMSK, 0); 3440 3441 synchronize_irq(hw->pdev->irq); 3442 napi_disable(&hw->napi); 3443 } 3444 3445 for (i = 0; i < hw->ports; i++) { 3446 struct net_device *dev = hw->dev[i]; 3447 struct sky2_port *sky2 = netdev_priv(dev); 3448 3449 if (!netif_running(dev)) 3450 continue; 3451 3452 netif_carrier_off(dev); 3453 netif_tx_disable(dev); 3454 sky2_hw_down(sky2); 3455 } 3456 } 3457 3458 static void sky2_all_up(struct sky2_hw *hw) 3459 { 3460 u32 imask = Y2_IS_BASE; 3461 int i; 3462 3463 for (i = 0; i < hw->ports; i++) { 3464 struct net_device *dev = hw->dev[i]; 3465 struct sky2_port *sky2 = netdev_priv(dev); 3466 3467 if (!netif_running(dev)) 3468 continue; 3469 3470 sky2_hw_up(sky2); 3471 sky2_set_multicast(dev); 3472 imask |= portirq_msk[i]; 3473 netif_wake_queue(dev); 3474 } 3475 3476 if (hw->flags & SKY2_HW_IRQ_SETUP) { 3477 sky2_write32(hw, B0_IMSK, imask); 3478 sky2_read32(hw, B0_IMSK); 3479 sky2_read32(hw, B0_Y2_SP_LISR); 3480 napi_enable(&hw->napi); 3481 } 3482 } 3483 3484 static void sky2_restart(struct work_struct *work) 3485 { 3486 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work); 3487 3488 rtnl_lock(); 3489 3490 sky2_all_down(hw); 3491 sky2_reset(hw); 3492 sky2_all_up(hw); 3493 3494 rtnl_unlock(); 3495 } 3496 3497 static inline u8 sky2_wol_supported(const struct sky2_hw *hw) 3498 { 3499 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0; 3500 } 3501 3502 static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 3503 { 3504 const struct sky2_port *sky2 = netdev_priv(dev); 3505 3506 wol->supported = sky2_wol_supported(sky2->hw); 3507 wol->wolopts = sky2->wol; 3508 } 3509 3510 static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 3511 { 3512 struct sky2_port *sky2 = netdev_priv(dev); 3513 struct sky2_hw *hw = sky2->hw; 3514 bool enable_wakeup = false; 3515 int i; 3516 3517 if ((wol->wolopts & ~sky2_wol_supported(sky2->hw)) || 3518 !device_can_wakeup(&hw->pdev->dev)) 3519 return -EOPNOTSUPP; 3520 3521 sky2->wol = wol->wolopts; 3522 3523 for (i = 0; i < hw->ports; i++) { 3524 struct net_device *dev = hw->dev[i]; 3525 struct sky2_port *sky2 = netdev_priv(dev); 3526 3527 if (sky2->wol) 3528 enable_wakeup = true; 3529 } 3530 device_set_wakeup_enable(&hw->pdev->dev, enable_wakeup); 3531 3532 return 0; 3533 } 3534 3535 static u32 sky2_supported_modes(const struct sky2_hw *hw) 3536 { 3537 if (sky2_is_copper(hw)) { 3538 u32 modes = SUPPORTED_10baseT_Half 3539 | SUPPORTED_10baseT_Full 3540 | SUPPORTED_100baseT_Half 3541 | SUPPORTED_100baseT_Full; 3542 3543 if (hw->flags & SKY2_HW_GIGABIT) 3544 modes |= SUPPORTED_1000baseT_Half 3545 | SUPPORTED_1000baseT_Full; 3546 return modes; 3547 } else 3548 return SUPPORTED_1000baseT_Half 3549 | SUPPORTED_1000baseT_Full; 3550 } 3551 3552 static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd) 3553 { 3554 struct sky2_port *sky2 = netdev_priv(dev); 3555 struct sky2_hw *hw = sky2->hw; 3556 3557 ecmd->transceiver = XCVR_INTERNAL; 3558 ecmd->supported = sky2_supported_modes(hw); 3559 ecmd->phy_address = PHY_ADDR_MARV; 3560 if (sky2_is_copper(hw)) { 3561 ecmd->port = PORT_TP; 3562 ethtool_cmd_speed_set(ecmd, sky2->speed); 3563 ecmd->supported |= SUPPORTED_Autoneg | SUPPORTED_TP; 3564 } else { 3565 ethtool_cmd_speed_set(ecmd, SPEED_1000); 3566 ecmd->port = PORT_FIBRE; 3567 ecmd->supported |= SUPPORTED_Autoneg | SUPPORTED_FIBRE; 3568 } 3569 3570 ecmd->advertising = sky2->advertising; 3571 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_SPEED) 3572 ? AUTONEG_ENABLE : AUTONEG_DISABLE; 3573 ecmd->duplex = sky2->duplex; 3574 return 0; 3575 } 3576 3577 static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd) 3578 { 3579 struct sky2_port *sky2 = netdev_priv(dev); 3580 const struct sky2_hw *hw = sky2->hw; 3581 u32 supported = sky2_supported_modes(hw); 3582 3583 if (ecmd->autoneg == AUTONEG_ENABLE) { 3584 if (ecmd->advertising & ~supported) 3585 return -EINVAL; 3586 3587 if (sky2_is_copper(hw)) 3588 sky2->advertising = ecmd->advertising | 3589 ADVERTISED_TP | 3590 ADVERTISED_Autoneg; 3591 else 3592 sky2->advertising = ecmd->advertising | 3593 ADVERTISED_FIBRE | 3594 ADVERTISED_Autoneg; 3595 3596 sky2->flags |= SKY2_FLAG_AUTO_SPEED; 3597 sky2->duplex = -1; 3598 sky2->speed = -1; 3599 } else { 3600 u32 setting; 3601 u32 speed = ethtool_cmd_speed(ecmd); 3602 3603 switch (speed) { 3604 case SPEED_1000: 3605 if (ecmd->duplex == DUPLEX_FULL) 3606 setting = SUPPORTED_1000baseT_Full; 3607 else if (ecmd->duplex == DUPLEX_HALF) 3608 setting = SUPPORTED_1000baseT_Half; 3609 else 3610 return -EINVAL; 3611 break; 3612 case SPEED_100: 3613 if (ecmd->duplex == DUPLEX_FULL) 3614 setting = SUPPORTED_100baseT_Full; 3615 else if (ecmd->duplex == DUPLEX_HALF) 3616 setting = SUPPORTED_100baseT_Half; 3617 else 3618 return -EINVAL; 3619 break; 3620 3621 case SPEED_10: 3622 if (ecmd->duplex == DUPLEX_FULL) 3623 setting = SUPPORTED_10baseT_Full; 3624 else if (ecmd->duplex == DUPLEX_HALF) 3625 setting = SUPPORTED_10baseT_Half; 3626 else 3627 return -EINVAL; 3628 break; 3629 default: 3630 return -EINVAL; 3631 } 3632 3633 if ((setting & supported) == 0) 3634 return -EINVAL; 3635 3636 sky2->speed = speed; 3637 sky2->duplex = ecmd->duplex; 3638 sky2->flags &= ~SKY2_FLAG_AUTO_SPEED; 3639 } 3640 3641 if (netif_running(dev)) { 3642 sky2_phy_reinit(sky2); 3643 sky2_set_multicast(dev); 3644 } 3645 3646 return 0; 3647 } 3648 3649 static void sky2_get_drvinfo(struct net_device *dev, 3650 struct ethtool_drvinfo *info) 3651 { 3652 struct sky2_port *sky2 = netdev_priv(dev); 3653 3654 strlcpy(info->driver, DRV_NAME, sizeof(info->driver)); 3655 strlcpy(info->version, DRV_VERSION, sizeof(info->version)); 3656 strlcpy(info->bus_info, pci_name(sky2->hw->pdev), 3657 sizeof(info->bus_info)); 3658 } 3659 3660 static const struct sky2_stat { 3661 char name[ETH_GSTRING_LEN]; 3662 u16 offset; 3663 } sky2_stats[] = { 3664 { "tx_bytes", GM_TXO_OK_HI }, 3665 { "rx_bytes", GM_RXO_OK_HI }, 3666 { "tx_broadcast", GM_TXF_BC_OK }, 3667 { "rx_broadcast", GM_RXF_BC_OK }, 3668 { "tx_multicast", GM_TXF_MC_OK }, 3669 { "rx_multicast", GM_RXF_MC_OK }, 3670 { "tx_unicast", GM_TXF_UC_OK }, 3671 { "rx_unicast", GM_RXF_UC_OK }, 3672 { "tx_mac_pause", GM_TXF_MPAUSE }, 3673 { "rx_mac_pause", GM_RXF_MPAUSE }, 3674 { "collisions", GM_TXF_COL }, 3675 { "late_collision",GM_TXF_LAT_COL }, 3676 { "aborted", GM_TXF_ABO_COL }, 3677 { "single_collisions", GM_TXF_SNG_COL }, 3678 { "multi_collisions", GM_TXF_MUL_COL }, 3679 3680 { "rx_short", GM_RXF_SHT }, 3681 { "rx_runt", GM_RXE_FRAG }, 3682 { "rx_64_byte_packets", GM_RXF_64B }, 3683 { "rx_65_to_127_byte_packets", GM_RXF_127B }, 3684 { "rx_128_to_255_byte_packets", GM_RXF_255B }, 3685 { "rx_256_to_511_byte_packets", GM_RXF_511B }, 3686 { "rx_512_to_1023_byte_packets", GM_RXF_1023B }, 3687 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B }, 3688 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ }, 3689 { "rx_too_long", GM_RXF_LNG_ERR }, 3690 { "rx_fifo_overflow", GM_RXE_FIFO_OV }, 3691 { "rx_jabber", GM_RXF_JAB_PKT }, 3692 { "rx_fcs_error", GM_RXF_FCS_ERR }, 3693 3694 { "tx_64_byte_packets", GM_TXF_64B }, 3695 { "tx_65_to_127_byte_packets", GM_TXF_127B }, 3696 { "tx_128_to_255_byte_packets", GM_TXF_255B }, 3697 { "tx_256_to_511_byte_packets", GM_TXF_511B }, 3698 { "tx_512_to_1023_byte_packets", GM_TXF_1023B }, 3699 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B }, 3700 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ }, 3701 { "tx_fifo_underrun", GM_TXE_FIFO_UR }, 3702 }; 3703 3704 static u32 sky2_get_msglevel(struct net_device *netdev) 3705 { 3706 struct sky2_port *sky2 = netdev_priv(netdev); 3707 return sky2->msg_enable; 3708 } 3709 3710 static int sky2_nway_reset(struct net_device *dev) 3711 { 3712 struct sky2_port *sky2 = netdev_priv(dev); 3713 3714 if (!netif_running(dev) || !(sky2->flags & SKY2_FLAG_AUTO_SPEED)) 3715 return -EINVAL; 3716 3717 sky2_phy_reinit(sky2); 3718 sky2_set_multicast(dev); 3719 3720 return 0; 3721 } 3722 3723 static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count) 3724 { 3725 struct sky2_hw *hw = sky2->hw; 3726 unsigned port = sky2->port; 3727 int i; 3728 3729 data[0] = get_stats64(hw, port, GM_TXO_OK_LO); 3730 data[1] = get_stats64(hw, port, GM_RXO_OK_LO); 3731 3732 for (i = 2; i < count; i++) 3733 data[i] = get_stats32(hw, port, sky2_stats[i].offset); 3734 } 3735 3736 static void sky2_set_msglevel(struct net_device *netdev, u32 value) 3737 { 3738 struct sky2_port *sky2 = netdev_priv(netdev); 3739 sky2->msg_enable = value; 3740 } 3741 3742 static int sky2_get_sset_count(struct net_device *dev, int sset) 3743 { 3744 switch (sset) { 3745 case ETH_SS_STATS: 3746 return ARRAY_SIZE(sky2_stats); 3747 default: 3748 return -EOPNOTSUPP; 3749 } 3750 } 3751 3752 static void sky2_get_ethtool_stats(struct net_device *dev, 3753 struct ethtool_stats *stats, u64 * data) 3754 { 3755 struct sky2_port *sky2 = netdev_priv(dev); 3756 3757 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats)); 3758 } 3759 3760 static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data) 3761 { 3762 int i; 3763 3764 switch (stringset) { 3765 case ETH_SS_STATS: 3766 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++) 3767 memcpy(data + i * ETH_GSTRING_LEN, 3768 sky2_stats[i].name, ETH_GSTRING_LEN); 3769 break; 3770 } 3771 } 3772 3773 static int sky2_set_mac_address(struct net_device *dev, void *p) 3774 { 3775 struct sky2_port *sky2 = netdev_priv(dev); 3776 struct sky2_hw *hw = sky2->hw; 3777 unsigned port = sky2->port; 3778 const struct sockaddr *addr = p; 3779 3780 if (!is_valid_ether_addr(addr->sa_data)) 3781 return -EADDRNOTAVAIL; 3782 3783 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN); 3784 memcpy_toio(hw->regs + B2_MAC_1 + port * 8, 3785 dev->dev_addr, ETH_ALEN); 3786 memcpy_toio(hw->regs + B2_MAC_2 + port * 8, 3787 dev->dev_addr, ETH_ALEN); 3788 3789 /* virtual address for data */ 3790 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr); 3791 3792 /* physical address: used for pause frames */ 3793 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr); 3794 3795 return 0; 3796 } 3797 3798 static inline void sky2_add_filter(u8 filter[8], const u8 *addr) 3799 { 3800 u32 bit; 3801 3802 bit = ether_crc(ETH_ALEN, addr) & 63; 3803 filter[bit >> 3] |= 1 << (bit & 7); 3804 } 3805 3806 static void sky2_set_multicast(struct net_device *dev) 3807 { 3808 struct sky2_port *sky2 = netdev_priv(dev); 3809 struct sky2_hw *hw = sky2->hw; 3810 unsigned port = sky2->port; 3811 struct netdev_hw_addr *ha; 3812 u16 reg; 3813 u8 filter[8]; 3814 int rx_pause; 3815 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 }; 3816 3817 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH); 3818 memset(filter, 0, sizeof(filter)); 3819 3820 reg = gma_read16(hw, port, GM_RX_CTRL); 3821 reg |= GM_RXCR_UCF_ENA; 3822 3823 if (dev->flags & IFF_PROMISC) /* promiscuous */ 3824 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA); 3825 else if (dev->flags & IFF_ALLMULTI) 3826 memset(filter, 0xff, sizeof(filter)); 3827 else if (netdev_mc_empty(dev) && !rx_pause) 3828 reg &= ~GM_RXCR_MCF_ENA; 3829 else { 3830 reg |= GM_RXCR_MCF_ENA; 3831 3832 if (rx_pause) 3833 sky2_add_filter(filter, pause_mc_addr); 3834 3835 netdev_for_each_mc_addr(ha, dev) 3836 sky2_add_filter(filter, ha->addr); 3837 } 3838 3839 gma_write16(hw, port, GM_MC_ADDR_H1, 3840 (u16) filter[0] | ((u16) filter[1] << 8)); 3841 gma_write16(hw, port, GM_MC_ADDR_H2, 3842 (u16) filter[2] | ((u16) filter[3] << 8)); 3843 gma_write16(hw, port, GM_MC_ADDR_H3, 3844 (u16) filter[4] | ((u16) filter[5] << 8)); 3845 gma_write16(hw, port, GM_MC_ADDR_H4, 3846 (u16) filter[6] | ((u16) filter[7] << 8)); 3847 3848 gma_write16(hw, port, GM_RX_CTRL, reg); 3849 } 3850 3851 static struct rtnl_link_stats64 *sky2_get_stats(struct net_device *dev, 3852 struct rtnl_link_stats64 *stats) 3853 { 3854 struct sky2_port *sky2 = netdev_priv(dev); 3855 struct sky2_hw *hw = sky2->hw; 3856 unsigned port = sky2->port; 3857 unsigned int start; 3858 u64 _bytes, _packets; 3859 3860 do { 3861 start = u64_stats_fetch_begin_bh(&sky2->rx_stats.syncp); 3862 _bytes = sky2->rx_stats.bytes; 3863 _packets = sky2->rx_stats.packets; 3864 } while (u64_stats_fetch_retry_bh(&sky2->rx_stats.syncp, start)); 3865 3866 stats->rx_packets = _packets; 3867 stats->rx_bytes = _bytes; 3868 3869 do { 3870 start = u64_stats_fetch_begin_bh(&sky2->tx_stats.syncp); 3871 _bytes = sky2->tx_stats.bytes; 3872 _packets = sky2->tx_stats.packets; 3873 } while (u64_stats_fetch_retry_bh(&sky2->tx_stats.syncp, start)); 3874 3875 stats->tx_packets = _packets; 3876 stats->tx_bytes = _bytes; 3877 3878 stats->multicast = get_stats32(hw, port, GM_RXF_MC_OK) 3879 + get_stats32(hw, port, GM_RXF_BC_OK); 3880 3881 stats->collisions = get_stats32(hw, port, GM_TXF_COL); 3882 3883 stats->rx_length_errors = get_stats32(hw, port, GM_RXF_LNG_ERR); 3884 stats->rx_crc_errors = get_stats32(hw, port, GM_RXF_FCS_ERR); 3885 stats->rx_frame_errors = get_stats32(hw, port, GM_RXF_SHT) 3886 + get_stats32(hw, port, GM_RXE_FRAG); 3887 stats->rx_over_errors = get_stats32(hw, port, GM_RXE_FIFO_OV); 3888 3889 stats->rx_dropped = dev->stats.rx_dropped; 3890 stats->rx_fifo_errors = dev->stats.rx_fifo_errors; 3891 stats->tx_fifo_errors = dev->stats.tx_fifo_errors; 3892 3893 return stats; 3894 } 3895 3896 /* Can have one global because blinking is controlled by 3897 * ethtool and that is always under RTNL mutex 3898 */ 3899 static void sky2_led(struct sky2_port *sky2, enum led_mode mode) 3900 { 3901 struct sky2_hw *hw = sky2->hw; 3902 unsigned port = sky2->port; 3903 3904 spin_lock_bh(&sky2->phy_lock); 3905 if (hw->chip_id == CHIP_ID_YUKON_EC_U || 3906 hw->chip_id == CHIP_ID_YUKON_EX || 3907 hw->chip_id == CHIP_ID_YUKON_SUPR) { 3908 u16 pg; 3909 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); 3910 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); 3911 3912 switch (mode) { 3913 case MO_LED_OFF: 3914 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, 3915 PHY_M_LEDC_LOS_CTRL(8) | 3916 PHY_M_LEDC_INIT_CTRL(8) | 3917 PHY_M_LEDC_STA1_CTRL(8) | 3918 PHY_M_LEDC_STA0_CTRL(8)); 3919 break; 3920 case MO_LED_ON: 3921 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, 3922 PHY_M_LEDC_LOS_CTRL(9) | 3923 PHY_M_LEDC_INIT_CTRL(9) | 3924 PHY_M_LEDC_STA1_CTRL(9) | 3925 PHY_M_LEDC_STA0_CTRL(9)); 3926 break; 3927 case MO_LED_BLINK: 3928 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, 3929 PHY_M_LEDC_LOS_CTRL(0xa) | 3930 PHY_M_LEDC_INIT_CTRL(0xa) | 3931 PHY_M_LEDC_STA1_CTRL(0xa) | 3932 PHY_M_LEDC_STA0_CTRL(0xa)); 3933 break; 3934 case MO_LED_NORM: 3935 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, 3936 PHY_M_LEDC_LOS_CTRL(1) | 3937 PHY_M_LEDC_INIT_CTRL(8) | 3938 PHY_M_LEDC_STA1_CTRL(7) | 3939 PHY_M_LEDC_STA0_CTRL(7)); 3940 } 3941 3942 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); 3943 } else 3944 gm_phy_write(hw, port, PHY_MARV_LED_OVER, 3945 PHY_M_LED_MO_DUP(mode) | 3946 PHY_M_LED_MO_10(mode) | 3947 PHY_M_LED_MO_100(mode) | 3948 PHY_M_LED_MO_1000(mode) | 3949 PHY_M_LED_MO_RX(mode) | 3950 PHY_M_LED_MO_TX(mode)); 3951 3952 spin_unlock_bh(&sky2->phy_lock); 3953 } 3954 3955 /* blink LED's for finding board */ 3956 static int sky2_set_phys_id(struct net_device *dev, 3957 enum ethtool_phys_id_state state) 3958 { 3959 struct sky2_port *sky2 = netdev_priv(dev); 3960 3961 switch (state) { 3962 case ETHTOOL_ID_ACTIVE: 3963 return 1; /* cycle on/off once per second */ 3964 case ETHTOOL_ID_INACTIVE: 3965 sky2_led(sky2, MO_LED_NORM); 3966 break; 3967 case ETHTOOL_ID_ON: 3968 sky2_led(sky2, MO_LED_ON); 3969 break; 3970 case ETHTOOL_ID_OFF: 3971 sky2_led(sky2, MO_LED_OFF); 3972 break; 3973 } 3974 3975 return 0; 3976 } 3977 3978 static void sky2_get_pauseparam(struct net_device *dev, 3979 struct ethtool_pauseparam *ecmd) 3980 { 3981 struct sky2_port *sky2 = netdev_priv(dev); 3982 3983 switch (sky2->flow_mode) { 3984 case FC_NONE: 3985 ecmd->tx_pause = ecmd->rx_pause = 0; 3986 break; 3987 case FC_TX: 3988 ecmd->tx_pause = 1, ecmd->rx_pause = 0; 3989 break; 3990 case FC_RX: 3991 ecmd->tx_pause = 0, ecmd->rx_pause = 1; 3992 break; 3993 case FC_BOTH: 3994 ecmd->tx_pause = ecmd->rx_pause = 1; 3995 } 3996 3997 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_PAUSE) 3998 ? AUTONEG_ENABLE : AUTONEG_DISABLE; 3999 } 4000 4001 static int sky2_set_pauseparam(struct net_device *dev, 4002 struct ethtool_pauseparam *ecmd) 4003 { 4004 struct sky2_port *sky2 = netdev_priv(dev); 4005 4006 if (ecmd->autoneg == AUTONEG_ENABLE) 4007 sky2->flags |= SKY2_FLAG_AUTO_PAUSE; 4008 else 4009 sky2->flags &= ~SKY2_FLAG_AUTO_PAUSE; 4010 4011 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause); 4012 4013 if (netif_running(dev)) 4014 sky2_phy_reinit(sky2); 4015 4016 return 0; 4017 } 4018 4019 static int sky2_get_coalesce(struct net_device *dev, 4020 struct ethtool_coalesce *ecmd) 4021 { 4022 struct sky2_port *sky2 = netdev_priv(dev); 4023 struct sky2_hw *hw = sky2->hw; 4024 4025 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP) 4026 ecmd->tx_coalesce_usecs = 0; 4027 else { 4028 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI); 4029 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks); 4030 } 4031 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH); 4032 4033 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP) 4034 ecmd->rx_coalesce_usecs = 0; 4035 else { 4036 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI); 4037 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks); 4038 } 4039 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM); 4040 4041 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP) 4042 ecmd->rx_coalesce_usecs_irq = 0; 4043 else { 4044 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI); 4045 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks); 4046 } 4047 4048 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM); 4049 4050 return 0; 4051 } 4052 4053 /* Note: this affect both ports */ 4054 static int sky2_set_coalesce(struct net_device *dev, 4055 struct ethtool_coalesce *ecmd) 4056 { 4057 struct sky2_port *sky2 = netdev_priv(dev); 4058 struct sky2_hw *hw = sky2->hw; 4059 const u32 tmax = sky2_clk2us(hw, 0x0ffffff); 4060 4061 if (ecmd->tx_coalesce_usecs > tmax || 4062 ecmd->rx_coalesce_usecs > tmax || 4063 ecmd->rx_coalesce_usecs_irq > tmax) 4064 return -EINVAL; 4065 4066 if (ecmd->tx_max_coalesced_frames >= sky2->tx_ring_size-1) 4067 return -EINVAL; 4068 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING) 4069 return -EINVAL; 4070 if (ecmd->rx_max_coalesced_frames_irq > RX_MAX_PENDING) 4071 return -EINVAL; 4072 4073 if (ecmd->tx_coalesce_usecs == 0) 4074 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP); 4075 else { 4076 sky2_write32(hw, STAT_TX_TIMER_INI, 4077 sky2_us2clk(hw, ecmd->tx_coalesce_usecs)); 4078 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START); 4079 } 4080 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames); 4081 4082 if (ecmd->rx_coalesce_usecs == 0) 4083 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP); 4084 else { 4085 sky2_write32(hw, STAT_LEV_TIMER_INI, 4086 sky2_us2clk(hw, ecmd->rx_coalesce_usecs)); 4087 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START); 4088 } 4089 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames); 4090 4091 if (ecmd->rx_coalesce_usecs_irq == 0) 4092 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP); 4093 else { 4094 sky2_write32(hw, STAT_ISR_TIMER_INI, 4095 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq)); 4096 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START); 4097 } 4098 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq); 4099 return 0; 4100 } 4101 4102 /* 4103 * Hardware is limited to min of 128 and max of 2048 for ring size 4104 * and rounded up to next power of two 4105 * to avoid division in modulus calclation 4106 */ 4107 static unsigned long roundup_ring_size(unsigned long pending) 4108 { 4109 return max(128ul, roundup_pow_of_two(pending+1)); 4110 } 4111 4112 static void sky2_get_ringparam(struct net_device *dev, 4113 struct ethtool_ringparam *ering) 4114 { 4115 struct sky2_port *sky2 = netdev_priv(dev); 4116 4117 ering->rx_max_pending = RX_MAX_PENDING; 4118 ering->tx_max_pending = TX_MAX_PENDING; 4119 4120 ering->rx_pending = sky2->rx_pending; 4121 ering->tx_pending = sky2->tx_pending; 4122 } 4123 4124 static int sky2_set_ringparam(struct net_device *dev, 4125 struct ethtool_ringparam *ering) 4126 { 4127 struct sky2_port *sky2 = netdev_priv(dev); 4128 4129 if (ering->rx_pending > RX_MAX_PENDING || 4130 ering->rx_pending < 8 || 4131 ering->tx_pending < TX_MIN_PENDING || 4132 ering->tx_pending > TX_MAX_PENDING) 4133 return -EINVAL; 4134 4135 sky2_detach(dev); 4136 4137 sky2->rx_pending = ering->rx_pending; 4138 sky2->tx_pending = ering->tx_pending; 4139 sky2->tx_ring_size = roundup_ring_size(sky2->tx_pending); 4140 4141 return sky2_reattach(dev); 4142 } 4143 4144 static int sky2_get_regs_len(struct net_device *dev) 4145 { 4146 return 0x4000; 4147 } 4148 4149 static int sky2_reg_access_ok(struct sky2_hw *hw, unsigned int b) 4150 { 4151 /* This complicated switch statement is to make sure and 4152 * only access regions that are unreserved. 4153 * Some blocks are only valid on dual port cards. 4154 */ 4155 switch (b) { 4156 /* second port */ 4157 case 5: /* Tx Arbiter 2 */ 4158 case 9: /* RX2 */ 4159 case 14 ... 15: /* TX2 */ 4160 case 17: case 19: /* Ram Buffer 2 */ 4161 case 22 ... 23: /* Tx Ram Buffer 2 */ 4162 case 25: /* Rx MAC Fifo 1 */ 4163 case 27: /* Tx MAC Fifo 2 */ 4164 case 31: /* GPHY 2 */ 4165 case 40 ... 47: /* Pattern Ram 2 */ 4166 case 52: case 54: /* TCP Segmentation 2 */ 4167 case 112 ... 116: /* GMAC 2 */ 4168 return hw->ports > 1; 4169 4170 case 0: /* Control */ 4171 case 2: /* Mac address */ 4172 case 4: /* Tx Arbiter 1 */ 4173 case 7: /* PCI express reg */ 4174 case 8: /* RX1 */ 4175 case 12 ... 13: /* TX1 */ 4176 case 16: case 18:/* Rx Ram Buffer 1 */ 4177 case 20 ... 21: /* Tx Ram Buffer 1 */ 4178 case 24: /* Rx MAC Fifo 1 */ 4179 case 26: /* Tx MAC Fifo 1 */ 4180 case 28 ... 29: /* Descriptor and status unit */ 4181 case 30: /* GPHY 1*/ 4182 case 32 ... 39: /* Pattern Ram 1 */ 4183 case 48: case 50: /* TCP Segmentation 1 */ 4184 case 56 ... 60: /* PCI space */ 4185 case 80 ... 84: /* GMAC 1 */ 4186 return 1; 4187 4188 default: 4189 return 0; 4190 } 4191 } 4192 4193 /* 4194 * Returns copy of control register region 4195 * Note: ethtool_get_regs always provides full size (16k) buffer 4196 */ 4197 static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs, 4198 void *p) 4199 { 4200 const struct sky2_port *sky2 = netdev_priv(dev); 4201 const void __iomem *io = sky2->hw->regs; 4202 unsigned int b; 4203 4204 regs->version = 1; 4205 4206 for (b = 0; b < 128; b++) { 4207 /* skip poisonous diagnostic ram region in block 3 */ 4208 if (b == 3) 4209 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10); 4210 else if (sky2_reg_access_ok(sky2->hw, b)) 4211 memcpy_fromio(p, io, 128); 4212 else 4213 memset(p, 0, 128); 4214 4215 p += 128; 4216 io += 128; 4217 } 4218 } 4219 4220 static int sky2_get_eeprom_len(struct net_device *dev) 4221 { 4222 struct sky2_port *sky2 = netdev_priv(dev); 4223 struct sky2_hw *hw = sky2->hw; 4224 u16 reg2; 4225 4226 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2); 4227 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8); 4228 } 4229 4230 static int sky2_vpd_wait(const struct sky2_hw *hw, int cap, u16 busy) 4231 { 4232 unsigned long start = jiffies; 4233 4234 while ( (sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F) == busy) { 4235 /* Can take up to 10.6 ms for write */ 4236 if (time_after(jiffies, start + HZ/4)) { 4237 dev_err(&hw->pdev->dev, "VPD cycle timed out\n"); 4238 return -ETIMEDOUT; 4239 } 4240 mdelay(1); 4241 } 4242 4243 return 0; 4244 } 4245 4246 static int sky2_vpd_read(struct sky2_hw *hw, int cap, void *data, 4247 u16 offset, size_t length) 4248 { 4249 int rc = 0; 4250 4251 while (length > 0) { 4252 u32 val; 4253 4254 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset); 4255 rc = sky2_vpd_wait(hw, cap, 0); 4256 if (rc) 4257 break; 4258 4259 val = sky2_pci_read32(hw, cap + PCI_VPD_DATA); 4260 4261 memcpy(data, &val, min(sizeof(val), length)); 4262 offset += sizeof(u32); 4263 data += sizeof(u32); 4264 length -= sizeof(u32); 4265 } 4266 4267 return rc; 4268 } 4269 4270 static int sky2_vpd_write(struct sky2_hw *hw, int cap, const void *data, 4271 u16 offset, unsigned int length) 4272 { 4273 unsigned int i; 4274 int rc = 0; 4275 4276 for (i = 0; i < length; i += sizeof(u32)) { 4277 u32 val = *(u32 *)(data + i); 4278 4279 sky2_pci_write32(hw, cap + PCI_VPD_DATA, val); 4280 sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F); 4281 4282 rc = sky2_vpd_wait(hw, cap, PCI_VPD_ADDR_F); 4283 if (rc) 4284 break; 4285 } 4286 return rc; 4287 } 4288 4289 static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, 4290 u8 *data) 4291 { 4292 struct sky2_port *sky2 = netdev_priv(dev); 4293 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD); 4294 4295 if (!cap) 4296 return -EINVAL; 4297 4298 eeprom->magic = SKY2_EEPROM_MAGIC; 4299 4300 return sky2_vpd_read(sky2->hw, cap, data, eeprom->offset, eeprom->len); 4301 } 4302 4303 static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, 4304 u8 *data) 4305 { 4306 struct sky2_port *sky2 = netdev_priv(dev); 4307 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD); 4308 4309 if (!cap) 4310 return -EINVAL; 4311 4312 if (eeprom->magic != SKY2_EEPROM_MAGIC) 4313 return -EINVAL; 4314 4315 /* Partial writes not supported */ 4316 if ((eeprom->offset & 3) || (eeprom->len & 3)) 4317 return -EINVAL; 4318 4319 return sky2_vpd_write(sky2->hw, cap, data, eeprom->offset, eeprom->len); 4320 } 4321 4322 static netdev_features_t sky2_fix_features(struct net_device *dev, 4323 netdev_features_t features) 4324 { 4325 const struct sky2_port *sky2 = netdev_priv(dev); 4326 const struct sky2_hw *hw = sky2->hw; 4327 4328 /* In order to do Jumbo packets on these chips, need to turn off the 4329 * transmit store/forward. Therefore checksum offload won't work. 4330 */ 4331 if (dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U) { 4332 netdev_info(dev, "checksum offload not possible with jumbo frames\n"); 4333 features &= ~(NETIF_F_TSO|NETIF_F_SG|NETIF_F_ALL_CSUM); 4334 } 4335 4336 /* Some hardware requires receive checksum for RSS to work. */ 4337 if ( (features & NETIF_F_RXHASH) && 4338 !(features & NETIF_F_RXCSUM) && 4339 (sky2->hw->flags & SKY2_HW_RSS_CHKSUM)) { 4340 netdev_info(dev, "receive hashing forces receive checksum\n"); 4341 features |= NETIF_F_RXCSUM; 4342 } 4343 4344 return features; 4345 } 4346 4347 static int sky2_set_features(struct net_device *dev, netdev_features_t features) 4348 { 4349 struct sky2_port *sky2 = netdev_priv(dev); 4350 netdev_features_t changed = dev->features ^ features; 4351 4352 if (changed & NETIF_F_RXCSUM) { 4353 bool on = features & NETIF_F_RXCSUM; 4354 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR), 4355 on ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM); 4356 } 4357 4358 if (changed & NETIF_F_RXHASH) 4359 rx_set_rss(dev, features); 4360 4361 if (changed & (NETIF_F_HW_VLAN_TX|NETIF_F_HW_VLAN_RX)) 4362 sky2_vlan_mode(dev, features); 4363 4364 return 0; 4365 } 4366 4367 static const struct ethtool_ops sky2_ethtool_ops = { 4368 .get_settings = sky2_get_settings, 4369 .set_settings = sky2_set_settings, 4370 .get_drvinfo = sky2_get_drvinfo, 4371 .get_wol = sky2_get_wol, 4372 .set_wol = sky2_set_wol, 4373 .get_msglevel = sky2_get_msglevel, 4374 .set_msglevel = sky2_set_msglevel, 4375 .nway_reset = sky2_nway_reset, 4376 .get_regs_len = sky2_get_regs_len, 4377 .get_regs = sky2_get_regs, 4378 .get_link = ethtool_op_get_link, 4379 .get_eeprom_len = sky2_get_eeprom_len, 4380 .get_eeprom = sky2_get_eeprom, 4381 .set_eeprom = sky2_set_eeprom, 4382 .get_strings = sky2_get_strings, 4383 .get_coalesce = sky2_get_coalesce, 4384 .set_coalesce = sky2_set_coalesce, 4385 .get_ringparam = sky2_get_ringparam, 4386 .set_ringparam = sky2_set_ringparam, 4387 .get_pauseparam = sky2_get_pauseparam, 4388 .set_pauseparam = sky2_set_pauseparam, 4389 .set_phys_id = sky2_set_phys_id, 4390 .get_sset_count = sky2_get_sset_count, 4391 .get_ethtool_stats = sky2_get_ethtool_stats, 4392 }; 4393 4394 #ifdef CONFIG_SKY2_DEBUG 4395 4396 static struct dentry *sky2_debug; 4397 4398 4399 /* 4400 * Read and parse the first part of Vital Product Data 4401 */ 4402 #define VPD_SIZE 128 4403 #define VPD_MAGIC 0x82 4404 4405 static const struct vpd_tag { 4406 char tag[2]; 4407 char *label; 4408 } vpd_tags[] = { 4409 { "PN", "Part Number" }, 4410 { "EC", "Engineering Level" }, 4411 { "MN", "Manufacturer" }, 4412 { "SN", "Serial Number" }, 4413 { "YA", "Asset Tag" }, 4414 { "VL", "First Error Log Message" }, 4415 { "VF", "Second Error Log Message" }, 4416 { "VB", "Boot Agent ROM Configuration" }, 4417 { "VE", "EFI UNDI Configuration" }, 4418 }; 4419 4420 static void sky2_show_vpd(struct seq_file *seq, struct sky2_hw *hw) 4421 { 4422 size_t vpd_size; 4423 loff_t offs; 4424 u8 len; 4425 unsigned char *buf; 4426 u16 reg2; 4427 4428 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2); 4429 vpd_size = 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8); 4430 4431 seq_printf(seq, "%s Product Data\n", pci_name(hw->pdev)); 4432 buf = kmalloc(vpd_size, GFP_KERNEL); 4433 if (!buf) { 4434 seq_puts(seq, "no memory!\n"); 4435 return; 4436 } 4437 4438 if (pci_read_vpd(hw->pdev, 0, vpd_size, buf) < 0) { 4439 seq_puts(seq, "VPD read failed\n"); 4440 goto out; 4441 } 4442 4443 if (buf[0] != VPD_MAGIC) { 4444 seq_printf(seq, "VPD tag mismatch: %#x\n", buf[0]); 4445 goto out; 4446 } 4447 len = buf[1]; 4448 if (len == 0 || len > vpd_size - 4) { 4449 seq_printf(seq, "Invalid id length: %d\n", len); 4450 goto out; 4451 } 4452 4453 seq_printf(seq, "%.*s\n", len, buf + 3); 4454 offs = len + 3; 4455 4456 while (offs < vpd_size - 4) { 4457 int i; 4458 4459 if (!memcmp("RW", buf + offs, 2)) /* end marker */ 4460 break; 4461 len = buf[offs + 2]; 4462 if (offs + len + 3 >= vpd_size) 4463 break; 4464 4465 for (i = 0; i < ARRAY_SIZE(vpd_tags); i++) { 4466 if (!memcmp(vpd_tags[i].tag, buf + offs, 2)) { 4467 seq_printf(seq, " %s: %.*s\n", 4468 vpd_tags[i].label, len, buf + offs + 3); 4469 break; 4470 } 4471 } 4472 offs += len + 3; 4473 } 4474 out: 4475 kfree(buf); 4476 } 4477 4478 static int sky2_debug_show(struct seq_file *seq, void *v) 4479 { 4480 struct net_device *dev = seq->private; 4481 const struct sky2_port *sky2 = netdev_priv(dev); 4482 struct sky2_hw *hw = sky2->hw; 4483 unsigned port = sky2->port; 4484 unsigned idx, last; 4485 int sop; 4486 4487 sky2_show_vpd(seq, hw); 4488 4489 seq_printf(seq, "\nIRQ src=%x mask=%x control=%x\n", 4490 sky2_read32(hw, B0_ISRC), 4491 sky2_read32(hw, B0_IMSK), 4492 sky2_read32(hw, B0_Y2_SP_ICR)); 4493 4494 if (!netif_running(dev)) { 4495 seq_printf(seq, "network not running\n"); 4496 return 0; 4497 } 4498 4499 napi_disable(&hw->napi); 4500 last = sky2_read16(hw, STAT_PUT_IDX); 4501 4502 seq_printf(seq, "Status ring %u\n", hw->st_size); 4503 if (hw->st_idx == last) 4504 seq_puts(seq, "Status ring (empty)\n"); 4505 else { 4506 seq_puts(seq, "Status ring\n"); 4507 for (idx = hw->st_idx; idx != last && idx < hw->st_size; 4508 idx = RING_NEXT(idx, hw->st_size)) { 4509 const struct sky2_status_le *le = hw->st_le + idx; 4510 seq_printf(seq, "[%d] %#x %d %#x\n", 4511 idx, le->opcode, le->length, le->status); 4512 } 4513 seq_puts(seq, "\n"); 4514 } 4515 4516 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n", 4517 sky2->tx_cons, sky2->tx_prod, 4518 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX), 4519 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE))); 4520 4521 /* Dump contents of tx ring */ 4522 sop = 1; 4523 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < sky2->tx_ring_size; 4524 idx = RING_NEXT(idx, sky2->tx_ring_size)) { 4525 const struct sky2_tx_le *le = sky2->tx_le + idx; 4526 u32 a = le32_to_cpu(le->addr); 4527 4528 if (sop) 4529 seq_printf(seq, "%u:", idx); 4530 sop = 0; 4531 4532 switch (le->opcode & ~HW_OWNER) { 4533 case OP_ADDR64: 4534 seq_printf(seq, " %#x:", a); 4535 break; 4536 case OP_LRGLEN: 4537 seq_printf(seq, " mtu=%d", a); 4538 break; 4539 case OP_VLAN: 4540 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length)); 4541 break; 4542 case OP_TCPLISW: 4543 seq_printf(seq, " csum=%#x", a); 4544 break; 4545 case OP_LARGESEND: 4546 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length)); 4547 break; 4548 case OP_PACKET: 4549 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length)); 4550 break; 4551 case OP_BUFFER: 4552 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length)); 4553 break; 4554 default: 4555 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode, 4556 a, le16_to_cpu(le->length)); 4557 } 4558 4559 if (le->ctrl & EOP) { 4560 seq_putc(seq, '\n'); 4561 sop = 1; 4562 } 4563 } 4564 4565 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n", 4566 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)), 4567 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)), 4568 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX))); 4569 4570 sky2_read32(hw, B0_Y2_SP_LISR); 4571 napi_enable(&hw->napi); 4572 return 0; 4573 } 4574 4575 static int sky2_debug_open(struct inode *inode, struct file *file) 4576 { 4577 return single_open(file, sky2_debug_show, inode->i_private); 4578 } 4579 4580 static const struct file_operations sky2_debug_fops = { 4581 .owner = THIS_MODULE, 4582 .open = sky2_debug_open, 4583 .read = seq_read, 4584 .llseek = seq_lseek, 4585 .release = single_release, 4586 }; 4587 4588 /* 4589 * Use network device events to create/remove/rename 4590 * debugfs file entries 4591 */ 4592 static int sky2_device_event(struct notifier_block *unused, 4593 unsigned long event, void *ptr) 4594 { 4595 struct net_device *dev = ptr; 4596 struct sky2_port *sky2 = netdev_priv(dev); 4597 4598 if (dev->netdev_ops->ndo_open != sky2_open || !sky2_debug) 4599 return NOTIFY_DONE; 4600 4601 switch (event) { 4602 case NETDEV_CHANGENAME: 4603 if (sky2->debugfs) { 4604 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs, 4605 sky2_debug, dev->name); 4606 } 4607 break; 4608 4609 case NETDEV_GOING_DOWN: 4610 if (sky2->debugfs) { 4611 netdev_printk(KERN_DEBUG, dev, "remove debugfs\n"); 4612 debugfs_remove(sky2->debugfs); 4613 sky2->debugfs = NULL; 4614 } 4615 break; 4616 4617 case NETDEV_UP: 4618 sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO, 4619 sky2_debug, dev, 4620 &sky2_debug_fops); 4621 if (IS_ERR(sky2->debugfs)) 4622 sky2->debugfs = NULL; 4623 } 4624 4625 return NOTIFY_DONE; 4626 } 4627 4628 static struct notifier_block sky2_notifier = { 4629 .notifier_call = sky2_device_event, 4630 }; 4631 4632 4633 static __init void sky2_debug_init(void) 4634 { 4635 struct dentry *ent; 4636 4637 ent = debugfs_create_dir("sky2", NULL); 4638 if (!ent || IS_ERR(ent)) 4639 return; 4640 4641 sky2_debug = ent; 4642 register_netdevice_notifier(&sky2_notifier); 4643 } 4644 4645 static __exit void sky2_debug_cleanup(void) 4646 { 4647 if (sky2_debug) { 4648 unregister_netdevice_notifier(&sky2_notifier); 4649 debugfs_remove(sky2_debug); 4650 sky2_debug = NULL; 4651 } 4652 } 4653 4654 #else 4655 #define sky2_debug_init() 4656 #define sky2_debug_cleanup() 4657 #endif 4658 4659 /* Two copies of network device operations to handle special case of 4660 not allowing netpoll on second port */ 4661 static const struct net_device_ops sky2_netdev_ops[2] = { 4662 { 4663 .ndo_open = sky2_open, 4664 .ndo_stop = sky2_close, 4665 .ndo_start_xmit = sky2_xmit_frame, 4666 .ndo_do_ioctl = sky2_ioctl, 4667 .ndo_validate_addr = eth_validate_addr, 4668 .ndo_set_mac_address = sky2_set_mac_address, 4669 .ndo_set_rx_mode = sky2_set_multicast, 4670 .ndo_change_mtu = sky2_change_mtu, 4671 .ndo_fix_features = sky2_fix_features, 4672 .ndo_set_features = sky2_set_features, 4673 .ndo_tx_timeout = sky2_tx_timeout, 4674 .ndo_get_stats64 = sky2_get_stats, 4675 #ifdef CONFIG_NET_POLL_CONTROLLER 4676 .ndo_poll_controller = sky2_netpoll, 4677 #endif 4678 }, 4679 { 4680 .ndo_open = sky2_open, 4681 .ndo_stop = sky2_close, 4682 .ndo_start_xmit = sky2_xmit_frame, 4683 .ndo_do_ioctl = sky2_ioctl, 4684 .ndo_validate_addr = eth_validate_addr, 4685 .ndo_set_mac_address = sky2_set_mac_address, 4686 .ndo_set_rx_mode = sky2_set_multicast, 4687 .ndo_change_mtu = sky2_change_mtu, 4688 .ndo_fix_features = sky2_fix_features, 4689 .ndo_set_features = sky2_set_features, 4690 .ndo_tx_timeout = sky2_tx_timeout, 4691 .ndo_get_stats64 = sky2_get_stats, 4692 }, 4693 }; 4694 4695 /* Initialize network device */ 4696 static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw, 4697 unsigned port, 4698 int highmem, int wol) 4699 { 4700 struct sky2_port *sky2; 4701 struct net_device *dev = alloc_etherdev(sizeof(*sky2)); 4702 4703 if (!dev) { 4704 dev_err(&hw->pdev->dev, "etherdev alloc failed\n"); 4705 return NULL; 4706 } 4707 4708 SET_NETDEV_DEV(dev, &hw->pdev->dev); 4709 dev->irq = hw->pdev->irq; 4710 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops); 4711 dev->watchdog_timeo = TX_WATCHDOG; 4712 dev->netdev_ops = &sky2_netdev_ops[port]; 4713 4714 sky2 = netdev_priv(dev); 4715 sky2->netdev = dev; 4716 sky2->hw = hw; 4717 sky2->msg_enable = netif_msg_init(debug, default_msg); 4718 4719 /* Auto speed and flow control */ 4720 sky2->flags = SKY2_FLAG_AUTO_SPEED | SKY2_FLAG_AUTO_PAUSE; 4721 if (hw->chip_id != CHIP_ID_YUKON_XL) 4722 dev->hw_features |= NETIF_F_RXCSUM; 4723 4724 sky2->flow_mode = FC_BOTH; 4725 4726 sky2->duplex = -1; 4727 sky2->speed = -1; 4728 sky2->advertising = sky2_supported_modes(hw); 4729 sky2->wol = wol; 4730 4731 spin_lock_init(&sky2->phy_lock); 4732 4733 sky2->tx_pending = TX_DEF_PENDING; 4734 sky2->tx_ring_size = roundup_ring_size(TX_DEF_PENDING); 4735 sky2->rx_pending = RX_DEF_PENDING; 4736 4737 hw->dev[port] = dev; 4738 4739 sky2->port = port; 4740 4741 dev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_TSO; 4742 4743 if (highmem) 4744 dev->features |= NETIF_F_HIGHDMA; 4745 4746 /* Enable receive hashing unless hardware is known broken */ 4747 if (!(hw->flags & SKY2_HW_RSS_BROKEN)) 4748 dev->hw_features |= NETIF_F_RXHASH; 4749 4750 if (!(hw->flags & SKY2_HW_VLAN_BROKEN)) { 4751 dev->hw_features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; 4752 dev->vlan_features |= SKY2_VLAN_OFFLOADS; 4753 } 4754 4755 dev->features |= dev->hw_features; 4756 4757 /* read the mac address */ 4758 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN); 4759 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); 4760 4761 return dev; 4762 } 4763 4764 static void __devinit sky2_show_addr(struct net_device *dev) 4765 { 4766 const struct sky2_port *sky2 = netdev_priv(dev); 4767 4768 netif_info(sky2, probe, dev, "addr %pM\n", dev->dev_addr); 4769 } 4770 4771 /* Handle software interrupt used during MSI test */ 4772 static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id) 4773 { 4774 struct sky2_hw *hw = dev_id; 4775 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2); 4776 4777 if (status == 0) 4778 return IRQ_NONE; 4779 4780 if (status & Y2_IS_IRQ_SW) { 4781 hw->flags |= SKY2_HW_USE_MSI; 4782 wake_up(&hw->msi_wait); 4783 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ); 4784 } 4785 sky2_write32(hw, B0_Y2_SP_ICR, 2); 4786 4787 return IRQ_HANDLED; 4788 } 4789 4790 /* Test interrupt path by forcing a a software IRQ */ 4791 static int __devinit sky2_test_msi(struct sky2_hw *hw) 4792 { 4793 struct pci_dev *pdev = hw->pdev; 4794 int err; 4795 4796 init_waitqueue_head(&hw->msi_wait); 4797 4798 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW); 4799 4800 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw); 4801 if (err) { 4802 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq); 4803 return err; 4804 } 4805 4806 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ); 4807 sky2_read8(hw, B0_CTST); 4808 4809 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10); 4810 4811 if (!(hw->flags & SKY2_HW_USE_MSI)) { 4812 /* MSI test failed, go back to INTx mode */ 4813 dev_info(&pdev->dev, "No interrupt generated using MSI, " 4814 "switching to INTx mode.\n"); 4815 4816 err = -EOPNOTSUPP; 4817 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ); 4818 } 4819 4820 sky2_write32(hw, B0_IMSK, 0); 4821 sky2_read32(hw, B0_IMSK); 4822 4823 free_irq(pdev->irq, hw); 4824 4825 return err; 4826 } 4827 4828 /* This driver supports yukon2 chipset only */ 4829 static const char *sky2_name(u8 chipid, char *buf, int sz) 4830 { 4831 const char *name[] = { 4832 "XL", /* 0xb3 */ 4833 "EC Ultra", /* 0xb4 */ 4834 "Extreme", /* 0xb5 */ 4835 "EC", /* 0xb6 */ 4836 "FE", /* 0xb7 */ 4837 "FE+", /* 0xb8 */ 4838 "Supreme", /* 0xb9 */ 4839 "UL 2", /* 0xba */ 4840 "Unknown", /* 0xbb */ 4841 "Optima", /* 0xbc */ 4842 "Optima Prime", /* 0xbd */ 4843 "Optima 2", /* 0xbe */ 4844 }; 4845 4846 if (chipid >= CHIP_ID_YUKON_XL && chipid <= CHIP_ID_YUKON_OP_2) 4847 strncpy(buf, name[chipid - CHIP_ID_YUKON_XL], sz); 4848 else 4849 snprintf(buf, sz, "(chip %#x)", chipid); 4850 return buf; 4851 } 4852 4853 static int __devinit sky2_probe(struct pci_dev *pdev, 4854 const struct pci_device_id *ent) 4855 { 4856 struct net_device *dev, *dev1; 4857 struct sky2_hw *hw; 4858 int err, using_dac = 0, wol_default; 4859 u32 reg; 4860 char buf1[16]; 4861 4862 err = pci_enable_device(pdev); 4863 if (err) { 4864 dev_err(&pdev->dev, "cannot enable PCI device\n"); 4865 goto err_out; 4866 } 4867 4868 /* Get configuration information 4869 * Note: only regular PCI config access once to test for HW issues 4870 * other PCI access through shared memory for speed and to 4871 * avoid MMCONFIG problems. 4872 */ 4873 err = pci_read_config_dword(pdev, PCI_DEV_REG2, ®); 4874 if (err) { 4875 dev_err(&pdev->dev, "PCI read config failed\n"); 4876 goto err_out; 4877 } 4878 4879 if (~reg == 0) { 4880 dev_err(&pdev->dev, "PCI configuration read error\n"); 4881 goto err_out; 4882 } 4883 4884 err = pci_request_regions(pdev, DRV_NAME); 4885 if (err) { 4886 dev_err(&pdev->dev, "cannot obtain PCI resources\n"); 4887 goto err_out_disable; 4888 } 4889 4890 pci_set_master(pdev); 4891 4892 if (sizeof(dma_addr_t) > sizeof(u32) && 4893 !(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))) { 4894 using_dac = 1; 4895 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); 4896 if (err < 0) { 4897 dev_err(&pdev->dev, "unable to obtain 64 bit DMA " 4898 "for consistent allocations\n"); 4899 goto err_out_free_regions; 4900 } 4901 } else { 4902 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 4903 if (err) { 4904 dev_err(&pdev->dev, "no usable DMA configuration\n"); 4905 goto err_out_free_regions; 4906 } 4907 } 4908 4909 4910 #ifdef __BIG_ENDIAN 4911 /* The sk98lin vendor driver uses hardware byte swapping but 4912 * this driver uses software swapping. 4913 */ 4914 reg &= ~PCI_REV_DESC; 4915 err = pci_write_config_dword(pdev, PCI_DEV_REG2, reg); 4916 if (err) { 4917 dev_err(&pdev->dev, "PCI write config failed\n"); 4918 goto err_out_free_regions; 4919 } 4920 #endif 4921 4922 wol_default = device_may_wakeup(&pdev->dev) ? WAKE_MAGIC : 0; 4923 4924 err = -ENOMEM; 4925 4926 hw = kzalloc(sizeof(*hw) + strlen(DRV_NAME "@pci:") 4927 + strlen(pci_name(pdev)) + 1, GFP_KERNEL); 4928 if (!hw) { 4929 dev_err(&pdev->dev, "cannot allocate hardware struct\n"); 4930 goto err_out_free_regions; 4931 } 4932 4933 hw->pdev = pdev; 4934 sprintf(hw->irq_name, DRV_NAME "@pci:%s", pci_name(pdev)); 4935 4936 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000); 4937 if (!hw->regs) { 4938 dev_err(&pdev->dev, "cannot map device registers\n"); 4939 goto err_out_free_hw; 4940 } 4941 4942 err = sky2_init(hw); 4943 if (err) 4944 goto err_out_iounmap; 4945 4946 /* ring for status responses */ 4947 hw->st_size = hw->ports * roundup_pow_of_two(3*RX_MAX_PENDING + TX_MAX_PENDING); 4948 hw->st_le = pci_alloc_consistent(pdev, hw->st_size * sizeof(struct sky2_status_le), 4949 &hw->st_dma); 4950 if (!hw->st_le) 4951 goto err_out_reset; 4952 4953 dev_info(&pdev->dev, "Yukon-2 %s chip revision %d\n", 4954 sky2_name(hw->chip_id, buf1, sizeof(buf1)), hw->chip_rev); 4955 4956 sky2_reset(hw); 4957 4958 dev = sky2_init_netdev(hw, 0, using_dac, wol_default); 4959 if (!dev) { 4960 err = -ENOMEM; 4961 goto err_out_free_pci; 4962 } 4963 4964 if (!disable_msi && pci_enable_msi(pdev) == 0) { 4965 err = sky2_test_msi(hw); 4966 if (err == -EOPNOTSUPP) 4967 pci_disable_msi(pdev); 4968 else if (err) 4969 goto err_out_free_netdev; 4970 } 4971 4972 err = register_netdev(dev); 4973 if (err) { 4974 dev_err(&pdev->dev, "cannot register net device\n"); 4975 goto err_out_free_netdev; 4976 } 4977 4978 netif_carrier_off(dev); 4979 4980 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT); 4981 4982 sky2_show_addr(dev); 4983 4984 if (hw->ports > 1) { 4985 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default); 4986 if (!dev1) { 4987 err = -ENOMEM; 4988 goto err_out_unregister; 4989 } 4990 4991 err = register_netdev(dev1); 4992 if (err) { 4993 dev_err(&pdev->dev, "cannot register second net device\n"); 4994 goto err_out_free_dev1; 4995 } 4996 4997 err = sky2_setup_irq(hw, hw->irq_name); 4998 if (err) 4999 goto err_out_unregister_dev1; 5000 5001 sky2_show_addr(dev1); 5002 } 5003 5004 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw); 5005 INIT_WORK(&hw->restart_work, sky2_restart); 5006 5007 pci_set_drvdata(pdev, hw); 5008 pdev->d3_delay = 150; 5009 5010 return 0; 5011 5012 err_out_unregister_dev1: 5013 unregister_netdev(dev1); 5014 err_out_free_dev1: 5015 free_netdev(dev1); 5016 err_out_unregister: 5017 if (hw->flags & SKY2_HW_USE_MSI) 5018 pci_disable_msi(pdev); 5019 unregister_netdev(dev); 5020 err_out_free_netdev: 5021 free_netdev(dev); 5022 err_out_free_pci: 5023 pci_free_consistent(pdev, hw->st_size * sizeof(struct sky2_status_le), 5024 hw->st_le, hw->st_dma); 5025 err_out_reset: 5026 sky2_write8(hw, B0_CTST, CS_RST_SET); 5027 err_out_iounmap: 5028 iounmap(hw->regs); 5029 err_out_free_hw: 5030 kfree(hw); 5031 err_out_free_regions: 5032 pci_release_regions(pdev); 5033 err_out_disable: 5034 pci_disable_device(pdev); 5035 err_out: 5036 pci_set_drvdata(pdev, NULL); 5037 return err; 5038 } 5039 5040 static void __devexit sky2_remove(struct pci_dev *pdev) 5041 { 5042 struct sky2_hw *hw = pci_get_drvdata(pdev); 5043 int i; 5044 5045 if (!hw) 5046 return; 5047 5048 del_timer_sync(&hw->watchdog_timer); 5049 cancel_work_sync(&hw->restart_work); 5050 5051 for (i = hw->ports-1; i >= 0; --i) 5052 unregister_netdev(hw->dev[i]); 5053 5054 sky2_write32(hw, B0_IMSK, 0); 5055 sky2_read32(hw, B0_IMSK); 5056 5057 sky2_power_aux(hw); 5058 5059 sky2_write8(hw, B0_CTST, CS_RST_SET); 5060 sky2_read8(hw, B0_CTST); 5061 5062 if (hw->ports > 1) { 5063 napi_disable(&hw->napi); 5064 free_irq(pdev->irq, hw); 5065 } 5066 5067 if (hw->flags & SKY2_HW_USE_MSI) 5068 pci_disable_msi(pdev); 5069 pci_free_consistent(pdev, hw->st_size * sizeof(struct sky2_status_le), 5070 hw->st_le, hw->st_dma); 5071 pci_release_regions(pdev); 5072 pci_disable_device(pdev); 5073 5074 for (i = hw->ports-1; i >= 0; --i) 5075 free_netdev(hw->dev[i]); 5076 5077 iounmap(hw->regs); 5078 kfree(hw); 5079 5080 pci_set_drvdata(pdev, NULL); 5081 } 5082 5083 static int sky2_suspend(struct device *dev) 5084 { 5085 struct pci_dev *pdev = to_pci_dev(dev); 5086 struct sky2_hw *hw = pci_get_drvdata(pdev); 5087 int i; 5088 5089 if (!hw) 5090 return 0; 5091 5092 del_timer_sync(&hw->watchdog_timer); 5093 cancel_work_sync(&hw->restart_work); 5094 5095 rtnl_lock(); 5096 5097 sky2_all_down(hw); 5098 for (i = 0; i < hw->ports; i++) { 5099 struct net_device *dev = hw->dev[i]; 5100 struct sky2_port *sky2 = netdev_priv(dev); 5101 5102 if (sky2->wol) 5103 sky2_wol_init(sky2); 5104 } 5105 5106 sky2_power_aux(hw); 5107 rtnl_unlock(); 5108 5109 return 0; 5110 } 5111 5112 #ifdef CONFIG_PM_SLEEP 5113 static int sky2_resume(struct device *dev) 5114 { 5115 struct pci_dev *pdev = to_pci_dev(dev); 5116 struct sky2_hw *hw = pci_get_drvdata(pdev); 5117 int err; 5118 5119 if (!hw) 5120 return 0; 5121 5122 /* Re-enable all clocks */ 5123 err = pci_write_config_dword(pdev, PCI_DEV_REG3, 0); 5124 if (err) { 5125 dev_err(&pdev->dev, "PCI write config failed\n"); 5126 goto out; 5127 } 5128 5129 rtnl_lock(); 5130 sky2_reset(hw); 5131 sky2_all_up(hw); 5132 rtnl_unlock(); 5133 5134 return 0; 5135 out: 5136 5137 dev_err(&pdev->dev, "resume failed (%d)\n", err); 5138 pci_disable_device(pdev); 5139 return err; 5140 } 5141 5142 static SIMPLE_DEV_PM_OPS(sky2_pm_ops, sky2_suspend, sky2_resume); 5143 #define SKY2_PM_OPS (&sky2_pm_ops) 5144 5145 #else 5146 5147 #define SKY2_PM_OPS NULL 5148 #endif 5149 5150 static void sky2_shutdown(struct pci_dev *pdev) 5151 { 5152 sky2_suspend(&pdev->dev); 5153 pci_wake_from_d3(pdev, device_may_wakeup(&pdev->dev)); 5154 pci_set_power_state(pdev, PCI_D3hot); 5155 } 5156 5157 static struct pci_driver sky2_driver = { 5158 .name = DRV_NAME, 5159 .id_table = sky2_id_table, 5160 .probe = sky2_probe, 5161 .remove = __devexit_p(sky2_remove), 5162 .shutdown = sky2_shutdown, 5163 .driver.pm = SKY2_PM_OPS, 5164 }; 5165 5166 static int __init sky2_init_module(void) 5167 { 5168 pr_info("driver version " DRV_VERSION "\n"); 5169 5170 sky2_debug_init(); 5171 return pci_register_driver(&sky2_driver); 5172 } 5173 5174 static void __exit sky2_cleanup_module(void) 5175 { 5176 pci_unregister_driver(&sky2_driver); 5177 sky2_debug_cleanup(); 5178 } 5179 5180 module_init(sky2_init_module); 5181 module_exit(sky2_cleanup_module); 5182 5183 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver"); 5184 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>"); 5185 MODULE_LICENSE("GPL"); 5186 MODULE_VERSION(DRV_VERSION); 5187