1 /* 2 * New driver for Marvell Yukon 2 chipset. 3 * Based on earlier sk98lin, and skge driver. 4 * 5 * This driver intentionally does not support all the features 6 * of the original driver such as link fail-over and link management because 7 * those should be done at higher levels. 8 * 9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org> 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 23 */ 24 25 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 26 27 #include <linux/crc32.h> 28 #include <linux/kernel.h> 29 #include <linux/module.h> 30 #include <linux/netdevice.h> 31 #include <linux/dma-mapping.h> 32 #include <linux/etherdevice.h> 33 #include <linux/ethtool.h> 34 #include <linux/pci.h> 35 #include <linux/interrupt.h> 36 #include <linux/ip.h> 37 #include <linux/slab.h> 38 #include <net/ip.h> 39 #include <linux/tcp.h> 40 #include <linux/in.h> 41 #include <linux/delay.h> 42 #include <linux/workqueue.h> 43 #include <linux/if_vlan.h> 44 #include <linux/prefetch.h> 45 #include <linux/debugfs.h> 46 #include <linux/mii.h> 47 48 #include <asm/irq.h> 49 50 #include "sky2.h" 51 52 #define DRV_NAME "sky2" 53 #define DRV_VERSION "1.29" 54 55 /* 56 * The Yukon II chipset takes 64 bit command blocks (called list elements) 57 * that are organized into three (receive, transmit, status) different rings 58 * similar to Tigon3. 59 */ 60 61 #define RX_LE_SIZE 1024 62 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le)) 63 #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2) 64 #define RX_DEF_PENDING RX_MAX_PENDING 65 66 /* This is the worst case number of transmit list elements for a single skb: 67 VLAN:GSO + CKSUM + Data + skb_frags * DMA */ 68 #define MAX_SKB_TX_LE (2 + (sizeof(dma_addr_t)/sizeof(u32))*(MAX_SKB_FRAGS+1)) 69 #define TX_MIN_PENDING (MAX_SKB_TX_LE+1) 70 #define TX_MAX_PENDING 1024 71 #define TX_DEF_PENDING 127 72 73 #define TX_WATCHDOG (5 * HZ) 74 #define NAPI_WEIGHT 64 75 #define PHY_RETRIES 1000 76 77 #define SKY2_EEPROM_MAGIC 0x9955aabb 78 79 #define RING_NEXT(x, s) (((x)+1) & ((s)-1)) 80 81 static const u32 default_msg = 82 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK 83 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR 84 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN; 85 86 static int debug = -1; /* defaults above */ 87 module_param(debug, int, 0); 88 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 89 90 static int copybreak __read_mostly = 128; 91 module_param(copybreak, int, 0); 92 MODULE_PARM_DESC(copybreak, "Receive copy threshold"); 93 94 static int disable_msi = 0; 95 module_param(disable_msi, int, 0); 96 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)"); 97 98 static DEFINE_PCI_DEVICE_TABLE(sky2_id_table) = { 99 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */ 100 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */ 101 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E01) }, /* SK-9E21M */ 102 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */ 103 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */ 104 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */ 105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */ 106 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */ 107 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */ 108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */ 109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */ 110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */ 111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */ 112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */ 113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */ 114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */ 115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */ 116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */ 117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */ 118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */ 119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4355) }, /* 88E8040T */ 120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */ 121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */ 122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */ 123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */ 124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */ 125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */ 126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */ 127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */ 128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */ 129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */ 130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */ 131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */ 132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */ 133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */ 134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */ 135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */ 136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */ 137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */ 138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4380) }, /* 88E8057 */ 139 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4381) }, /* 88E8059 */ 140 { 0 } 141 }; 142 143 MODULE_DEVICE_TABLE(pci, sky2_id_table); 144 145 /* Avoid conditionals by using array */ 146 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 }; 147 static const unsigned rxqaddr[] = { Q_R1, Q_R2 }; 148 static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 }; 149 150 static void sky2_set_multicast(struct net_device *dev); 151 152 /* Access to PHY via serial interconnect */ 153 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val) 154 { 155 int i; 156 157 gma_write16(hw, port, GM_SMI_DATA, val); 158 gma_write16(hw, port, GM_SMI_CTRL, 159 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg)); 160 161 for (i = 0; i < PHY_RETRIES; i++) { 162 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL); 163 if (ctrl == 0xffff) 164 goto io_error; 165 166 if (!(ctrl & GM_SMI_CT_BUSY)) 167 return 0; 168 169 udelay(10); 170 } 171 172 dev_warn(&hw->pdev->dev, "%s: phy write timeout\n", hw->dev[port]->name); 173 return -ETIMEDOUT; 174 175 io_error: 176 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name); 177 return -EIO; 178 } 179 180 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val) 181 { 182 int i; 183 184 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) 185 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD); 186 187 for (i = 0; i < PHY_RETRIES; i++) { 188 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL); 189 if (ctrl == 0xffff) 190 goto io_error; 191 192 if (ctrl & GM_SMI_CT_RD_VAL) { 193 *val = gma_read16(hw, port, GM_SMI_DATA); 194 return 0; 195 } 196 197 udelay(10); 198 } 199 200 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name); 201 return -ETIMEDOUT; 202 io_error: 203 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name); 204 return -EIO; 205 } 206 207 static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg) 208 { 209 u16 v; 210 __gm_phy_read(hw, port, reg, &v); 211 return v; 212 } 213 214 215 static void sky2_power_on(struct sky2_hw *hw) 216 { 217 /* switch power to VCC (WA for VAUX problem) */ 218 sky2_write8(hw, B0_POWER_CTRL, 219 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON); 220 221 /* disable Core Clock Division, */ 222 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS); 223 224 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1) 225 /* enable bits are inverted */ 226 sky2_write8(hw, B2_Y2_CLK_GATE, 227 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | 228 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | 229 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS); 230 else 231 sky2_write8(hw, B2_Y2_CLK_GATE, 0); 232 233 if (hw->flags & SKY2_HW_ADV_POWER_CTL) { 234 u32 reg; 235 236 sky2_pci_write32(hw, PCI_DEV_REG3, 0); 237 238 reg = sky2_pci_read32(hw, PCI_DEV_REG4); 239 /* set all bits to 0 except bits 15..12 and 8 */ 240 reg &= P_ASPM_CONTROL_MSK; 241 sky2_pci_write32(hw, PCI_DEV_REG4, reg); 242 243 reg = sky2_pci_read32(hw, PCI_DEV_REG5); 244 /* set all bits to 0 except bits 28 & 27 */ 245 reg &= P_CTL_TIM_VMAIN_AV_MSK; 246 sky2_pci_write32(hw, PCI_DEV_REG5, reg); 247 248 sky2_pci_write32(hw, PCI_CFG_REG_1, 0); 249 250 sky2_write16(hw, B0_CTST, Y2_HW_WOL_ON); 251 252 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */ 253 reg = sky2_read32(hw, B2_GP_IO); 254 reg |= GLB_GPIO_STAT_RACE_DIS; 255 sky2_write32(hw, B2_GP_IO, reg); 256 257 sky2_read32(hw, B2_GP_IO); 258 } 259 260 /* Turn on "driver loaded" LED */ 261 sky2_write16(hw, B0_CTST, Y2_LED_STAT_ON); 262 } 263 264 static void sky2_power_aux(struct sky2_hw *hw) 265 { 266 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1) 267 sky2_write8(hw, B2_Y2_CLK_GATE, 0); 268 else 269 /* enable bits are inverted */ 270 sky2_write8(hw, B2_Y2_CLK_GATE, 271 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | 272 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | 273 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS); 274 275 /* switch power to VAUX if supported and PME from D3cold */ 276 if ( (sky2_read32(hw, B0_CTST) & Y2_VAUX_AVAIL) && 277 pci_pme_capable(hw->pdev, PCI_D3cold)) 278 sky2_write8(hw, B0_POWER_CTRL, 279 (PC_VAUX_ENA | PC_VCC_ENA | 280 PC_VAUX_ON | PC_VCC_OFF)); 281 282 /* turn off "driver loaded LED" */ 283 sky2_write16(hw, B0_CTST, Y2_LED_STAT_OFF); 284 } 285 286 static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port) 287 { 288 u16 reg; 289 290 /* disable all GMAC IRQ's */ 291 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0); 292 293 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */ 294 gma_write16(hw, port, GM_MC_ADDR_H2, 0); 295 gma_write16(hw, port, GM_MC_ADDR_H3, 0); 296 gma_write16(hw, port, GM_MC_ADDR_H4, 0); 297 298 reg = gma_read16(hw, port, GM_RX_CTRL); 299 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA; 300 gma_write16(hw, port, GM_RX_CTRL, reg); 301 } 302 303 /* flow control to advertise bits */ 304 static const u16 copper_fc_adv[] = { 305 [FC_NONE] = 0, 306 [FC_TX] = PHY_M_AN_ASP, 307 [FC_RX] = PHY_M_AN_PC, 308 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP, 309 }; 310 311 /* flow control to advertise bits when using 1000BaseX */ 312 static const u16 fiber_fc_adv[] = { 313 [FC_NONE] = PHY_M_P_NO_PAUSE_X, 314 [FC_TX] = PHY_M_P_ASYM_MD_X, 315 [FC_RX] = PHY_M_P_SYM_MD_X, 316 [FC_BOTH] = PHY_M_P_BOTH_MD_X, 317 }; 318 319 /* flow control to GMA disable bits */ 320 static const u16 gm_fc_disable[] = { 321 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS, 322 [FC_TX] = GM_GPCR_FC_RX_DIS, 323 [FC_RX] = GM_GPCR_FC_TX_DIS, 324 [FC_BOTH] = 0, 325 }; 326 327 328 static void sky2_phy_init(struct sky2_hw *hw, unsigned port) 329 { 330 struct sky2_port *sky2 = netdev_priv(hw->dev[port]); 331 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg; 332 333 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) && 334 !(hw->flags & SKY2_HW_NEWER_PHY)) { 335 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL); 336 337 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK | 338 PHY_M_EC_MAC_S_MSK); 339 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ); 340 341 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */ 342 if (hw->chip_id == CHIP_ID_YUKON_EC) 343 /* set downshift counter to 3x and enable downshift */ 344 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA; 345 else 346 /* set master & slave downshift counter to 1x */ 347 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1); 348 349 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl); 350 } 351 352 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); 353 if (sky2_is_copper(hw)) { 354 if (!(hw->flags & SKY2_HW_GIGABIT)) { 355 /* enable automatic crossover */ 356 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1; 357 358 if (hw->chip_id == CHIP_ID_YUKON_FE_P && 359 hw->chip_rev == CHIP_REV_YU_FE2_A0) { 360 u16 spec; 361 362 /* Enable Class A driver for FE+ A0 */ 363 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2); 364 spec |= PHY_M_FESC_SEL_CL_A; 365 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec); 366 } 367 } else { 368 if (hw->chip_id >= CHIP_ID_YUKON_OPT) { 369 u16 ctrl2 = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL_2); 370 371 /* enable PHY Reverse Auto-Negotiation */ 372 ctrl2 |= 1u << 13; 373 374 /* Write PHY changes (SW-reset must follow) */ 375 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL_2, ctrl2); 376 } 377 378 379 /* disable energy detect */ 380 ctrl &= ~PHY_M_PC_EN_DET_MSK; 381 382 /* enable automatic crossover */ 383 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO); 384 385 /* downshift on PHY 88E1112 and 88E1149 is changed */ 386 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) && 387 (hw->flags & SKY2_HW_NEWER_PHY)) { 388 /* set downshift counter to 3x and enable downshift */ 389 ctrl &= ~PHY_M_PC_DSC_MSK; 390 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA; 391 } 392 } 393 } else { 394 /* workaround for deviation #4.88 (CRC errors) */ 395 /* disable Automatic Crossover */ 396 397 ctrl &= ~PHY_M_PC_MDIX_MSK; 398 } 399 400 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); 401 402 /* special setup for PHY 88E1112 Fiber */ 403 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) { 404 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); 405 406 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */ 407 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2); 408 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); 409 ctrl &= ~PHY_M_MAC_MD_MSK; 410 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX); 411 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); 412 413 if (hw->pmd_type == 'P') { 414 /* select page 1 to access Fiber registers */ 415 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1); 416 417 /* for SFP-module set SIGDET polarity to low */ 418 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); 419 ctrl |= PHY_M_FIB_SIGD_POL; 420 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); 421 } 422 423 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); 424 } 425 426 ctrl = PHY_CT_RESET; 427 ct1000 = 0; 428 adv = PHY_AN_CSMA; 429 reg = 0; 430 431 if (sky2->flags & SKY2_FLAG_AUTO_SPEED) { 432 if (sky2_is_copper(hw)) { 433 if (sky2->advertising & ADVERTISED_1000baseT_Full) 434 ct1000 |= PHY_M_1000C_AFD; 435 if (sky2->advertising & ADVERTISED_1000baseT_Half) 436 ct1000 |= PHY_M_1000C_AHD; 437 if (sky2->advertising & ADVERTISED_100baseT_Full) 438 adv |= PHY_M_AN_100_FD; 439 if (sky2->advertising & ADVERTISED_100baseT_Half) 440 adv |= PHY_M_AN_100_HD; 441 if (sky2->advertising & ADVERTISED_10baseT_Full) 442 adv |= PHY_M_AN_10_FD; 443 if (sky2->advertising & ADVERTISED_10baseT_Half) 444 adv |= PHY_M_AN_10_HD; 445 446 } else { /* special defines for FIBER (88E1040S only) */ 447 if (sky2->advertising & ADVERTISED_1000baseT_Full) 448 adv |= PHY_M_AN_1000X_AFD; 449 if (sky2->advertising & ADVERTISED_1000baseT_Half) 450 adv |= PHY_M_AN_1000X_AHD; 451 } 452 453 /* Restart Auto-negotiation */ 454 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG; 455 } else { 456 /* forced speed/duplex settings */ 457 ct1000 = PHY_M_1000C_MSE; 458 459 /* Disable auto update for duplex flow control and duplex */ 460 reg |= GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_SPD_DIS; 461 462 switch (sky2->speed) { 463 case SPEED_1000: 464 ctrl |= PHY_CT_SP1000; 465 reg |= GM_GPCR_SPEED_1000; 466 break; 467 case SPEED_100: 468 ctrl |= PHY_CT_SP100; 469 reg |= GM_GPCR_SPEED_100; 470 break; 471 } 472 473 if (sky2->duplex == DUPLEX_FULL) { 474 reg |= GM_GPCR_DUP_FULL; 475 ctrl |= PHY_CT_DUP_MD; 476 } else if (sky2->speed < SPEED_1000) 477 sky2->flow_mode = FC_NONE; 478 } 479 480 if (sky2->flags & SKY2_FLAG_AUTO_PAUSE) { 481 if (sky2_is_copper(hw)) 482 adv |= copper_fc_adv[sky2->flow_mode]; 483 else 484 adv |= fiber_fc_adv[sky2->flow_mode]; 485 } else { 486 reg |= GM_GPCR_AU_FCT_DIS; 487 reg |= gm_fc_disable[sky2->flow_mode]; 488 489 /* Forward pause packets to GMAC? */ 490 if (sky2->flow_mode & FC_RX) 491 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON); 492 else 493 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); 494 } 495 496 gma_write16(hw, port, GM_GP_CTRL, reg); 497 498 if (hw->flags & SKY2_HW_GIGABIT) 499 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000); 500 501 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv); 502 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl); 503 504 /* Setup Phy LED's */ 505 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS); 506 ledover = 0; 507 508 switch (hw->chip_id) { 509 case CHIP_ID_YUKON_FE: 510 /* on 88E3082 these bits are at 11..9 (shifted left) */ 511 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1; 512 513 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR); 514 515 /* delete ACT LED control bits */ 516 ctrl &= ~PHY_M_FELP_LED1_MSK; 517 /* change ACT LED control to blink mode */ 518 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL); 519 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl); 520 break; 521 522 case CHIP_ID_YUKON_FE_P: 523 /* Enable Link Partner Next Page */ 524 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); 525 ctrl |= PHY_M_PC_ENA_LIP_NP; 526 527 /* disable Energy Detect and enable scrambler */ 528 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB); 529 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); 530 531 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */ 532 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) | 533 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) | 534 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED); 535 536 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl); 537 break; 538 539 case CHIP_ID_YUKON_XL: 540 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); 541 542 /* select page 3 to access LED control register */ 543 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); 544 545 /* set LED Function Control register */ 546 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, 547 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */ 548 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */ 549 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */ 550 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */ 551 552 /* set Polarity Control register */ 553 gm_phy_write(hw, port, PHY_MARV_PHY_STAT, 554 (PHY_M_POLC_LS1_P_MIX(4) | 555 PHY_M_POLC_IS0_P_MIX(4) | 556 PHY_M_POLC_LOS_CTRL(2) | 557 PHY_M_POLC_INIT_CTRL(2) | 558 PHY_M_POLC_STA1_CTRL(2) | 559 PHY_M_POLC_STA0_CTRL(2))); 560 561 /* restore page register */ 562 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); 563 break; 564 565 case CHIP_ID_YUKON_EC_U: 566 case CHIP_ID_YUKON_EX: 567 case CHIP_ID_YUKON_SUPR: 568 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); 569 570 /* select page 3 to access LED control register */ 571 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); 572 573 /* set LED Function Control register */ 574 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, 575 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */ 576 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */ 577 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */ 578 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */ 579 580 /* set Blink Rate in LED Timer Control Register */ 581 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 582 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS)); 583 /* restore page register */ 584 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); 585 break; 586 587 default: 588 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */ 589 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL; 590 591 /* turn off the Rx LED (LED_RX) */ 592 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF); 593 } 594 595 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_UL_2) { 596 /* apply fixes in PHY AFE */ 597 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255); 598 599 /* increase differential signal amplitude in 10BASE-T */ 600 gm_phy_write(hw, port, 0x18, 0xaa99); 601 gm_phy_write(hw, port, 0x17, 0x2011); 602 603 if (hw->chip_id == CHIP_ID_YUKON_EC_U) { 604 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */ 605 gm_phy_write(hw, port, 0x18, 0xa204); 606 gm_phy_write(hw, port, 0x17, 0x2002); 607 } 608 609 /* set page register to 0 */ 610 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0); 611 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P && 612 hw->chip_rev == CHIP_REV_YU_FE2_A0) { 613 /* apply workaround for integrated resistors calibration */ 614 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17); 615 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60); 616 } else if (hw->chip_id == CHIP_ID_YUKON_OPT && hw->chip_rev == 0) { 617 /* apply fixes in PHY AFE */ 618 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00ff); 619 620 /* apply RDAC termination workaround */ 621 gm_phy_write(hw, port, 24, 0x2800); 622 gm_phy_write(hw, port, 23, 0x2001); 623 624 /* set page register back to 0 */ 625 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0); 626 } else if (hw->chip_id != CHIP_ID_YUKON_EX && 627 hw->chip_id < CHIP_ID_YUKON_SUPR) { 628 /* no effect on Yukon-XL */ 629 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl); 630 631 if (!(sky2->flags & SKY2_FLAG_AUTO_SPEED) || 632 sky2->speed == SPEED_100) { 633 /* turn on 100 Mbps LED (LED_LINK100) */ 634 ledover |= PHY_M_LED_MO_100(MO_LED_ON); 635 } 636 637 if (ledover) 638 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover); 639 640 } else if (hw->chip_id == CHIP_ID_YUKON_PRM && 641 (sky2_read8(hw, B2_MAC_CFG) & 0xf) == 0x7) { 642 int i; 643 /* This a phy register setup workaround copied from vendor driver. */ 644 static const struct { 645 u16 reg, val; 646 } eee_afe[] = { 647 { 0x156, 0x58ce }, 648 { 0x153, 0x99eb }, 649 { 0x141, 0x8064 }, 650 /* { 0x155, 0x130b },*/ 651 { 0x000, 0x0000 }, 652 { 0x151, 0x8433 }, 653 { 0x14b, 0x8c44 }, 654 { 0x14c, 0x0f90 }, 655 { 0x14f, 0x39aa }, 656 /* { 0x154, 0x2f39 },*/ 657 { 0x14d, 0xba33 }, 658 { 0x144, 0x0048 }, 659 { 0x152, 0x2010 }, 660 /* { 0x158, 0x1223 },*/ 661 { 0x140, 0x4444 }, 662 { 0x154, 0x2f3b }, 663 { 0x158, 0xb203 }, 664 { 0x157, 0x2029 }, 665 }; 666 667 /* Start Workaround for OptimaEEE Rev.Z0 */ 668 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00fb); 669 670 gm_phy_write(hw, port, 1, 0x4099); 671 gm_phy_write(hw, port, 3, 0x1120); 672 gm_phy_write(hw, port, 11, 0x113c); 673 gm_phy_write(hw, port, 14, 0x8100); 674 gm_phy_write(hw, port, 15, 0x112a); 675 gm_phy_write(hw, port, 17, 0x1008); 676 677 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00fc); 678 gm_phy_write(hw, port, 1, 0x20b0); 679 680 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00ff); 681 682 for (i = 0; i < ARRAY_SIZE(eee_afe); i++) { 683 /* apply AFE settings */ 684 gm_phy_write(hw, port, 17, eee_afe[i].val); 685 gm_phy_write(hw, port, 16, eee_afe[i].reg | 1u<<13); 686 } 687 688 /* End Workaround for OptimaEEE */ 689 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0); 690 691 /* Enable 10Base-Te (EEE) */ 692 if (hw->chip_id >= CHIP_ID_YUKON_PRM) { 693 reg = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL); 694 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, 695 reg | PHY_M_10B_TE_ENABLE); 696 } 697 } 698 699 /* Enable phy interrupt on auto-negotiation complete (or link up) */ 700 if (sky2->flags & SKY2_FLAG_AUTO_SPEED) 701 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL); 702 else 703 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK); 704 } 705 706 static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD }; 707 static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA }; 708 709 static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port) 710 { 711 u32 reg1; 712 713 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); 714 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1); 715 reg1 &= ~phy_power[port]; 716 717 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1) 718 reg1 |= coma_mode[port]; 719 720 sky2_pci_write32(hw, PCI_DEV_REG1, reg1); 721 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 722 sky2_pci_read32(hw, PCI_DEV_REG1); 723 724 if (hw->chip_id == CHIP_ID_YUKON_FE) 725 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_ANE); 726 else if (hw->flags & SKY2_HW_ADV_POWER_CTL) 727 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR); 728 } 729 730 static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port) 731 { 732 u32 reg1; 733 u16 ctrl; 734 735 /* release GPHY Control reset */ 736 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR); 737 738 /* release GMAC reset */ 739 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR); 740 741 if (hw->flags & SKY2_HW_NEWER_PHY) { 742 /* select page 2 to access MAC control register */ 743 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2); 744 745 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); 746 /* allow GMII Power Down */ 747 ctrl &= ~PHY_M_MAC_GMIF_PUP; 748 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); 749 750 /* set page register back to 0 */ 751 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0); 752 } 753 754 /* setup General Purpose Control Register */ 755 gma_write16(hw, port, GM_GP_CTRL, 756 GM_GPCR_FL_PASS | GM_GPCR_SPEED_100 | 757 GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS | 758 GM_GPCR_AU_SPD_DIS); 759 760 if (hw->chip_id != CHIP_ID_YUKON_EC) { 761 if (hw->chip_id == CHIP_ID_YUKON_EC_U) { 762 /* select page 2 to access MAC control register */ 763 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2); 764 765 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); 766 /* enable Power Down */ 767 ctrl |= PHY_M_PC_POW_D_ENA; 768 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); 769 770 /* set page register back to 0 */ 771 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0); 772 } 773 774 /* set IEEE compatible Power Down Mode (dev. #4.99) */ 775 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_PDOWN); 776 } 777 778 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); 779 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1); 780 reg1 |= phy_power[port]; /* set PHY to PowerDown/COMA Mode */ 781 sky2_pci_write32(hw, PCI_DEV_REG1, reg1); 782 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 783 } 784 785 /* configure IPG according to used link speed */ 786 static void sky2_set_ipg(struct sky2_port *sky2) 787 { 788 u16 reg; 789 790 reg = gma_read16(sky2->hw, sky2->port, GM_SERIAL_MODE); 791 reg &= ~GM_SMOD_IPG_MSK; 792 if (sky2->speed > SPEED_100) 793 reg |= IPG_DATA_VAL(IPG_DATA_DEF_1000); 794 else 795 reg |= IPG_DATA_VAL(IPG_DATA_DEF_10_100); 796 gma_write16(sky2->hw, sky2->port, GM_SERIAL_MODE, reg); 797 } 798 799 /* Enable Rx/Tx */ 800 static void sky2_enable_rx_tx(struct sky2_port *sky2) 801 { 802 struct sky2_hw *hw = sky2->hw; 803 unsigned port = sky2->port; 804 u16 reg; 805 806 reg = gma_read16(hw, port, GM_GP_CTRL); 807 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA; 808 gma_write16(hw, port, GM_GP_CTRL, reg); 809 } 810 811 /* Force a renegotiation */ 812 static void sky2_phy_reinit(struct sky2_port *sky2) 813 { 814 spin_lock_bh(&sky2->phy_lock); 815 sky2_phy_init(sky2->hw, sky2->port); 816 sky2_enable_rx_tx(sky2); 817 spin_unlock_bh(&sky2->phy_lock); 818 } 819 820 /* Put device in state to listen for Wake On Lan */ 821 static void sky2_wol_init(struct sky2_port *sky2) 822 { 823 struct sky2_hw *hw = sky2->hw; 824 unsigned port = sky2->port; 825 enum flow_control save_mode; 826 u16 ctrl; 827 828 /* Bring hardware out of reset */ 829 sky2_write16(hw, B0_CTST, CS_RST_CLR); 830 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR); 831 832 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR); 833 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR); 834 835 /* Force to 10/100 836 * sky2_reset will re-enable on resume 837 */ 838 save_mode = sky2->flow_mode; 839 ctrl = sky2->advertising; 840 841 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full); 842 sky2->flow_mode = FC_NONE; 843 844 spin_lock_bh(&sky2->phy_lock); 845 sky2_phy_power_up(hw, port); 846 sky2_phy_init(hw, port); 847 spin_unlock_bh(&sky2->phy_lock); 848 849 sky2->flow_mode = save_mode; 850 sky2->advertising = ctrl; 851 852 /* Set GMAC to no flow control and auto update for speed/duplex */ 853 gma_write16(hw, port, GM_GP_CTRL, 854 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA| 855 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS); 856 857 /* Set WOL address */ 858 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR), 859 sky2->netdev->dev_addr, ETH_ALEN); 860 861 /* Turn on appropriate WOL control bits */ 862 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT); 863 ctrl = 0; 864 if (sky2->wol & WAKE_PHY) 865 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT; 866 else 867 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT; 868 869 if (sky2->wol & WAKE_MAGIC) 870 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT; 871 else 872 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT; 873 874 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT; 875 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl); 876 877 /* Disable PiG firmware */ 878 sky2_write16(hw, B0_CTST, Y2_HW_WOL_OFF); 879 880 /* block receiver */ 881 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET); 882 } 883 884 static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port) 885 { 886 struct net_device *dev = hw->dev[port]; 887 888 if ( (hw->chip_id == CHIP_ID_YUKON_EX && 889 hw->chip_rev != CHIP_REV_YU_EX_A0) || 890 hw->chip_id >= CHIP_ID_YUKON_FE_P) { 891 /* Yukon-Extreme B0 and further Extreme devices */ 892 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA); 893 } else if (dev->mtu > ETH_DATA_LEN) { 894 /* set Tx GMAC FIFO Almost Empty Threshold */ 895 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 896 (ECU_JUMBO_WM << 16) | ECU_AE_THR); 897 898 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS); 899 } else 900 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA); 901 } 902 903 static void sky2_mac_init(struct sky2_hw *hw, unsigned port) 904 { 905 struct sky2_port *sky2 = netdev_priv(hw->dev[port]); 906 u16 reg; 907 u32 rx_reg; 908 int i; 909 const u8 *addr = hw->dev[port]->dev_addr; 910 911 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET); 912 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR); 913 914 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR); 915 916 if (hw->chip_id == CHIP_ID_YUKON_XL && 917 hw->chip_rev == CHIP_REV_YU_XL_A0 && 918 port == 1) { 919 /* WA DEV_472 -- looks like crossed wires on port 2 */ 920 /* clear GMAC 1 Control reset */ 921 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR); 922 do { 923 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET); 924 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR); 925 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL || 926 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 || 927 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0); 928 } 929 930 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC)); 931 932 /* Enable Transmit FIFO Underrun */ 933 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK); 934 935 spin_lock_bh(&sky2->phy_lock); 936 sky2_phy_power_up(hw, port); 937 sky2_phy_init(hw, port); 938 spin_unlock_bh(&sky2->phy_lock); 939 940 /* MIB clear */ 941 reg = gma_read16(hw, port, GM_PHY_ADDR); 942 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR); 943 944 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4) 945 gma_read16(hw, port, i); 946 gma_write16(hw, port, GM_PHY_ADDR, reg); 947 948 /* transmit control */ 949 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF)); 950 951 /* receive control reg: unicast + multicast + no FCS */ 952 gma_write16(hw, port, GM_RX_CTRL, 953 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA); 954 955 /* transmit flow control */ 956 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff); 957 958 /* transmit parameter */ 959 gma_write16(hw, port, GM_TX_PARAM, 960 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) | 961 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) | 962 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) | 963 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF)); 964 965 /* serial mode register */ 966 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) | 967 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF_1000); 968 969 if (hw->dev[port]->mtu > ETH_DATA_LEN) 970 reg |= GM_SMOD_JUMBO_ENA; 971 972 if (hw->chip_id == CHIP_ID_YUKON_EC_U && 973 hw->chip_rev == CHIP_REV_YU_EC_U_B1) 974 reg |= GM_NEW_FLOW_CTRL; 975 976 gma_write16(hw, port, GM_SERIAL_MODE, reg); 977 978 /* virtual address for data */ 979 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr); 980 981 /* physical address: used for pause frames */ 982 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr); 983 984 /* ignore counter overflows */ 985 gma_write16(hw, port, GM_TX_IRQ_MSK, 0); 986 gma_write16(hw, port, GM_RX_IRQ_MSK, 0); 987 gma_write16(hw, port, GM_TR_IRQ_MSK, 0); 988 989 /* Configure Rx MAC FIFO */ 990 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR); 991 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON; 992 if (hw->chip_id == CHIP_ID_YUKON_EX || 993 hw->chip_id == CHIP_ID_YUKON_FE_P) 994 rx_reg |= GMF_RX_OVER_ON; 995 996 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg); 997 998 if (hw->chip_id == CHIP_ID_YUKON_XL) { 999 /* Hardware errata - clear flush mask */ 1000 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0); 1001 } else { 1002 /* Flush Rx MAC FIFO on any flow control or error */ 1003 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR); 1004 } 1005 1006 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */ 1007 reg = RX_GMF_FL_THR_DEF + 1; 1008 /* Another magic mystery workaround from sk98lin */ 1009 if (hw->chip_id == CHIP_ID_YUKON_FE_P && 1010 hw->chip_rev == CHIP_REV_YU_FE2_A0) 1011 reg = 0x178; 1012 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg); 1013 1014 /* Configure Tx MAC FIFO */ 1015 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR); 1016 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON); 1017 1018 /* On chips without ram buffer, pause is controlled by MAC level */ 1019 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) { 1020 /* Pause threshold is scaled by 8 in bytes */ 1021 if (hw->chip_id == CHIP_ID_YUKON_FE_P && 1022 hw->chip_rev == CHIP_REV_YU_FE2_A0) 1023 reg = 1568 / 8; 1024 else 1025 reg = 1024 / 8; 1026 sky2_write16(hw, SK_REG(port, RX_GMF_UP_THR), reg); 1027 sky2_write16(hw, SK_REG(port, RX_GMF_LP_THR), 768 / 8); 1028 1029 sky2_set_tx_stfwd(hw, port); 1030 } 1031 1032 if (hw->chip_id == CHIP_ID_YUKON_FE_P && 1033 hw->chip_rev == CHIP_REV_YU_FE2_A0) { 1034 /* disable dynamic watermark */ 1035 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA)); 1036 reg &= ~TX_DYN_WM_ENA; 1037 sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg); 1038 } 1039 } 1040 1041 /* Assign Ram Buffer allocation to queue */ 1042 static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space) 1043 { 1044 u32 end; 1045 1046 /* convert from K bytes to qwords used for hw register */ 1047 start *= 1024/8; 1048 space *= 1024/8; 1049 end = start + space - 1; 1050 1051 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR); 1052 sky2_write32(hw, RB_ADDR(q, RB_START), start); 1053 sky2_write32(hw, RB_ADDR(q, RB_END), end); 1054 sky2_write32(hw, RB_ADDR(q, RB_WP), start); 1055 sky2_write32(hw, RB_ADDR(q, RB_RP), start); 1056 1057 if (q == Q_R1 || q == Q_R2) { 1058 u32 tp = space - space/4; 1059 1060 /* On receive queue's set the thresholds 1061 * give receiver priority when > 3/4 full 1062 * send pause when down to 2K 1063 */ 1064 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp); 1065 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2); 1066 1067 tp = space - 2048/8; 1068 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp); 1069 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4); 1070 } else { 1071 /* Enable store & forward on Tx queue's because 1072 * Tx FIFO is only 1K on Yukon 1073 */ 1074 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD); 1075 } 1076 1077 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD); 1078 sky2_read8(hw, RB_ADDR(q, RB_CTRL)); 1079 } 1080 1081 /* Setup Bus Memory Interface */ 1082 static void sky2_qset(struct sky2_hw *hw, u16 q) 1083 { 1084 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET); 1085 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT); 1086 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON); 1087 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT); 1088 } 1089 1090 /* Setup prefetch unit registers. This is the interface between 1091 * hardware and driver list elements 1092 */ 1093 static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr, 1094 dma_addr_t addr, u32 last) 1095 { 1096 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET); 1097 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR); 1098 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), upper_32_bits(addr)); 1099 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), lower_32_bits(addr)); 1100 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last); 1101 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON); 1102 1103 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL)); 1104 } 1105 1106 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2, u16 *slot) 1107 { 1108 struct sky2_tx_le *le = sky2->tx_le + *slot; 1109 1110 *slot = RING_NEXT(*slot, sky2->tx_ring_size); 1111 le->ctrl = 0; 1112 return le; 1113 } 1114 1115 static void tx_init(struct sky2_port *sky2) 1116 { 1117 struct sky2_tx_le *le; 1118 1119 sky2->tx_prod = sky2->tx_cons = 0; 1120 sky2->tx_tcpsum = 0; 1121 sky2->tx_last_mss = 0; 1122 1123 le = get_tx_le(sky2, &sky2->tx_prod); 1124 le->addr = 0; 1125 le->opcode = OP_ADDR64 | HW_OWNER; 1126 sky2->tx_last_upper = 0; 1127 } 1128 1129 /* Update chip's next pointer */ 1130 static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx) 1131 { 1132 /* Make sure write' to descriptors are complete before we tell hardware */ 1133 wmb(); 1134 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx); 1135 1136 /* Synchronize I/O on since next processor may write to tail */ 1137 mmiowb(); 1138 } 1139 1140 1141 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2) 1142 { 1143 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put; 1144 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE); 1145 le->ctrl = 0; 1146 return le; 1147 } 1148 1149 static unsigned sky2_get_rx_threshold(struct sky2_port *sky2) 1150 { 1151 unsigned size; 1152 1153 /* Space needed for frame data + headers rounded up */ 1154 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8); 1155 1156 /* Stopping point for hardware truncation */ 1157 return (size - 8) / sizeof(u32); 1158 } 1159 1160 static unsigned sky2_get_rx_data_size(struct sky2_port *sky2) 1161 { 1162 struct rx_ring_info *re; 1163 unsigned size; 1164 1165 /* Space needed for frame data + headers rounded up */ 1166 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8); 1167 1168 sky2->rx_nfrags = size >> PAGE_SHIFT; 1169 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr)); 1170 1171 /* Compute residue after pages */ 1172 size -= sky2->rx_nfrags << PAGE_SHIFT; 1173 1174 /* Optimize to handle small packets and headers */ 1175 if (size < copybreak) 1176 size = copybreak; 1177 if (size < ETH_HLEN) 1178 size = ETH_HLEN; 1179 1180 return size; 1181 } 1182 1183 /* Build description to hardware for one receive segment */ 1184 static void sky2_rx_add(struct sky2_port *sky2, u8 op, 1185 dma_addr_t map, unsigned len) 1186 { 1187 struct sky2_rx_le *le; 1188 1189 if (sizeof(dma_addr_t) > sizeof(u32)) { 1190 le = sky2_next_rx(sky2); 1191 le->addr = cpu_to_le32(upper_32_bits(map)); 1192 le->opcode = OP_ADDR64 | HW_OWNER; 1193 } 1194 1195 le = sky2_next_rx(sky2); 1196 le->addr = cpu_to_le32(lower_32_bits(map)); 1197 le->length = cpu_to_le16(len); 1198 le->opcode = op | HW_OWNER; 1199 } 1200 1201 /* Build description to hardware for one possibly fragmented skb */ 1202 static void sky2_rx_submit(struct sky2_port *sky2, 1203 const struct rx_ring_info *re) 1204 { 1205 int i; 1206 1207 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size); 1208 1209 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++) 1210 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE); 1211 } 1212 1213 1214 static int sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re, 1215 unsigned size) 1216 { 1217 struct sk_buff *skb = re->skb; 1218 int i; 1219 1220 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE); 1221 if (pci_dma_mapping_error(pdev, re->data_addr)) 1222 goto mapping_error; 1223 1224 dma_unmap_len_set(re, data_size, size); 1225 1226 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1227 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1228 1229 re->frag_addr[i] = pci_map_page(pdev, frag->page, 1230 frag->page_offset, 1231 frag->size, 1232 PCI_DMA_FROMDEVICE); 1233 1234 if (pci_dma_mapping_error(pdev, re->frag_addr[i])) 1235 goto map_page_error; 1236 } 1237 return 0; 1238 1239 map_page_error: 1240 while (--i >= 0) { 1241 pci_unmap_page(pdev, re->frag_addr[i], 1242 skb_shinfo(skb)->frags[i].size, 1243 PCI_DMA_FROMDEVICE); 1244 } 1245 1246 pci_unmap_single(pdev, re->data_addr, dma_unmap_len(re, data_size), 1247 PCI_DMA_FROMDEVICE); 1248 1249 mapping_error: 1250 if (net_ratelimit()) 1251 dev_warn(&pdev->dev, "%s: rx mapping error\n", 1252 skb->dev->name); 1253 return -EIO; 1254 } 1255 1256 static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re) 1257 { 1258 struct sk_buff *skb = re->skb; 1259 int i; 1260 1261 pci_unmap_single(pdev, re->data_addr, dma_unmap_len(re, data_size), 1262 PCI_DMA_FROMDEVICE); 1263 1264 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) 1265 pci_unmap_page(pdev, re->frag_addr[i], 1266 skb_shinfo(skb)->frags[i].size, 1267 PCI_DMA_FROMDEVICE); 1268 } 1269 1270 /* Tell chip where to start receive checksum. 1271 * Actually has two checksums, but set both same to avoid possible byte 1272 * order problems. 1273 */ 1274 static void rx_set_checksum(struct sky2_port *sky2) 1275 { 1276 struct sky2_rx_le *le = sky2_next_rx(sky2); 1277 1278 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN); 1279 le->ctrl = 0; 1280 le->opcode = OP_TCPSTART | HW_OWNER; 1281 1282 sky2_write32(sky2->hw, 1283 Q_ADDR(rxqaddr[sky2->port], Q_CSR), 1284 (sky2->netdev->features & NETIF_F_RXCSUM) 1285 ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM); 1286 } 1287 1288 /* Enable/disable receive hash calculation (RSS) */ 1289 static void rx_set_rss(struct net_device *dev, u32 features) 1290 { 1291 struct sky2_port *sky2 = netdev_priv(dev); 1292 struct sky2_hw *hw = sky2->hw; 1293 int i, nkeys = 4; 1294 1295 /* Supports IPv6 and other modes */ 1296 if (hw->flags & SKY2_HW_NEW_LE) { 1297 nkeys = 10; 1298 sky2_write32(hw, SK_REG(sky2->port, RSS_CFG), HASH_ALL); 1299 } 1300 1301 /* Program RSS initial values */ 1302 if (features & NETIF_F_RXHASH) { 1303 u32 key[nkeys]; 1304 1305 get_random_bytes(key, nkeys * sizeof(u32)); 1306 for (i = 0; i < nkeys; i++) 1307 sky2_write32(hw, SK_REG(sky2->port, RSS_KEY + i * 4), 1308 key[i]); 1309 1310 /* Need to turn on (undocumented) flag to make hashing work */ 1311 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), 1312 RX_STFW_ENA); 1313 1314 sky2_write32(hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR), 1315 BMU_ENA_RX_RSS_HASH); 1316 } else 1317 sky2_write32(hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR), 1318 BMU_DIS_RX_RSS_HASH); 1319 } 1320 1321 /* 1322 * The RX Stop command will not work for Yukon-2 if the BMU does not 1323 * reach the end of packet and since we can't make sure that we have 1324 * incoming data, we must reset the BMU while it is not doing a DMA 1325 * transfer. Since it is possible that the RX path is still active, 1326 * the RX RAM buffer will be stopped first, so any possible incoming 1327 * data will not trigger a DMA. After the RAM buffer is stopped, the 1328 * BMU is polled until any DMA in progress is ended and only then it 1329 * will be reset. 1330 */ 1331 static void sky2_rx_stop(struct sky2_port *sky2) 1332 { 1333 struct sky2_hw *hw = sky2->hw; 1334 unsigned rxq = rxqaddr[sky2->port]; 1335 int i; 1336 1337 /* disable the RAM Buffer receive queue */ 1338 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD); 1339 1340 for (i = 0; i < 0xffff; i++) 1341 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL)) 1342 == sky2_read8(hw, RB_ADDR(rxq, Q_RL))) 1343 goto stopped; 1344 1345 netdev_warn(sky2->netdev, "receiver stop failed\n"); 1346 stopped: 1347 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST); 1348 1349 /* reset the Rx prefetch unit */ 1350 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET); 1351 mmiowb(); 1352 } 1353 1354 /* Clean out receive buffer area, assumes receiver hardware stopped */ 1355 static void sky2_rx_clean(struct sky2_port *sky2) 1356 { 1357 unsigned i; 1358 1359 memset(sky2->rx_le, 0, RX_LE_BYTES); 1360 for (i = 0; i < sky2->rx_pending; i++) { 1361 struct rx_ring_info *re = sky2->rx_ring + i; 1362 1363 if (re->skb) { 1364 sky2_rx_unmap_skb(sky2->hw->pdev, re); 1365 kfree_skb(re->skb); 1366 re->skb = NULL; 1367 } 1368 } 1369 } 1370 1371 /* Basic MII support */ 1372 static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 1373 { 1374 struct mii_ioctl_data *data = if_mii(ifr); 1375 struct sky2_port *sky2 = netdev_priv(dev); 1376 struct sky2_hw *hw = sky2->hw; 1377 int err = -EOPNOTSUPP; 1378 1379 if (!netif_running(dev)) 1380 return -ENODEV; /* Phy still in reset */ 1381 1382 switch (cmd) { 1383 case SIOCGMIIPHY: 1384 data->phy_id = PHY_ADDR_MARV; 1385 1386 /* fallthru */ 1387 case SIOCGMIIREG: { 1388 u16 val = 0; 1389 1390 spin_lock_bh(&sky2->phy_lock); 1391 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val); 1392 spin_unlock_bh(&sky2->phy_lock); 1393 1394 data->val_out = val; 1395 break; 1396 } 1397 1398 case SIOCSMIIREG: 1399 spin_lock_bh(&sky2->phy_lock); 1400 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f, 1401 data->val_in); 1402 spin_unlock_bh(&sky2->phy_lock); 1403 break; 1404 } 1405 return err; 1406 } 1407 1408 #define SKY2_VLAN_OFFLOADS (NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_TSO) 1409 1410 static void sky2_vlan_mode(struct net_device *dev, u32 features) 1411 { 1412 struct sky2_port *sky2 = netdev_priv(dev); 1413 struct sky2_hw *hw = sky2->hw; 1414 u16 port = sky2->port; 1415 1416 if (features & NETIF_F_HW_VLAN_RX) 1417 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), 1418 RX_VLAN_STRIP_ON); 1419 else 1420 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), 1421 RX_VLAN_STRIP_OFF); 1422 1423 if (features & NETIF_F_HW_VLAN_TX) { 1424 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), 1425 TX_VLAN_TAG_ON); 1426 1427 dev->vlan_features |= SKY2_VLAN_OFFLOADS; 1428 } else { 1429 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), 1430 TX_VLAN_TAG_OFF); 1431 1432 /* Can't do transmit offload of vlan without hw vlan */ 1433 dev->vlan_features &= ~SKY2_VLAN_OFFLOADS; 1434 } 1435 } 1436 1437 /* Amount of required worst case padding in rx buffer */ 1438 static inline unsigned sky2_rx_pad(const struct sky2_hw *hw) 1439 { 1440 return (hw->flags & SKY2_HW_RAM_BUFFER) ? 8 : 2; 1441 } 1442 1443 /* 1444 * Allocate an skb for receiving. If the MTU is large enough 1445 * make the skb non-linear with a fragment list of pages. 1446 */ 1447 static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2, gfp_t gfp) 1448 { 1449 struct sk_buff *skb; 1450 int i; 1451 1452 skb = __netdev_alloc_skb(sky2->netdev, 1453 sky2->rx_data_size + sky2_rx_pad(sky2->hw), 1454 gfp); 1455 if (!skb) 1456 goto nomem; 1457 1458 if (sky2->hw->flags & SKY2_HW_RAM_BUFFER) { 1459 unsigned char *start; 1460 /* 1461 * Workaround for a bug in FIFO that cause hang 1462 * if the FIFO if the receive buffer is not 64 byte aligned. 1463 * The buffer returned from netdev_alloc_skb is 1464 * aligned except if slab debugging is enabled. 1465 */ 1466 start = PTR_ALIGN(skb->data, 8); 1467 skb_reserve(skb, start - skb->data); 1468 } else 1469 skb_reserve(skb, NET_IP_ALIGN); 1470 1471 for (i = 0; i < sky2->rx_nfrags; i++) { 1472 struct page *page = alloc_page(gfp); 1473 1474 if (!page) 1475 goto free_partial; 1476 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE); 1477 } 1478 1479 return skb; 1480 free_partial: 1481 kfree_skb(skb); 1482 nomem: 1483 return NULL; 1484 } 1485 1486 static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq) 1487 { 1488 sky2_put_idx(sky2->hw, rxq, sky2->rx_put); 1489 } 1490 1491 static int sky2_alloc_rx_skbs(struct sky2_port *sky2) 1492 { 1493 struct sky2_hw *hw = sky2->hw; 1494 unsigned i; 1495 1496 sky2->rx_data_size = sky2_get_rx_data_size(sky2); 1497 1498 /* Fill Rx ring */ 1499 for (i = 0; i < sky2->rx_pending; i++) { 1500 struct rx_ring_info *re = sky2->rx_ring + i; 1501 1502 re->skb = sky2_rx_alloc(sky2, GFP_KERNEL); 1503 if (!re->skb) 1504 return -ENOMEM; 1505 1506 if (sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size)) { 1507 dev_kfree_skb(re->skb); 1508 re->skb = NULL; 1509 return -ENOMEM; 1510 } 1511 } 1512 return 0; 1513 } 1514 1515 /* 1516 * Setup receiver buffer pool. 1517 * Normal case this ends up creating one list element for skb 1518 * in the receive ring. Worst case if using large MTU and each 1519 * allocation falls on a different 64 bit region, that results 1520 * in 6 list elements per ring entry. 1521 * One element is used for checksum enable/disable, and one 1522 * extra to avoid wrap. 1523 */ 1524 static void sky2_rx_start(struct sky2_port *sky2) 1525 { 1526 struct sky2_hw *hw = sky2->hw; 1527 struct rx_ring_info *re; 1528 unsigned rxq = rxqaddr[sky2->port]; 1529 unsigned i, thresh; 1530 1531 sky2->rx_put = sky2->rx_next = 0; 1532 sky2_qset(hw, rxq); 1533 1534 /* On PCI express lowering the watermark gives better performance */ 1535 if (pci_is_pcie(hw->pdev)) 1536 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX); 1537 1538 /* These chips have no ram buffer? 1539 * MAC Rx RAM Read is controlled by hardware */ 1540 if (hw->chip_id == CHIP_ID_YUKON_EC_U && 1541 hw->chip_rev > CHIP_REV_YU_EC_U_A0) 1542 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS); 1543 1544 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1); 1545 1546 if (!(hw->flags & SKY2_HW_NEW_LE)) 1547 rx_set_checksum(sky2); 1548 1549 if (!(hw->flags & SKY2_HW_RSS_BROKEN)) 1550 rx_set_rss(sky2->netdev, sky2->netdev->features); 1551 1552 /* submit Rx ring */ 1553 for (i = 0; i < sky2->rx_pending; i++) { 1554 re = sky2->rx_ring + i; 1555 sky2_rx_submit(sky2, re); 1556 } 1557 1558 /* 1559 * The receiver hangs if it receives frames larger than the 1560 * packet buffer. As a workaround, truncate oversize frames, but 1561 * the register is limited to 9 bits, so if you do frames > 2052 1562 * you better get the MTU right! 1563 */ 1564 thresh = sky2_get_rx_threshold(sky2); 1565 if (thresh > 0x1ff) 1566 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF); 1567 else { 1568 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh); 1569 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON); 1570 } 1571 1572 /* Tell chip about available buffers */ 1573 sky2_rx_update(sky2, rxq); 1574 1575 if (hw->chip_id == CHIP_ID_YUKON_EX || 1576 hw->chip_id == CHIP_ID_YUKON_SUPR) { 1577 /* 1578 * Disable flushing of non ASF packets; 1579 * must be done after initializing the BMUs; 1580 * drivers without ASF support should do this too, otherwise 1581 * it may happen that they cannot run on ASF devices; 1582 * remember that the MAC FIFO isn't reset during initialization. 1583 */ 1584 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_MACSEC_FLUSH_OFF); 1585 } 1586 1587 if (hw->chip_id >= CHIP_ID_YUKON_SUPR) { 1588 /* Enable RX Home Address & Routing Header checksum fix */ 1589 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_FL_CTRL), 1590 RX_IPV6_SA_MOB_ENA | RX_IPV6_DA_MOB_ENA); 1591 1592 /* Enable TX Home Address & Routing Header checksum fix */ 1593 sky2_write32(hw, Q_ADDR(txqaddr[sky2->port], Q_TEST), 1594 TBMU_TEST_HOME_ADD_FIX_EN | TBMU_TEST_ROUTING_ADD_FIX_EN); 1595 } 1596 } 1597 1598 static int sky2_alloc_buffers(struct sky2_port *sky2) 1599 { 1600 struct sky2_hw *hw = sky2->hw; 1601 1602 /* must be power of 2 */ 1603 sky2->tx_le = pci_alloc_consistent(hw->pdev, 1604 sky2->tx_ring_size * 1605 sizeof(struct sky2_tx_le), 1606 &sky2->tx_le_map); 1607 if (!sky2->tx_le) 1608 goto nomem; 1609 1610 sky2->tx_ring = kcalloc(sky2->tx_ring_size, sizeof(struct tx_ring_info), 1611 GFP_KERNEL); 1612 if (!sky2->tx_ring) 1613 goto nomem; 1614 1615 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES, 1616 &sky2->rx_le_map); 1617 if (!sky2->rx_le) 1618 goto nomem; 1619 memset(sky2->rx_le, 0, RX_LE_BYTES); 1620 1621 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info), 1622 GFP_KERNEL); 1623 if (!sky2->rx_ring) 1624 goto nomem; 1625 1626 return sky2_alloc_rx_skbs(sky2); 1627 nomem: 1628 return -ENOMEM; 1629 } 1630 1631 static void sky2_free_buffers(struct sky2_port *sky2) 1632 { 1633 struct sky2_hw *hw = sky2->hw; 1634 1635 sky2_rx_clean(sky2); 1636 1637 if (sky2->rx_le) { 1638 pci_free_consistent(hw->pdev, RX_LE_BYTES, 1639 sky2->rx_le, sky2->rx_le_map); 1640 sky2->rx_le = NULL; 1641 } 1642 if (sky2->tx_le) { 1643 pci_free_consistent(hw->pdev, 1644 sky2->tx_ring_size * sizeof(struct sky2_tx_le), 1645 sky2->tx_le, sky2->tx_le_map); 1646 sky2->tx_le = NULL; 1647 } 1648 kfree(sky2->tx_ring); 1649 kfree(sky2->rx_ring); 1650 1651 sky2->tx_ring = NULL; 1652 sky2->rx_ring = NULL; 1653 } 1654 1655 static void sky2_hw_up(struct sky2_port *sky2) 1656 { 1657 struct sky2_hw *hw = sky2->hw; 1658 unsigned port = sky2->port; 1659 u32 ramsize; 1660 int cap; 1661 struct net_device *otherdev = hw->dev[sky2->port^1]; 1662 1663 tx_init(sky2); 1664 1665 /* 1666 * On dual port PCI-X card, there is an problem where status 1667 * can be received out of order due to split transactions 1668 */ 1669 if (otherdev && netif_running(otherdev) && 1670 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) { 1671 u16 cmd; 1672 1673 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD); 1674 cmd &= ~PCI_X_CMD_MAX_SPLIT; 1675 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd); 1676 } 1677 1678 sky2_mac_init(hw, port); 1679 1680 /* Register is number of 4K blocks on internal RAM buffer. */ 1681 ramsize = sky2_read8(hw, B2_E_0) * 4; 1682 if (ramsize > 0) { 1683 u32 rxspace; 1684 1685 netdev_dbg(sky2->netdev, "ram buffer %dK\n", ramsize); 1686 if (ramsize < 16) 1687 rxspace = ramsize / 2; 1688 else 1689 rxspace = 8 + (2*(ramsize - 16))/3; 1690 1691 sky2_ramset(hw, rxqaddr[port], 0, rxspace); 1692 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace); 1693 1694 /* Make sure SyncQ is disabled */ 1695 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL), 1696 RB_RST_SET); 1697 } 1698 1699 sky2_qset(hw, txqaddr[port]); 1700 1701 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */ 1702 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0) 1703 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF); 1704 1705 /* Set almost empty threshold */ 1706 if (hw->chip_id == CHIP_ID_YUKON_EC_U && 1707 hw->chip_rev == CHIP_REV_YU_EC_U_A0) 1708 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV); 1709 1710 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map, 1711 sky2->tx_ring_size - 1); 1712 1713 sky2_vlan_mode(sky2->netdev, sky2->netdev->features); 1714 netdev_update_features(sky2->netdev); 1715 1716 sky2_rx_start(sky2); 1717 } 1718 1719 /* Bring up network interface. */ 1720 static int sky2_up(struct net_device *dev) 1721 { 1722 struct sky2_port *sky2 = netdev_priv(dev); 1723 struct sky2_hw *hw = sky2->hw; 1724 unsigned port = sky2->port; 1725 u32 imask; 1726 int err; 1727 1728 netif_carrier_off(dev); 1729 1730 err = sky2_alloc_buffers(sky2); 1731 if (err) 1732 goto err_out; 1733 1734 sky2_hw_up(sky2); 1735 1736 /* Enable interrupts from phy/mac for port */ 1737 imask = sky2_read32(hw, B0_IMSK); 1738 imask |= portirq_msk[port]; 1739 sky2_write32(hw, B0_IMSK, imask); 1740 sky2_read32(hw, B0_IMSK); 1741 1742 netif_info(sky2, ifup, dev, "enabling interface\n"); 1743 1744 return 0; 1745 1746 err_out: 1747 sky2_free_buffers(sky2); 1748 return err; 1749 } 1750 1751 /* Modular subtraction in ring */ 1752 static inline int tx_inuse(const struct sky2_port *sky2) 1753 { 1754 return (sky2->tx_prod - sky2->tx_cons) & (sky2->tx_ring_size - 1); 1755 } 1756 1757 /* Number of list elements available for next tx */ 1758 static inline int tx_avail(const struct sky2_port *sky2) 1759 { 1760 return sky2->tx_pending - tx_inuse(sky2); 1761 } 1762 1763 /* Estimate of number of transmit list elements required */ 1764 static unsigned tx_le_req(const struct sk_buff *skb) 1765 { 1766 unsigned count; 1767 1768 count = (skb_shinfo(skb)->nr_frags + 1) 1769 * (sizeof(dma_addr_t) / sizeof(u32)); 1770 1771 if (skb_is_gso(skb)) 1772 ++count; 1773 else if (sizeof(dma_addr_t) == sizeof(u32)) 1774 ++count; /* possible vlan */ 1775 1776 if (skb->ip_summed == CHECKSUM_PARTIAL) 1777 ++count; 1778 1779 return count; 1780 } 1781 1782 static void sky2_tx_unmap(struct pci_dev *pdev, struct tx_ring_info *re) 1783 { 1784 if (re->flags & TX_MAP_SINGLE) 1785 pci_unmap_single(pdev, dma_unmap_addr(re, mapaddr), 1786 dma_unmap_len(re, maplen), 1787 PCI_DMA_TODEVICE); 1788 else if (re->flags & TX_MAP_PAGE) 1789 pci_unmap_page(pdev, dma_unmap_addr(re, mapaddr), 1790 dma_unmap_len(re, maplen), 1791 PCI_DMA_TODEVICE); 1792 re->flags = 0; 1793 } 1794 1795 /* 1796 * Put one packet in ring for transmit. 1797 * A single packet can generate multiple list elements, and 1798 * the number of ring elements will probably be less than the number 1799 * of list elements used. 1800 */ 1801 static netdev_tx_t sky2_xmit_frame(struct sk_buff *skb, 1802 struct net_device *dev) 1803 { 1804 struct sky2_port *sky2 = netdev_priv(dev); 1805 struct sky2_hw *hw = sky2->hw; 1806 struct sky2_tx_le *le = NULL; 1807 struct tx_ring_info *re; 1808 unsigned i, len; 1809 dma_addr_t mapping; 1810 u32 upper; 1811 u16 slot; 1812 u16 mss; 1813 u8 ctrl; 1814 1815 if (unlikely(tx_avail(sky2) < tx_le_req(skb))) 1816 return NETDEV_TX_BUSY; 1817 1818 len = skb_headlen(skb); 1819 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE); 1820 1821 if (pci_dma_mapping_error(hw->pdev, mapping)) 1822 goto mapping_error; 1823 1824 slot = sky2->tx_prod; 1825 netif_printk(sky2, tx_queued, KERN_DEBUG, dev, 1826 "tx queued, slot %u, len %d\n", slot, skb->len); 1827 1828 /* Send high bits if needed */ 1829 upper = upper_32_bits(mapping); 1830 if (upper != sky2->tx_last_upper) { 1831 le = get_tx_le(sky2, &slot); 1832 le->addr = cpu_to_le32(upper); 1833 sky2->tx_last_upper = upper; 1834 le->opcode = OP_ADDR64 | HW_OWNER; 1835 } 1836 1837 /* Check for TCP Segmentation Offload */ 1838 mss = skb_shinfo(skb)->gso_size; 1839 if (mss != 0) { 1840 1841 if (!(hw->flags & SKY2_HW_NEW_LE)) 1842 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb); 1843 1844 if (mss != sky2->tx_last_mss) { 1845 le = get_tx_le(sky2, &slot); 1846 le->addr = cpu_to_le32(mss); 1847 1848 if (hw->flags & SKY2_HW_NEW_LE) 1849 le->opcode = OP_MSS | HW_OWNER; 1850 else 1851 le->opcode = OP_LRGLEN | HW_OWNER; 1852 sky2->tx_last_mss = mss; 1853 } 1854 } 1855 1856 ctrl = 0; 1857 1858 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */ 1859 if (vlan_tx_tag_present(skb)) { 1860 if (!le) { 1861 le = get_tx_le(sky2, &slot); 1862 le->addr = 0; 1863 le->opcode = OP_VLAN|HW_OWNER; 1864 } else 1865 le->opcode |= OP_VLAN; 1866 le->length = cpu_to_be16(vlan_tx_tag_get(skb)); 1867 ctrl |= INS_VLAN; 1868 } 1869 1870 /* Handle TCP checksum offload */ 1871 if (skb->ip_summed == CHECKSUM_PARTIAL) { 1872 /* On Yukon EX (some versions) encoding change. */ 1873 if (hw->flags & SKY2_HW_AUTO_TX_SUM) 1874 ctrl |= CALSUM; /* auto checksum */ 1875 else { 1876 const unsigned offset = skb_transport_offset(skb); 1877 u32 tcpsum; 1878 1879 tcpsum = offset << 16; /* sum start */ 1880 tcpsum |= offset + skb->csum_offset; /* sum write */ 1881 1882 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM; 1883 if (ip_hdr(skb)->protocol == IPPROTO_UDP) 1884 ctrl |= UDPTCP; 1885 1886 if (tcpsum != sky2->tx_tcpsum) { 1887 sky2->tx_tcpsum = tcpsum; 1888 1889 le = get_tx_le(sky2, &slot); 1890 le->addr = cpu_to_le32(tcpsum); 1891 le->length = 0; /* initial checksum value */ 1892 le->ctrl = 1; /* one packet */ 1893 le->opcode = OP_TCPLISW | HW_OWNER; 1894 } 1895 } 1896 } 1897 1898 re = sky2->tx_ring + slot; 1899 re->flags = TX_MAP_SINGLE; 1900 dma_unmap_addr_set(re, mapaddr, mapping); 1901 dma_unmap_len_set(re, maplen, len); 1902 1903 le = get_tx_le(sky2, &slot); 1904 le->addr = cpu_to_le32(lower_32_bits(mapping)); 1905 le->length = cpu_to_le16(len); 1906 le->ctrl = ctrl; 1907 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER); 1908 1909 1910 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1911 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1912 1913 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset, 1914 frag->size, PCI_DMA_TODEVICE); 1915 1916 if (pci_dma_mapping_error(hw->pdev, mapping)) 1917 goto mapping_unwind; 1918 1919 upper = upper_32_bits(mapping); 1920 if (upper != sky2->tx_last_upper) { 1921 le = get_tx_le(sky2, &slot); 1922 le->addr = cpu_to_le32(upper); 1923 sky2->tx_last_upper = upper; 1924 le->opcode = OP_ADDR64 | HW_OWNER; 1925 } 1926 1927 re = sky2->tx_ring + slot; 1928 re->flags = TX_MAP_PAGE; 1929 dma_unmap_addr_set(re, mapaddr, mapping); 1930 dma_unmap_len_set(re, maplen, frag->size); 1931 1932 le = get_tx_le(sky2, &slot); 1933 le->addr = cpu_to_le32(lower_32_bits(mapping)); 1934 le->length = cpu_to_le16(frag->size); 1935 le->ctrl = ctrl; 1936 le->opcode = OP_BUFFER | HW_OWNER; 1937 } 1938 1939 re->skb = skb; 1940 le->ctrl |= EOP; 1941 1942 sky2->tx_prod = slot; 1943 1944 if (tx_avail(sky2) <= MAX_SKB_TX_LE) 1945 netif_stop_queue(dev); 1946 1947 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod); 1948 1949 return NETDEV_TX_OK; 1950 1951 mapping_unwind: 1952 for (i = sky2->tx_prod; i != slot; i = RING_NEXT(i, sky2->tx_ring_size)) { 1953 re = sky2->tx_ring + i; 1954 1955 sky2_tx_unmap(hw->pdev, re); 1956 } 1957 1958 mapping_error: 1959 if (net_ratelimit()) 1960 dev_warn(&hw->pdev->dev, "%s: tx mapping error\n", dev->name); 1961 dev_kfree_skb(skb); 1962 return NETDEV_TX_OK; 1963 } 1964 1965 /* 1966 * Free ring elements from starting at tx_cons until "done" 1967 * 1968 * NB: 1969 * 1. The hardware will tell us about partial completion of multi-part 1970 * buffers so make sure not to free skb to early. 1971 * 2. This may run in parallel start_xmit because the it only 1972 * looks at the tail of the queue of FIFO (tx_cons), not 1973 * the head (tx_prod) 1974 */ 1975 static void sky2_tx_complete(struct sky2_port *sky2, u16 done) 1976 { 1977 struct net_device *dev = sky2->netdev; 1978 unsigned idx; 1979 1980 BUG_ON(done >= sky2->tx_ring_size); 1981 1982 for (idx = sky2->tx_cons; idx != done; 1983 idx = RING_NEXT(idx, sky2->tx_ring_size)) { 1984 struct tx_ring_info *re = sky2->tx_ring + idx; 1985 struct sk_buff *skb = re->skb; 1986 1987 sky2_tx_unmap(sky2->hw->pdev, re); 1988 1989 if (skb) { 1990 netif_printk(sky2, tx_done, KERN_DEBUG, dev, 1991 "tx done %u\n", idx); 1992 1993 u64_stats_update_begin(&sky2->tx_stats.syncp); 1994 ++sky2->tx_stats.packets; 1995 sky2->tx_stats.bytes += skb->len; 1996 u64_stats_update_end(&sky2->tx_stats.syncp); 1997 1998 re->skb = NULL; 1999 dev_kfree_skb_any(skb); 2000 2001 sky2->tx_next = RING_NEXT(idx, sky2->tx_ring_size); 2002 } 2003 } 2004 2005 sky2->tx_cons = idx; 2006 smp_mb(); 2007 } 2008 2009 static void sky2_tx_reset(struct sky2_hw *hw, unsigned port) 2010 { 2011 /* Disable Force Sync bit and Enable Alloc bit */ 2012 sky2_write8(hw, SK_REG(port, TXA_CTRL), 2013 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC); 2014 2015 /* Stop Interval Timer and Limit Counter of Tx Arbiter */ 2016 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L); 2017 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L); 2018 2019 /* Reset the PCI FIFO of the async Tx queue */ 2020 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), 2021 BMU_RST_SET | BMU_FIFO_RST); 2022 2023 /* Reset the Tx prefetch units */ 2024 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL), 2025 PREF_UNIT_RST_SET); 2026 2027 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET); 2028 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET); 2029 } 2030 2031 static void sky2_hw_down(struct sky2_port *sky2) 2032 { 2033 struct sky2_hw *hw = sky2->hw; 2034 unsigned port = sky2->port; 2035 u16 ctrl; 2036 2037 /* Force flow control off */ 2038 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); 2039 2040 /* Stop transmitter */ 2041 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP); 2042 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR)); 2043 2044 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), 2045 RB_RST_SET | RB_DIS_OP_MD); 2046 2047 ctrl = gma_read16(hw, port, GM_GP_CTRL); 2048 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA); 2049 gma_write16(hw, port, GM_GP_CTRL, ctrl); 2050 2051 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET); 2052 2053 /* Workaround shared GMAC reset */ 2054 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && 2055 port == 0 && hw->dev[1] && netif_running(hw->dev[1]))) 2056 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET); 2057 2058 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET); 2059 2060 /* Force any delayed status interrrupt and NAPI */ 2061 sky2_write32(hw, STAT_LEV_TIMER_CNT, 0); 2062 sky2_write32(hw, STAT_TX_TIMER_CNT, 0); 2063 sky2_write32(hw, STAT_ISR_TIMER_CNT, 0); 2064 sky2_read8(hw, STAT_ISR_TIMER_CTRL); 2065 2066 sky2_rx_stop(sky2); 2067 2068 spin_lock_bh(&sky2->phy_lock); 2069 sky2_phy_power_down(hw, port); 2070 spin_unlock_bh(&sky2->phy_lock); 2071 2072 sky2_tx_reset(hw, port); 2073 2074 /* Free any pending frames stuck in HW queue */ 2075 sky2_tx_complete(sky2, sky2->tx_prod); 2076 } 2077 2078 /* Network shutdown */ 2079 static int sky2_down(struct net_device *dev) 2080 { 2081 struct sky2_port *sky2 = netdev_priv(dev); 2082 struct sky2_hw *hw = sky2->hw; 2083 2084 /* Never really got started! */ 2085 if (!sky2->tx_le) 2086 return 0; 2087 2088 netif_info(sky2, ifdown, dev, "disabling interface\n"); 2089 2090 /* Disable port IRQ */ 2091 sky2_write32(hw, B0_IMSK, 2092 sky2_read32(hw, B0_IMSK) & ~portirq_msk[sky2->port]); 2093 sky2_read32(hw, B0_IMSK); 2094 2095 synchronize_irq(hw->pdev->irq); 2096 napi_synchronize(&hw->napi); 2097 2098 sky2_hw_down(sky2); 2099 2100 sky2_free_buffers(sky2); 2101 2102 return 0; 2103 } 2104 2105 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux) 2106 { 2107 if (hw->flags & SKY2_HW_FIBRE_PHY) 2108 return SPEED_1000; 2109 2110 if (!(hw->flags & SKY2_HW_GIGABIT)) { 2111 if (aux & PHY_M_PS_SPEED_100) 2112 return SPEED_100; 2113 else 2114 return SPEED_10; 2115 } 2116 2117 switch (aux & PHY_M_PS_SPEED_MSK) { 2118 case PHY_M_PS_SPEED_1000: 2119 return SPEED_1000; 2120 case PHY_M_PS_SPEED_100: 2121 return SPEED_100; 2122 default: 2123 return SPEED_10; 2124 } 2125 } 2126 2127 static void sky2_link_up(struct sky2_port *sky2) 2128 { 2129 struct sky2_hw *hw = sky2->hw; 2130 unsigned port = sky2->port; 2131 static const char *fc_name[] = { 2132 [FC_NONE] = "none", 2133 [FC_TX] = "tx", 2134 [FC_RX] = "rx", 2135 [FC_BOTH] = "both", 2136 }; 2137 2138 sky2_set_ipg(sky2); 2139 2140 sky2_enable_rx_tx(sky2); 2141 2142 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK); 2143 2144 netif_carrier_on(sky2->netdev); 2145 2146 mod_timer(&hw->watchdog_timer, jiffies + 1); 2147 2148 /* Turn on link LED */ 2149 sky2_write8(hw, SK_REG(port, LNK_LED_REG), 2150 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF); 2151 2152 netif_info(sky2, link, sky2->netdev, 2153 "Link is up at %d Mbps, %s duplex, flow control %s\n", 2154 sky2->speed, 2155 sky2->duplex == DUPLEX_FULL ? "full" : "half", 2156 fc_name[sky2->flow_status]); 2157 } 2158 2159 static void sky2_link_down(struct sky2_port *sky2) 2160 { 2161 struct sky2_hw *hw = sky2->hw; 2162 unsigned port = sky2->port; 2163 u16 reg; 2164 2165 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0); 2166 2167 reg = gma_read16(hw, port, GM_GP_CTRL); 2168 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); 2169 gma_write16(hw, port, GM_GP_CTRL, reg); 2170 2171 netif_carrier_off(sky2->netdev); 2172 2173 /* Turn off link LED */ 2174 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF); 2175 2176 netif_info(sky2, link, sky2->netdev, "Link is down\n"); 2177 2178 sky2_phy_init(hw, port); 2179 } 2180 2181 static enum flow_control sky2_flow(int rx, int tx) 2182 { 2183 if (rx) 2184 return tx ? FC_BOTH : FC_RX; 2185 else 2186 return tx ? FC_TX : FC_NONE; 2187 } 2188 2189 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux) 2190 { 2191 struct sky2_hw *hw = sky2->hw; 2192 unsigned port = sky2->port; 2193 u16 advert, lpa; 2194 2195 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV); 2196 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP); 2197 if (lpa & PHY_M_AN_RF) { 2198 netdev_err(sky2->netdev, "remote fault\n"); 2199 return -1; 2200 } 2201 2202 if (!(aux & PHY_M_PS_SPDUP_RES)) { 2203 netdev_err(sky2->netdev, "speed/duplex mismatch\n"); 2204 return -1; 2205 } 2206 2207 sky2->speed = sky2_phy_speed(hw, aux); 2208 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF; 2209 2210 /* Since the pause result bits seem to in different positions on 2211 * different chips. look at registers. 2212 */ 2213 if (hw->flags & SKY2_HW_FIBRE_PHY) { 2214 /* Shift for bits in fiber PHY */ 2215 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM); 2216 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM); 2217 2218 if (advert & ADVERTISE_1000XPAUSE) 2219 advert |= ADVERTISE_PAUSE_CAP; 2220 if (advert & ADVERTISE_1000XPSE_ASYM) 2221 advert |= ADVERTISE_PAUSE_ASYM; 2222 if (lpa & LPA_1000XPAUSE) 2223 lpa |= LPA_PAUSE_CAP; 2224 if (lpa & LPA_1000XPAUSE_ASYM) 2225 lpa |= LPA_PAUSE_ASYM; 2226 } 2227 2228 sky2->flow_status = FC_NONE; 2229 if (advert & ADVERTISE_PAUSE_CAP) { 2230 if (lpa & LPA_PAUSE_CAP) 2231 sky2->flow_status = FC_BOTH; 2232 else if (advert & ADVERTISE_PAUSE_ASYM) 2233 sky2->flow_status = FC_RX; 2234 } else if (advert & ADVERTISE_PAUSE_ASYM) { 2235 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM)) 2236 sky2->flow_status = FC_TX; 2237 } 2238 2239 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000 && 2240 !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX)) 2241 sky2->flow_status = FC_NONE; 2242 2243 if (sky2->flow_status & FC_TX) 2244 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON); 2245 else 2246 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); 2247 2248 return 0; 2249 } 2250 2251 /* Interrupt from PHY */ 2252 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port) 2253 { 2254 struct net_device *dev = hw->dev[port]; 2255 struct sky2_port *sky2 = netdev_priv(dev); 2256 u16 istatus, phystat; 2257 2258 if (!netif_running(dev)) 2259 return; 2260 2261 spin_lock(&sky2->phy_lock); 2262 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT); 2263 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT); 2264 2265 netif_info(sky2, intr, sky2->netdev, "phy interrupt status 0x%x 0x%x\n", 2266 istatus, phystat); 2267 2268 if (istatus & PHY_M_IS_AN_COMPL) { 2269 if (sky2_autoneg_done(sky2, phystat) == 0 && 2270 !netif_carrier_ok(dev)) 2271 sky2_link_up(sky2); 2272 goto out; 2273 } 2274 2275 if (istatus & PHY_M_IS_LSP_CHANGE) 2276 sky2->speed = sky2_phy_speed(hw, phystat); 2277 2278 if (istatus & PHY_M_IS_DUP_CHANGE) 2279 sky2->duplex = 2280 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF; 2281 2282 if (istatus & PHY_M_IS_LST_CHANGE) { 2283 if (phystat & PHY_M_PS_LINK_UP) 2284 sky2_link_up(sky2); 2285 else 2286 sky2_link_down(sky2); 2287 } 2288 out: 2289 spin_unlock(&sky2->phy_lock); 2290 } 2291 2292 /* Special quick link interrupt (Yukon-2 Optima only) */ 2293 static void sky2_qlink_intr(struct sky2_hw *hw) 2294 { 2295 struct sky2_port *sky2 = netdev_priv(hw->dev[0]); 2296 u32 imask; 2297 u16 phy; 2298 2299 /* disable irq */ 2300 imask = sky2_read32(hw, B0_IMSK); 2301 imask &= ~Y2_IS_PHY_QLNK; 2302 sky2_write32(hw, B0_IMSK, imask); 2303 2304 /* reset PHY Link Detect */ 2305 phy = sky2_pci_read16(hw, PSM_CONFIG_REG4); 2306 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); 2307 sky2_pci_write16(hw, PSM_CONFIG_REG4, phy | 1); 2308 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 2309 2310 sky2_link_up(sky2); 2311 } 2312 2313 /* Transmit timeout is only called if we are running, carrier is up 2314 * and tx queue is full (stopped). 2315 */ 2316 static void sky2_tx_timeout(struct net_device *dev) 2317 { 2318 struct sky2_port *sky2 = netdev_priv(dev); 2319 struct sky2_hw *hw = sky2->hw; 2320 2321 netif_err(sky2, timer, dev, "tx timeout\n"); 2322 2323 netdev_printk(KERN_DEBUG, dev, "transmit ring %u .. %u report=%u done=%u\n", 2324 sky2->tx_cons, sky2->tx_prod, 2325 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX), 2326 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE))); 2327 2328 /* can't restart safely under softirq */ 2329 schedule_work(&hw->restart_work); 2330 } 2331 2332 static int sky2_change_mtu(struct net_device *dev, int new_mtu) 2333 { 2334 struct sky2_port *sky2 = netdev_priv(dev); 2335 struct sky2_hw *hw = sky2->hw; 2336 unsigned port = sky2->port; 2337 int err; 2338 u16 ctl, mode; 2339 u32 imask; 2340 2341 /* MTU size outside the spec */ 2342 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU) 2343 return -EINVAL; 2344 2345 /* MTU > 1500 on yukon FE and FE+ not allowed */ 2346 if (new_mtu > ETH_DATA_LEN && 2347 (hw->chip_id == CHIP_ID_YUKON_FE || 2348 hw->chip_id == CHIP_ID_YUKON_FE_P)) 2349 return -EINVAL; 2350 2351 if (!netif_running(dev)) { 2352 dev->mtu = new_mtu; 2353 netdev_update_features(dev); 2354 return 0; 2355 } 2356 2357 imask = sky2_read32(hw, B0_IMSK); 2358 sky2_write32(hw, B0_IMSK, 0); 2359 2360 dev->trans_start = jiffies; /* prevent tx timeout */ 2361 napi_disable(&hw->napi); 2362 netif_tx_disable(dev); 2363 2364 synchronize_irq(hw->pdev->irq); 2365 2366 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) 2367 sky2_set_tx_stfwd(hw, port); 2368 2369 ctl = gma_read16(hw, port, GM_GP_CTRL); 2370 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA); 2371 sky2_rx_stop(sky2); 2372 sky2_rx_clean(sky2); 2373 2374 dev->mtu = new_mtu; 2375 netdev_update_features(dev); 2376 2377 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) | GM_SMOD_VLAN_ENA; 2378 if (sky2->speed > SPEED_100) 2379 mode |= IPG_DATA_VAL(IPG_DATA_DEF_1000); 2380 else 2381 mode |= IPG_DATA_VAL(IPG_DATA_DEF_10_100); 2382 2383 if (dev->mtu > ETH_DATA_LEN) 2384 mode |= GM_SMOD_JUMBO_ENA; 2385 2386 gma_write16(hw, port, GM_SERIAL_MODE, mode); 2387 2388 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD); 2389 2390 err = sky2_alloc_rx_skbs(sky2); 2391 if (!err) 2392 sky2_rx_start(sky2); 2393 else 2394 sky2_rx_clean(sky2); 2395 sky2_write32(hw, B0_IMSK, imask); 2396 2397 sky2_read32(hw, B0_Y2_SP_LISR); 2398 napi_enable(&hw->napi); 2399 2400 if (err) 2401 dev_close(dev); 2402 else { 2403 gma_write16(hw, port, GM_GP_CTRL, ctl); 2404 2405 netif_wake_queue(dev); 2406 } 2407 2408 return err; 2409 } 2410 2411 /* For small just reuse existing skb for next receive */ 2412 static struct sk_buff *receive_copy(struct sky2_port *sky2, 2413 const struct rx_ring_info *re, 2414 unsigned length) 2415 { 2416 struct sk_buff *skb; 2417 2418 skb = netdev_alloc_skb_ip_align(sky2->netdev, length); 2419 if (likely(skb)) { 2420 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr, 2421 length, PCI_DMA_FROMDEVICE); 2422 skb_copy_from_linear_data(re->skb, skb->data, length); 2423 skb->ip_summed = re->skb->ip_summed; 2424 skb->csum = re->skb->csum; 2425 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr, 2426 length, PCI_DMA_FROMDEVICE); 2427 re->skb->ip_summed = CHECKSUM_NONE; 2428 skb_put(skb, length); 2429 } 2430 return skb; 2431 } 2432 2433 /* Adjust length of skb with fragments to match received data */ 2434 static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space, 2435 unsigned int length) 2436 { 2437 int i, num_frags; 2438 unsigned int size; 2439 2440 /* put header into skb */ 2441 size = min(length, hdr_space); 2442 skb->tail += size; 2443 skb->len += size; 2444 length -= size; 2445 2446 num_frags = skb_shinfo(skb)->nr_frags; 2447 for (i = 0; i < num_frags; i++) { 2448 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 2449 2450 if (length == 0) { 2451 /* don't need this page */ 2452 __free_page(frag->page); 2453 --skb_shinfo(skb)->nr_frags; 2454 } else { 2455 size = min(length, (unsigned) PAGE_SIZE); 2456 2457 frag->size = size; 2458 skb->data_len += size; 2459 skb->truesize += size; 2460 skb->len += size; 2461 length -= size; 2462 } 2463 } 2464 } 2465 2466 /* Normal packet - take skb from ring element and put in a new one */ 2467 static struct sk_buff *receive_new(struct sky2_port *sky2, 2468 struct rx_ring_info *re, 2469 unsigned int length) 2470 { 2471 struct sk_buff *skb; 2472 struct rx_ring_info nre; 2473 unsigned hdr_space = sky2->rx_data_size; 2474 2475 nre.skb = sky2_rx_alloc(sky2, GFP_ATOMIC); 2476 if (unlikely(!nre.skb)) 2477 goto nobuf; 2478 2479 if (sky2_rx_map_skb(sky2->hw->pdev, &nre, hdr_space)) 2480 goto nomap; 2481 2482 skb = re->skb; 2483 sky2_rx_unmap_skb(sky2->hw->pdev, re); 2484 prefetch(skb->data); 2485 *re = nre; 2486 2487 if (skb_shinfo(skb)->nr_frags) 2488 skb_put_frags(skb, hdr_space, length); 2489 else 2490 skb_put(skb, length); 2491 return skb; 2492 2493 nomap: 2494 dev_kfree_skb(nre.skb); 2495 nobuf: 2496 return NULL; 2497 } 2498 2499 /* 2500 * Receive one packet. 2501 * For larger packets, get new buffer. 2502 */ 2503 static struct sk_buff *sky2_receive(struct net_device *dev, 2504 u16 length, u32 status) 2505 { 2506 struct sky2_port *sky2 = netdev_priv(dev); 2507 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next; 2508 struct sk_buff *skb = NULL; 2509 u16 count = (status & GMR_FS_LEN) >> 16; 2510 2511 if (status & GMR_FS_VLAN) 2512 count -= VLAN_HLEN; /* Account for vlan tag */ 2513 2514 netif_printk(sky2, rx_status, KERN_DEBUG, dev, 2515 "rx slot %u status 0x%x len %d\n", 2516 sky2->rx_next, status, length); 2517 2518 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending; 2519 prefetch(sky2->rx_ring + sky2->rx_next); 2520 2521 /* This chip has hardware problems that generates bogus status. 2522 * So do only marginal checking and expect higher level protocols 2523 * to handle crap frames. 2524 */ 2525 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P && 2526 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 && 2527 length != count) 2528 goto okay; 2529 2530 if (status & GMR_FS_ANY_ERR) 2531 goto error; 2532 2533 if (!(status & GMR_FS_RX_OK)) 2534 goto resubmit; 2535 2536 /* if length reported by DMA does not match PHY, packet was truncated */ 2537 if (length != count) 2538 goto error; 2539 2540 okay: 2541 if (length < copybreak) 2542 skb = receive_copy(sky2, re, length); 2543 else 2544 skb = receive_new(sky2, re, length); 2545 2546 dev->stats.rx_dropped += (skb == NULL); 2547 2548 resubmit: 2549 sky2_rx_submit(sky2, re); 2550 2551 return skb; 2552 2553 error: 2554 ++dev->stats.rx_errors; 2555 2556 if (net_ratelimit()) 2557 netif_info(sky2, rx_err, dev, 2558 "rx error, status 0x%x length %d\n", status, length); 2559 2560 goto resubmit; 2561 } 2562 2563 /* Transmit complete */ 2564 static inline void sky2_tx_done(struct net_device *dev, u16 last) 2565 { 2566 struct sky2_port *sky2 = netdev_priv(dev); 2567 2568 if (netif_running(dev)) { 2569 sky2_tx_complete(sky2, last); 2570 2571 /* Wake unless it's detached, and called e.g. from sky2_down() */ 2572 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4) 2573 netif_wake_queue(dev); 2574 } 2575 } 2576 2577 static inline void sky2_skb_rx(const struct sky2_port *sky2, 2578 u32 status, struct sk_buff *skb) 2579 { 2580 if (status & GMR_FS_VLAN) 2581 __vlan_hwaccel_put_tag(skb, be16_to_cpu(sky2->rx_tag)); 2582 2583 if (skb->ip_summed == CHECKSUM_NONE) 2584 netif_receive_skb(skb); 2585 else 2586 napi_gro_receive(&sky2->hw->napi, skb); 2587 } 2588 2589 static inline void sky2_rx_done(struct sky2_hw *hw, unsigned port, 2590 unsigned packets, unsigned bytes) 2591 { 2592 struct net_device *dev = hw->dev[port]; 2593 struct sky2_port *sky2 = netdev_priv(dev); 2594 2595 if (packets == 0) 2596 return; 2597 2598 u64_stats_update_begin(&sky2->rx_stats.syncp); 2599 sky2->rx_stats.packets += packets; 2600 sky2->rx_stats.bytes += bytes; 2601 u64_stats_update_end(&sky2->rx_stats.syncp); 2602 2603 dev->last_rx = jiffies; 2604 sky2_rx_update(netdev_priv(dev), rxqaddr[port]); 2605 } 2606 2607 static void sky2_rx_checksum(struct sky2_port *sky2, u32 status) 2608 { 2609 /* If this happens then driver assuming wrong format for chip type */ 2610 BUG_ON(sky2->hw->flags & SKY2_HW_NEW_LE); 2611 2612 /* Both checksum counters are programmed to start at 2613 * the same offset, so unless there is a problem they 2614 * should match. This failure is an early indication that 2615 * hardware receive checksumming won't work. 2616 */ 2617 if (likely((u16)(status >> 16) == (u16)status)) { 2618 struct sk_buff *skb = sky2->rx_ring[sky2->rx_next].skb; 2619 skb->ip_summed = CHECKSUM_COMPLETE; 2620 skb->csum = le16_to_cpu(status); 2621 } else { 2622 dev_notice(&sky2->hw->pdev->dev, 2623 "%s: receive checksum problem (status = %#x)\n", 2624 sky2->netdev->name, status); 2625 2626 /* Disable checksum offload 2627 * It will be reenabled on next ndo_set_features, but if it's 2628 * really broken, will get disabled again 2629 */ 2630 sky2->netdev->features &= ~NETIF_F_RXCSUM; 2631 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR), 2632 BMU_DIS_RX_CHKSUM); 2633 } 2634 } 2635 2636 static void sky2_rx_hash(struct sky2_port *sky2, u32 status) 2637 { 2638 struct sk_buff *skb; 2639 2640 skb = sky2->rx_ring[sky2->rx_next].skb; 2641 skb->rxhash = le32_to_cpu(status); 2642 } 2643 2644 /* Process status response ring */ 2645 static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx) 2646 { 2647 int work_done = 0; 2648 unsigned int total_bytes[2] = { 0 }; 2649 unsigned int total_packets[2] = { 0 }; 2650 2651 rmb(); 2652 do { 2653 struct sky2_port *sky2; 2654 struct sky2_status_le *le = hw->st_le + hw->st_idx; 2655 unsigned port; 2656 struct net_device *dev; 2657 struct sk_buff *skb; 2658 u32 status; 2659 u16 length; 2660 u8 opcode = le->opcode; 2661 2662 if (!(opcode & HW_OWNER)) 2663 break; 2664 2665 hw->st_idx = RING_NEXT(hw->st_idx, hw->st_size); 2666 2667 port = le->css & CSS_LINK_BIT; 2668 dev = hw->dev[port]; 2669 sky2 = netdev_priv(dev); 2670 length = le16_to_cpu(le->length); 2671 status = le32_to_cpu(le->status); 2672 2673 le->opcode = 0; 2674 switch (opcode & ~HW_OWNER) { 2675 case OP_RXSTAT: 2676 total_packets[port]++; 2677 total_bytes[port] += length; 2678 2679 skb = sky2_receive(dev, length, status); 2680 if (!skb) 2681 break; 2682 2683 /* This chip reports checksum status differently */ 2684 if (hw->flags & SKY2_HW_NEW_LE) { 2685 if ((dev->features & NETIF_F_RXCSUM) && 2686 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) && 2687 (le->css & CSS_TCPUDPCSOK)) 2688 skb->ip_summed = CHECKSUM_UNNECESSARY; 2689 else 2690 skb->ip_summed = CHECKSUM_NONE; 2691 } 2692 2693 skb->protocol = eth_type_trans(skb, dev); 2694 2695 sky2_skb_rx(sky2, status, skb); 2696 2697 /* Stop after net poll weight */ 2698 if (++work_done >= to_do) 2699 goto exit_loop; 2700 break; 2701 2702 case OP_RXVLAN: 2703 sky2->rx_tag = length; 2704 break; 2705 2706 case OP_RXCHKSVLAN: 2707 sky2->rx_tag = length; 2708 /* fall through */ 2709 case OP_RXCHKS: 2710 if (likely(dev->features & NETIF_F_RXCSUM)) 2711 sky2_rx_checksum(sky2, status); 2712 break; 2713 2714 case OP_RSS_HASH: 2715 sky2_rx_hash(sky2, status); 2716 break; 2717 2718 case OP_TXINDEXLE: 2719 /* TX index reports status for both ports */ 2720 sky2_tx_done(hw->dev[0], status & 0xfff); 2721 if (hw->dev[1]) 2722 sky2_tx_done(hw->dev[1], 2723 ((status >> 24) & 0xff) 2724 | (u16)(length & 0xf) << 8); 2725 break; 2726 2727 default: 2728 if (net_ratelimit()) 2729 pr_warning("unknown status opcode 0x%x\n", opcode); 2730 } 2731 } while (hw->st_idx != idx); 2732 2733 /* Fully processed status ring so clear irq */ 2734 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ); 2735 2736 exit_loop: 2737 sky2_rx_done(hw, 0, total_packets[0], total_bytes[0]); 2738 sky2_rx_done(hw, 1, total_packets[1], total_bytes[1]); 2739 2740 return work_done; 2741 } 2742 2743 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status) 2744 { 2745 struct net_device *dev = hw->dev[port]; 2746 2747 if (net_ratelimit()) 2748 netdev_info(dev, "hw error interrupt status 0x%x\n", status); 2749 2750 if (status & Y2_IS_PAR_RD1) { 2751 if (net_ratelimit()) 2752 netdev_err(dev, "ram data read parity error\n"); 2753 /* Clear IRQ */ 2754 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR); 2755 } 2756 2757 if (status & Y2_IS_PAR_WR1) { 2758 if (net_ratelimit()) 2759 netdev_err(dev, "ram data write parity error\n"); 2760 2761 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR); 2762 } 2763 2764 if (status & Y2_IS_PAR_MAC1) { 2765 if (net_ratelimit()) 2766 netdev_err(dev, "MAC parity error\n"); 2767 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE); 2768 } 2769 2770 if (status & Y2_IS_PAR_RX1) { 2771 if (net_ratelimit()) 2772 netdev_err(dev, "RX parity error\n"); 2773 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR); 2774 } 2775 2776 if (status & Y2_IS_TCP_TXA1) { 2777 if (net_ratelimit()) 2778 netdev_err(dev, "TCP segmentation error\n"); 2779 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP); 2780 } 2781 } 2782 2783 static void sky2_hw_intr(struct sky2_hw *hw) 2784 { 2785 struct pci_dev *pdev = hw->pdev; 2786 u32 status = sky2_read32(hw, B0_HWE_ISRC); 2787 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK); 2788 2789 status &= hwmsk; 2790 2791 if (status & Y2_IS_TIST_OV) 2792 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); 2793 2794 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) { 2795 u16 pci_err; 2796 2797 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); 2798 pci_err = sky2_pci_read16(hw, PCI_STATUS); 2799 if (net_ratelimit()) 2800 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n", 2801 pci_err); 2802 2803 sky2_pci_write16(hw, PCI_STATUS, 2804 pci_err | PCI_STATUS_ERROR_BITS); 2805 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 2806 } 2807 2808 if (status & Y2_IS_PCI_EXP) { 2809 /* PCI-Express uncorrectable Error occurred */ 2810 u32 err; 2811 2812 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); 2813 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS); 2814 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS, 2815 0xfffffffful); 2816 if (net_ratelimit()) 2817 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err); 2818 2819 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS); 2820 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 2821 } 2822 2823 if (status & Y2_HWE_L1_MASK) 2824 sky2_hw_error(hw, 0, status); 2825 status >>= 8; 2826 if (status & Y2_HWE_L1_MASK) 2827 sky2_hw_error(hw, 1, status); 2828 } 2829 2830 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port) 2831 { 2832 struct net_device *dev = hw->dev[port]; 2833 struct sky2_port *sky2 = netdev_priv(dev); 2834 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC)); 2835 2836 netif_info(sky2, intr, dev, "mac interrupt status 0x%x\n", status); 2837 2838 if (status & GM_IS_RX_CO_OV) 2839 gma_read16(hw, port, GM_RX_IRQ_SRC); 2840 2841 if (status & GM_IS_TX_CO_OV) 2842 gma_read16(hw, port, GM_TX_IRQ_SRC); 2843 2844 if (status & GM_IS_RX_FF_OR) { 2845 ++dev->stats.rx_fifo_errors; 2846 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO); 2847 } 2848 2849 if (status & GM_IS_TX_FF_UR) { 2850 ++dev->stats.tx_fifo_errors; 2851 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU); 2852 } 2853 } 2854 2855 /* This should never happen it is a bug. */ 2856 static void sky2_le_error(struct sky2_hw *hw, unsigned port, u16 q) 2857 { 2858 struct net_device *dev = hw->dev[port]; 2859 u16 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX)); 2860 2861 dev_err(&hw->pdev->dev, "%s: descriptor error q=%#x get=%u put=%u\n", 2862 dev->name, (unsigned) q, (unsigned) idx, 2863 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX))); 2864 2865 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK); 2866 } 2867 2868 static int sky2_rx_hung(struct net_device *dev) 2869 { 2870 struct sky2_port *sky2 = netdev_priv(dev); 2871 struct sky2_hw *hw = sky2->hw; 2872 unsigned port = sky2->port; 2873 unsigned rxq = rxqaddr[port]; 2874 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP)); 2875 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV)); 2876 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP)); 2877 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL)); 2878 2879 /* If idle and MAC or PCI is stuck */ 2880 if (sky2->check.last == dev->last_rx && 2881 ((mac_rp == sky2->check.mac_rp && 2882 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) || 2883 /* Check if the PCI RX hang */ 2884 (fifo_rp == sky2->check.fifo_rp && 2885 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) { 2886 netdev_printk(KERN_DEBUG, dev, 2887 "hung mac %d:%d fifo %d (%d:%d)\n", 2888 mac_lev, mac_rp, fifo_lev, 2889 fifo_rp, sky2_read8(hw, Q_ADDR(rxq, Q_WP))); 2890 return 1; 2891 } else { 2892 sky2->check.last = dev->last_rx; 2893 sky2->check.mac_rp = mac_rp; 2894 sky2->check.mac_lev = mac_lev; 2895 sky2->check.fifo_rp = fifo_rp; 2896 sky2->check.fifo_lev = fifo_lev; 2897 return 0; 2898 } 2899 } 2900 2901 static void sky2_watchdog(unsigned long arg) 2902 { 2903 struct sky2_hw *hw = (struct sky2_hw *) arg; 2904 2905 /* Check for lost IRQ once a second */ 2906 if (sky2_read32(hw, B0_ISRC)) { 2907 napi_schedule(&hw->napi); 2908 } else { 2909 int i, active = 0; 2910 2911 for (i = 0; i < hw->ports; i++) { 2912 struct net_device *dev = hw->dev[i]; 2913 if (!netif_running(dev)) 2914 continue; 2915 ++active; 2916 2917 /* For chips with Rx FIFO, check if stuck */ 2918 if ((hw->flags & SKY2_HW_RAM_BUFFER) && 2919 sky2_rx_hung(dev)) { 2920 netdev_info(dev, "receiver hang detected\n"); 2921 schedule_work(&hw->restart_work); 2922 return; 2923 } 2924 } 2925 2926 if (active == 0) 2927 return; 2928 } 2929 2930 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ)); 2931 } 2932 2933 /* Hardware/software error handling */ 2934 static void sky2_err_intr(struct sky2_hw *hw, u32 status) 2935 { 2936 if (net_ratelimit()) 2937 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status); 2938 2939 if (status & Y2_IS_HW_ERR) 2940 sky2_hw_intr(hw); 2941 2942 if (status & Y2_IS_IRQ_MAC1) 2943 sky2_mac_intr(hw, 0); 2944 2945 if (status & Y2_IS_IRQ_MAC2) 2946 sky2_mac_intr(hw, 1); 2947 2948 if (status & Y2_IS_CHK_RX1) 2949 sky2_le_error(hw, 0, Q_R1); 2950 2951 if (status & Y2_IS_CHK_RX2) 2952 sky2_le_error(hw, 1, Q_R2); 2953 2954 if (status & Y2_IS_CHK_TXA1) 2955 sky2_le_error(hw, 0, Q_XA1); 2956 2957 if (status & Y2_IS_CHK_TXA2) 2958 sky2_le_error(hw, 1, Q_XA2); 2959 } 2960 2961 static int sky2_poll(struct napi_struct *napi, int work_limit) 2962 { 2963 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi); 2964 u32 status = sky2_read32(hw, B0_Y2_SP_EISR); 2965 int work_done = 0; 2966 u16 idx; 2967 2968 if (unlikely(status & Y2_IS_ERROR)) 2969 sky2_err_intr(hw, status); 2970 2971 if (status & Y2_IS_IRQ_PHY1) 2972 sky2_phy_intr(hw, 0); 2973 2974 if (status & Y2_IS_IRQ_PHY2) 2975 sky2_phy_intr(hw, 1); 2976 2977 if (status & Y2_IS_PHY_QLNK) 2978 sky2_qlink_intr(hw); 2979 2980 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) { 2981 work_done += sky2_status_intr(hw, work_limit - work_done, idx); 2982 2983 if (work_done >= work_limit) 2984 goto done; 2985 } 2986 2987 napi_complete(napi); 2988 sky2_read32(hw, B0_Y2_SP_LISR); 2989 done: 2990 2991 return work_done; 2992 } 2993 2994 static irqreturn_t sky2_intr(int irq, void *dev_id) 2995 { 2996 struct sky2_hw *hw = dev_id; 2997 u32 status; 2998 2999 /* Reading this mask interrupts as side effect */ 3000 status = sky2_read32(hw, B0_Y2_SP_ISRC2); 3001 if (status == 0 || status == ~0) 3002 return IRQ_NONE; 3003 3004 prefetch(&hw->st_le[hw->st_idx]); 3005 3006 napi_schedule(&hw->napi); 3007 3008 return IRQ_HANDLED; 3009 } 3010 3011 #ifdef CONFIG_NET_POLL_CONTROLLER 3012 static void sky2_netpoll(struct net_device *dev) 3013 { 3014 struct sky2_port *sky2 = netdev_priv(dev); 3015 3016 napi_schedule(&sky2->hw->napi); 3017 } 3018 #endif 3019 3020 /* Chip internal frequency for clock calculations */ 3021 static u32 sky2_mhz(const struct sky2_hw *hw) 3022 { 3023 switch (hw->chip_id) { 3024 case CHIP_ID_YUKON_EC: 3025 case CHIP_ID_YUKON_EC_U: 3026 case CHIP_ID_YUKON_EX: 3027 case CHIP_ID_YUKON_SUPR: 3028 case CHIP_ID_YUKON_UL_2: 3029 case CHIP_ID_YUKON_OPT: 3030 case CHIP_ID_YUKON_PRM: 3031 case CHIP_ID_YUKON_OP_2: 3032 return 125; 3033 3034 case CHIP_ID_YUKON_FE: 3035 return 100; 3036 3037 case CHIP_ID_YUKON_FE_P: 3038 return 50; 3039 3040 case CHIP_ID_YUKON_XL: 3041 return 156; 3042 3043 default: 3044 BUG(); 3045 } 3046 } 3047 3048 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us) 3049 { 3050 return sky2_mhz(hw) * us; 3051 } 3052 3053 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk) 3054 { 3055 return clk / sky2_mhz(hw); 3056 } 3057 3058 3059 static int __devinit sky2_init(struct sky2_hw *hw) 3060 { 3061 u8 t8; 3062 3063 /* Enable all clocks and check for bad PCI access */ 3064 sky2_pci_write32(hw, PCI_DEV_REG3, 0); 3065 3066 sky2_write8(hw, B0_CTST, CS_RST_CLR); 3067 3068 hw->chip_id = sky2_read8(hw, B2_CHIP_ID); 3069 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4; 3070 3071 switch (hw->chip_id) { 3072 case CHIP_ID_YUKON_XL: 3073 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY; 3074 if (hw->chip_rev < CHIP_REV_YU_XL_A2) 3075 hw->flags |= SKY2_HW_RSS_BROKEN; 3076 break; 3077 3078 case CHIP_ID_YUKON_EC_U: 3079 hw->flags = SKY2_HW_GIGABIT 3080 | SKY2_HW_NEWER_PHY 3081 | SKY2_HW_ADV_POWER_CTL; 3082 break; 3083 3084 case CHIP_ID_YUKON_EX: 3085 hw->flags = SKY2_HW_GIGABIT 3086 | SKY2_HW_NEWER_PHY 3087 | SKY2_HW_NEW_LE 3088 | SKY2_HW_ADV_POWER_CTL 3089 | SKY2_HW_RSS_CHKSUM; 3090 3091 /* New transmit checksum */ 3092 if (hw->chip_rev != CHIP_REV_YU_EX_B0) 3093 hw->flags |= SKY2_HW_AUTO_TX_SUM; 3094 break; 3095 3096 case CHIP_ID_YUKON_EC: 3097 /* This rev is really old, and requires untested workarounds */ 3098 if (hw->chip_rev == CHIP_REV_YU_EC_A1) { 3099 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n"); 3100 return -EOPNOTSUPP; 3101 } 3102 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_RSS_BROKEN; 3103 break; 3104 3105 case CHIP_ID_YUKON_FE: 3106 hw->flags = SKY2_HW_RSS_BROKEN; 3107 break; 3108 3109 case CHIP_ID_YUKON_FE_P: 3110 hw->flags = SKY2_HW_NEWER_PHY 3111 | SKY2_HW_NEW_LE 3112 | SKY2_HW_AUTO_TX_SUM 3113 | SKY2_HW_ADV_POWER_CTL; 3114 3115 /* The workaround for status conflicts VLAN tag detection. */ 3116 if (hw->chip_rev == CHIP_REV_YU_FE2_A0) 3117 hw->flags |= SKY2_HW_VLAN_BROKEN | SKY2_HW_RSS_CHKSUM; 3118 break; 3119 3120 case CHIP_ID_YUKON_SUPR: 3121 hw->flags = SKY2_HW_GIGABIT 3122 | SKY2_HW_NEWER_PHY 3123 | SKY2_HW_NEW_LE 3124 | SKY2_HW_AUTO_TX_SUM 3125 | SKY2_HW_ADV_POWER_CTL; 3126 3127 if (hw->chip_rev == CHIP_REV_YU_SU_A0) 3128 hw->flags |= SKY2_HW_RSS_CHKSUM; 3129 break; 3130 3131 case CHIP_ID_YUKON_UL_2: 3132 hw->flags = SKY2_HW_GIGABIT 3133 | SKY2_HW_ADV_POWER_CTL; 3134 break; 3135 3136 case CHIP_ID_YUKON_OPT: 3137 case CHIP_ID_YUKON_PRM: 3138 case CHIP_ID_YUKON_OP_2: 3139 hw->flags = SKY2_HW_GIGABIT 3140 | SKY2_HW_NEW_LE 3141 | SKY2_HW_ADV_POWER_CTL; 3142 break; 3143 3144 default: 3145 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n", 3146 hw->chip_id); 3147 return -EOPNOTSUPP; 3148 } 3149 3150 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP); 3151 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P') 3152 hw->flags |= SKY2_HW_FIBRE_PHY; 3153 3154 hw->ports = 1; 3155 t8 = sky2_read8(hw, B2_Y2_HW_RES); 3156 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) { 3157 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC)) 3158 ++hw->ports; 3159 } 3160 3161 if (sky2_read8(hw, B2_E_0)) 3162 hw->flags |= SKY2_HW_RAM_BUFFER; 3163 3164 return 0; 3165 } 3166 3167 static void sky2_reset(struct sky2_hw *hw) 3168 { 3169 struct pci_dev *pdev = hw->pdev; 3170 u16 status; 3171 int i; 3172 u32 hwe_mask = Y2_HWE_ALL_MASK; 3173 3174 /* disable ASF */ 3175 if (hw->chip_id == CHIP_ID_YUKON_EX 3176 || hw->chip_id == CHIP_ID_YUKON_SUPR) { 3177 sky2_write32(hw, CPU_WDOG, 0); 3178 status = sky2_read16(hw, HCU_CCSR); 3179 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE | 3180 HCU_CCSR_UC_STATE_MSK); 3181 /* 3182 * CPU clock divider shouldn't be used because 3183 * - ASF firmware may malfunction 3184 * - Yukon-Supreme: Parallel FLASH doesn't support divided clocks 3185 */ 3186 status &= ~HCU_CCSR_CPU_CLK_DIVIDE_MSK; 3187 sky2_write16(hw, HCU_CCSR, status); 3188 sky2_write32(hw, CPU_WDOG, 0); 3189 } else 3190 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET); 3191 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE); 3192 3193 /* do a SW reset */ 3194 sky2_write8(hw, B0_CTST, CS_RST_SET); 3195 sky2_write8(hw, B0_CTST, CS_RST_CLR); 3196 3197 /* allow writes to PCI config */ 3198 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); 3199 3200 /* clear PCI errors, if any */ 3201 status = sky2_pci_read16(hw, PCI_STATUS); 3202 status |= PCI_STATUS_ERROR_BITS; 3203 sky2_pci_write16(hw, PCI_STATUS, status); 3204 3205 sky2_write8(hw, B0_CTST, CS_MRST_CLR); 3206 3207 if (pci_is_pcie(pdev)) { 3208 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS, 3209 0xfffffffful); 3210 3211 /* If error bit is stuck on ignore it */ 3212 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP) 3213 dev_info(&pdev->dev, "ignoring stuck error report bit\n"); 3214 else 3215 hwe_mask |= Y2_IS_PCI_EXP; 3216 } 3217 3218 sky2_power_on(hw); 3219 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 3220 3221 for (i = 0; i < hw->ports; i++) { 3222 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET); 3223 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR); 3224 3225 if (hw->chip_id == CHIP_ID_YUKON_EX || 3226 hw->chip_id == CHIP_ID_YUKON_SUPR) 3227 sky2_write16(hw, SK_REG(i, GMAC_CTRL), 3228 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON 3229 | GMC_BYP_RETR_ON); 3230 3231 } 3232 3233 if (hw->chip_id == CHIP_ID_YUKON_SUPR && hw->chip_rev > CHIP_REV_YU_SU_B0) { 3234 /* enable MACSec clock gating */ 3235 sky2_pci_write32(hw, PCI_DEV_REG3, P_CLK_MACSEC_DIS); 3236 } 3237 3238 if (hw->chip_id == CHIP_ID_YUKON_OPT || 3239 hw->chip_id == CHIP_ID_YUKON_PRM || 3240 hw->chip_id == CHIP_ID_YUKON_OP_2) { 3241 u16 reg; 3242 u32 msk; 3243 3244 if (hw->chip_id == CHIP_ID_YUKON_OPT && hw->chip_rev == 0) { 3245 /* disable PCI-E PHY power down (set PHY reg 0x80, bit 7 */ 3246 sky2_write32(hw, Y2_PEX_PHY_DATA, (0x80UL << 16) | (1 << 7)); 3247 3248 /* set PHY Link Detect Timer to 1.1 second (11x 100ms) */ 3249 reg = 10; 3250 3251 /* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */ 3252 sky2_write32(hw, Y2_PEX_PHY_DATA, PEX_DB_ACCESS | (0x08UL << 16)); 3253 } else { 3254 /* set PHY Link Detect Timer to 0.4 second (4x 100ms) */ 3255 reg = 3; 3256 } 3257 3258 reg <<= PSM_CONFIG_REG4_TIMER_PHY_LINK_DETECT_BASE; 3259 reg |= PSM_CONFIG_REG4_RST_PHY_LINK_DETECT; 3260 3261 /* reset PHY Link Detect */ 3262 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); 3263 sky2_pci_write16(hw, PSM_CONFIG_REG4, reg); 3264 3265 /* enable PHY Quick Link */ 3266 msk = sky2_read32(hw, B0_IMSK); 3267 msk |= Y2_IS_PHY_QLNK; 3268 sky2_write32(hw, B0_IMSK, msk); 3269 3270 /* check if PSMv2 was running before */ 3271 reg = sky2_pci_read16(hw, PSM_CONFIG_REG3); 3272 if (reg & PCI_EXP_LNKCTL_ASPMC) 3273 /* restore the PCIe Link Control register */ 3274 sky2_pci_write16(hw, pdev->pcie_cap + PCI_EXP_LNKCTL, 3275 reg); 3276 3277 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 3278 3279 /* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */ 3280 sky2_write32(hw, Y2_PEX_PHY_DATA, PEX_DB_ACCESS | (0x08UL << 16)); 3281 } 3282 3283 /* Clear I2C IRQ noise */ 3284 sky2_write32(hw, B2_I2C_IRQ, 1); 3285 3286 /* turn off hardware timer (unused) */ 3287 sky2_write8(hw, B2_TI_CTRL, TIM_STOP); 3288 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ); 3289 3290 /* Turn off descriptor polling */ 3291 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP); 3292 3293 /* Turn off receive timestamp */ 3294 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP); 3295 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); 3296 3297 /* enable the Tx Arbiters */ 3298 for (i = 0; i < hw->ports; i++) 3299 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB); 3300 3301 /* Initialize ram interface */ 3302 for (i = 0; i < hw->ports; i++) { 3303 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR); 3304 3305 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53); 3306 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53); 3307 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53); 3308 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53); 3309 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53); 3310 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53); 3311 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53); 3312 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53); 3313 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53); 3314 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53); 3315 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53); 3316 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53); 3317 } 3318 3319 sky2_write32(hw, B0_HWE_IMSK, hwe_mask); 3320 3321 for (i = 0; i < hw->ports; i++) 3322 sky2_gmac_reset(hw, i); 3323 3324 memset(hw->st_le, 0, hw->st_size * sizeof(struct sky2_status_le)); 3325 hw->st_idx = 0; 3326 3327 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET); 3328 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR); 3329 3330 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma); 3331 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32); 3332 3333 /* Set the list last index */ 3334 sky2_write16(hw, STAT_LAST_IDX, hw->st_size - 1); 3335 3336 sky2_write16(hw, STAT_TX_IDX_TH, 10); 3337 sky2_write8(hw, STAT_FIFO_WM, 16); 3338 3339 /* set Status-FIFO ISR watermark */ 3340 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0) 3341 sky2_write8(hw, STAT_FIFO_ISR_WM, 4); 3342 else 3343 sky2_write8(hw, STAT_FIFO_ISR_WM, 16); 3344 3345 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000)); 3346 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20)); 3347 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100)); 3348 3349 /* enable status unit */ 3350 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON); 3351 3352 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START); 3353 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START); 3354 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START); 3355 } 3356 3357 /* Take device down (offline). 3358 * Equivalent to doing dev_stop() but this does not 3359 * inform upper layers of the transition. 3360 */ 3361 static void sky2_detach(struct net_device *dev) 3362 { 3363 if (netif_running(dev)) { 3364 netif_tx_lock(dev); 3365 netif_device_detach(dev); /* stop txq */ 3366 netif_tx_unlock(dev); 3367 sky2_down(dev); 3368 } 3369 } 3370 3371 /* Bring device back after doing sky2_detach */ 3372 static int sky2_reattach(struct net_device *dev) 3373 { 3374 int err = 0; 3375 3376 if (netif_running(dev)) { 3377 err = sky2_up(dev); 3378 if (err) { 3379 netdev_info(dev, "could not restart %d\n", err); 3380 dev_close(dev); 3381 } else { 3382 netif_device_attach(dev); 3383 sky2_set_multicast(dev); 3384 } 3385 } 3386 3387 return err; 3388 } 3389 3390 static void sky2_all_down(struct sky2_hw *hw) 3391 { 3392 int i; 3393 3394 sky2_read32(hw, B0_IMSK); 3395 sky2_write32(hw, B0_IMSK, 0); 3396 synchronize_irq(hw->pdev->irq); 3397 napi_disable(&hw->napi); 3398 3399 for (i = 0; i < hw->ports; i++) { 3400 struct net_device *dev = hw->dev[i]; 3401 struct sky2_port *sky2 = netdev_priv(dev); 3402 3403 if (!netif_running(dev)) 3404 continue; 3405 3406 netif_carrier_off(dev); 3407 netif_tx_disable(dev); 3408 sky2_hw_down(sky2); 3409 } 3410 } 3411 3412 static void sky2_all_up(struct sky2_hw *hw) 3413 { 3414 u32 imask = Y2_IS_BASE; 3415 int i; 3416 3417 for (i = 0; i < hw->ports; i++) { 3418 struct net_device *dev = hw->dev[i]; 3419 struct sky2_port *sky2 = netdev_priv(dev); 3420 3421 if (!netif_running(dev)) 3422 continue; 3423 3424 sky2_hw_up(sky2); 3425 sky2_set_multicast(dev); 3426 imask |= portirq_msk[i]; 3427 netif_wake_queue(dev); 3428 } 3429 3430 sky2_write32(hw, B0_IMSK, imask); 3431 sky2_read32(hw, B0_IMSK); 3432 3433 sky2_read32(hw, B0_Y2_SP_LISR); 3434 napi_enable(&hw->napi); 3435 } 3436 3437 static void sky2_restart(struct work_struct *work) 3438 { 3439 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work); 3440 3441 rtnl_lock(); 3442 3443 sky2_all_down(hw); 3444 sky2_reset(hw); 3445 sky2_all_up(hw); 3446 3447 rtnl_unlock(); 3448 } 3449 3450 static inline u8 sky2_wol_supported(const struct sky2_hw *hw) 3451 { 3452 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0; 3453 } 3454 3455 static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 3456 { 3457 const struct sky2_port *sky2 = netdev_priv(dev); 3458 3459 wol->supported = sky2_wol_supported(sky2->hw); 3460 wol->wolopts = sky2->wol; 3461 } 3462 3463 static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 3464 { 3465 struct sky2_port *sky2 = netdev_priv(dev); 3466 struct sky2_hw *hw = sky2->hw; 3467 bool enable_wakeup = false; 3468 int i; 3469 3470 if ((wol->wolopts & ~sky2_wol_supported(sky2->hw)) || 3471 !device_can_wakeup(&hw->pdev->dev)) 3472 return -EOPNOTSUPP; 3473 3474 sky2->wol = wol->wolopts; 3475 3476 for (i = 0; i < hw->ports; i++) { 3477 struct net_device *dev = hw->dev[i]; 3478 struct sky2_port *sky2 = netdev_priv(dev); 3479 3480 if (sky2->wol) 3481 enable_wakeup = true; 3482 } 3483 device_set_wakeup_enable(&hw->pdev->dev, enable_wakeup); 3484 3485 return 0; 3486 } 3487 3488 static u32 sky2_supported_modes(const struct sky2_hw *hw) 3489 { 3490 if (sky2_is_copper(hw)) { 3491 u32 modes = SUPPORTED_10baseT_Half 3492 | SUPPORTED_10baseT_Full 3493 | SUPPORTED_100baseT_Half 3494 | SUPPORTED_100baseT_Full; 3495 3496 if (hw->flags & SKY2_HW_GIGABIT) 3497 modes |= SUPPORTED_1000baseT_Half 3498 | SUPPORTED_1000baseT_Full; 3499 return modes; 3500 } else 3501 return SUPPORTED_1000baseT_Half 3502 | SUPPORTED_1000baseT_Full; 3503 } 3504 3505 static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd) 3506 { 3507 struct sky2_port *sky2 = netdev_priv(dev); 3508 struct sky2_hw *hw = sky2->hw; 3509 3510 ecmd->transceiver = XCVR_INTERNAL; 3511 ecmd->supported = sky2_supported_modes(hw); 3512 ecmd->phy_address = PHY_ADDR_MARV; 3513 if (sky2_is_copper(hw)) { 3514 ecmd->port = PORT_TP; 3515 ethtool_cmd_speed_set(ecmd, sky2->speed); 3516 ecmd->supported |= SUPPORTED_Autoneg | SUPPORTED_TP; 3517 } else { 3518 ethtool_cmd_speed_set(ecmd, SPEED_1000); 3519 ecmd->port = PORT_FIBRE; 3520 ecmd->supported |= SUPPORTED_Autoneg | SUPPORTED_FIBRE; 3521 } 3522 3523 ecmd->advertising = sky2->advertising; 3524 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_SPEED) 3525 ? AUTONEG_ENABLE : AUTONEG_DISABLE; 3526 ecmd->duplex = sky2->duplex; 3527 return 0; 3528 } 3529 3530 static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd) 3531 { 3532 struct sky2_port *sky2 = netdev_priv(dev); 3533 const struct sky2_hw *hw = sky2->hw; 3534 u32 supported = sky2_supported_modes(hw); 3535 3536 if (ecmd->autoneg == AUTONEG_ENABLE) { 3537 if (ecmd->advertising & ~supported) 3538 return -EINVAL; 3539 3540 if (sky2_is_copper(hw)) 3541 sky2->advertising = ecmd->advertising | 3542 ADVERTISED_TP | 3543 ADVERTISED_Autoneg; 3544 else 3545 sky2->advertising = ecmd->advertising | 3546 ADVERTISED_FIBRE | 3547 ADVERTISED_Autoneg; 3548 3549 sky2->flags |= SKY2_FLAG_AUTO_SPEED; 3550 sky2->duplex = -1; 3551 sky2->speed = -1; 3552 } else { 3553 u32 setting; 3554 u32 speed = ethtool_cmd_speed(ecmd); 3555 3556 switch (speed) { 3557 case SPEED_1000: 3558 if (ecmd->duplex == DUPLEX_FULL) 3559 setting = SUPPORTED_1000baseT_Full; 3560 else if (ecmd->duplex == DUPLEX_HALF) 3561 setting = SUPPORTED_1000baseT_Half; 3562 else 3563 return -EINVAL; 3564 break; 3565 case SPEED_100: 3566 if (ecmd->duplex == DUPLEX_FULL) 3567 setting = SUPPORTED_100baseT_Full; 3568 else if (ecmd->duplex == DUPLEX_HALF) 3569 setting = SUPPORTED_100baseT_Half; 3570 else 3571 return -EINVAL; 3572 break; 3573 3574 case SPEED_10: 3575 if (ecmd->duplex == DUPLEX_FULL) 3576 setting = SUPPORTED_10baseT_Full; 3577 else if (ecmd->duplex == DUPLEX_HALF) 3578 setting = SUPPORTED_10baseT_Half; 3579 else 3580 return -EINVAL; 3581 break; 3582 default: 3583 return -EINVAL; 3584 } 3585 3586 if ((setting & supported) == 0) 3587 return -EINVAL; 3588 3589 sky2->speed = speed; 3590 sky2->duplex = ecmd->duplex; 3591 sky2->flags &= ~SKY2_FLAG_AUTO_SPEED; 3592 } 3593 3594 if (netif_running(dev)) { 3595 sky2_phy_reinit(sky2); 3596 sky2_set_multicast(dev); 3597 } 3598 3599 return 0; 3600 } 3601 3602 static void sky2_get_drvinfo(struct net_device *dev, 3603 struct ethtool_drvinfo *info) 3604 { 3605 struct sky2_port *sky2 = netdev_priv(dev); 3606 3607 strcpy(info->driver, DRV_NAME); 3608 strcpy(info->version, DRV_VERSION); 3609 strcpy(info->fw_version, "N/A"); 3610 strcpy(info->bus_info, pci_name(sky2->hw->pdev)); 3611 } 3612 3613 static const struct sky2_stat { 3614 char name[ETH_GSTRING_LEN]; 3615 u16 offset; 3616 } sky2_stats[] = { 3617 { "tx_bytes", GM_TXO_OK_HI }, 3618 { "rx_bytes", GM_RXO_OK_HI }, 3619 { "tx_broadcast", GM_TXF_BC_OK }, 3620 { "rx_broadcast", GM_RXF_BC_OK }, 3621 { "tx_multicast", GM_TXF_MC_OK }, 3622 { "rx_multicast", GM_RXF_MC_OK }, 3623 { "tx_unicast", GM_TXF_UC_OK }, 3624 { "rx_unicast", GM_RXF_UC_OK }, 3625 { "tx_mac_pause", GM_TXF_MPAUSE }, 3626 { "rx_mac_pause", GM_RXF_MPAUSE }, 3627 { "collisions", GM_TXF_COL }, 3628 { "late_collision",GM_TXF_LAT_COL }, 3629 { "aborted", GM_TXF_ABO_COL }, 3630 { "single_collisions", GM_TXF_SNG_COL }, 3631 { "multi_collisions", GM_TXF_MUL_COL }, 3632 3633 { "rx_short", GM_RXF_SHT }, 3634 { "rx_runt", GM_RXE_FRAG }, 3635 { "rx_64_byte_packets", GM_RXF_64B }, 3636 { "rx_65_to_127_byte_packets", GM_RXF_127B }, 3637 { "rx_128_to_255_byte_packets", GM_RXF_255B }, 3638 { "rx_256_to_511_byte_packets", GM_RXF_511B }, 3639 { "rx_512_to_1023_byte_packets", GM_RXF_1023B }, 3640 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B }, 3641 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ }, 3642 { "rx_too_long", GM_RXF_LNG_ERR }, 3643 { "rx_fifo_overflow", GM_RXE_FIFO_OV }, 3644 { "rx_jabber", GM_RXF_JAB_PKT }, 3645 { "rx_fcs_error", GM_RXF_FCS_ERR }, 3646 3647 { "tx_64_byte_packets", GM_TXF_64B }, 3648 { "tx_65_to_127_byte_packets", GM_TXF_127B }, 3649 { "tx_128_to_255_byte_packets", GM_TXF_255B }, 3650 { "tx_256_to_511_byte_packets", GM_TXF_511B }, 3651 { "tx_512_to_1023_byte_packets", GM_TXF_1023B }, 3652 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B }, 3653 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ }, 3654 { "tx_fifo_underrun", GM_TXE_FIFO_UR }, 3655 }; 3656 3657 static u32 sky2_get_msglevel(struct net_device *netdev) 3658 { 3659 struct sky2_port *sky2 = netdev_priv(netdev); 3660 return sky2->msg_enable; 3661 } 3662 3663 static int sky2_nway_reset(struct net_device *dev) 3664 { 3665 struct sky2_port *sky2 = netdev_priv(dev); 3666 3667 if (!netif_running(dev) || !(sky2->flags & SKY2_FLAG_AUTO_SPEED)) 3668 return -EINVAL; 3669 3670 sky2_phy_reinit(sky2); 3671 sky2_set_multicast(dev); 3672 3673 return 0; 3674 } 3675 3676 static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count) 3677 { 3678 struct sky2_hw *hw = sky2->hw; 3679 unsigned port = sky2->port; 3680 int i; 3681 3682 data[0] = get_stats64(hw, port, GM_TXO_OK_LO); 3683 data[1] = get_stats64(hw, port, GM_RXO_OK_LO); 3684 3685 for (i = 2; i < count; i++) 3686 data[i] = get_stats32(hw, port, sky2_stats[i].offset); 3687 } 3688 3689 static void sky2_set_msglevel(struct net_device *netdev, u32 value) 3690 { 3691 struct sky2_port *sky2 = netdev_priv(netdev); 3692 sky2->msg_enable = value; 3693 } 3694 3695 static int sky2_get_sset_count(struct net_device *dev, int sset) 3696 { 3697 switch (sset) { 3698 case ETH_SS_STATS: 3699 return ARRAY_SIZE(sky2_stats); 3700 default: 3701 return -EOPNOTSUPP; 3702 } 3703 } 3704 3705 static void sky2_get_ethtool_stats(struct net_device *dev, 3706 struct ethtool_stats *stats, u64 * data) 3707 { 3708 struct sky2_port *sky2 = netdev_priv(dev); 3709 3710 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats)); 3711 } 3712 3713 static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data) 3714 { 3715 int i; 3716 3717 switch (stringset) { 3718 case ETH_SS_STATS: 3719 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++) 3720 memcpy(data + i * ETH_GSTRING_LEN, 3721 sky2_stats[i].name, ETH_GSTRING_LEN); 3722 break; 3723 } 3724 } 3725 3726 static int sky2_set_mac_address(struct net_device *dev, void *p) 3727 { 3728 struct sky2_port *sky2 = netdev_priv(dev); 3729 struct sky2_hw *hw = sky2->hw; 3730 unsigned port = sky2->port; 3731 const struct sockaddr *addr = p; 3732 3733 if (!is_valid_ether_addr(addr->sa_data)) 3734 return -EADDRNOTAVAIL; 3735 3736 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN); 3737 memcpy_toio(hw->regs + B2_MAC_1 + port * 8, 3738 dev->dev_addr, ETH_ALEN); 3739 memcpy_toio(hw->regs + B2_MAC_2 + port * 8, 3740 dev->dev_addr, ETH_ALEN); 3741 3742 /* virtual address for data */ 3743 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr); 3744 3745 /* physical address: used for pause frames */ 3746 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr); 3747 3748 return 0; 3749 } 3750 3751 static inline void sky2_add_filter(u8 filter[8], const u8 *addr) 3752 { 3753 u32 bit; 3754 3755 bit = ether_crc(ETH_ALEN, addr) & 63; 3756 filter[bit >> 3] |= 1 << (bit & 7); 3757 } 3758 3759 static void sky2_set_multicast(struct net_device *dev) 3760 { 3761 struct sky2_port *sky2 = netdev_priv(dev); 3762 struct sky2_hw *hw = sky2->hw; 3763 unsigned port = sky2->port; 3764 struct netdev_hw_addr *ha; 3765 u16 reg; 3766 u8 filter[8]; 3767 int rx_pause; 3768 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 }; 3769 3770 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH); 3771 memset(filter, 0, sizeof(filter)); 3772 3773 reg = gma_read16(hw, port, GM_RX_CTRL); 3774 reg |= GM_RXCR_UCF_ENA; 3775 3776 if (dev->flags & IFF_PROMISC) /* promiscuous */ 3777 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA); 3778 else if (dev->flags & IFF_ALLMULTI) 3779 memset(filter, 0xff, sizeof(filter)); 3780 else if (netdev_mc_empty(dev) && !rx_pause) 3781 reg &= ~GM_RXCR_MCF_ENA; 3782 else { 3783 reg |= GM_RXCR_MCF_ENA; 3784 3785 if (rx_pause) 3786 sky2_add_filter(filter, pause_mc_addr); 3787 3788 netdev_for_each_mc_addr(ha, dev) 3789 sky2_add_filter(filter, ha->addr); 3790 } 3791 3792 gma_write16(hw, port, GM_MC_ADDR_H1, 3793 (u16) filter[0] | ((u16) filter[1] << 8)); 3794 gma_write16(hw, port, GM_MC_ADDR_H2, 3795 (u16) filter[2] | ((u16) filter[3] << 8)); 3796 gma_write16(hw, port, GM_MC_ADDR_H3, 3797 (u16) filter[4] | ((u16) filter[5] << 8)); 3798 gma_write16(hw, port, GM_MC_ADDR_H4, 3799 (u16) filter[6] | ((u16) filter[7] << 8)); 3800 3801 gma_write16(hw, port, GM_RX_CTRL, reg); 3802 } 3803 3804 static struct rtnl_link_stats64 *sky2_get_stats(struct net_device *dev, 3805 struct rtnl_link_stats64 *stats) 3806 { 3807 struct sky2_port *sky2 = netdev_priv(dev); 3808 struct sky2_hw *hw = sky2->hw; 3809 unsigned port = sky2->port; 3810 unsigned int start; 3811 u64 _bytes, _packets; 3812 3813 do { 3814 start = u64_stats_fetch_begin_bh(&sky2->rx_stats.syncp); 3815 _bytes = sky2->rx_stats.bytes; 3816 _packets = sky2->rx_stats.packets; 3817 } while (u64_stats_fetch_retry_bh(&sky2->rx_stats.syncp, start)); 3818 3819 stats->rx_packets = _packets; 3820 stats->rx_bytes = _bytes; 3821 3822 do { 3823 start = u64_stats_fetch_begin_bh(&sky2->tx_stats.syncp); 3824 _bytes = sky2->tx_stats.bytes; 3825 _packets = sky2->tx_stats.packets; 3826 } while (u64_stats_fetch_retry_bh(&sky2->tx_stats.syncp, start)); 3827 3828 stats->tx_packets = _packets; 3829 stats->tx_bytes = _bytes; 3830 3831 stats->multicast = get_stats32(hw, port, GM_RXF_MC_OK) 3832 + get_stats32(hw, port, GM_RXF_BC_OK); 3833 3834 stats->collisions = get_stats32(hw, port, GM_TXF_COL); 3835 3836 stats->rx_length_errors = get_stats32(hw, port, GM_RXF_LNG_ERR); 3837 stats->rx_crc_errors = get_stats32(hw, port, GM_RXF_FCS_ERR); 3838 stats->rx_frame_errors = get_stats32(hw, port, GM_RXF_SHT) 3839 + get_stats32(hw, port, GM_RXE_FRAG); 3840 stats->rx_over_errors = get_stats32(hw, port, GM_RXE_FIFO_OV); 3841 3842 stats->rx_dropped = dev->stats.rx_dropped; 3843 stats->rx_fifo_errors = dev->stats.rx_fifo_errors; 3844 stats->tx_fifo_errors = dev->stats.tx_fifo_errors; 3845 3846 return stats; 3847 } 3848 3849 /* Can have one global because blinking is controlled by 3850 * ethtool and that is always under RTNL mutex 3851 */ 3852 static void sky2_led(struct sky2_port *sky2, enum led_mode mode) 3853 { 3854 struct sky2_hw *hw = sky2->hw; 3855 unsigned port = sky2->port; 3856 3857 spin_lock_bh(&sky2->phy_lock); 3858 if (hw->chip_id == CHIP_ID_YUKON_EC_U || 3859 hw->chip_id == CHIP_ID_YUKON_EX || 3860 hw->chip_id == CHIP_ID_YUKON_SUPR) { 3861 u16 pg; 3862 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); 3863 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); 3864 3865 switch (mode) { 3866 case MO_LED_OFF: 3867 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, 3868 PHY_M_LEDC_LOS_CTRL(8) | 3869 PHY_M_LEDC_INIT_CTRL(8) | 3870 PHY_M_LEDC_STA1_CTRL(8) | 3871 PHY_M_LEDC_STA0_CTRL(8)); 3872 break; 3873 case MO_LED_ON: 3874 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, 3875 PHY_M_LEDC_LOS_CTRL(9) | 3876 PHY_M_LEDC_INIT_CTRL(9) | 3877 PHY_M_LEDC_STA1_CTRL(9) | 3878 PHY_M_LEDC_STA0_CTRL(9)); 3879 break; 3880 case MO_LED_BLINK: 3881 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, 3882 PHY_M_LEDC_LOS_CTRL(0xa) | 3883 PHY_M_LEDC_INIT_CTRL(0xa) | 3884 PHY_M_LEDC_STA1_CTRL(0xa) | 3885 PHY_M_LEDC_STA0_CTRL(0xa)); 3886 break; 3887 case MO_LED_NORM: 3888 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, 3889 PHY_M_LEDC_LOS_CTRL(1) | 3890 PHY_M_LEDC_INIT_CTRL(8) | 3891 PHY_M_LEDC_STA1_CTRL(7) | 3892 PHY_M_LEDC_STA0_CTRL(7)); 3893 } 3894 3895 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); 3896 } else 3897 gm_phy_write(hw, port, PHY_MARV_LED_OVER, 3898 PHY_M_LED_MO_DUP(mode) | 3899 PHY_M_LED_MO_10(mode) | 3900 PHY_M_LED_MO_100(mode) | 3901 PHY_M_LED_MO_1000(mode) | 3902 PHY_M_LED_MO_RX(mode) | 3903 PHY_M_LED_MO_TX(mode)); 3904 3905 spin_unlock_bh(&sky2->phy_lock); 3906 } 3907 3908 /* blink LED's for finding board */ 3909 static int sky2_set_phys_id(struct net_device *dev, 3910 enum ethtool_phys_id_state state) 3911 { 3912 struct sky2_port *sky2 = netdev_priv(dev); 3913 3914 switch (state) { 3915 case ETHTOOL_ID_ACTIVE: 3916 return 1; /* cycle on/off once per second */ 3917 case ETHTOOL_ID_INACTIVE: 3918 sky2_led(sky2, MO_LED_NORM); 3919 break; 3920 case ETHTOOL_ID_ON: 3921 sky2_led(sky2, MO_LED_ON); 3922 break; 3923 case ETHTOOL_ID_OFF: 3924 sky2_led(sky2, MO_LED_OFF); 3925 break; 3926 } 3927 3928 return 0; 3929 } 3930 3931 static void sky2_get_pauseparam(struct net_device *dev, 3932 struct ethtool_pauseparam *ecmd) 3933 { 3934 struct sky2_port *sky2 = netdev_priv(dev); 3935 3936 switch (sky2->flow_mode) { 3937 case FC_NONE: 3938 ecmd->tx_pause = ecmd->rx_pause = 0; 3939 break; 3940 case FC_TX: 3941 ecmd->tx_pause = 1, ecmd->rx_pause = 0; 3942 break; 3943 case FC_RX: 3944 ecmd->tx_pause = 0, ecmd->rx_pause = 1; 3945 break; 3946 case FC_BOTH: 3947 ecmd->tx_pause = ecmd->rx_pause = 1; 3948 } 3949 3950 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_PAUSE) 3951 ? AUTONEG_ENABLE : AUTONEG_DISABLE; 3952 } 3953 3954 static int sky2_set_pauseparam(struct net_device *dev, 3955 struct ethtool_pauseparam *ecmd) 3956 { 3957 struct sky2_port *sky2 = netdev_priv(dev); 3958 3959 if (ecmd->autoneg == AUTONEG_ENABLE) 3960 sky2->flags |= SKY2_FLAG_AUTO_PAUSE; 3961 else 3962 sky2->flags &= ~SKY2_FLAG_AUTO_PAUSE; 3963 3964 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause); 3965 3966 if (netif_running(dev)) 3967 sky2_phy_reinit(sky2); 3968 3969 return 0; 3970 } 3971 3972 static int sky2_get_coalesce(struct net_device *dev, 3973 struct ethtool_coalesce *ecmd) 3974 { 3975 struct sky2_port *sky2 = netdev_priv(dev); 3976 struct sky2_hw *hw = sky2->hw; 3977 3978 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP) 3979 ecmd->tx_coalesce_usecs = 0; 3980 else { 3981 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI); 3982 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks); 3983 } 3984 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH); 3985 3986 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP) 3987 ecmd->rx_coalesce_usecs = 0; 3988 else { 3989 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI); 3990 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks); 3991 } 3992 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM); 3993 3994 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP) 3995 ecmd->rx_coalesce_usecs_irq = 0; 3996 else { 3997 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI); 3998 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks); 3999 } 4000 4001 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM); 4002 4003 return 0; 4004 } 4005 4006 /* Note: this affect both ports */ 4007 static int sky2_set_coalesce(struct net_device *dev, 4008 struct ethtool_coalesce *ecmd) 4009 { 4010 struct sky2_port *sky2 = netdev_priv(dev); 4011 struct sky2_hw *hw = sky2->hw; 4012 const u32 tmax = sky2_clk2us(hw, 0x0ffffff); 4013 4014 if (ecmd->tx_coalesce_usecs > tmax || 4015 ecmd->rx_coalesce_usecs > tmax || 4016 ecmd->rx_coalesce_usecs_irq > tmax) 4017 return -EINVAL; 4018 4019 if (ecmd->tx_max_coalesced_frames >= sky2->tx_ring_size-1) 4020 return -EINVAL; 4021 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING) 4022 return -EINVAL; 4023 if (ecmd->rx_max_coalesced_frames_irq > RX_MAX_PENDING) 4024 return -EINVAL; 4025 4026 if (ecmd->tx_coalesce_usecs == 0) 4027 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP); 4028 else { 4029 sky2_write32(hw, STAT_TX_TIMER_INI, 4030 sky2_us2clk(hw, ecmd->tx_coalesce_usecs)); 4031 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START); 4032 } 4033 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames); 4034 4035 if (ecmd->rx_coalesce_usecs == 0) 4036 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP); 4037 else { 4038 sky2_write32(hw, STAT_LEV_TIMER_INI, 4039 sky2_us2clk(hw, ecmd->rx_coalesce_usecs)); 4040 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START); 4041 } 4042 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames); 4043 4044 if (ecmd->rx_coalesce_usecs_irq == 0) 4045 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP); 4046 else { 4047 sky2_write32(hw, STAT_ISR_TIMER_INI, 4048 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq)); 4049 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START); 4050 } 4051 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq); 4052 return 0; 4053 } 4054 4055 static void sky2_get_ringparam(struct net_device *dev, 4056 struct ethtool_ringparam *ering) 4057 { 4058 struct sky2_port *sky2 = netdev_priv(dev); 4059 4060 ering->rx_max_pending = RX_MAX_PENDING; 4061 ering->rx_mini_max_pending = 0; 4062 ering->rx_jumbo_max_pending = 0; 4063 ering->tx_max_pending = TX_MAX_PENDING; 4064 4065 ering->rx_pending = sky2->rx_pending; 4066 ering->rx_mini_pending = 0; 4067 ering->rx_jumbo_pending = 0; 4068 ering->tx_pending = sky2->tx_pending; 4069 } 4070 4071 static int sky2_set_ringparam(struct net_device *dev, 4072 struct ethtool_ringparam *ering) 4073 { 4074 struct sky2_port *sky2 = netdev_priv(dev); 4075 4076 if (ering->rx_pending > RX_MAX_PENDING || 4077 ering->rx_pending < 8 || 4078 ering->tx_pending < TX_MIN_PENDING || 4079 ering->tx_pending > TX_MAX_PENDING) 4080 return -EINVAL; 4081 4082 sky2_detach(dev); 4083 4084 sky2->rx_pending = ering->rx_pending; 4085 sky2->tx_pending = ering->tx_pending; 4086 sky2->tx_ring_size = roundup_pow_of_two(sky2->tx_pending+1); 4087 4088 return sky2_reattach(dev); 4089 } 4090 4091 static int sky2_get_regs_len(struct net_device *dev) 4092 { 4093 return 0x4000; 4094 } 4095 4096 static int sky2_reg_access_ok(struct sky2_hw *hw, unsigned int b) 4097 { 4098 /* This complicated switch statement is to make sure and 4099 * only access regions that are unreserved. 4100 * Some blocks are only valid on dual port cards. 4101 */ 4102 switch (b) { 4103 /* second port */ 4104 case 5: /* Tx Arbiter 2 */ 4105 case 9: /* RX2 */ 4106 case 14 ... 15: /* TX2 */ 4107 case 17: case 19: /* Ram Buffer 2 */ 4108 case 22 ... 23: /* Tx Ram Buffer 2 */ 4109 case 25: /* Rx MAC Fifo 1 */ 4110 case 27: /* Tx MAC Fifo 2 */ 4111 case 31: /* GPHY 2 */ 4112 case 40 ... 47: /* Pattern Ram 2 */ 4113 case 52: case 54: /* TCP Segmentation 2 */ 4114 case 112 ... 116: /* GMAC 2 */ 4115 return hw->ports > 1; 4116 4117 case 0: /* Control */ 4118 case 2: /* Mac address */ 4119 case 4: /* Tx Arbiter 1 */ 4120 case 7: /* PCI express reg */ 4121 case 8: /* RX1 */ 4122 case 12 ... 13: /* TX1 */ 4123 case 16: case 18:/* Rx Ram Buffer 1 */ 4124 case 20 ... 21: /* Tx Ram Buffer 1 */ 4125 case 24: /* Rx MAC Fifo 1 */ 4126 case 26: /* Tx MAC Fifo 1 */ 4127 case 28 ... 29: /* Descriptor and status unit */ 4128 case 30: /* GPHY 1*/ 4129 case 32 ... 39: /* Pattern Ram 1 */ 4130 case 48: case 50: /* TCP Segmentation 1 */ 4131 case 56 ... 60: /* PCI space */ 4132 case 80 ... 84: /* GMAC 1 */ 4133 return 1; 4134 4135 default: 4136 return 0; 4137 } 4138 } 4139 4140 /* 4141 * Returns copy of control register region 4142 * Note: ethtool_get_regs always provides full size (16k) buffer 4143 */ 4144 static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs, 4145 void *p) 4146 { 4147 const struct sky2_port *sky2 = netdev_priv(dev); 4148 const void __iomem *io = sky2->hw->regs; 4149 unsigned int b; 4150 4151 regs->version = 1; 4152 4153 for (b = 0; b < 128; b++) { 4154 /* skip poisonous diagnostic ram region in block 3 */ 4155 if (b == 3) 4156 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10); 4157 else if (sky2_reg_access_ok(sky2->hw, b)) 4158 memcpy_fromio(p, io, 128); 4159 else 4160 memset(p, 0, 128); 4161 4162 p += 128; 4163 io += 128; 4164 } 4165 } 4166 4167 static int sky2_get_eeprom_len(struct net_device *dev) 4168 { 4169 struct sky2_port *sky2 = netdev_priv(dev); 4170 struct sky2_hw *hw = sky2->hw; 4171 u16 reg2; 4172 4173 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2); 4174 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8); 4175 } 4176 4177 static int sky2_vpd_wait(const struct sky2_hw *hw, int cap, u16 busy) 4178 { 4179 unsigned long start = jiffies; 4180 4181 while ( (sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F) == busy) { 4182 /* Can take up to 10.6 ms for write */ 4183 if (time_after(jiffies, start + HZ/4)) { 4184 dev_err(&hw->pdev->dev, "VPD cycle timed out\n"); 4185 return -ETIMEDOUT; 4186 } 4187 mdelay(1); 4188 } 4189 4190 return 0; 4191 } 4192 4193 static int sky2_vpd_read(struct sky2_hw *hw, int cap, void *data, 4194 u16 offset, size_t length) 4195 { 4196 int rc = 0; 4197 4198 while (length > 0) { 4199 u32 val; 4200 4201 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset); 4202 rc = sky2_vpd_wait(hw, cap, 0); 4203 if (rc) 4204 break; 4205 4206 val = sky2_pci_read32(hw, cap + PCI_VPD_DATA); 4207 4208 memcpy(data, &val, min(sizeof(val), length)); 4209 offset += sizeof(u32); 4210 data += sizeof(u32); 4211 length -= sizeof(u32); 4212 } 4213 4214 return rc; 4215 } 4216 4217 static int sky2_vpd_write(struct sky2_hw *hw, int cap, const void *data, 4218 u16 offset, unsigned int length) 4219 { 4220 unsigned int i; 4221 int rc = 0; 4222 4223 for (i = 0; i < length; i += sizeof(u32)) { 4224 u32 val = *(u32 *)(data + i); 4225 4226 sky2_pci_write32(hw, cap + PCI_VPD_DATA, val); 4227 sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F); 4228 4229 rc = sky2_vpd_wait(hw, cap, PCI_VPD_ADDR_F); 4230 if (rc) 4231 break; 4232 } 4233 return rc; 4234 } 4235 4236 static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, 4237 u8 *data) 4238 { 4239 struct sky2_port *sky2 = netdev_priv(dev); 4240 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD); 4241 4242 if (!cap) 4243 return -EINVAL; 4244 4245 eeprom->magic = SKY2_EEPROM_MAGIC; 4246 4247 return sky2_vpd_read(sky2->hw, cap, data, eeprom->offset, eeprom->len); 4248 } 4249 4250 static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, 4251 u8 *data) 4252 { 4253 struct sky2_port *sky2 = netdev_priv(dev); 4254 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD); 4255 4256 if (!cap) 4257 return -EINVAL; 4258 4259 if (eeprom->magic != SKY2_EEPROM_MAGIC) 4260 return -EINVAL; 4261 4262 /* Partial writes not supported */ 4263 if ((eeprom->offset & 3) || (eeprom->len & 3)) 4264 return -EINVAL; 4265 4266 return sky2_vpd_write(sky2->hw, cap, data, eeprom->offset, eeprom->len); 4267 } 4268 4269 static u32 sky2_fix_features(struct net_device *dev, u32 features) 4270 { 4271 const struct sky2_port *sky2 = netdev_priv(dev); 4272 const struct sky2_hw *hw = sky2->hw; 4273 4274 /* In order to do Jumbo packets on these chips, need to turn off the 4275 * transmit store/forward. Therefore checksum offload won't work. 4276 */ 4277 if (dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U) { 4278 netdev_info(dev, "checksum offload not possible with jumbo frames\n"); 4279 features &= ~(NETIF_F_TSO|NETIF_F_SG|NETIF_F_ALL_CSUM); 4280 } 4281 4282 /* Some hardware requires receive checksum for RSS to work. */ 4283 if ( (features & NETIF_F_RXHASH) && 4284 !(features & NETIF_F_RXCSUM) && 4285 (sky2->hw->flags & SKY2_HW_RSS_CHKSUM)) { 4286 netdev_info(dev, "receive hashing forces receive checksum\n"); 4287 features |= NETIF_F_RXCSUM; 4288 } 4289 4290 return features; 4291 } 4292 4293 static int sky2_set_features(struct net_device *dev, u32 features) 4294 { 4295 struct sky2_port *sky2 = netdev_priv(dev); 4296 u32 changed = dev->features ^ features; 4297 4298 if (changed & NETIF_F_RXCSUM) { 4299 u32 on = features & NETIF_F_RXCSUM; 4300 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR), 4301 on ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM); 4302 } 4303 4304 if (changed & NETIF_F_RXHASH) 4305 rx_set_rss(dev, features); 4306 4307 if (changed & (NETIF_F_HW_VLAN_TX|NETIF_F_HW_VLAN_RX)) 4308 sky2_vlan_mode(dev, features); 4309 4310 return 0; 4311 } 4312 4313 static const struct ethtool_ops sky2_ethtool_ops = { 4314 .get_settings = sky2_get_settings, 4315 .set_settings = sky2_set_settings, 4316 .get_drvinfo = sky2_get_drvinfo, 4317 .get_wol = sky2_get_wol, 4318 .set_wol = sky2_set_wol, 4319 .get_msglevel = sky2_get_msglevel, 4320 .set_msglevel = sky2_set_msglevel, 4321 .nway_reset = sky2_nway_reset, 4322 .get_regs_len = sky2_get_regs_len, 4323 .get_regs = sky2_get_regs, 4324 .get_link = ethtool_op_get_link, 4325 .get_eeprom_len = sky2_get_eeprom_len, 4326 .get_eeprom = sky2_get_eeprom, 4327 .set_eeprom = sky2_set_eeprom, 4328 .get_strings = sky2_get_strings, 4329 .get_coalesce = sky2_get_coalesce, 4330 .set_coalesce = sky2_set_coalesce, 4331 .get_ringparam = sky2_get_ringparam, 4332 .set_ringparam = sky2_set_ringparam, 4333 .get_pauseparam = sky2_get_pauseparam, 4334 .set_pauseparam = sky2_set_pauseparam, 4335 .set_phys_id = sky2_set_phys_id, 4336 .get_sset_count = sky2_get_sset_count, 4337 .get_ethtool_stats = sky2_get_ethtool_stats, 4338 }; 4339 4340 #ifdef CONFIG_SKY2_DEBUG 4341 4342 static struct dentry *sky2_debug; 4343 4344 4345 /* 4346 * Read and parse the first part of Vital Product Data 4347 */ 4348 #define VPD_SIZE 128 4349 #define VPD_MAGIC 0x82 4350 4351 static const struct vpd_tag { 4352 char tag[2]; 4353 char *label; 4354 } vpd_tags[] = { 4355 { "PN", "Part Number" }, 4356 { "EC", "Engineering Level" }, 4357 { "MN", "Manufacturer" }, 4358 { "SN", "Serial Number" }, 4359 { "YA", "Asset Tag" }, 4360 { "VL", "First Error Log Message" }, 4361 { "VF", "Second Error Log Message" }, 4362 { "VB", "Boot Agent ROM Configuration" }, 4363 { "VE", "EFI UNDI Configuration" }, 4364 }; 4365 4366 static void sky2_show_vpd(struct seq_file *seq, struct sky2_hw *hw) 4367 { 4368 size_t vpd_size; 4369 loff_t offs; 4370 u8 len; 4371 unsigned char *buf; 4372 u16 reg2; 4373 4374 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2); 4375 vpd_size = 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8); 4376 4377 seq_printf(seq, "%s Product Data\n", pci_name(hw->pdev)); 4378 buf = kmalloc(vpd_size, GFP_KERNEL); 4379 if (!buf) { 4380 seq_puts(seq, "no memory!\n"); 4381 return; 4382 } 4383 4384 if (pci_read_vpd(hw->pdev, 0, vpd_size, buf) < 0) { 4385 seq_puts(seq, "VPD read failed\n"); 4386 goto out; 4387 } 4388 4389 if (buf[0] != VPD_MAGIC) { 4390 seq_printf(seq, "VPD tag mismatch: %#x\n", buf[0]); 4391 goto out; 4392 } 4393 len = buf[1]; 4394 if (len == 0 || len > vpd_size - 4) { 4395 seq_printf(seq, "Invalid id length: %d\n", len); 4396 goto out; 4397 } 4398 4399 seq_printf(seq, "%.*s\n", len, buf + 3); 4400 offs = len + 3; 4401 4402 while (offs < vpd_size - 4) { 4403 int i; 4404 4405 if (!memcmp("RW", buf + offs, 2)) /* end marker */ 4406 break; 4407 len = buf[offs + 2]; 4408 if (offs + len + 3 >= vpd_size) 4409 break; 4410 4411 for (i = 0; i < ARRAY_SIZE(vpd_tags); i++) { 4412 if (!memcmp(vpd_tags[i].tag, buf + offs, 2)) { 4413 seq_printf(seq, " %s: %.*s\n", 4414 vpd_tags[i].label, len, buf + offs + 3); 4415 break; 4416 } 4417 } 4418 offs += len + 3; 4419 } 4420 out: 4421 kfree(buf); 4422 } 4423 4424 static int sky2_debug_show(struct seq_file *seq, void *v) 4425 { 4426 struct net_device *dev = seq->private; 4427 const struct sky2_port *sky2 = netdev_priv(dev); 4428 struct sky2_hw *hw = sky2->hw; 4429 unsigned port = sky2->port; 4430 unsigned idx, last; 4431 int sop; 4432 4433 sky2_show_vpd(seq, hw); 4434 4435 seq_printf(seq, "\nIRQ src=%x mask=%x control=%x\n", 4436 sky2_read32(hw, B0_ISRC), 4437 sky2_read32(hw, B0_IMSK), 4438 sky2_read32(hw, B0_Y2_SP_ICR)); 4439 4440 if (!netif_running(dev)) { 4441 seq_printf(seq, "network not running\n"); 4442 return 0; 4443 } 4444 4445 napi_disable(&hw->napi); 4446 last = sky2_read16(hw, STAT_PUT_IDX); 4447 4448 seq_printf(seq, "Status ring %u\n", hw->st_size); 4449 if (hw->st_idx == last) 4450 seq_puts(seq, "Status ring (empty)\n"); 4451 else { 4452 seq_puts(seq, "Status ring\n"); 4453 for (idx = hw->st_idx; idx != last && idx < hw->st_size; 4454 idx = RING_NEXT(idx, hw->st_size)) { 4455 const struct sky2_status_le *le = hw->st_le + idx; 4456 seq_printf(seq, "[%d] %#x %d %#x\n", 4457 idx, le->opcode, le->length, le->status); 4458 } 4459 seq_puts(seq, "\n"); 4460 } 4461 4462 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n", 4463 sky2->tx_cons, sky2->tx_prod, 4464 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX), 4465 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE))); 4466 4467 /* Dump contents of tx ring */ 4468 sop = 1; 4469 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < sky2->tx_ring_size; 4470 idx = RING_NEXT(idx, sky2->tx_ring_size)) { 4471 const struct sky2_tx_le *le = sky2->tx_le + idx; 4472 u32 a = le32_to_cpu(le->addr); 4473 4474 if (sop) 4475 seq_printf(seq, "%u:", idx); 4476 sop = 0; 4477 4478 switch (le->opcode & ~HW_OWNER) { 4479 case OP_ADDR64: 4480 seq_printf(seq, " %#x:", a); 4481 break; 4482 case OP_LRGLEN: 4483 seq_printf(seq, " mtu=%d", a); 4484 break; 4485 case OP_VLAN: 4486 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length)); 4487 break; 4488 case OP_TCPLISW: 4489 seq_printf(seq, " csum=%#x", a); 4490 break; 4491 case OP_LARGESEND: 4492 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length)); 4493 break; 4494 case OP_PACKET: 4495 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length)); 4496 break; 4497 case OP_BUFFER: 4498 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length)); 4499 break; 4500 default: 4501 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode, 4502 a, le16_to_cpu(le->length)); 4503 } 4504 4505 if (le->ctrl & EOP) { 4506 seq_putc(seq, '\n'); 4507 sop = 1; 4508 } 4509 } 4510 4511 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n", 4512 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)), 4513 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)), 4514 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX))); 4515 4516 sky2_read32(hw, B0_Y2_SP_LISR); 4517 napi_enable(&hw->napi); 4518 return 0; 4519 } 4520 4521 static int sky2_debug_open(struct inode *inode, struct file *file) 4522 { 4523 return single_open(file, sky2_debug_show, inode->i_private); 4524 } 4525 4526 static const struct file_operations sky2_debug_fops = { 4527 .owner = THIS_MODULE, 4528 .open = sky2_debug_open, 4529 .read = seq_read, 4530 .llseek = seq_lseek, 4531 .release = single_release, 4532 }; 4533 4534 /* 4535 * Use network device events to create/remove/rename 4536 * debugfs file entries 4537 */ 4538 static int sky2_device_event(struct notifier_block *unused, 4539 unsigned long event, void *ptr) 4540 { 4541 struct net_device *dev = ptr; 4542 struct sky2_port *sky2 = netdev_priv(dev); 4543 4544 if (dev->netdev_ops->ndo_open != sky2_up || !sky2_debug) 4545 return NOTIFY_DONE; 4546 4547 switch (event) { 4548 case NETDEV_CHANGENAME: 4549 if (sky2->debugfs) { 4550 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs, 4551 sky2_debug, dev->name); 4552 } 4553 break; 4554 4555 case NETDEV_GOING_DOWN: 4556 if (sky2->debugfs) { 4557 netdev_printk(KERN_DEBUG, dev, "remove debugfs\n"); 4558 debugfs_remove(sky2->debugfs); 4559 sky2->debugfs = NULL; 4560 } 4561 break; 4562 4563 case NETDEV_UP: 4564 sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO, 4565 sky2_debug, dev, 4566 &sky2_debug_fops); 4567 if (IS_ERR(sky2->debugfs)) 4568 sky2->debugfs = NULL; 4569 } 4570 4571 return NOTIFY_DONE; 4572 } 4573 4574 static struct notifier_block sky2_notifier = { 4575 .notifier_call = sky2_device_event, 4576 }; 4577 4578 4579 static __init void sky2_debug_init(void) 4580 { 4581 struct dentry *ent; 4582 4583 ent = debugfs_create_dir("sky2", NULL); 4584 if (!ent || IS_ERR(ent)) 4585 return; 4586 4587 sky2_debug = ent; 4588 register_netdevice_notifier(&sky2_notifier); 4589 } 4590 4591 static __exit void sky2_debug_cleanup(void) 4592 { 4593 if (sky2_debug) { 4594 unregister_netdevice_notifier(&sky2_notifier); 4595 debugfs_remove(sky2_debug); 4596 sky2_debug = NULL; 4597 } 4598 } 4599 4600 #else 4601 #define sky2_debug_init() 4602 #define sky2_debug_cleanup() 4603 #endif 4604 4605 /* Two copies of network device operations to handle special case of 4606 not allowing netpoll on second port */ 4607 static const struct net_device_ops sky2_netdev_ops[2] = { 4608 { 4609 .ndo_open = sky2_up, 4610 .ndo_stop = sky2_down, 4611 .ndo_start_xmit = sky2_xmit_frame, 4612 .ndo_do_ioctl = sky2_ioctl, 4613 .ndo_validate_addr = eth_validate_addr, 4614 .ndo_set_mac_address = sky2_set_mac_address, 4615 .ndo_set_rx_mode = sky2_set_multicast, 4616 .ndo_change_mtu = sky2_change_mtu, 4617 .ndo_fix_features = sky2_fix_features, 4618 .ndo_set_features = sky2_set_features, 4619 .ndo_tx_timeout = sky2_tx_timeout, 4620 .ndo_get_stats64 = sky2_get_stats, 4621 #ifdef CONFIG_NET_POLL_CONTROLLER 4622 .ndo_poll_controller = sky2_netpoll, 4623 #endif 4624 }, 4625 { 4626 .ndo_open = sky2_up, 4627 .ndo_stop = sky2_down, 4628 .ndo_start_xmit = sky2_xmit_frame, 4629 .ndo_do_ioctl = sky2_ioctl, 4630 .ndo_validate_addr = eth_validate_addr, 4631 .ndo_set_mac_address = sky2_set_mac_address, 4632 .ndo_set_rx_mode = sky2_set_multicast, 4633 .ndo_change_mtu = sky2_change_mtu, 4634 .ndo_fix_features = sky2_fix_features, 4635 .ndo_set_features = sky2_set_features, 4636 .ndo_tx_timeout = sky2_tx_timeout, 4637 .ndo_get_stats64 = sky2_get_stats, 4638 }, 4639 }; 4640 4641 /* Initialize network device */ 4642 static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw, 4643 unsigned port, 4644 int highmem, int wol) 4645 { 4646 struct sky2_port *sky2; 4647 struct net_device *dev = alloc_etherdev(sizeof(*sky2)); 4648 4649 if (!dev) { 4650 dev_err(&hw->pdev->dev, "etherdev alloc failed\n"); 4651 return NULL; 4652 } 4653 4654 SET_NETDEV_DEV(dev, &hw->pdev->dev); 4655 dev->irq = hw->pdev->irq; 4656 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops); 4657 dev->watchdog_timeo = TX_WATCHDOG; 4658 dev->netdev_ops = &sky2_netdev_ops[port]; 4659 4660 sky2 = netdev_priv(dev); 4661 sky2->netdev = dev; 4662 sky2->hw = hw; 4663 sky2->msg_enable = netif_msg_init(debug, default_msg); 4664 4665 /* Auto speed and flow control */ 4666 sky2->flags = SKY2_FLAG_AUTO_SPEED | SKY2_FLAG_AUTO_PAUSE; 4667 if (hw->chip_id != CHIP_ID_YUKON_XL) 4668 dev->hw_features |= NETIF_F_RXCSUM; 4669 4670 sky2->flow_mode = FC_BOTH; 4671 4672 sky2->duplex = -1; 4673 sky2->speed = -1; 4674 sky2->advertising = sky2_supported_modes(hw); 4675 sky2->wol = wol; 4676 4677 spin_lock_init(&sky2->phy_lock); 4678 4679 sky2->tx_pending = TX_DEF_PENDING; 4680 sky2->tx_ring_size = roundup_pow_of_two(TX_DEF_PENDING+1); 4681 sky2->rx_pending = RX_DEF_PENDING; 4682 4683 hw->dev[port] = dev; 4684 4685 sky2->port = port; 4686 4687 dev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_TSO; 4688 4689 if (highmem) 4690 dev->features |= NETIF_F_HIGHDMA; 4691 4692 /* Enable receive hashing unless hardware is known broken */ 4693 if (!(hw->flags & SKY2_HW_RSS_BROKEN)) 4694 dev->hw_features |= NETIF_F_RXHASH; 4695 4696 if (!(hw->flags & SKY2_HW_VLAN_BROKEN)) { 4697 dev->hw_features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; 4698 dev->vlan_features |= SKY2_VLAN_OFFLOADS; 4699 } 4700 4701 dev->features |= dev->hw_features; 4702 4703 /* read the mac address */ 4704 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN); 4705 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); 4706 4707 return dev; 4708 } 4709 4710 static void __devinit sky2_show_addr(struct net_device *dev) 4711 { 4712 const struct sky2_port *sky2 = netdev_priv(dev); 4713 4714 netif_info(sky2, probe, dev, "addr %pM\n", dev->dev_addr); 4715 } 4716 4717 /* Handle software interrupt used during MSI test */ 4718 static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id) 4719 { 4720 struct sky2_hw *hw = dev_id; 4721 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2); 4722 4723 if (status == 0) 4724 return IRQ_NONE; 4725 4726 if (status & Y2_IS_IRQ_SW) { 4727 hw->flags |= SKY2_HW_USE_MSI; 4728 wake_up(&hw->msi_wait); 4729 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ); 4730 } 4731 sky2_write32(hw, B0_Y2_SP_ICR, 2); 4732 4733 return IRQ_HANDLED; 4734 } 4735 4736 /* Test interrupt path by forcing a a software IRQ */ 4737 static int __devinit sky2_test_msi(struct sky2_hw *hw) 4738 { 4739 struct pci_dev *pdev = hw->pdev; 4740 int err; 4741 4742 init_waitqueue_head(&hw->msi_wait); 4743 4744 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW); 4745 4746 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw); 4747 if (err) { 4748 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq); 4749 return err; 4750 } 4751 4752 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ); 4753 sky2_read8(hw, B0_CTST); 4754 4755 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10); 4756 4757 if (!(hw->flags & SKY2_HW_USE_MSI)) { 4758 /* MSI test failed, go back to INTx mode */ 4759 dev_info(&pdev->dev, "No interrupt generated using MSI, " 4760 "switching to INTx mode.\n"); 4761 4762 err = -EOPNOTSUPP; 4763 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ); 4764 } 4765 4766 sky2_write32(hw, B0_IMSK, 0); 4767 sky2_read32(hw, B0_IMSK); 4768 4769 free_irq(pdev->irq, hw); 4770 4771 return err; 4772 } 4773 4774 /* This driver supports yukon2 chipset only */ 4775 static const char *sky2_name(u8 chipid, char *buf, int sz) 4776 { 4777 const char *name[] = { 4778 "XL", /* 0xb3 */ 4779 "EC Ultra", /* 0xb4 */ 4780 "Extreme", /* 0xb5 */ 4781 "EC", /* 0xb6 */ 4782 "FE", /* 0xb7 */ 4783 "FE+", /* 0xb8 */ 4784 "Supreme", /* 0xb9 */ 4785 "UL 2", /* 0xba */ 4786 "Unknown", /* 0xbb */ 4787 "Optima", /* 0xbc */ 4788 "Optima Prime", /* 0xbd */ 4789 "Optima 2", /* 0xbe */ 4790 }; 4791 4792 if (chipid >= CHIP_ID_YUKON_XL && chipid <= CHIP_ID_YUKON_OP_2) 4793 strncpy(buf, name[chipid - CHIP_ID_YUKON_XL], sz); 4794 else 4795 snprintf(buf, sz, "(chip %#x)", chipid); 4796 return buf; 4797 } 4798 4799 static int __devinit sky2_probe(struct pci_dev *pdev, 4800 const struct pci_device_id *ent) 4801 { 4802 struct net_device *dev; 4803 struct sky2_hw *hw; 4804 int err, using_dac = 0, wol_default; 4805 u32 reg; 4806 char buf1[16]; 4807 4808 err = pci_enable_device(pdev); 4809 if (err) { 4810 dev_err(&pdev->dev, "cannot enable PCI device\n"); 4811 goto err_out; 4812 } 4813 4814 /* Get configuration information 4815 * Note: only regular PCI config access once to test for HW issues 4816 * other PCI access through shared memory for speed and to 4817 * avoid MMCONFIG problems. 4818 */ 4819 err = pci_read_config_dword(pdev, PCI_DEV_REG2, ®); 4820 if (err) { 4821 dev_err(&pdev->dev, "PCI read config failed\n"); 4822 goto err_out; 4823 } 4824 4825 if (~reg == 0) { 4826 dev_err(&pdev->dev, "PCI configuration read error\n"); 4827 goto err_out; 4828 } 4829 4830 err = pci_request_regions(pdev, DRV_NAME); 4831 if (err) { 4832 dev_err(&pdev->dev, "cannot obtain PCI resources\n"); 4833 goto err_out_disable; 4834 } 4835 4836 pci_set_master(pdev); 4837 4838 if (sizeof(dma_addr_t) > sizeof(u32) && 4839 !(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))) { 4840 using_dac = 1; 4841 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); 4842 if (err < 0) { 4843 dev_err(&pdev->dev, "unable to obtain 64 bit DMA " 4844 "for consistent allocations\n"); 4845 goto err_out_free_regions; 4846 } 4847 } else { 4848 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 4849 if (err) { 4850 dev_err(&pdev->dev, "no usable DMA configuration\n"); 4851 goto err_out_free_regions; 4852 } 4853 } 4854 4855 4856 #ifdef __BIG_ENDIAN 4857 /* The sk98lin vendor driver uses hardware byte swapping but 4858 * this driver uses software swapping. 4859 */ 4860 reg &= ~PCI_REV_DESC; 4861 err = pci_write_config_dword(pdev, PCI_DEV_REG2, reg); 4862 if (err) { 4863 dev_err(&pdev->dev, "PCI write config failed\n"); 4864 goto err_out_free_regions; 4865 } 4866 #endif 4867 4868 wol_default = device_may_wakeup(&pdev->dev) ? WAKE_MAGIC : 0; 4869 4870 err = -ENOMEM; 4871 4872 hw = kzalloc(sizeof(*hw) + strlen(DRV_NAME "@pci:") 4873 + strlen(pci_name(pdev)) + 1, GFP_KERNEL); 4874 if (!hw) { 4875 dev_err(&pdev->dev, "cannot allocate hardware struct\n"); 4876 goto err_out_free_regions; 4877 } 4878 4879 hw->pdev = pdev; 4880 sprintf(hw->irq_name, DRV_NAME "@pci:%s", pci_name(pdev)); 4881 4882 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000); 4883 if (!hw->regs) { 4884 dev_err(&pdev->dev, "cannot map device registers\n"); 4885 goto err_out_free_hw; 4886 } 4887 4888 err = sky2_init(hw); 4889 if (err) 4890 goto err_out_iounmap; 4891 4892 /* ring for status responses */ 4893 hw->st_size = hw->ports * roundup_pow_of_two(3*RX_MAX_PENDING + TX_MAX_PENDING); 4894 hw->st_le = pci_alloc_consistent(pdev, hw->st_size * sizeof(struct sky2_status_le), 4895 &hw->st_dma); 4896 if (!hw->st_le) 4897 goto err_out_reset; 4898 4899 dev_info(&pdev->dev, "Yukon-2 %s chip revision %d\n", 4900 sky2_name(hw->chip_id, buf1, sizeof(buf1)), hw->chip_rev); 4901 4902 sky2_reset(hw); 4903 4904 dev = sky2_init_netdev(hw, 0, using_dac, wol_default); 4905 if (!dev) { 4906 err = -ENOMEM; 4907 goto err_out_free_pci; 4908 } 4909 4910 if (!disable_msi && pci_enable_msi(pdev) == 0) { 4911 err = sky2_test_msi(hw); 4912 if (err == -EOPNOTSUPP) 4913 pci_disable_msi(pdev); 4914 else if (err) 4915 goto err_out_free_netdev; 4916 } 4917 4918 err = register_netdev(dev); 4919 if (err) { 4920 dev_err(&pdev->dev, "cannot register net device\n"); 4921 goto err_out_free_netdev; 4922 } 4923 4924 netif_carrier_off(dev); 4925 4926 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT); 4927 4928 err = request_irq(pdev->irq, sky2_intr, 4929 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED, 4930 hw->irq_name, hw); 4931 if (err) { 4932 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq); 4933 goto err_out_unregister; 4934 } 4935 sky2_write32(hw, B0_IMSK, Y2_IS_BASE); 4936 napi_enable(&hw->napi); 4937 4938 sky2_show_addr(dev); 4939 4940 if (hw->ports > 1) { 4941 struct net_device *dev1; 4942 4943 err = -ENOMEM; 4944 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default); 4945 if (dev1 && (err = register_netdev(dev1)) == 0) 4946 sky2_show_addr(dev1); 4947 else { 4948 dev_warn(&pdev->dev, 4949 "register of second port failed (%d)\n", err); 4950 hw->dev[1] = NULL; 4951 hw->ports = 1; 4952 if (dev1) 4953 free_netdev(dev1); 4954 } 4955 } 4956 4957 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw); 4958 INIT_WORK(&hw->restart_work, sky2_restart); 4959 4960 pci_set_drvdata(pdev, hw); 4961 pdev->d3_delay = 150; 4962 4963 return 0; 4964 4965 err_out_unregister: 4966 if (hw->flags & SKY2_HW_USE_MSI) 4967 pci_disable_msi(pdev); 4968 unregister_netdev(dev); 4969 err_out_free_netdev: 4970 free_netdev(dev); 4971 err_out_free_pci: 4972 pci_free_consistent(pdev, hw->st_size * sizeof(struct sky2_status_le), 4973 hw->st_le, hw->st_dma); 4974 err_out_reset: 4975 sky2_write8(hw, B0_CTST, CS_RST_SET); 4976 err_out_iounmap: 4977 iounmap(hw->regs); 4978 err_out_free_hw: 4979 kfree(hw); 4980 err_out_free_regions: 4981 pci_release_regions(pdev); 4982 err_out_disable: 4983 pci_disable_device(pdev); 4984 err_out: 4985 pci_set_drvdata(pdev, NULL); 4986 return err; 4987 } 4988 4989 static void __devexit sky2_remove(struct pci_dev *pdev) 4990 { 4991 struct sky2_hw *hw = pci_get_drvdata(pdev); 4992 int i; 4993 4994 if (!hw) 4995 return; 4996 4997 del_timer_sync(&hw->watchdog_timer); 4998 cancel_work_sync(&hw->restart_work); 4999 5000 for (i = hw->ports-1; i >= 0; --i) 5001 unregister_netdev(hw->dev[i]); 5002 5003 sky2_write32(hw, B0_IMSK, 0); 5004 5005 sky2_power_aux(hw); 5006 5007 sky2_write8(hw, B0_CTST, CS_RST_SET); 5008 sky2_read8(hw, B0_CTST); 5009 5010 free_irq(pdev->irq, hw); 5011 if (hw->flags & SKY2_HW_USE_MSI) 5012 pci_disable_msi(pdev); 5013 pci_free_consistent(pdev, hw->st_size * sizeof(struct sky2_status_le), 5014 hw->st_le, hw->st_dma); 5015 pci_release_regions(pdev); 5016 pci_disable_device(pdev); 5017 5018 for (i = hw->ports-1; i >= 0; --i) 5019 free_netdev(hw->dev[i]); 5020 5021 iounmap(hw->regs); 5022 kfree(hw); 5023 5024 pci_set_drvdata(pdev, NULL); 5025 } 5026 5027 static int sky2_suspend(struct device *dev) 5028 { 5029 struct pci_dev *pdev = to_pci_dev(dev); 5030 struct sky2_hw *hw = pci_get_drvdata(pdev); 5031 int i; 5032 5033 if (!hw) 5034 return 0; 5035 5036 del_timer_sync(&hw->watchdog_timer); 5037 cancel_work_sync(&hw->restart_work); 5038 5039 rtnl_lock(); 5040 5041 sky2_all_down(hw); 5042 for (i = 0; i < hw->ports; i++) { 5043 struct net_device *dev = hw->dev[i]; 5044 struct sky2_port *sky2 = netdev_priv(dev); 5045 5046 if (sky2->wol) 5047 sky2_wol_init(sky2); 5048 } 5049 5050 sky2_power_aux(hw); 5051 rtnl_unlock(); 5052 5053 return 0; 5054 } 5055 5056 #ifdef CONFIG_PM_SLEEP 5057 static int sky2_resume(struct device *dev) 5058 { 5059 struct pci_dev *pdev = to_pci_dev(dev); 5060 struct sky2_hw *hw = pci_get_drvdata(pdev); 5061 int err; 5062 5063 if (!hw) 5064 return 0; 5065 5066 /* Re-enable all clocks */ 5067 err = pci_write_config_dword(pdev, PCI_DEV_REG3, 0); 5068 if (err) { 5069 dev_err(&pdev->dev, "PCI write config failed\n"); 5070 goto out; 5071 } 5072 5073 rtnl_lock(); 5074 sky2_reset(hw); 5075 sky2_all_up(hw); 5076 rtnl_unlock(); 5077 5078 return 0; 5079 out: 5080 5081 dev_err(&pdev->dev, "resume failed (%d)\n", err); 5082 pci_disable_device(pdev); 5083 return err; 5084 } 5085 5086 static SIMPLE_DEV_PM_OPS(sky2_pm_ops, sky2_suspend, sky2_resume); 5087 #define SKY2_PM_OPS (&sky2_pm_ops) 5088 5089 #else 5090 5091 #define SKY2_PM_OPS NULL 5092 #endif 5093 5094 static void sky2_shutdown(struct pci_dev *pdev) 5095 { 5096 sky2_suspend(&pdev->dev); 5097 pci_wake_from_d3(pdev, device_may_wakeup(&pdev->dev)); 5098 pci_set_power_state(pdev, PCI_D3hot); 5099 } 5100 5101 static struct pci_driver sky2_driver = { 5102 .name = DRV_NAME, 5103 .id_table = sky2_id_table, 5104 .probe = sky2_probe, 5105 .remove = __devexit_p(sky2_remove), 5106 .shutdown = sky2_shutdown, 5107 .driver.pm = SKY2_PM_OPS, 5108 }; 5109 5110 static int __init sky2_init_module(void) 5111 { 5112 pr_info("driver version " DRV_VERSION "\n"); 5113 5114 sky2_debug_init(); 5115 return pci_register_driver(&sky2_driver); 5116 } 5117 5118 static void __exit sky2_cleanup_module(void) 5119 { 5120 pci_unregister_driver(&sky2_driver); 5121 sky2_debug_cleanup(); 5122 } 5123 5124 module_init(sky2_init_module); 5125 module_exit(sky2_cleanup_module); 5126 5127 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver"); 5128 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>"); 5129 MODULE_LICENSE("GPL"); 5130 MODULE_VERSION(DRV_VERSION); 5131