1 /* 2 * New driver for Marvell Yukon 2 chipset. 3 * Based on earlier sk98lin, and skge driver. 4 * 5 * This driver intentionally does not support all the features 6 * of the original driver such as link fail-over and link management because 7 * those should be done at higher levels. 8 * 9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org> 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 23 */ 24 25 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 26 27 #include <linux/crc32.h> 28 #include <linux/kernel.h> 29 #include <linux/module.h> 30 #include <linux/netdevice.h> 31 #include <linux/dma-mapping.h> 32 #include <linux/etherdevice.h> 33 #include <linux/ethtool.h> 34 #include <linux/pci.h> 35 #include <linux/interrupt.h> 36 #include <linux/ip.h> 37 #include <linux/slab.h> 38 #include <net/ip.h> 39 #include <linux/tcp.h> 40 #include <linux/in.h> 41 #include <linux/delay.h> 42 #include <linux/workqueue.h> 43 #include <linux/if_vlan.h> 44 #include <linux/prefetch.h> 45 #include <linux/debugfs.h> 46 #include <linux/mii.h> 47 48 #include <asm/irq.h> 49 50 #include "sky2.h" 51 52 #define DRV_NAME "sky2" 53 #define DRV_VERSION "1.30" 54 55 /* 56 * The Yukon II chipset takes 64 bit command blocks (called list elements) 57 * that are organized into three (receive, transmit, status) different rings 58 * similar to Tigon3. 59 */ 60 61 #define RX_LE_SIZE 1024 62 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le)) 63 #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2) 64 #define RX_DEF_PENDING RX_MAX_PENDING 65 66 /* This is the worst case number of transmit list elements for a single skb: 67 VLAN:GSO + CKSUM + Data + skb_frags * DMA */ 68 #define MAX_SKB_TX_LE (2 + (sizeof(dma_addr_t)/sizeof(u32))*(MAX_SKB_FRAGS+1)) 69 #define TX_MIN_PENDING (MAX_SKB_TX_LE+1) 70 #define TX_MAX_PENDING 1024 71 #define TX_DEF_PENDING 63 72 73 #define TX_WATCHDOG (5 * HZ) 74 #define NAPI_WEIGHT 64 75 #define PHY_RETRIES 1000 76 77 #define SKY2_EEPROM_MAGIC 0x9955aabb 78 79 #define RING_NEXT(x, s) (((x)+1) & ((s)-1)) 80 81 static const u32 default_msg = 82 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK 83 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR 84 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN; 85 86 static int debug = -1; /* defaults above */ 87 module_param(debug, int, 0); 88 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 89 90 static int copybreak __read_mostly = 128; 91 module_param(copybreak, int, 0); 92 MODULE_PARM_DESC(copybreak, "Receive copy threshold"); 93 94 static int disable_msi = 0; 95 module_param(disable_msi, int, 0); 96 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)"); 97 98 static DEFINE_PCI_DEVICE_TABLE(sky2_id_table) = { 99 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */ 100 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */ 101 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E01) }, /* SK-9E21M */ 102 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */ 103 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */ 104 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */ 105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */ 106 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */ 107 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */ 108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */ 109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */ 110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */ 111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */ 112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */ 113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */ 114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */ 115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */ 116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */ 117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */ 118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */ 119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4355) }, /* 88E8040T */ 120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */ 121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */ 122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */ 123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */ 124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */ 125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */ 126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */ 127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */ 128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */ 129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */ 130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */ 131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */ 132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */ 133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */ 134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */ 135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */ 136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */ 137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */ 138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4380) }, /* 88E8057 */ 139 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4381) }, /* 88E8059 */ 140 { 0 } 141 }; 142 143 MODULE_DEVICE_TABLE(pci, sky2_id_table); 144 145 /* Avoid conditionals by using array */ 146 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 }; 147 static const unsigned rxqaddr[] = { Q_R1, Q_R2 }; 148 static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 }; 149 150 static void sky2_set_multicast(struct net_device *dev); 151 static irqreturn_t sky2_intr(int irq, void *dev_id); 152 153 /* Access to PHY via serial interconnect */ 154 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val) 155 { 156 int i; 157 158 gma_write16(hw, port, GM_SMI_DATA, val); 159 gma_write16(hw, port, GM_SMI_CTRL, 160 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg)); 161 162 for (i = 0; i < PHY_RETRIES; i++) { 163 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL); 164 if (ctrl == 0xffff) 165 goto io_error; 166 167 if (!(ctrl & GM_SMI_CT_BUSY)) 168 return 0; 169 170 udelay(10); 171 } 172 173 dev_warn(&hw->pdev->dev, "%s: phy write timeout\n", hw->dev[port]->name); 174 return -ETIMEDOUT; 175 176 io_error: 177 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name); 178 return -EIO; 179 } 180 181 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val) 182 { 183 int i; 184 185 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) 186 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD); 187 188 for (i = 0; i < PHY_RETRIES; i++) { 189 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL); 190 if (ctrl == 0xffff) 191 goto io_error; 192 193 if (ctrl & GM_SMI_CT_RD_VAL) { 194 *val = gma_read16(hw, port, GM_SMI_DATA); 195 return 0; 196 } 197 198 udelay(10); 199 } 200 201 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name); 202 return -ETIMEDOUT; 203 io_error: 204 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name); 205 return -EIO; 206 } 207 208 static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg) 209 { 210 u16 v; 211 __gm_phy_read(hw, port, reg, &v); 212 return v; 213 } 214 215 216 static void sky2_power_on(struct sky2_hw *hw) 217 { 218 /* switch power to VCC (WA for VAUX problem) */ 219 sky2_write8(hw, B0_POWER_CTRL, 220 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON); 221 222 /* disable Core Clock Division, */ 223 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS); 224 225 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1) 226 /* enable bits are inverted */ 227 sky2_write8(hw, B2_Y2_CLK_GATE, 228 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | 229 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | 230 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS); 231 else 232 sky2_write8(hw, B2_Y2_CLK_GATE, 0); 233 234 if (hw->flags & SKY2_HW_ADV_POWER_CTL) { 235 u32 reg; 236 237 sky2_pci_write32(hw, PCI_DEV_REG3, 0); 238 239 reg = sky2_pci_read32(hw, PCI_DEV_REG4); 240 /* set all bits to 0 except bits 15..12 and 8 */ 241 reg &= P_ASPM_CONTROL_MSK; 242 sky2_pci_write32(hw, PCI_DEV_REG4, reg); 243 244 reg = sky2_pci_read32(hw, PCI_DEV_REG5); 245 /* set all bits to 0 except bits 28 & 27 */ 246 reg &= P_CTL_TIM_VMAIN_AV_MSK; 247 sky2_pci_write32(hw, PCI_DEV_REG5, reg); 248 249 sky2_pci_write32(hw, PCI_CFG_REG_1, 0); 250 251 sky2_write16(hw, B0_CTST, Y2_HW_WOL_ON); 252 253 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */ 254 reg = sky2_read32(hw, B2_GP_IO); 255 reg |= GLB_GPIO_STAT_RACE_DIS; 256 sky2_write32(hw, B2_GP_IO, reg); 257 258 sky2_read32(hw, B2_GP_IO); 259 } 260 261 /* Turn on "driver loaded" LED */ 262 sky2_write16(hw, B0_CTST, Y2_LED_STAT_ON); 263 } 264 265 static void sky2_power_aux(struct sky2_hw *hw) 266 { 267 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1) 268 sky2_write8(hw, B2_Y2_CLK_GATE, 0); 269 else 270 /* enable bits are inverted */ 271 sky2_write8(hw, B2_Y2_CLK_GATE, 272 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | 273 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | 274 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS); 275 276 /* switch power to VAUX if supported and PME from D3cold */ 277 if ( (sky2_read32(hw, B0_CTST) & Y2_VAUX_AVAIL) && 278 pci_pme_capable(hw->pdev, PCI_D3cold)) 279 sky2_write8(hw, B0_POWER_CTRL, 280 (PC_VAUX_ENA | PC_VCC_ENA | 281 PC_VAUX_ON | PC_VCC_OFF)); 282 283 /* turn off "driver loaded LED" */ 284 sky2_write16(hw, B0_CTST, Y2_LED_STAT_OFF); 285 } 286 287 static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port) 288 { 289 u16 reg; 290 291 /* disable all GMAC IRQ's */ 292 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0); 293 294 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */ 295 gma_write16(hw, port, GM_MC_ADDR_H2, 0); 296 gma_write16(hw, port, GM_MC_ADDR_H3, 0); 297 gma_write16(hw, port, GM_MC_ADDR_H4, 0); 298 299 reg = gma_read16(hw, port, GM_RX_CTRL); 300 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA; 301 gma_write16(hw, port, GM_RX_CTRL, reg); 302 } 303 304 /* flow control to advertise bits */ 305 static const u16 copper_fc_adv[] = { 306 [FC_NONE] = 0, 307 [FC_TX] = PHY_M_AN_ASP, 308 [FC_RX] = PHY_M_AN_PC, 309 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP, 310 }; 311 312 /* flow control to advertise bits when using 1000BaseX */ 313 static const u16 fiber_fc_adv[] = { 314 [FC_NONE] = PHY_M_P_NO_PAUSE_X, 315 [FC_TX] = PHY_M_P_ASYM_MD_X, 316 [FC_RX] = PHY_M_P_SYM_MD_X, 317 [FC_BOTH] = PHY_M_P_BOTH_MD_X, 318 }; 319 320 /* flow control to GMA disable bits */ 321 static const u16 gm_fc_disable[] = { 322 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS, 323 [FC_TX] = GM_GPCR_FC_RX_DIS, 324 [FC_RX] = GM_GPCR_FC_TX_DIS, 325 [FC_BOTH] = 0, 326 }; 327 328 329 static void sky2_phy_init(struct sky2_hw *hw, unsigned port) 330 { 331 struct sky2_port *sky2 = netdev_priv(hw->dev[port]); 332 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg; 333 334 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) && 335 !(hw->flags & SKY2_HW_NEWER_PHY)) { 336 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL); 337 338 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK | 339 PHY_M_EC_MAC_S_MSK); 340 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ); 341 342 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */ 343 if (hw->chip_id == CHIP_ID_YUKON_EC) 344 /* set downshift counter to 3x and enable downshift */ 345 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA; 346 else 347 /* set master & slave downshift counter to 1x */ 348 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1); 349 350 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl); 351 } 352 353 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); 354 if (sky2_is_copper(hw)) { 355 if (!(hw->flags & SKY2_HW_GIGABIT)) { 356 /* enable automatic crossover */ 357 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1; 358 359 if (hw->chip_id == CHIP_ID_YUKON_FE_P && 360 hw->chip_rev == CHIP_REV_YU_FE2_A0) { 361 u16 spec; 362 363 /* Enable Class A driver for FE+ A0 */ 364 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2); 365 spec |= PHY_M_FESC_SEL_CL_A; 366 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec); 367 } 368 } else { 369 /* disable energy detect */ 370 ctrl &= ~PHY_M_PC_EN_DET_MSK; 371 372 /* enable automatic crossover */ 373 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO); 374 375 /* downshift on PHY 88E1112 and 88E1149 is changed */ 376 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) && 377 (hw->flags & SKY2_HW_NEWER_PHY)) { 378 /* set downshift counter to 3x and enable downshift */ 379 ctrl &= ~PHY_M_PC_DSC_MSK; 380 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA; 381 } 382 } 383 } else { 384 /* workaround for deviation #4.88 (CRC errors) */ 385 /* disable Automatic Crossover */ 386 387 ctrl &= ~PHY_M_PC_MDIX_MSK; 388 } 389 390 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); 391 392 /* special setup for PHY 88E1112 Fiber */ 393 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) { 394 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); 395 396 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */ 397 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2); 398 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); 399 ctrl &= ~PHY_M_MAC_MD_MSK; 400 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX); 401 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); 402 403 if (hw->pmd_type == 'P') { 404 /* select page 1 to access Fiber registers */ 405 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1); 406 407 /* for SFP-module set SIGDET polarity to low */ 408 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); 409 ctrl |= PHY_M_FIB_SIGD_POL; 410 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); 411 } 412 413 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); 414 } 415 416 ctrl = PHY_CT_RESET; 417 ct1000 = 0; 418 adv = PHY_AN_CSMA; 419 reg = 0; 420 421 if (sky2->flags & SKY2_FLAG_AUTO_SPEED) { 422 if (sky2_is_copper(hw)) { 423 if (sky2->advertising & ADVERTISED_1000baseT_Full) 424 ct1000 |= PHY_M_1000C_AFD; 425 if (sky2->advertising & ADVERTISED_1000baseT_Half) 426 ct1000 |= PHY_M_1000C_AHD; 427 if (sky2->advertising & ADVERTISED_100baseT_Full) 428 adv |= PHY_M_AN_100_FD; 429 if (sky2->advertising & ADVERTISED_100baseT_Half) 430 adv |= PHY_M_AN_100_HD; 431 if (sky2->advertising & ADVERTISED_10baseT_Full) 432 adv |= PHY_M_AN_10_FD; 433 if (sky2->advertising & ADVERTISED_10baseT_Half) 434 adv |= PHY_M_AN_10_HD; 435 436 } else { /* special defines for FIBER (88E1040S only) */ 437 if (sky2->advertising & ADVERTISED_1000baseT_Full) 438 adv |= PHY_M_AN_1000X_AFD; 439 if (sky2->advertising & ADVERTISED_1000baseT_Half) 440 adv |= PHY_M_AN_1000X_AHD; 441 } 442 443 /* Restart Auto-negotiation */ 444 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG; 445 } else { 446 /* forced speed/duplex settings */ 447 ct1000 = PHY_M_1000C_MSE; 448 449 /* Disable auto update for duplex flow control and duplex */ 450 reg |= GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_SPD_DIS; 451 452 switch (sky2->speed) { 453 case SPEED_1000: 454 ctrl |= PHY_CT_SP1000; 455 reg |= GM_GPCR_SPEED_1000; 456 break; 457 case SPEED_100: 458 ctrl |= PHY_CT_SP100; 459 reg |= GM_GPCR_SPEED_100; 460 break; 461 } 462 463 if (sky2->duplex == DUPLEX_FULL) { 464 reg |= GM_GPCR_DUP_FULL; 465 ctrl |= PHY_CT_DUP_MD; 466 } else if (sky2->speed < SPEED_1000) 467 sky2->flow_mode = FC_NONE; 468 } 469 470 if (sky2->flags & SKY2_FLAG_AUTO_PAUSE) { 471 if (sky2_is_copper(hw)) 472 adv |= copper_fc_adv[sky2->flow_mode]; 473 else 474 adv |= fiber_fc_adv[sky2->flow_mode]; 475 } else { 476 reg |= GM_GPCR_AU_FCT_DIS; 477 reg |= gm_fc_disable[sky2->flow_mode]; 478 479 /* Forward pause packets to GMAC? */ 480 if (sky2->flow_mode & FC_RX) 481 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON); 482 else 483 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); 484 } 485 486 gma_write16(hw, port, GM_GP_CTRL, reg); 487 488 if (hw->flags & SKY2_HW_GIGABIT) 489 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000); 490 491 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv); 492 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl); 493 494 /* Setup Phy LED's */ 495 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS); 496 ledover = 0; 497 498 switch (hw->chip_id) { 499 case CHIP_ID_YUKON_FE: 500 /* on 88E3082 these bits are at 11..9 (shifted left) */ 501 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1; 502 503 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR); 504 505 /* delete ACT LED control bits */ 506 ctrl &= ~PHY_M_FELP_LED1_MSK; 507 /* change ACT LED control to blink mode */ 508 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL); 509 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl); 510 break; 511 512 case CHIP_ID_YUKON_FE_P: 513 /* Enable Link Partner Next Page */ 514 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); 515 ctrl |= PHY_M_PC_ENA_LIP_NP; 516 517 /* disable Energy Detect and enable scrambler */ 518 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB); 519 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); 520 521 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */ 522 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) | 523 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) | 524 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED); 525 526 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl); 527 break; 528 529 case CHIP_ID_YUKON_XL: 530 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); 531 532 /* select page 3 to access LED control register */ 533 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); 534 535 /* set LED Function Control register */ 536 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, 537 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */ 538 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */ 539 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */ 540 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */ 541 542 /* set Polarity Control register */ 543 gm_phy_write(hw, port, PHY_MARV_PHY_STAT, 544 (PHY_M_POLC_LS1_P_MIX(4) | 545 PHY_M_POLC_IS0_P_MIX(4) | 546 PHY_M_POLC_LOS_CTRL(2) | 547 PHY_M_POLC_INIT_CTRL(2) | 548 PHY_M_POLC_STA1_CTRL(2) | 549 PHY_M_POLC_STA0_CTRL(2))); 550 551 /* restore page register */ 552 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); 553 break; 554 555 case CHIP_ID_YUKON_EC_U: 556 case CHIP_ID_YUKON_EX: 557 case CHIP_ID_YUKON_SUPR: 558 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); 559 560 /* select page 3 to access LED control register */ 561 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); 562 563 /* set LED Function Control register */ 564 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, 565 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */ 566 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */ 567 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */ 568 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */ 569 570 /* set Blink Rate in LED Timer Control Register */ 571 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 572 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS)); 573 /* restore page register */ 574 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); 575 break; 576 577 default: 578 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */ 579 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL; 580 581 /* turn off the Rx LED (LED_RX) */ 582 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF); 583 } 584 585 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_UL_2) { 586 /* apply fixes in PHY AFE */ 587 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255); 588 589 /* increase differential signal amplitude in 10BASE-T */ 590 gm_phy_write(hw, port, 0x18, 0xaa99); 591 gm_phy_write(hw, port, 0x17, 0x2011); 592 593 if (hw->chip_id == CHIP_ID_YUKON_EC_U) { 594 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */ 595 gm_phy_write(hw, port, 0x18, 0xa204); 596 gm_phy_write(hw, port, 0x17, 0x2002); 597 } 598 599 /* set page register to 0 */ 600 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0); 601 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P && 602 hw->chip_rev == CHIP_REV_YU_FE2_A0) { 603 /* apply workaround for integrated resistors calibration */ 604 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17); 605 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60); 606 } else if (hw->chip_id == CHIP_ID_YUKON_OPT && hw->chip_rev == 0) { 607 /* apply fixes in PHY AFE */ 608 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00ff); 609 610 /* apply RDAC termination workaround */ 611 gm_phy_write(hw, port, 24, 0x2800); 612 gm_phy_write(hw, port, 23, 0x2001); 613 614 /* set page register back to 0 */ 615 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0); 616 } else if (hw->chip_id != CHIP_ID_YUKON_EX && 617 hw->chip_id < CHIP_ID_YUKON_SUPR) { 618 /* no effect on Yukon-XL */ 619 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl); 620 621 if (!(sky2->flags & SKY2_FLAG_AUTO_SPEED) || 622 sky2->speed == SPEED_100) { 623 /* turn on 100 Mbps LED (LED_LINK100) */ 624 ledover |= PHY_M_LED_MO_100(MO_LED_ON); 625 } 626 627 if (ledover) 628 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover); 629 630 } else if (hw->chip_id == CHIP_ID_YUKON_PRM && 631 (sky2_read8(hw, B2_MAC_CFG) & 0xf) == 0x7) { 632 int i; 633 /* This a phy register setup workaround copied from vendor driver. */ 634 static const struct { 635 u16 reg, val; 636 } eee_afe[] = { 637 { 0x156, 0x58ce }, 638 { 0x153, 0x99eb }, 639 { 0x141, 0x8064 }, 640 /* { 0x155, 0x130b },*/ 641 { 0x000, 0x0000 }, 642 { 0x151, 0x8433 }, 643 { 0x14b, 0x8c44 }, 644 { 0x14c, 0x0f90 }, 645 { 0x14f, 0x39aa }, 646 /* { 0x154, 0x2f39 },*/ 647 { 0x14d, 0xba33 }, 648 { 0x144, 0x0048 }, 649 { 0x152, 0x2010 }, 650 /* { 0x158, 0x1223 },*/ 651 { 0x140, 0x4444 }, 652 { 0x154, 0x2f3b }, 653 { 0x158, 0xb203 }, 654 { 0x157, 0x2029 }, 655 }; 656 657 /* Start Workaround for OptimaEEE Rev.Z0 */ 658 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00fb); 659 660 gm_phy_write(hw, port, 1, 0x4099); 661 gm_phy_write(hw, port, 3, 0x1120); 662 gm_phy_write(hw, port, 11, 0x113c); 663 gm_phy_write(hw, port, 14, 0x8100); 664 gm_phy_write(hw, port, 15, 0x112a); 665 gm_phy_write(hw, port, 17, 0x1008); 666 667 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00fc); 668 gm_phy_write(hw, port, 1, 0x20b0); 669 670 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00ff); 671 672 for (i = 0; i < ARRAY_SIZE(eee_afe); i++) { 673 /* apply AFE settings */ 674 gm_phy_write(hw, port, 17, eee_afe[i].val); 675 gm_phy_write(hw, port, 16, eee_afe[i].reg | 1u<<13); 676 } 677 678 /* End Workaround for OptimaEEE */ 679 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0); 680 681 /* Enable 10Base-Te (EEE) */ 682 if (hw->chip_id >= CHIP_ID_YUKON_PRM) { 683 reg = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL); 684 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, 685 reg | PHY_M_10B_TE_ENABLE); 686 } 687 } 688 689 /* Enable phy interrupt on auto-negotiation complete (or link up) */ 690 if (sky2->flags & SKY2_FLAG_AUTO_SPEED) 691 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL); 692 else 693 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK); 694 } 695 696 static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD }; 697 static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA }; 698 699 static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port) 700 { 701 u32 reg1; 702 703 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); 704 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1); 705 reg1 &= ~phy_power[port]; 706 707 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1) 708 reg1 |= coma_mode[port]; 709 710 sky2_pci_write32(hw, PCI_DEV_REG1, reg1); 711 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 712 sky2_pci_read32(hw, PCI_DEV_REG1); 713 714 if (hw->chip_id == CHIP_ID_YUKON_FE) 715 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_ANE); 716 else if (hw->flags & SKY2_HW_ADV_POWER_CTL) 717 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR); 718 } 719 720 static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port) 721 { 722 u32 reg1; 723 u16 ctrl; 724 725 /* release GPHY Control reset */ 726 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR); 727 728 /* release GMAC reset */ 729 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR); 730 731 if (hw->flags & SKY2_HW_NEWER_PHY) { 732 /* select page 2 to access MAC control register */ 733 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2); 734 735 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); 736 /* allow GMII Power Down */ 737 ctrl &= ~PHY_M_MAC_GMIF_PUP; 738 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); 739 740 /* set page register back to 0 */ 741 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0); 742 } 743 744 /* setup General Purpose Control Register */ 745 gma_write16(hw, port, GM_GP_CTRL, 746 GM_GPCR_FL_PASS | GM_GPCR_SPEED_100 | 747 GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS | 748 GM_GPCR_AU_SPD_DIS); 749 750 if (hw->chip_id != CHIP_ID_YUKON_EC) { 751 if (hw->chip_id == CHIP_ID_YUKON_EC_U) { 752 /* select page 2 to access MAC control register */ 753 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2); 754 755 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); 756 /* enable Power Down */ 757 ctrl |= PHY_M_PC_POW_D_ENA; 758 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); 759 760 /* set page register back to 0 */ 761 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0); 762 } 763 764 /* set IEEE compatible Power Down Mode (dev. #4.99) */ 765 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_PDOWN); 766 } 767 768 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); 769 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1); 770 reg1 |= phy_power[port]; /* set PHY to PowerDown/COMA Mode */ 771 sky2_pci_write32(hw, PCI_DEV_REG1, reg1); 772 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 773 } 774 775 /* configure IPG according to used link speed */ 776 static void sky2_set_ipg(struct sky2_port *sky2) 777 { 778 u16 reg; 779 780 reg = gma_read16(sky2->hw, sky2->port, GM_SERIAL_MODE); 781 reg &= ~GM_SMOD_IPG_MSK; 782 if (sky2->speed > SPEED_100) 783 reg |= IPG_DATA_VAL(IPG_DATA_DEF_1000); 784 else 785 reg |= IPG_DATA_VAL(IPG_DATA_DEF_10_100); 786 gma_write16(sky2->hw, sky2->port, GM_SERIAL_MODE, reg); 787 } 788 789 /* Enable Rx/Tx */ 790 static void sky2_enable_rx_tx(struct sky2_port *sky2) 791 { 792 struct sky2_hw *hw = sky2->hw; 793 unsigned port = sky2->port; 794 u16 reg; 795 796 reg = gma_read16(hw, port, GM_GP_CTRL); 797 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA; 798 gma_write16(hw, port, GM_GP_CTRL, reg); 799 } 800 801 /* Force a renegotiation */ 802 static void sky2_phy_reinit(struct sky2_port *sky2) 803 { 804 spin_lock_bh(&sky2->phy_lock); 805 sky2_phy_init(sky2->hw, sky2->port); 806 sky2_enable_rx_tx(sky2); 807 spin_unlock_bh(&sky2->phy_lock); 808 } 809 810 /* Put device in state to listen for Wake On Lan */ 811 static void sky2_wol_init(struct sky2_port *sky2) 812 { 813 struct sky2_hw *hw = sky2->hw; 814 unsigned port = sky2->port; 815 enum flow_control save_mode; 816 u16 ctrl; 817 818 /* Bring hardware out of reset */ 819 sky2_write16(hw, B0_CTST, CS_RST_CLR); 820 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR); 821 822 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR); 823 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR); 824 825 /* Force to 10/100 826 * sky2_reset will re-enable on resume 827 */ 828 save_mode = sky2->flow_mode; 829 ctrl = sky2->advertising; 830 831 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full); 832 sky2->flow_mode = FC_NONE; 833 834 spin_lock_bh(&sky2->phy_lock); 835 sky2_phy_power_up(hw, port); 836 sky2_phy_init(hw, port); 837 spin_unlock_bh(&sky2->phy_lock); 838 839 sky2->flow_mode = save_mode; 840 sky2->advertising = ctrl; 841 842 /* Set GMAC to no flow control and auto update for speed/duplex */ 843 gma_write16(hw, port, GM_GP_CTRL, 844 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA| 845 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS); 846 847 /* Set WOL address */ 848 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR), 849 sky2->netdev->dev_addr, ETH_ALEN); 850 851 /* Turn on appropriate WOL control bits */ 852 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT); 853 ctrl = 0; 854 if (sky2->wol & WAKE_PHY) 855 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT; 856 else 857 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT; 858 859 if (sky2->wol & WAKE_MAGIC) 860 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT; 861 else 862 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT; 863 864 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT; 865 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl); 866 867 /* Disable PiG firmware */ 868 sky2_write16(hw, B0_CTST, Y2_HW_WOL_OFF); 869 870 /* block receiver */ 871 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET); 872 sky2_read32(hw, B0_CTST); 873 } 874 875 static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port) 876 { 877 struct net_device *dev = hw->dev[port]; 878 879 if ( (hw->chip_id == CHIP_ID_YUKON_EX && 880 hw->chip_rev != CHIP_REV_YU_EX_A0) || 881 hw->chip_id >= CHIP_ID_YUKON_FE_P) { 882 /* Yukon-Extreme B0 and further Extreme devices */ 883 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA); 884 } else if (dev->mtu > ETH_DATA_LEN) { 885 /* set Tx GMAC FIFO Almost Empty Threshold */ 886 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 887 (ECU_JUMBO_WM << 16) | ECU_AE_THR); 888 889 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS); 890 } else 891 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA); 892 } 893 894 static void sky2_mac_init(struct sky2_hw *hw, unsigned port) 895 { 896 struct sky2_port *sky2 = netdev_priv(hw->dev[port]); 897 u16 reg; 898 u32 rx_reg; 899 int i; 900 const u8 *addr = hw->dev[port]->dev_addr; 901 902 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET); 903 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR); 904 905 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR); 906 907 if (hw->chip_id == CHIP_ID_YUKON_XL && 908 hw->chip_rev == CHIP_REV_YU_XL_A0 && 909 port == 1) { 910 /* WA DEV_472 -- looks like crossed wires on port 2 */ 911 /* clear GMAC 1 Control reset */ 912 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR); 913 do { 914 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET); 915 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR); 916 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL || 917 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 || 918 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0); 919 } 920 921 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC)); 922 923 /* Enable Transmit FIFO Underrun */ 924 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK); 925 926 spin_lock_bh(&sky2->phy_lock); 927 sky2_phy_power_up(hw, port); 928 sky2_phy_init(hw, port); 929 spin_unlock_bh(&sky2->phy_lock); 930 931 /* MIB clear */ 932 reg = gma_read16(hw, port, GM_PHY_ADDR); 933 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR); 934 935 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4) 936 gma_read16(hw, port, i); 937 gma_write16(hw, port, GM_PHY_ADDR, reg); 938 939 /* transmit control */ 940 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF)); 941 942 /* receive control reg: unicast + multicast + no FCS */ 943 gma_write16(hw, port, GM_RX_CTRL, 944 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA); 945 946 /* transmit flow control */ 947 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff); 948 949 /* transmit parameter */ 950 gma_write16(hw, port, GM_TX_PARAM, 951 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) | 952 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) | 953 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) | 954 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF)); 955 956 /* serial mode register */ 957 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) | 958 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF_1000); 959 960 if (hw->dev[port]->mtu > ETH_DATA_LEN) 961 reg |= GM_SMOD_JUMBO_ENA; 962 963 if (hw->chip_id == CHIP_ID_YUKON_EC_U && 964 hw->chip_rev == CHIP_REV_YU_EC_U_B1) 965 reg |= GM_NEW_FLOW_CTRL; 966 967 gma_write16(hw, port, GM_SERIAL_MODE, reg); 968 969 /* virtual address for data */ 970 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr); 971 972 /* physical address: used for pause frames */ 973 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr); 974 975 /* ignore counter overflows */ 976 gma_write16(hw, port, GM_TX_IRQ_MSK, 0); 977 gma_write16(hw, port, GM_RX_IRQ_MSK, 0); 978 gma_write16(hw, port, GM_TR_IRQ_MSK, 0); 979 980 /* Configure Rx MAC FIFO */ 981 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR); 982 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON; 983 if (hw->chip_id == CHIP_ID_YUKON_EX || 984 hw->chip_id == CHIP_ID_YUKON_FE_P) 985 rx_reg |= GMF_RX_OVER_ON; 986 987 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg); 988 989 if (hw->chip_id == CHIP_ID_YUKON_XL) { 990 /* Hardware errata - clear flush mask */ 991 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0); 992 } else { 993 /* Flush Rx MAC FIFO on any flow control or error */ 994 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR); 995 } 996 997 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */ 998 reg = RX_GMF_FL_THR_DEF + 1; 999 /* Another magic mystery workaround from sk98lin */ 1000 if (hw->chip_id == CHIP_ID_YUKON_FE_P && 1001 hw->chip_rev == CHIP_REV_YU_FE2_A0) 1002 reg = 0x178; 1003 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg); 1004 1005 /* Configure Tx MAC FIFO */ 1006 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR); 1007 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON); 1008 1009 /* On chips without ram buffer, pause is controlled by MAC level */ 1010 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) { 1011 /* Pause threshold is scaled by 8 in bytes */ 1012 if (hw->chip_id == CHIP_ID_YUKON_FE_P && 1013 hw->chip_rev == CHIP_REV_YU_FE2_A0) 1014 reg = 1568 / 8; 1015 else 1016 reg = 1024 / 8; 1017 sky2_write16(hw, SK_REG(port, RX_GMF_UP_THR), reg); 1018 sky2_write16(hw, SK_REG(port, RX_GMF_LP_THR), 768 / 8); 1019 1020 sky2_set_tx_stfwd(hw, port); 1021 } 1022 1023 if (hw->chip_id == CHIP_ID_YUKON_FE_P && 1024 hw->chip_rev == CHIP_REV_YU_FE2_A0) { 1025 /* disable dynamic watermark */ 1026 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA)); 1027 reg &= ~TX_DYN_WM_ENA; 1028 sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg); 1029 } 1030 } 1031 1032 /* Assign Ram Buffer allocation to queue */ 1033 static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space) 1034 { 1035 u32 end; 1036 1037 /* convert from K bytes to qwords used for hw register */ 1038 start *= 1024/8; 1039 space *= 1024/8; 1040 end = start + space - 1; 1041 1042 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR); 1043 sky2_write32(hw, RB_ADDR(q, RB_START), start); 1044 sky2_write32(hw, RB_ADDR(q, RB_END), end); 1045 sky2_write32(hw, RB_ADDR(q, RB_WP), start); 1046 sky2_write32(hw, RB_ADDR(q, RB_RP), start); 1047 1048 if (q == Q_R1 || q == Q_R2) { 1049 u32 tp = space - space/4; 1050 1051 /* On receive queue's set the thresholds 1052 * give receiver priority when > 3/4 full 1053 * send pause when down to 2K 1054 */ 1055 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp); 1056 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2); 1057 1058 tp = space - 2048/8; 1059 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp); 1060 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4); 1061 } else { 1062 /* Enable store & forward on Tx queue's because 1063 * Tx FIFO is only 1K on Yukon 1064 */ 1065 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD); 1066 } 1067 1068 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD); 1069 sky2_read8(hw, RB_ADDR(q, RB_CTRL)); 1070 } 1071 1072 /* Setup Bus Memory Interface */ 1073 static void sky2_qset(struct sky2_hw *hw, u16 q) 1074 { 1075 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET); 1076 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT); 1077 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON); 1078 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT); 1079 } 1080 1081 /* Setup prefetch unit registers. This is the interface between 1082 * hardware and driver list elements 1083 */ 1084 static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr, 1085 dma_addr_t addr, u32 last) 1086 { 1087 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET); 1088 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR); 1089 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), upper_32_bits(addr)); 1090 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), lower_32_bits(addr)); 1091 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last); 1092 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON); 1093 1094 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL)); 1095 } 1096 1097 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2, u16 *slot) 1098 { 1099 struct sky2_tx_le *le = sky2->tx_le + *slot; 1100 1101 *slot = RING_NEXT(*slot, sky2->tx_ring_size); 1102 le->ctrl = 0; 1103 return le; 1104 } 1105 1106 static void tx_init(struct sky2_port *sky2) 1107 { 1108 struct sky2_tx_le *le; 1109 1110 sky2->tx_prod = sky2->tx_cons = 0; 1111 sky2->tx_tcpsum = 0; 1112 sky2->tx_last_mss = 0; 1113 1114 le = get_tx_le(sky2, &sky2->tx_prod); 1115 le->addr = 0; 1116 le->opcode = OP_ADDR64 | HW_OWNER; 1117 sky2->tx_last_upper = 0; 1118 } 1119 1120 /* Update chip's next pointer */ 1121 static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx) 1122 { 1123 /* Make sure write' to descriptors are complete before we tell hardware */ 1124 wmb(); 1125 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx); 1126 1127 /* Synchronize I/O on since next processor may write to tail */ 1128 mmiowb(); 1129 } 1130 1131 1132 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2) 1133 { 1134 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put; 1135 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE); 1136 le->ctrl = 0; 1137 return le; 1138 } 1139 1140 static unsigned sky2_get_rx_threshold(struct sky2_port *sky2) 1141 { 1142 unsigned size; 1143 1144 /* Space needed for frame data + headers rounded up */ 1145 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8); 1146 1147 /* Stopping point for hardware truncation */ 1148 return (size - 8) / sizeof(u32); 1149 } 1150 1151 static unsigned sky2_get_rx_data_size(struct sky2_port *sky2) 1152 { 1153 struct rx_ring_info *re; 1154 unsigned size; 1155 1156 /* Space needed for frame data + headers rounded up */ 1157 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8); 1158 1159 sky2->rx_nfrags = size >> PAGE_SHIFT; 1160 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr)); 1161 1162 /* Compute residue after pages */ 1163 size -= sky2->rx_nfrags << PAGE_SHIFT; 1164 1165 /* Optimize to handle small packets and headers */ 1166 if (size < copybreak) 1167 size = copybreak; 1168 if (size < ETH_HLEN) 1169 size = ETH_HLEN; 1170 1171 return size; 1172 } 1173 1174 /* Build description to hardware for one receive segment */ 1175 static void sky2_rx_add(struct sky2_port *sky2, u8 op, 1176 dma_addr_t map, unsigned len) 1177 { 1178 struct sky2_rx_le *le; 1179 1180 if (sizeof(dma_addr_t) > sizeof(u32)) { 1181 le = sky2_next_rx(sky2); 1182 le->addr = cpu_to_le32(upper_32_bits(map)); 1183 le->opcode = OP_ADDR64 | HW_OWNER; 1184 } 1185 1186 le = sky2_next_rx(sky2); 1187 le->addr = cpu_to_le32(lower_32_bits(map)); 1188 le->length = cpu_to_le16(len); 1189 le->opcode = op | HW_OWNER; 1190 } 1191 1192 /* Build description to hardware for one possibly fragmented skb */ 1193 static void sky2_rx_submit(struct sky2_port *sky2, 1194 const struct rx_ring_info *re) 1195 { 1196 int i; 1197 1198 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size); 1199 1200 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++) 1201 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE); 1202 } 1203 1204 1205 static int sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re, 1206 unsigned size) 1207 { 1208 struct sk_buff *skb = re->skb; 1209 int i; 1210 1211 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE); 1212 if (pci_dma_mapping_error(pdev, re->data_addr)) 1213 goto mapping_error; 1214 1215 dma_unmap_len_set(re, data_size, size); 1216 1217 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1218 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1219 1220 re->frag_addr[i] = skb_frag_dma_map(&pdev->dev, frag, 0, 1221 skb_frag_size(frag), 1222 DMA_FROM_DEVICE); 1223 1224 if (dma_mapping_error(&pdev->dev, re->frag_addr[i])) 1225 goto map_page_error; 1226 } 1227 return 0; 1228 1229 map_page_error: 1230 while (--i >= 0) { 1231 pci_unmap_page(pdev, re->frag_addr[i], 1232 skb_frag_size(&skb_shinfo(skb)->frags[i]), 1233 PCI_DMA_FROMDEVICE); 1234 } 1235 1236 pci_unmap_single(pdev, re->data_addr, dma_unmap_len(re, data_size), 1237 PCI_DMA_FROMDEVICE); 1238 1239 mapping_error: 1240 if (net_ratelimit()) 1241 dev_warn(&pdev->dev, "%s: rx mapping error\n", 1242 skb->dev->name); 1243 return -EIO; 1244 } 1245 1246 static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re) 1247 { 1248 struct sk_buff *skb = re->skb; 1249 int i; 1250 1251 pci_unmap_single(pdev, re->data_addr, dma_unmap_len(re, data_size), 1252 PCI_DMA_FROMDEVICE); 1253 1254 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) 1255 pci_unmap_page(pdev, re->frag_addr[i], 1256 skb_frag_size(&skb_shinfo(skb)->frags[i]), 1257 PCI_DMA_FROMDEVICE); 1258 } 1259 1260 /* Tell chip where to start receive checksum. 1261 * Actually has two checksums, but set both same to avoid possible byte 1262 * order problems. 1263 */ 1264 static void rx_set_checksum(struct sky2_port *sky2) 1265 { 1266 struct sky2_rx_le *le = sky2_next_rx(sky2); 1267 1268 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN); 1269 le->ctrl = 0; 1270 le->opcode = OP_TCPSTART | HW_OWNER; 1271 1272 sky2_write32(sky2->hw, 1273 Q_ADDR(rxqaddr[sky2->port], Q_CSR), 1274 (sky2->netdev->features & NETIF_F_RXCSUM) 1275 ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM); 1276 } 1277 1278 /* 1279 * Fixed initial key as seed to RSS. 1280 */ 1281 static const uint32_t rss_init_key[10] = { 1282 0x7c3351da, 0x51c5cf4e, 0x44adbdd1, 0xe8d38d18, 0x48897c43, 1283 0xb1d60e7e, 0x6a3dd760, 0x01a2e453, 0x16f46f13, 0x1a0e7b30 1284 }; 1285 1286 /* Enable/disable receive hash calculation (RSS) */ 1287 static void rx_set_rss(struct net_device *dev, u32 features) 1288 { 1289 struct sky2_port *sky2 = netdev_priv(dev); 1290 struct sky2_hw *hw = sky2->hw; 1291 int i, nkeys = 4; 1292 1293 /* Supports IPv6 and other modes */ 1294 if (hw->flags & SKY2_HW_NEW_LE) { 1295 nkeys = 10; 1296 sky2_write32(hw, SK_REG(sky2->port, RSS_CFG), HASH_ALL); 1297 } 1298 1299 /* Program RSS initial values */ 1300 if (features & NETIF_F_RXHASH) { 1301 for (i = 0; i < nkeys; i++) 1302 sky2_write32(hw, SK_REG(sky2->port, RSS_KEY + i * 4), 1303 rss_init_key[i]); 1304 1305 /* Need to turn on (undocumented) flag to make hashing work */ 1306 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), 1307 RX_STFW_ENA); 1308 1309 sky2_write32(hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR), 1310 BMU_ENA_RX_RSS_HASH); 1311 } else 1312 sky2_write32(hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR), 1313 BMU_DIS_RX_RSS_HASH); 1314 } 1315 1316 /* 1317 * The RX Stop command will not work for Yukon-2 if the BMU does not 1318 * reach the end of packet and since we can't make sure that we have 1319 * incoming data, we must reset the BMU while it is not doing a DMA 1320 * transfer. Since it is possible that the RX path is still active, 1321 * the RX RAM buffer will be stopped first, so any possible incoming 1322 * data will not trigger a DMA. After the RAM buffer is stopped, the 1323 * BMU is polled until any DMA in progress is ended and only then it 1324 * will be reset. 1325 */ 1326 static void sky2_rx_stop(struct sky2_port *sky2) 1327 { 1328 struct sky2_hw *hw = sky2->hw; 1329 unsigned rxq = rxqaddr[sky2->port]; 1330 int i; 1331 1332 /* disable the RAM Buffer receive queue */ 1333 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD); 1334 1335 for (i = 0; i < 0xffff; i++) 1336 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL)) 1337 == sky2_read8(hw, RB_ADDR(rxq, Q_RL))) 1338 goto stopped; 1339 1340 netdev_warn(sky2->netdev, "receiver stop failed\n"); 1341 stopped: 1342 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST); 1343 1344 /* reset the Rx prefetch unit */ 1345 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET); 1346 mmiowb(); 1347 } 1348 1349 /* Clean out receive buffer area, assumes receiver hardware stopped */ 1350 static void sky2_rx_clean(struct sky2_port *sky2) 1351 { 1352 unsigned i; 1353 1354 memset(sky2->rx_le, 0, RX_LE_BYTES); 1355 for (i = 0; i < sky2->rx_pending; i++) { 1356 struct rx_ring_info *re = sky2->rx_ring + i; 1357 1358 if (re->skb) { 1359 sky2_rx_unmap_skb(sky2->hw->pdev, re); 1360 kfree_skb(re->skb); 1361 re->skb = NULL; 1362 } 1363 } 1364 } 1365 1366 /* Basic MII support */ 1367 static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 1368 { 1369 struct mii_ioctl_data *data = if_mii(ifr); 1370 struct sky2_port *sky2 = netdev_priv(dev); 1371 struct sky2_hw *hw = sky2->hw; 1372 int err = -EOPNOTSUPP; 1373 1374 if (!netif_running(dev)) 1375 return -ENODEV; /* Phy still in reset */ 1376 1377 switch (cmd) { 1378 case SIOCGMIIPHY: 1379 data->phy_id = PHY_ADDR_MARV; 1380 1381 /* fallthru */ 1382 case SIOCGMIIREG: { 1383 u16 val = 0; 1384 1385 spin_lock_bh(&sky2->phy_lock); 1386 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val); 1387 spin_unlock_bh(&sky2->phy_lock); 1388 1389 data->val_out = val; 1390 break; 1391 } 1392 1393 case SIOCSMIIREG: 1394 spin_lock_bh(&sky2->phy_lock); 1395 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f, 1396 data->val_in); 1397 spin_unlock_bh(&sky2->phy_lock); 1398 break; 1399 } 1400 return err; 1401 } 1402 1403 #define SKY2_VLAN_OFFLOADS (NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_TSO) 1404 1405 static void sky2_vlan_mode(struct net_device *dev, u32 features) 1406 { 1407 struct sky2_port *sky2 = netdev_priv(dev); 1408 struct sky2_hw *hw = sky2->hw; 1409 u16 port = sky2->port; 1410 1411 if (features & NETIF_F_HW_VLAN_RX) 1412 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), 1413 RX_VLAN_STRIP_ON); 1414 else 1415 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), 1416 RX_VLAN_STRIP_OFF); 1417 1418 if (features & NETIF_F_HW_VLAN_TX) { 1419 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), 1420 TX_VLAN_TAG_ON); 1421 1422 dev->vlan_features |= SKY2_VLAN_OFFLOADS; 1423 } else { 1424 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), 1425 TX_VLAN_TAG_OFF); 1426 1427 /* Can't do transmit offload of vlan without hw vlan */ 1428 dev->vlan_features &= ~SKY2_VLAN_OFFLOADS; 1429 } 1430 } 1431 1432 /* Amount of required worst case padding in rx buffer */ 1433 static inline unsigned sky2_rx_pad(const struct sky2_hw *hw) 1434 { 1435 return (hw->flags & SKY2_HW_RAM_BUFFER) ? 8 : 2; 1436 } 1437 1438 /* 1439 * Allocate an skb for receiving. If the MTU is large enough 1440 * make the skb non-linear with a fragment list of pages. 1441 */ 1442 static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2, gfp_t gfp) 1443 { 1444 struct sk_buff *skb; 1445 int i; 1446 1447 skb = __netdev_alloc_skb(sky2->netdev, 1448 sky2->rx_data_size + sky2_rx_pad(sky2->hw), 1449 gfp); 1450 if (!skb) 1451 goto nomem; 1452 1453 if (sky2->hw->flags & SKY2_HW_RAM_BUFFER) { 1454 unsigned char *start; 1455 /* 1456 * Workaround for a bug in FIFO that cause hang 1457 * if the FIFO if the receive buffer is not 64 byte aligned. 1458 * The buffer returned from netdev_alloc_skb is 1459 * aligned except if slab debugging is enabled. 1460 */ 1461 start = PTR_ALIGN(skb->data, 8); 1462 skb_reserve(skb, start - skb->data); 1463 } else 1464 skb_reserve(skb, NET_IP_ALIGN); 1465 1466 for (i = 0; i < sky2->rx_nfrags; i++) { 1467 struct page *page = alloc_page(gfp); 1468 1469 if (!page) 1470 goto free_partial; 1471 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE); 1472 } 1473 1474 return skb; 1475 free_partial: 1476 kfree_skb(skb); 1477 nomem: 1478 return NULL; 1479 } 1480 1481 static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq) 1482 { 1483 sky2_put_idx(sky2->hw, rxq, sky2->rx_put); 1484 } 1485 1486 static int sky2_alloc_rx_skbs(struct sky2_port *sky2) 1487 { 1488 struct sky2_hw *hw = sky2->hw; 1489 unsigned i; 1490 1491 sky2->rx_data_size = sky2_get_rx_data_size(sky2); 1492 1493 /* Fill Rx ring */ 1494 for (i = 0; i < sky2->rx_pending; i++) { 1495 struct rx_ring_info *re = sky2->rx_ring + i; 1496 1497 re->skb = sky2_rx_alloc(sky2, GFP_KERNEL); 1498 if (!re->skb) 1499 return -ENOMEM; 1500 1501 if (sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size)) { 1502 dev_kfree_skb(re->skb); 1503 re->skb = NULL; 1504 return -ENOMEM; 1505 } 1506 } 1507 return 0; 1508 } 1509 1510 /* 1511 * Setup receiver buffer pool. 1512 * Normal case this ends up creating one list element for skb 1513 * in the receive ring. Worst case if using large MTU and each 1514 * allocation falls on a different 64 bit region, that results 1515 * in 6 list elements per ring entry. 1516 * One element is used for checksum enable/disable, and one 1517 * extra to avoid wrap. 1518 */ 1519 static void sky2_rx_start(struct sky2_port *sky2) 1520 { 1521 struct sky2_hw *hw = sky2->hw; 1522 struct rx_ring_info *re; 1523 unsigned rxq = rxqaddr[sky2->port]; 1524 unsigned i, thresh; 1525 1526 sky2->rx_put = sky2->rx_next = 0; 1527 sky2_qset(hw, rxq); 1528 1529 /* On PCI express lowering the watermark gives better performance */ 1530 if (pci_is_pcie(hw->pdev)) 1531 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX); 1532 1533 /* These chips have no ram buffer? 1534 * MAC Rx RAM Read is controlled by hardware */ 1535 if (hw->chip_id == CHIP_ID_YUKON_EC_U && 1536 hw->chip_rev > CHIP_REV_YU_EC_U_A0) 1537 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS); 1538 1539 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1); 1540 1541 if (!(hw->flags & SKY2_HW_NEW_LE)) 1542 rx_set_checksum(sky2); 1543 1544 if (!(hw->flags & SKY2_HW_RSS_BROKEN)) 1545 rx_set_rss(sky2->netdev, sky2->netdev->features); 1546 1547 /* submit Rx ring */ 1548 for (i = 0; i < sky2->rx_pending; i++) { 1549 re = sky2->rx_ring + i; 1550 sky2_rx_submit(sky2, re); 1551 } 1552 1553 /* 1554 * The receiver hangs if it receives frames larger than the 1555 * packet buffer. As a workaround, truncate oversize frames, but 1556 * the register is limited to 9 bits, so if you do frames > 2052 1557 * you better get the MTU right! 1558 */ 1559 thresh = sky2_get_rx_threshold(sky2); 1560 if (thresh > 0x1ff) 1561 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF); 1562 else { 1563 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh); 1564 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON); 1565 } 1566 1567 /* Tell chip about available buffers */ 1568 sky2_rx_update(sky2, rxq); 1569 1570 if (hw->chip_id == CHIP_ID_YUKON_EX || 1571 hw->chip_id == CHIP_ID_YUKON_SUPR) { 1572 /* 1573 * Disable flushing of non ASF packets; 1574 * must be done after initializing the BMUs; 1575 * drivers without ASF support should do this too, otherwise 1576 * it may happen that they cannot run on ASF devices; 1577 * remember that the MAC FIFO isn't reset during initialization. 1578 */ 1579 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_MACSEC_FLUSH_OFF); 1580 } 1581 1582 if (hw->chip_id >= CHIP_ID_YUKON_SUPR) { 1583 /* Enable RX Home Address & Routing Header checksum fix */ 1584 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_FL_CTRL), 1585 RX_IPV6_SA_MOB_ENA | RX_IPV6_DA_MOB_ENA); 1586 1587 /* Enable TX Home Address & Routing Header checksum fix */ 1588 sky2_write32(hw, Q_ADDR(txqaddr[sky2->port], Q_TEST), 1589 TBMU_TEST_HOME_ADD_FIX_EN | TBMU_TEST_ROUTING_ADD_FIX_EN); 1590 } 1591 } 1592 1593 static int sky2_alloc_buffers(struct sky2_port *sky2) 1594 { 1595 struct sky2_hw *hw = sky2->hw; 1596 1597 /* must be power of 2 */ 1598 sky2->tx_le = pci_alloc_consistent(hw->pdev, 1599 sky2->tx_ring_size * 1600 sizeof(struct sky2_tx_le), 1601 &sky2->tx_le_map); 1602 if (!sky2->tx_le) 1603 goto nomem; 1604 1605 sky2->tx_ring = kcalloc(sky2->tx_ring_size, sizeof(struct tx_ring_info), 1606 GFP_KERNEL); 1607 if (!sky2->tx_ring) 1608 goto nomem; 1609 1610 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES, 1611 &sky2->rx_le_map); 1612 if (!sky2->rx_le) 1613 goto nomem; 1614 memset(sky2->rx_le, 0, RX_LE_BYTES); 1615 1616 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info), 1617 GFP_KERNEL); 1618 if (!sky2->rx_ring) 1619 goto nomem; 1620 1621 return sky2_alloc_rx_skbs(sky2); 1622 nomem: 1623 return -ENOMEM; 1624 } 1625 1626 static void sky2_free_buffers(struct sky2_port *sky2) 1627 { 1628 struct sky2_hw *hw = sky2->hw; 1629 1630 sky2_rx_clean(sky2); 1631 1632 if (sky2->rx_le) { 1633 pci_free_consistent(hw->pdev, RX_LE_BYTES, 1634 sky2->rx_le, sky2->rx_le_map); 1635 sky2->rx_le = NULL; 1636 } 1637 if (sky2->tx_le) { 1638 pci_free_consistent(hw->pdev, 1639 sky2->tx_ring_size * sizeof(struct sky2_tx_le), 1640 sky2->tx_le, sky2->tx_le_map); 1641 sky2->tx_le = NULL; 1642 } 1643 kfree(sky2->tx_ring); 1644 kfree(sky2->rx_ring); 1645 1646 sky2->tx_ring = NULL; 1647 sky2->rx_ring = NULL; 1648 } 1649 1650 static void sky2_hw_up(struct sky2_port *sky2) 1651 { 1652 struct sky2_hw *hw = sky2->hw; 1653 unsigned port = sky2->port; 1654 u32 ramsize; 1655 int cap; 1656 struct net_device *otherdev = hw->dev[sky2->port^1]; 1657 1658 tx_init(sky2); 1659 1660 /* 1661 * On dual port PCI-X card, there is an problem where status 1662 * can be received out of order due to split transactions 1663 */ 1664 if (otherdev && netif_running(otherdev) && 1665 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) { 1666 u16 cmd; 1667 1668 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD); 1669 cmd &= ~PCI_X_CMD_MAX_SPLIT; 1670 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd); 1671 } 1672 1673 sky2_mac_init(hw, port); 1674 1675 /* Register is number of 4K blocks on internal RAM buffer. */ 1676 ramsize = sky2_read8(hw, B2_E_0) * 4; 1677 if (ramsize > 0) { 1678 u32 rxspace; 1679 1680 netdev_dbg(sky2->netdev, "ram buffer %dK\n", ramsize); 1681 if (ramsize < 16) 1682 rxspace = ramsize / 2; 1683 else 1684 rxspace = 8 + (2*(ramsize - 16))/3; 1685 1686 sky2_ramset(hw, rxqaddr[port], 0, rxspace); 1687 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace); 1688 1689 /* Make sure SyncQ is disabled */ 1690 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL), 1691 RB_RST_SET); 1692 } 1693 1694 sky2_qset(hw, txqaddr[port]); 1695 1696 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */ 1697 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0) 1698 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF); 1699 1700 /* Set almost empty threshold */ 1701 if (hw->chip_id == CHIP_ID_YUKON_EC_U && 1702 hw->chip_rev == CHIP_REV_YU_EC_U_A0) 1703 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV); 1704 1705 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map, 1706 sky2->tx_ring_size - 1); 1707 1708 sky2_vlan_mode(sky2->netdev, sky2->netdev->features); 1709 netdev_update_features(sky2->netdev); 1710 1711 sky2_rx_start(sky2); 1712 } 1713 1714 /* Setup device IRQ and enable napi to process */ 1715 static int sky2_setup_irq(struct sky2_hw *hw, const char *name) 1716 { 1717 struct pci_dev *pdev = hw->pdev; 1718 int err; 1719 1720 err = request_irq(pdev->irq, sky2_intr, 1721 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED, 1722 name, hw); 1723 if (err) 1724 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq); 1725 else { 1726 hw->flags |= SKY2_HW_IRQ_SETUP; 1727 1728 napi_enable(&hw->napi); 1729 sky2_write32(hw, B0_IMSK, Y2_IS_BASE); 1730 sky2_read32(hw, B0_IMSK); 1731 } 1732 1733 return err; 1734 } 1735 1736 1737 /* Bring up network interface. */ 1738 static int sky2_open(struct net_device *dev) 1739 { 1740 struct sky2_port *sky2 = netdev_priv(dev); 1741 struct sky2_hw *hw = sky2->hw; 1742 unsigned port = sky2->port; 1743 u32 imask; 1744 int err; 1745 1746 netif_carrier_off(dev); 1747 1748 err = sky2_alloc_buffers(sky2); 1749 if (err) 1750 goto err_out; 1751 1752 /* With single port, IRQ is setup when device is brought up */ 1753 if (hw->ports == 1 && (err = sky2_setup_irq(hw, dev->name))) 1754 goto err_out; 1755 1756 sky2_hw_up(sky2); 1757 1758 if (hw->chip_id == CHIP_ID_YUKON_OPT || 1759 hw->chip_id == CHIP_ID_YUKON_PRM || 1760 hw->chip_id == CHIP_ID_YUKON_OP_2) 1761 imask |= Y2_IS_PHY_QLNK; /* enable PHY Quick Link */ 1762 1763 /* Enable interrupts from phy/mac for port */ 1764 imask = sky2_read32(hw, B0_IMSK); 1765 imask |= portirq_msk[port]; 1766 sky2_write32(hw, B0_IMSK, imask); 1767 sky2_read32(hw, B0_IMSK); 1768 1769 netif_info(sky2, ifup, dev, "enabling interface\n"); 1770 1771 return 0; 1772 1773 err_out: 1774 sky2_free_buffers(sky2); 1775 return err; 1776 } 1777 1778 /* Modular subtraction in ring */ 1779 static inline int tx_inuse(const struct sky2_port *sky2) 1780 { 1781 return (sky2->tx_prod - sky2->tx_cons) & (sky2->tx_ring_size - 1); 1782 } 1783 1784 /* Number of list elements available for next tx */ 1785 static inline int tx_avail(const struct sky2_port *sky2) 1786 { 1787 return sky2->tx_pending - tx_inuse(sky2); 1788 } 1789 1790 /* Estimate of number of transmit list elements required */ 1791 static unsigned tx_le_req(const struct sk_buff *skb) 1792 { 1793 unsigned count; 1794 1795 count = (skb_shinfo(skb)->nr_frags + 1) 1796 * (sizeof(dma_addr_t) / sizeof(u32)); 1797 1798 if (skb_is_gso(skb)) 1799 ++count; 1800 else if (sizeof(dma_addr_t) == sizeof(u32)) 1801 ++count; /* possible vlan */ 1802 1803 if (skb->ip_summed == CHECKSUM_PARTIAL) 1804 ++count; 1805 1806 return count; 1807 } 1808 1809 static void sky2_tx_unmap(struct pci_dev *pdev, struct tx_ring_info *re) 1810 { 1811 if (re->flags & TX_MAP_SINGLE) 1812 pci_unmap_single(pdev, dma_unmap_addr(re, mapaddr), 1813 dma_unmap_len(re, maplen), 1814 PCI_DMA_TODEVICE); 1815 else if (re->flags & TX_MAP_PAGE) 1816 pci_unmap_page(pdev, dma_unmap_addr(re, mapaddr), 1817 dma_unmap_len(re, maplen), 1818 PCI_DMA_TODEVICE); 1819 re->flags = 0; 1820 } 1821 1822 /* 1823 * Put one packet in ring for transmit. 1824 * A single packet can generate multiple list elements, and 1825 * the number of ring elements will probably be less than the number 1826 * of list elements used. 1827 */ 1828 static netdev_tx_t sky2_xmit_frame(struct sk_buff *skb, 1829 struct net_device *dev) 1830 { 1831 struct sky2_port *sky2 = netdev_priv(dev); 1832 struct sky2_hw *hw = sky2->hw; 1833 struct sky2_tx_le *le = NULL; 1834 struct tx_ring_info *re; 1835 unsigned i, len; 1836 dma_addr_t mapping; 1837 u32 upper; 1838 u16 slot; 1839 u16 mss; 1840 u8 ctrl; 1841 1842 if (unlikely(tx_avail(sky2) < tx_le_req(skb))) 1843 return NETDEV_TX_BUSY; 1844 1845 len = skb_headlen(skb); 1846 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE); 1847 1848 if (pci_dma_mapping_error(hw->pdev, mapping)) 1849 goto mapping_error; 1850 1851 slot = sky2->tx_prod; 1852 netif_printk(sky2, tx_queued, KERN_DEBUG, dev, 1853 "tx queued, slot %u, len %d\n", slot, skb->len); 1854 1855 /* Send high bits if needed */ 1856 upper = upper_32_bits(mapping); 1857 if (upper != sky2->tx_last_upper) { 1858 le = get_tx_le(sky2, &slot); 1859 le->addr = cpu_to_le32(upper); 1860 sky2->tx_last_upper = upper; 1861 le->opcode = OP_ADDR64 | HW_OWNER; 1862 } 1863 1864 /* Check for TCP Segmentation Offload */ 1865 mss = skb_shinfo(skb)->gso_size; 1866 if (mss != 0) { 1867 1868 if (!(hw->flags & SKY2_HW_NEW_LE)) 1869 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb); 1870 1871 if (mss != sky2->tx_last_mss) { 1872 le = get_tx_le(sky2, &slot); 1873 le->addr = cpu_to_le32(mss); 1874 1875 if (hw->flags & SKY2_HW_NEW_LE) 1876 le->opcode = OP_MSS | HW_OWNER; 1877 else 1878 le->opcode = OP_LRGLEN | HW_OWNER; 1879 sky2->tx_last_mss = mss; 1880 } 1881 } 1882 1883 ctrl = 0; 1884 1885 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */ 1886 if (vlan_tx_tag_present(skb)) { 1887 if (!le) { 1888 le = get_tx_le(sky2, &slot); 1889 le->addr = 0; 1890 le->opcode = OP_VLAN|HW_OWNER; 1891 } else 1892 le->opcode |= OP_VLAN; 1893 le->length = cpu_to_be16(vlan_tx_tag_get(skb)); 1894 ctrl |= INS_VLAN; 1895 } 1896 1897 /* Handle TCP checksum offload */ 1898 if (skb->ip_summed == CHECKSUM_PARTIAL) { 1899 /* On Yukon EX (some versions) encoding change. */ 1900 if (hw->flags & SKY2_HW_AUTO_TX_SUM) 1901 ctrl |= CALSUM; /* auto checksum */ 1902 else { 1903 const unsigned offset = skb_transport_offset(skb); 1904 u32 tcpsum; 1905 1906 tcpsum = offset << 16; /* sum start */ 1907 tcpsum |= offset + skb->csum_offset; /* sum write */ 1908 1909 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM; 1910 if (ip_hdr(skb)->protocol == IPPROTO_UDP) 1911 ctrl |= UDPTCP; 1912 1913 if (tcpsum != sky2->tx_tcpsum) { 1914 sky2->tx_tcpsum = tcpsum; 1915 1916 le = get_tx_le(sky2, &slot); 1917 le->addr = cpu_to_le32(tcpsum); 1918 le->length = 0; /* initial checksum value */ 1919 le->ctrl = 1; /* one packet */ 1920 le->opcode = OP_TCPLISW | HW_OWNER; 1921 } 1922 } 1923 } 1924 1925 re = sky2->tx_ring + slot; 1926 re->flags = TX_MAP_SINGLE; 1927 dma_unmap_addr_set(re, mapaddr, mapping); 1928 dma_unmap_len_set(re, maplen, len); 1929 1930 le = get_tx_le(sky2, &slot); 1931 le->addr = cpu_to_le32(lower_32_bits(mapping)); 1932 le->length = cpu_to_le16(len); 1933 le->ctrl = ctrl; 1934 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER); 1935 1936 1937 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1938 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1939 1940 mapping = skb_frag_dma_map(&hw->pdev->dev, frag, 0, 1941 skb_frag_size(frag), DMA_TO_DEVICE); 1942 1943 if (dma_mapping_error(&hw->pdev->dev, mapping)) 1944 goto mapping_unwind; 1945 1946 upper = upper_32_bits(mapping); 1947 if (upper != sky2->tx_last_upper) { 1948 le = get_tx_le(sky2, &slot); 1949 le->addr = cpu_to_le32(upper); 1950 sky2->tx_last_upper = upper; 1951 le->opcode = OP_ADDR64 | HW_OWNER; 1952 } 1953 1954 re = sky2->tx_ring + slot; 1955 re->flags = TX_MAP_PAGE; 1956 dma_unmap_addr_set(re, mapaddr, mapping); 1957 dma_unmap_len_set(re, maplen, skb_frag_size(frag)); 1958 1959 le = get_tx_le(sky2, &slot); 1960 le->addr = cpu_to_le32(lower_32_bits(mapping)); 1961 le->length = cpu_to_le16(skb_frag_size(frag)); 1962 le->ctrl = ctrl; 1963 le->opcode = OP_BUFFER | HW_OWNER; 1964 } 1965 1966 re->skb = skb; 1967 le->ctrl |= EOP; 1968 1969 sky2->tx_prod = slot; 1970 1971 if (tx_avail(sky2) <= MAX_SKB_TX_LE) 1972 netif_stop_queue(dev); 1973 1974 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod); 1975 1976 return NETDEV_TX_OK; 1977 1978 mapping_unwind: 1979 for (i = sky2->tx_prod; i != slot; i = RING_NEXT(i, sky2->tx_ring_size)) { 1980 re = sky2->tx_ring + i; 1981 1982 sky2_tx_unmap(hw->pdev, re); 1983 } 1984 1985 mapping_error: 1986 if (net_ratelimit()) 1987 dev_warn(&hw->pdev->dev, "%s: tx mapping error\n", dev->name); 1988 dev_kfree_skb(skb); 1989 return NETDEV_TX_OK; 1990 } 1991 1992 /* 1993 * Free ring elements from starting at tx_cons until "done" 1994 * 1995 * NB: 1996 * 1. The hardware will tell us about partial completion of multi-part 1997 * buffers so make sure not to free skb to early. 1998 * 2. This may run in parallel start_xmit because the it only 1999 * looks at the tail of the queue of FIFO (tx_cons), not 2000 * the head (tx_prod) 2001 */ 2002 static void sky2_tx_complete(struct sky2_port *sky2, u16 done) 2003 { 2004 struct net_device *dev = sky2->netdev; 2005 unsigned idx; 2006 2007 BUG_ON(done >= sky2->tx_ring_size); 2008 2009 for (idx = sky2->tx_cons; idx != done; 2010 idx = RING_NEXT(idx, sky2->tx_ring_size)) { 2011 struct tx_ring_info *re = sky2->tx_ring + idx; 2012 struct sk_buff *skb = re->skb; 2013 2014 sky2_tx_unmap(sky2->hw->pdev, re); 2015 2016 if (skb) { 2017 netif_printk(sky2, tx_done, KERN_DEBUG, dev, 2018 "tx done %u\n", idx); 2019 2020 u64_stats_update_begin(&sky2->tx_stats.syncp); 2021 ++sky2->tx_stats.packets; 2022 sky2->tx_stats.bytes += skb->len; 2023 u64_stats_update_end(&sky2->tx_stats.syncp); 2024 2025 re->skb = NULL; 2026 dev_kfree_skb_any(skb); 2027 2028 sky2->tx_next = RING_NEXT(idx, sky2->tx_ring_size); 2029 } 2030 } 2031 2032 sky2->tx_cons = idx; 2033 smp_mb(); 2034 } 2035 2036 static void sky2_tx_reset(struct sky2_hw *hw, unsigned port) 2037 { 2038 /* Disable Force Sync bit and Enable Alloc bit */ 2039 sky2_write8(hw, SK_REG(port, TXA_CTRL), 2040 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC); 2041 2042 /* Stop Interval Timer and Limit Counter of Tx Arbiter */ 2043 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L); 2044 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L); 2045 2046 /* Reset the PCI FIFO of the async Tx queue */ 2047 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), 2048 BMU_RST_SET | BMU_FIFO_RST); 2049 2050 /* Reset the Tx prefetch units */ 2051 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL), 2052 PREF_UNIT_RST_SET); 2053 2054 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET); 2055 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET); 2056 2057 sky2_read32(hw, B0_CTST); 2058 } 2059 2060 static void sky2_hw_down(struct sky2_port *sky2) 2061 { 2062 struct sky2_hw *hw = sky2->hw; 2063 unsigned port = sky2->port; 2064 u16 ctrl; 2065 2066 /* Force flow control off */ 2067 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); 2068 2069 /* Stop transmitter */ 2070 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP); 2071 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR)); 2072 2073 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), 2074 RB_RST_SET | RB_DIS_OP_MD); 2075 2076 ctrl = gma_read16(hw, port, GM_GP_CTRL); 2077 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA); 2078 gma_write16(hw, port, GM_GP_CTRL, ctrl); 2079 2080 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET); 2081 2082 /* Workaround shared GMAC reset */ 2083 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && 2084 port == 0 && hw->dev[1] && netif_running(hw->dev[1]))) 2085 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET); 2086 2087 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET); 2088 2089 /* Force any delayed status interrupt and NAPI */ 2090 sky2_write32(hw, STAT_LEV_TIMER_CNT, 0); 2091 sky2_write32(hw, STAT_TX_TIMER_CNT, 0); 2092 sky2_write32(hw, STAT_ISR_TIMER_CNT, 0); 2093 sky2_read8(hw, STAT_ISR_TIMER_CTRL); 2094 2095 sky2_rx_stop(sky2); 2096 2097 spin_lock_bh(&sky2->phy_lock); 2098 sky2_phy_power_down(hw, port); 2099 spin_unlock_bh(&sky2->phy_lock); 2100 2101 sky2_tx_reset(hw, port); 2102 2103 /* Free any pending frames stuck in HW queue */ 2104 sky2_tx_complete(sky2, sky2->tx_prod); 2105 } 2106 2107 /* Network shutdown */ 2108 static int sky2_close(struct net_device *dev) 2109 { 2110 struct sky2_port *sky2 = netdev_priv(dev); 2111 struct sky2_hw *hw = sky2->hw; 2112 2113 /* Never really got started! */ 2114 if (!sky2->tx_le) 2115 return 0; 2116 2117 netif_info(sky2, ifdown, dev, "disabling interface\n"); 2118 2119 if (hw->ports == 1) { 2120 sky2_write32(hw, B0_IMSK, 0); 2121 sky2_read32(hw, B0_IMSK); 2122 2123 napi_disable(&hw->napi); 2124 free_irq(hw->pdev->irq, hw); 2125 hw->flags &= ~SKY2_HW_IRQ_SETUP; 2126 } else { 2127 u32 imask; 2128 2129 /* Disable port IRQ */ 2130 imask = sky2_read32(hw, B0_IMSK); 2131 imask &= ~portirq_msk[sky2->port]; 2132 sky2_write32(hw, B0_IMSK, imask); 2133 sky2_read32(hw, B0_IMSK); 2134 2135 synchronize_irq(hw->pdev->irq); 2136 napi_synchronize(&hw->napi); 2137 } 2138 2139 sky2_hw_down(sky2); 2140 2141 sky2_free_buffers(sky2); 2142 2143 return 0; 2144 } 2145 2146 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux) 2147 { 2148 if (hw->flags & SKY2_HW_FIBRE_PHY) 2149 return SPEED_1000; 2150 2151 if (!(hw->flags & SKY2_HW_GIGABIT)) { 2152 if (aux & PHY_M_PS_SPEED_100) 2153 return SPEED_100; 2154 else 2155 return SPEED_10; 2156 } 2157 2158 switch (aux & PHY_M_PS_SPEED_MSK) { 2159 case PHY_M_PS_SPEED_1000: 2160 return SPEED_1000; 2161 case PHY_M_PS_SPEED_100: 2162 return SPEED_100; 2163 default: 2164 return SPEED_10; 2165 } 2166 } 2167 2168 static void sky2_link_up(struct sky2_port *sky2) 2169 { 2170 struct sky2_hw *hw = sky2->hw; 2171 unsigned port = sky2->port; 2172 static const char *fc_name[] = { 2173 [FC_NONE] = "none", 2174 [FC_TX] = "tx", 2175 [FC_RX] = "rx", 2176 [FC_BOTH] = "both", 2177 }; 2178 2179 sky2_set_ipg(sky2); 2180 2181 sky2_enable_rx_tx(sky2); 2182 2183 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK); 2184 2185 netif_carrier_on(sky2->netdev); 2186 2187 mod_timer(&hw->watchdog_timer, jiffies + 1); 2188 2189 /* Turn on link LED */ 2190 sky2_write8(hw, SK_REG(port, LNK_LED_REG), 2191 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF); 2192 2193 netif_info(sky2, link, sky2->netdev, 2194 "Link is up at %d Mbps, %s duplex, flow control %s\n", 2195 sky2->speed, 2196 sky2->duplex == DUPLEX_FULL ? "full" : "half", 2197 fc_name[sky2->flow_status]); 2198 } 2199 2200 static void sky2_link_down(struct sky2_port *sky2) 2201 { 2202 struct sky2_hw *hw = sky2->hw; 2203 unsigned port = sky2->port; 2204 u16 reg; 2205 2206 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0); 2207 2208 reg = gma_read16(hw, port, GM_GP_CTRL); 2209 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); 2210 gma_write16(hw, port, GM_GP_CTRL, reg); 2211 2212 netif_carrier_off(sky2->netdev); 2213 2214 /* Turn off link LED */ 2215 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF); 2216 2217 netif_info(sky2, link, sky2->netdev, "Link is down\n"); 2218 2219 sky2_phy_init(hw, port); 2220 } 2221 2222 static enum flow_control sky2_flow(int rx, int tx) 2223 { 2224 if (rx) 2225 return tx ? FC_BOTH : FC_RX; 2226 else 2227 return tx ? FC_TX : FC_NONE; 2228 } 2229 2230 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux) 2231 { 2232 struct sky2_hw *hw = sky2->hw; 2233 unsigned port = sky2->port; 2234 u16 advert, lpa; 2235 2236 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV); 2237 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP); 2238 if (lpa & PHY_M_AN_RF) { 2239 netdev_err(sky2->netdev, "remote fault\n"); 2240 return -1; 2241 } 2242 2243 if (!(aux & PHY_M_PS_SPDUP_RES)) { 2244 netdev_err(sky2->netdev, "speed/duplex mismatch\n"); 2245 return -1; 2246 } 2247 2248 sky2->speed = sky2_phy_speed(hw, aux); 2249 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF; 2250 2251 /* Since the pause result bits seem to in different positions on 2252 * different chips. look at registers. 2253 */ 2254 if (hw->flags & SKY2_HW_FIBRE_PHY) { 2255 /* Shift for bits in fiber PHY */ 2256 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM); 2257 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM); 2258 2259 if (advert & ADVERTISE_1000XPAUSE) 2260 advert |= ADVERTISE_PAUSE_CAP; 2261 if (advert & ADVERTISE_1000XPSE_ASYM) 2262 advert |= ADVERTISE_PAUSE_ASYM; 2263 if (lpa & LPA_1000XPAUSE) 2264 lpa |= LPA_PAUSE_CAP; 2265 if (lpa & LPA_1000XPAUSE_ASYM) 2266 lpa |= LPA_PAUSE_ASYM; 2267 } 2268 2269 sky2->flow_status = FC_NONE; 2270 if (advert & ADVERTISE_PAUSE_CAP) { 2271 if (lpa & LPA_PAUSE_CAP) 2272 sky2->flow_status = FC_BOTH; 2273 else if (advert & ADVERTISE_PAUSE_ASYM) 2274 sky2->flow_status = FC_RX; 2275 } else if (advert & ADVERTISE_PAUSE_ASYM) { 2276 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM)) 2277 sky2->flow_status = FC_TX; 2278 } 2279 2280 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000 && 2281 !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX)) 2282 sky2->flow_status = FC_NONE; 2283 2284 if (sky2->flow_status & FC_TX) 2285 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON); 2286 else 2287 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); 2288 2289 return 0; 2290 } 2291 2292 /* Interrupt from PHY */ 2293 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port) 2294 { 2295 struct net_device *dev = hw->dev[port]; 2296 struct sky2_port *sky2 = netdev_priv(dev); 2297 u16 istatus, phystat; 2298 2299 if (!netif_running(dev)) 2300 return; 2301 2302 spin_lock(&sky2->phy_lock); 2303 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT); 2304 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT); 2305 2306 netif_info(sky2, intr, sky2->netdev, "phy interrupt status 0x%x 0x%x\n", 2307 istatus, phystat); 2308 2309 if (istatus & PHY_M_IS_AN_COMPL) { 2310 if (sky2_autoneg_done(sky2, phystat) == 0 && 2311 !netif_carrier_ok(dev)) 2312 sky2_link_up(sky2); 2313 goto out; 2314 } 2315 2316 if (istatus & PHY_M_IS_LSP_CHANGE) 2317 sky2->speed = sky2_phy_speed(hw, phystat); 2318 2319 if (istatus & PHY_M_IS_DUP_CHANGE) 2320 sky2->duplex = 2321 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF; 2322 2323 if (istatus & PHY_M_IS_LST_CHANGE) { 2324 if (phystat & PHY_M_PS_LINK_UP) 2325 sky2_link_up(sky2); 2326 else 2327 sky2_link_down(sky2); 2328 } 2329 out: 2330 spin_unlock(&sky2->phy_lock); 2331 } 2332 2333 /* Special quick link interrupt (Yukon-2 Optima only) */ 2334 static void sky2_qlink_intr(struct sky2_hw *hw) 2335 { 2336 struct sky2_port *sky2 = netdev_priv(hw->dev[0]); 2337 u32 imask; 2338 u16 phy; 2339 2340 /* disable irq */ 2341 imask = sky2_read32(hw, B0_IMSK); 2342 imask &= ~Y2_IS_PHY_QLNK; 2343 sky2_write32(hw, B0_IMSK, imask); 2344 2345 /* reset PHY Link Detect */ 2346 phy = sky2_pci_read16(hw, PSM_CONFIG_REG4); 2347 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); 2348 sky2_pci_write16(hw, PSM_CONFIG_REG4, phy | 1); 2349 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 2350 2351 sky2_link_up(sky2); 2352 } 2353 2354 /* Transmit timeout is only called if we are running, carrier is up 2355 * and tx queue is full (stopped). 2356 */ 2357 static void sky2_tx_timeout(struct net_device *dev) 2358 { 2359 struct sky2_port *sky2 = netdev_priv(dev); 2360 struct sky2_hw *hw = sky2->hw; 2361 2362 netif_err(sky2, timer, dev, "tx timeout\n"); 2363 2364 netdev_printk(KERN_DEBUG, dev, "transmit ring %u .. %u report=%u done=%u\n", 2365 sky2->tx_cons, sky2->tx_prod, 2366 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX), 2367 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE))); 2368 2369 /* can't restart safely under softirq */ 2370 schedule_work(&hw->restart_work); 2371 } 2372 2373 static int sky2_change_mtu(struct net_device *dev, int new_mtu) 2374 { 2375 struct sky2_port *sky2 = netdev_priv(dev); 2376 struct sky2_hw *hw = sky2->hw; 2377 unsigned port = sky2->port; 2378 int err; 2379 u16 ctl, mode; 2380 u32 imask; 2381 2382 /* MTU size outside the spec */ 2383 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU) 2384 return -EINVAL; 2385 2386 /* MTU > 1500 on yukon FE and FE+ not allowed */ 2387 if (new_mtu > ETH_DATA_LEN && 2388 (hw->chip_id == CHIP_ID_YUKON_FE || 2389 hw->chip_id == CHIP_ID_YUKON_FE_P)) 2390 return -EINVAL; 2391 2392 if (!netif_running(dev)) { 2393 dev->mtu = new_mtu; 2394 netdev_update_features(dev); 2395 return 0; 2396 } 2397 2398 imask = sky2_read32(hw, B0_IMSK); 2399 sky2_write32(hw, B0_IMSK, 0); 2400 2401 dev->trans_start = jiffies; /* prevent tx timeout */ 2402 napi_disable(&hw->napi); 2403 netif_tx_disable(dev); 2404 2405 synchronize_irq(hw->pdev->irq); 2406 2407 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) 2408 sky2_set_tx_stfwd(hw, port); 2409 2410 ctl = gma_read16(hw, port, GM_GP_CTRL); 2411 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA); 2412 sky2_rx_stop(sky2); 2413 sky2_rx_clean(sky2); 2414 2415 dev->mtu = new_mtu; 2416 netdev_update_features(dev); 2417 2418 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) | GM_SMOD_VLAN_ENA; 2419 if (sky2->speed > SPEED_100) 2420 mode |= IPG_DATA_VAL(IPG_DATA_DEF_1000); 2421 else 2422 mode |= IPG_DATA_VAL(IPG_DATA_DEF_10_100); 2423 2424 if (dev->mtu > ETH_DATA_LEN) 2425 mode |= GM_SMOD_JUMBO_ENA; 2426 2427 gma_write16(hw, port, GM_SERIAL_MODE, mode); 2428 2429 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD); 2430 2431 err = sky2_alloc_rx_skbs(sky2); 2432 if (!err) 2433 sky2_rx_start(sky2); 2434 else 2435 sky2_rx_clean(sky2); 2436 sky2_write32(hw, B0_IMSK, imask); 2437 2438 sky2_read32(hw, B0_Y2_SP_LISR); 2439 napi_enable(&hw->napi); 2440 2441 if (err) 2442 dev_close(dev); 2443 else { 2444 gma_write16(hw, port, GM_GP_CTRL, ctl); 2445 2446 netif_wake_queue(dev); 2447 } 2448 2449 return err; 2450 } 2451 2452 /* For small just reuse existing skb for next receive */ 2453 static struct sk_buff *receive_copy(struct sky2_port *sky2, 2454 const struct rx_ring_info *re, 2455 unsigned length) 2456 { 2457 struct sk_buff *skb; 2458 2459 skb = netdev_alloc_skb_ip_align(sky2->netdev, length); 2460 if (likely(skb)) { 2461 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr, 2462 length, PCI_DMA_FROMDEVICE); 2463 skb_copy_from_linear_data(re->skb, skb->data, length); 2464 skb->ip_summed = re->skb->ip_summed; 2465 skb->csum = re->skb->csum; 2466 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr, 2467 length, PCI_DMA_FROMDEVICE); 2468 re->skb->ip_summed = CHECKSUM_NONE; 2469 skb_put(skb, length); 2470 } 2471 return skb; 2472 } 2473 2474 /* Adjust length of skb with fragments to match received data */ 2475 static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space, 2476 unsigned int length) 2477 { 2478 int i, num_frags; 2479 unsigned int size; 2480 2481 /* put header into skb */ 2482 size = min(length, hdr_space); 2483 skb->tail += size; 2484 skb->len += size; 2485 length -= size; 2486 2487 num_frags = skb_shinfo(skb)->nr_frags; 2488 for (i = 0; i < num_frags; i++) { 2489 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 2490 2491 if (length == 0) { 2492 /* don't need this page */ 2493 __skb_frag_unref(frag); 2494 --skb_shinfo(skb)->nr_frags; 2495 } else { 2496 size = min(length, (unsigned) PAGE_SIZE); 2497 2498 skb_frag_size_set(frag, size); 2499 skb->data_len += size; 2500 skb->truesize += PAGE_SIZE; 2501 skb->len += size; 2502 length -= size; 2503 } 2504 } 2505 } 2506 2507 /* Normal packet - take skb from ring element and put in a new one */ 2508 static struct sk_buff *receive_new(struct sky2_port *sky2, 2509 struct rx_ring_info *re, 2510 unsigned int length) 2511 { 2512 struct sk_buff *skb; 2513 struct rx_ring_info nre; 2514 unsigned hdr_space = sky2->rx_data_size; 2515 2516 nre.skb = sky2_rx_alloc(sky2, GFP_ATOMIC); 2517 if (unlikely(!nre.skb)) 2518 goto nobuf; 2519 2520 if (sky2_rx_map_skb(sky2->hw->pdev, &nre, hdr_space)) 2521 goto nomap; 2522 2523 skb = re->skb; 2524 sky2_rx_unmap_skb(sky2->hw->pdev, re); 2525 prefetch(skb->data); 2526 *re = nre; 2527 2528 if (skb_shinfo(skb)->nr_frags) 2529 skb_put_frags(skb, hdr_space, length); 2530 else 2531 skb_put(skb, length); 2532 return skb; 2533 2534 nomap: 2535 dev_kfree_skb(nre.skb); 2536 nobuf: 2537 return NULL; 2538 } 2539 2540 /* 2541 * Receive one packet. 2542 * For larger packets, get new buffer. 2543 */ 2544 static struct sk_buff *sky2_receive(struct net_device *dev, 2545 u16 length, u32 status) 2546 { 2547 struct sky2_port *sky2 = netdev_priv(dev); 2548 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next; 2549 struct sk_buff *skb = NULL; 2550 u16 count = (status & GMR_FS_LEN) >> 16; 2551 2552 if (status & GMR_FS_VLAN) 2553 count -= VLAN_HLEN; /* Account for vlan tag */ 2554 2555 netif_printk(sky2, rx_status, KERN_DEBUG, dev, 2556 "rx slot %u status 0x%x len %d\n", 2557 sky2->rx_next, status, length); 2558 2559 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending; 2560 prefetch(sky2->rx_ring + sky2->rx_next); 2561 2562 /* This chip has hardware problems that generates bogus status. 2563 * So do only marginal checking and expect higher level protocols 2564 * to handle crap frames. 2565 */ 2566 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P && 2567 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 && 2568 length != count) 2569 goto okay; 2570 2571 if (status & GMR_FS_ANY_ERR) 2572 goto error; 2573 2574 if (!(status & GMR_FS_RX_OK)) 2575 goto resubmit; 2576 2577 /* if length reported by DMA does not match PHY, packet was truncated */ 2578 if (length != count) 2579 goto error; 2580 2581 okay: 2582 if (length < copybreak) 2583 skb = receive_copy(sky2, re, length); 2584 else 2585 skb = receive_new(sky2, re, length); 2586 2587 dev->stats.rx_dropped += (skb == NULL); 2588 2589 resubmit: 2590 sky2_rx_submit(sky2, re); 2591 2592 return skb; 2593 2594 error: 2595 ++dev->stats.rx_errors; 2596 2597 if (net_ratelimit()) 2598 netif_info(sky2, rx_err, dev, 2599 "rx error, status 0x%x length %d\n", status, length); 2600 2601 goto resubmit; 2602 } 2603 2604 /* Transmit complete */ 2605 static inline void sky2_tx_done(struct net_device *dev, u16 last) 2606 { 2607 struct sky2_port *sky2 = netdev_priv(dev); 2608 2609 if (netif_running(dev)) { 2610 sky2_tx_complete(sky2, last); 2611 2612 /* Wake unless it's detached, and called e.g. from sky2_close() */ 2613 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4) 2614 netif_wake_queue(dev); 2615 } 2616 } 2617 2618 static inline void sky2_skb_rx(const struct sky2_port *sky2, 2619 u32 status, struct sk_buff *skb) 2620 { 2621 if (status & GMR_FS_VLAN) 2622 __vlan_hwaccel_put_tag(skb, be16_to_cpu(sky2->rx_tag)); 2623 2624 if (skb->ip_summed == CHECKSUM_NONE) 2625 netif_receive_skb(skb); 2626 else 2627 napi_gro_receive(&sky2->hw->napi, skb); 2628 } 2629 2630 static inline void sky2_rx_done(struct sky2_hw *hw, unsigned port, 2631 unsigned packets, unsigned bytes) 2632 { 2633 struct net_device *dev = hw->dev[port]; 2634 struct sky2_port *sky2 = netdev_priv(dev); 2635 2636 if (packets == 0) 2637 return; 2638 2639 u64_stats_update_begin(&sky2->rx_stats.syncp); 2640 sky2->rx_stats.packets += packets; 2641 sky2->rx_stats.bytes += bytes; 2642 u64_stats_update_end(&sky2->rx_stats.syncp); 2643 2644 dev->last_rx = jiffies; 2645 sky2_rx_update(netdev_priv(dev), rxqaddr[port]); 2646 } 2647 2648 static void sky2_rx_checksum(struct sky2_port *sky2, u32 status) 2649 { 2650 /* If this happens then driver assuming wrong format for chip type */ 2651 BUG_ON(sky2->hw->flags & SKY2_HW_NEW_LE); 2652 2653 /* Both checksum counters are programmed to start at 2654 * the same offset, so unless there is a problem they 2655 * should match. This failure is an early indication that 2656 * hardware receive checksumming won't work. 2657 */ 2658 if (likely((u16)(status >> 16) == (u16)status)) { 2659 struct sk_buff *skb = sky2->rx_ring[sky2->rx_next].skb; 2660 skb->ip_summed = CHECKSUM_COMPLETE; 2661 skb->csum = le16_to_cpu(status); 2662 } else { 2663 dev_notice(&sky2->hw->pdev->dev, 2664 "%s: receive checksum problem (status = %#x)\n", 2665 sky2->netdev->name, status); 2666 2667 /* Disable checksum offload 2668 * It will be reenabled on next ndo_set_features, but if it's 2669 * really broken, will get disabled again 2670 */ 2671 sky2->netdev->features &= ~NETIF_F_RXCSUM; 2672 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR), 2673 BMU_DIS_RX_CHKSUM); 2674 } 2675 } 2676 2677 static void sky2_rx_hash(struct sky2_port *sky2, u32 status) 2678 { 2679 struct sk_buff *skb; 2680 2681 skb = sky2->rx_ring[sky2->rx_next].skb; 2682 skb->rxhash = le32_to_cpu(status); 2683 } 2684 2685 /* Process status response ring */ 2686 static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx) 2687 { 2688 int work_done = 0; 2689 unsigned int total_bytes[2] = { 0 }; 2690 unsigned int total_packets[2] = { 0 }; 2691 2692 rmb(); 2693 do { 2694 struct sky2_port *sky2; 2695 struct sky2_status_le *le = hw->st_le + hw->st_idx; 2696 unsigned port; 2697 struct net_device *dev; 2698 struct sk_buff *skb; 2699 u32 status; 2700 u16 length; 2701 u8 opcode = le->opcode; 2702 2703 if (!(opcode & HW_OWNER)) 2704 break; 2705 2706 hw->st_idx = RING_NEXT(hw->st_idx, hw->st_size); 2707 2708 port = le->css & CSS_LINK_BIT; 2709 dev = hw->dev[port]; 2710 sky2 = netdev_priv(dev); 2711 length = le16_to_cpu(le->length); 2712 status = le32_to_cpu(le->status); 2713 2714 le->opcode = 0; 2715 switch (opcode & ~HW_OWNER) { 2716 case OP_RXSTAT: 2717 total_packets[port]++; 2718 total_bytes[port] += length; 2719 2720 skb = sky2_receive(dev, length, status); 2721 if (!skb) 2722 break; 2723 2724 /* This chip reports checksum status differently */ 2725 if (hw->flags & SKY2_HW_NEW_LE) { 2726 if ((dev->features & NETIF_F_RXCSUM) && 2727 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) && 2728 (le->css & CSS_TCPUDPCSOK)) 2729 skb->ip_summed = CHECKSUM_UNNECESSARY; 2730 else 2731 skb->ip_summed = CHECKSUM_NONE; 2732 } 2733 2734 skb->protocol = eth_type_trans(skb, dev); 2735 2736 sky2_skb_rx(sky2, status, skb); 2737 2738 /* Stop after net poll weight */ 2739 if (++work_done >= to_do) 2740 goto exit_loop; 2741 break; 2742 2743 case OP_RXVLAN: 2744 sky2->rx_tag = length; 2745 break; 2746 2747 case OP_RXCHKSVLAN: 2748 sky2->rx_tag = length; 2749 /* fall through */ 2750 case OP_RXCHKS: 2751 if (likely(dev->features & NETIF_F_RXCSUM)) 2752 sky2_rx_checksum(sky2, status); 2753 break; 2754 2755 case OP_RSS_HASH: 2756 sky2_rx_hash(sky2, status); 2757 break; 2758 2759 case OP_TXINDEXLE: 2760 /* TX index reports status for both ports */ 2761 sky2_tx_done(hw->dev[0], status & 0xfff); 2762 if (hw->dev[1]) 2763 sky2_tx_done(hw->dev[1], 2764 ((status >> 24) & 0xff) 2765 | (u16)(length & 0xf) << 8); 2766 break; 2767 2768 default: 2769 if (net_ratelimit()) 2770 pr_warning("unknown status opcode 0x%x\n", opcode); 2771 } 2772 } while (hw->st_idx != idx); 2773 2774 /* Fully processed status ring so clear irq */ 2775 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ); 2776 2777 exit_loop: 2778 sky2_rx_done(hw, 0, total_packets[0], total_bytes[0]); 2779 sky2_rx_done(hw, 1, total_packets[1], total_bytes[1]); 2780 2781 return work_done; 2782 } 2783 2784 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status) 2785 { 2786 struct net_device *dev = hw->dev[port]; 2787 2788 if (net_ratelimit()) 2789 netdev_info(dev, "hw error interrupt status 0x%x\n", status); 2790 2791 if (status & Y2_IS_PAR_RD1) { 2792 if (net_ratelimit()) 2793 netdev_err(dev, "ram data read parity error\n"); 2794 /* Clear IRQ */ 2795 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR); 2796 } 2797 2798 if (status & Y2_IS_PAR_WR1) { 2799 if (net_ratelimit()) 2800 netdev_err(dev, "ram data write parity error\n"); 2801 2802 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR); 2803 } 2804 2805 if (status & Y2_IS_PAR_MAC1) { 2806 if (net_ratelimit()) 2807 netdev_err(dev, "MAC parity error\n"); 2808 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE); 2809 } 2810 2811 if (status & Y2_IS_PAR_RX1) { 2812 if (net_ratelimit()) 2813 netdev_err(dev, "RX parity error\n"); 2814 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR); 2815 } 2816 2817 if (status & Y2_IS_TCP_TXA1) { 2818 if (net_ratelimit()) 2819 netdev_err(dev, "TCP segmentation error\n"); 2820 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP); 2821 } 2822 } 2823 2824 static void sky2_hw_intr(struct sky2_hw *hw) 2825 { 2826 struct pci_dev *pdev = hw->pdev; 2827 u32 status = sky2_read32(hw, B0_HWE_ISRC); 2828 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK); 2829 2830 status &= hwmsk; 2831 2832 if (status & Y2_IS_TIST_OV) 2833 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); 2834 2835 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) { 2836 u16 pci_err; 2837 2838 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); 2839 pci_err = sky2_pci_read16(hw, PCI_STATUS); 2840 if (net_ratelimit()) 2841 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n", 2842 pci_err); 2843 2844 sky2_pci_write16(hw, PCI_STATUS, 2845 pci_err | PCI_STATUS_ERROR_BITS); 2846 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 2847 } 2848 2849 if (status & Y2_IS_PCI_EXP) { 2850 /* PCI-Express uncorrectable Error occurred */ 2851 u32 err; 2852 2853 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); 2854 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS); 2855 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS, 2856 0xfffffffful); 2857 if (net_ratelimit()) 2858 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err); 2859 2860 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS); 2861 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 2862 } 2863 2864 if (status & Y2_HWE_L1_MASK) 2865 sky2_hw_error(hw, 0, status); 2866 status >>= 8; 2867 if (status & Y2_HWE_L1_MASK) 2868 sky2_hw_error(hw, 1, status); 2869 } 2870 2871 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port) 2872 { 2873 struct net_device *dev = hw->dev[port]; 2874 struct sky2_port *sky2 = netdev_priv(dev); 2875 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC)); 2876 2877 netif_info(sky2, intr, dev, "mac interrupt status 0x%x\n", status); 2878 2879 if (status & GM_IS_RX_CO_OV) 2880 gma_read16(hw, port, GM_RX_IRQ_SRC); 2881 2882 if (status & GM_IS_TX_CO_OV) 2883 gma_read16(hw, port, GM_TX_IRQ_SRC); 2884 2885 if (status & GM_IS_RX_FF_OR) { 2886 ++dev->stats.rx_fifo_errors; 2887 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO); 2888 } 2889 2890 if (status & GM_IS_TX_FF_UR) { 2891 ++dev->stats.tx_fifo_errors; 2892 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU); 2893 } 2894 } 2895 2896 /* This should never happen it is a bug. */ 2897 static void sky2_le_error(struct sky2_hw *hw, unsigned port, u16 q) 2898 { 2899 struct net_device *dev = hw->dev[port]; 2900 u16 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX)); 2901 2902 dev_err(&hw->pdev->dev, "%s: descriptor error q=%#x get=%u put=%u\n", 2903 dev->name, (unsigned) q, (unsigned) idx, 2904 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX))); 2905 2906 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK); 2907 } 2908 2909 static int sky2_rx_hung(struct net_device *dev) 2910 { 2911 struct sky2_port *sky2 = netdev_priv(dev); 2912 struct sky2_hw *hw = sky2->hw; 2913 unsigned port = sky2->port; 2914 unsigned rxq = rxqaddr[port]; 2915 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP)); 2916 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV)); 2917 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP)); 2918 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL)); 2919 2920 /* If idle and MAC or PCI is stuck */ 2921 if (sky2->check.last == dev->last_rx && 2922 ((mac_rp == sky2->check.mac_rp && 2923 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) || 2924 /* Check if the PCI RX hang */ 2925 (fifo_rp == sky2->check.fifo_rp && 2926 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) { 2927 netdev_printk(KERN_DEBUG, dev, 2928 "hung mac %d:%d fifo %d (%d:%d)\n", 2929 mac_lev, mac_rp, fifo_lev, 2930 fifo_rp, sky2_read8(hw, Q_ADDR(rxq, Q_WP))); 2931 return 1; 2932 } else { 2933 sky2->check.last = dev->last_rx; 2934 sky2->check.mac_rp = mac_rp; 2935 sky2->check.mac_lev = mac_lev; 2936 sky2->check.fifo_rp = fifo_rp; 2937 sky2->check.fifo_lev = fifo_lev; 2938 return 0; 2939 } 2940 } 2941 2942 static void sky2_watchdog(unsigned long arg) 2943 { 2944 struct sky2_hw *hw = (struct sky2_hw *) arg; 2945 2946 /* Check for lost IRQ once a second */ 2947 if (sky2_read32(hw, B0_ISRC)) { 2948 napi_schedule(&hw->napi); 2949 } else { 2950 int i, active = 0; 2951 2952 for (i = 0; i < hw->ports; i++) { 2953 struct net_device *dev = hw->dev[i]; 2954 if (!netif_running(dev)) 2955 continue; 2956 ++active; 2957 2958 /* For chips with Rx FIFO, check if stuck */ 2959 if ((hw->flags & SKY2_HW_RAM_BUFFER) && 2960 sky2_rx_hung(dev)) { 2961 netdev_info(dev, "receiver hang detected\n"); 2962 schedule_work(&hw->restart_work); 2963 return; 2964 } 2965 } 2966 2967 if (active == 0) 2968 return; 2969 } 2970 2971 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ)); 2972 } 2973 2974 /* Hardware/software error handling */ 2975 static void sky2_err_intr(struct sky2_hw *hw, u32 status) 2976 { 2977 if (net_ratelimit()) 2978 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status); 2979 2980 if (status & Y2_IS_HW_ERR) 2981 sky2_hw_intr(hw); 2982 2983 if (status & Y2_IS_IRQ_MAC1) 2984 sky2_mac_intr(hw, 0); 2985 2986 if (status & Y2_IS_IRQ_MAC2) 2987 sky2_mac_intr(hw, 1); 2988 2989 if (status & Y2_IS_CHK_RX1) 2990 sky2_le_error(hw, 0, Q_R1); 2991 2992 if (status & Y2_IS_CHK_RX2) 2993 sky2_le_error(hw, 1, Q_R2); 2994 2995 if (status & Y2_IS_CHK_TXA1) 2996 sky2_le_error(hw, 0, Q_XA1); 2997 2998 if (status & Y2_IS_CHK_TXA2) 2999 sky2_le_error(hw, 1, Q_XA2); 3000 } 3001 3002 static int sky2_poll(struct napi_struct *napi, int work_limit) 3003 { 3004 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi); 3005 u32 status = sky2_read32(hw, B0_Y2_SP_EISR); 3006 int work_done = 0; 3007 u16 idx; 3008 3009 if (unlikely(status & Y2_IS_ERROR)) 3010 sky2_err_intr(hw, status); 3011 3012 if (status & Y2_IS_IRQ_PHY1) 3013 sky2_phy_intr(hw, 0); 3014 3015 if (status & Y2_IS_IRQ_PHY2) 3016 sky2_phy_intr(hw, 1); 3017 3018 if (status & Y2_IS_PHY_QLNK) 3019 sky2_qlink_intr(hw); 3020 3021 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) { 3022 work_done += sky2_status_intr(hw, work_limit - work_done, idx); 3023 3024 if (work_done >= work_limit) 3025 goto done; 3026 } 3027 3028 napi_complete(napi); 3029 sky2_read32(hw, B0_Y2_SP_LISR); 3030 done: 3031 3032 return work_done; 3033 } 3034 3035 static irqreturn_t sky2_intr(int irq, void *dev_id) 3036 { 3037 struct sky2_hw *hw = dev_id; 3038 u32 status; 3039 3040 /* Reading this mask interrupts as side effect */ 3041 status = sky2_read32(hw, B0_Y2_SP_ISRC2); 3042 if (status == 0 || status == ~0) 3043 return IRQ_NONE; 3044 3045 prefetch(&hw->st_le[hw->st_idx]); 3046 3047 napi_schedule(&hw->napi); 3048 3049 return IRQ_HANDLED; 3050 } 3051 3052 #ifdef CONFIG_NET_POLL_CONTROLLER 3053 static void sky2_netpoll(struct net_device *dev) 3054 { 3055 struct sky2_port *sky2 = netdev_priv(dev); 3056 3057 napi_schedule(&sky2->hw->napi); 3058 } 3059 #endif 3060 3061 /* Chip internal frequency for clock calculations */ 3062 static u32 sky2_mhz(const struct sky2_hw *hw) 3063 { 3064 switch (hw->chip_id) { 3065 case CHIP_ID_YUKON_EC: 3066 case CHIP_ID_YUKON_EC_U: 3067 case CHIP_ID_YUKON_EX: 3068 case CHIP_ID_YUKON_SUPR: 3069 case CHIP_ID_YUKON_UL_2: 3070 case CHIP_ID_YUKON_OPT: 3071 case CHIP_ID_YUKON_PRM: 3072 case CHIP_ID_YUKON_OP_2: 3073 return 125; 3074 3075 case CHIP_ID_YUKON_FE: 3076 return 100; 3077 3078 case CHIP_ID_YUKON_FE_P: 3079 return 50; 3080 3081 case CHIP_ID_YUKON_XL: 3082 return 156; 3083 3084 default: 3085 BUG(); 3086 } 3087 } 3088 3089 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us) 3090 { 3091 return sky2_mhz(hw) * us; 3092 } 3093 3094 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk) 3095 { 3096 return clk / sky2_mhz(hw); 3097 } 3098 3099 3100 static int __devinit sky2_init(struct sky2_hw *hw) 3101 { 3102 u8 t8; 3103 3104 /* Enable all clocks and check for bad PCI access */ 3105 sky2_pci_write32(hw, PCI_DEV_REG3, 0); 3106 3107 sky2_write8(hw, B0_CTST, CS_RST_CLR); 3108 3109 hw->chip_id = sky2_read8(hw, B2_CHIP_ID); 3110 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4; 3111 3112 switch (hw->chip_id) { 3113 case CHIP_ID_YUKON_XL: 3114 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY; 3115 if (hw->chip_rev < CHIP_REV_YU_XL_A2) 3116 hw->flags |= SKY2_HW_RSS_BROKEN; 3117 break; 3118 3119 case CHIP_ID_YUKON_EC_U: 3120 hw->flags = SKY2_HW_GIGABIT 3121 | SKY2_HW_NEWER_PHY 3122 | SKY2_HW_ADV_POWER_CTL; 3123 break; 3124 3125 case CHIP_ID_YUKON_EX: 3126 hw->flags = SKY2_HW_GIGABIT 3127 | SKY2_HW_NEWER_PHY 3128 | SKY2_HW_NEW_LE 3129 | SKY2_HW_ADV_POWER_CTL 3130 | SKY2_HW_RSS_CHKSUM; 3131 3132 /* New transmit checksum */ 3133 if (hw->chip_rev != CHIP_REV_YU_EX_B0) 3134 hw->flags |= SKY2_HW_AUTO_TX_SUM; 3135 break; 3136 3137 case CHIP_ID_YUKON_EC: 3138 /* This rev is really old, and requires untested workarounds */ 3139 if (hw->chip_rev == CHIP_REV_YU_EC_A1) { 3140 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n"); 3141 return -EOPNOTSUPP; 3142 } 3143 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_RSS_BROKEN; 3144 break; 3145 3146 case CHIP_ID_YUKON_FE: 3147 hw->flags = SKY2_HW_RSS_BROKEN; 3148 break; 3149 3150 case CHIP_ID_YUKON_FE_P: 3151 hw->flags = SKY2_HW_NEWER_PHY 3152 | SKY2_HW_NEW_LE 3153 | SKY2_HW_AUTO_TX_SUM 3154 | SKY2_HW_ADV_POWER_CTL; 3155 3156 /* The workaround for status conflicts VLAN tag detection. */ 3157 if (hw->chip_rev == CHIP_REV_YU_FE2_A0) 3158 hw->flags |= SKY2_HW_VLAN_BROKEN | SKY2_HW_RSS_CHKSUM; 3159 break; 3160 3161 case CHIP_ID_YUKON_SUPR: 3162 hw->flags = SKY2_HW_GIGABIT 3163 | SKY2_HW_NEWER_PHY 3164 | SKY2_HW_NEW_LE 3165 | SKY2_HW_AUTO_TX_SUM 3166 | SKY2_HW_ADV_POWER_CTL; 3167 3168 if (hw->chip_rev == CHIP_REV_YU_SU_A0) 3169 hw->flags |= SKY2_HW_RSS_CHKSUM; 3170 break; 3171 3172 case CHIP_ID_YUKON_UL_2: 3173 hw->flags = SKY2_HW_GIGABIT 3174 | SKY2_HW_ADV_POWER_CTL; 3175 break; 3176 3177 case CHIP_ID_YUKON_OPT: 3178 case CHIP_ID_YUKON_PRM: 3179 case CHIP_ID_YUKON_OP_2: 3180 hw->flags = SKY2_HW_GIGABIT 3181 | SKY2_HW_NEW_LE 3182 | SKY2_HW_ADV_POWER_CTL; 3183 break; 3184 3185 default: 3186 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n", 3187 hw->chip_id); 3188 return -EOPNOTSUPP; 3189 } 3190 3191 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP); 3192 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P') 3193 hw->flags |= SKY2_HW_FIBRE_PHY; 3194 3195 hw->ports = 1; 3196 t8 = sky2_read8(hw, B2_Y2_HW_RES); 3197 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) { 3198 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC)) 3199 ++hw->ports; 3200 } 3201 3202 if (sky2_read8(hw, B2_E_0)) 3203 hw->flags |= SKY2_HW_RAM_BUFFER; 3204 3205 return 0; 3206 } 3207 3208 static void sky2_reset(struct sky2_hw *hw) 3209 { 3210 struct pci_dev *pdev = hw->pdev; 3211 u16 status; 3212 int i; 3213 u32 hwe_mask = Y2_HWE_ALL_MASK; 3214 3215 /* disable ASF */ 3216 if (hw->chip_id == CHIP_ID_YUKON_EX 3217 || hw->chip_id == CHIP_ID_YUKON_SUPR) { 3218 sky2_write32(hw, CPU_WDOG, 0); 3219 status = sky2_read16(hw, HCU_CCSR); 3220 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE | 3221 HCU_CCSR_UC_STATE_MSK); 3222 /* 3223 * CPU clock divider shouldn't be used because 3224 * - ASF firmware may malfunction 3225 * - Yukon-Supreme: Parallel FLASH doesn't support divided clocks 3226 */ 3227 status &= ~HCU_CCSR_CPU_CLK_DIVIDE_MSK; 3228 sky2_write16(hw, HCU_CCSR, status); 3229 sky2_write32(hw, CPU_WDOG, 0); 3230 } else 3231 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET); 3232 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE); 3233 3234 /* do a SW reset */ 3235 sky2_write8(hw, B0_CTST, CS_RST_SET); 3236 sky2_write8(hw, B0_CTST, CS_RST_CLR); 3237 3238 /* allow writes to PCI config */ 3239 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); 3240 3241 /* clear PCI errors, if any */ 3242 status = sky2_pci_read16(hw, PCI_STATUS); 3243 status |= PCI_STATUS_ERROR_BITS; 3244 sky2_pci_write16(hw, PCI_STATUS, status); 3245 3246 sky2_write8(hw, B0_CTST, CS_MRST_CLR); 3247 3248 if (pci_is_pcie(pdev)) { 3249 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS, 3250 0xfffffffful); 3251 3252 /* If error bit is stuck on ignore it */ 3253 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP) 3254 dev_info(&pdev->dev, "ignoring stuck error report bit\n"); 3255 else 3256 hwe_mask |= Y2_IS_PCI_EXP; 3257 } 3258 3259 sky2_power_on(hw); 3260 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 3261 3262 for (i = 0; i < hw->ports; i++) { 3263 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET); 3264 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR); 3265 3266 if (hw->chip_id == CHIP_ID_YUKON_EX || 3267 hw->chip_id == CHIP_ID_YUKON_SUPR) 3268 sky2_write16(hw, SK_REG(i, GMAC_CTRL), 3269 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON 3270 | GMC_BYP_RETR_ON); 3271 3272 } 3273 3274 if (hw->chip_id == CHIP_ID_YUKON_SUPR && hw->chip_rev > CHIP_REV_YU_SU_B0) { 3275 /* enable MACSec clock gating */ 3276 sky2_pci_write32(hw, PCI_DEV_REG3, P_CLK_MACSEC_DIS); 3277 } 3278 3279 if (hw->chip_id == CHIP_ID_YUKON_OPT || 3280 hw->chip_id == CHIP_ID_YUKON_PRM || 3281 hw->chip_id == CHIP_ID_YUKON_OP_2) { 3282 u16 reg; 3283 3284 if (hw->chip_id == CHIP_ID_YUKON_OPT && hw->chip_rev == 0) { 3285 /* disable PCI-E PHY power down (set PHY reg 0x80, bit 7 */ 3286 sky2_write32(hw, Y2_PEX_PHY_DATA, (0x80UL << 16) | (1 << 7)); 3287 3288 /* set PHY Link Detect Timer to 1.1 second (11x 100ms) */ 3289 reg = 10; 3290 3291 /* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */ 3292 sky2_write32(hw, Y2_PEX_PHY_DATA, PEX_DB_ACCESS | (0x08UL << 16)); 3293 } else { 3294 /* set PHY Link Detect Timer to 0.4 second (4x 100ms) */ 3295 reg = 3; 3296 } 3297 3298 reg <<= PSM_CONFIG_REG4_TIMER_PHY_LINK_DETECT_BASE; 3299 reg |= PSM_CONFIG_REG4_RST_PHY_LINK_DETECT; 3300 3301 /* reset PHY Link Detect */ 3302 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); 3303 sky2_pci_write16(hw, PSM_CONFIG_REG4, reg); 3304 3305 /* check if PSMv2 was running before */ 3306 reg = sky2_pci_read16(hw, PSM_CONFIG_REG3); 3307 if (reg & PCI_EXP_LNKCTL_ASPMC) 3308 /* restore the PCIe Link Control register */ 3309 sky2_pci_write16(hw, pdev->pcie_cap + PCI_EXP_LNKCTL, 3310 reg); 3311 3312 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 3313 3314 /* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */ 3315 sky2_write32(hw, Y2_PEX_PHY_DATA, PEX_DB_ACCESS | (0x08UL << 16)); 3316 } 3317 3318 /* Clear I2C IRQ noise */ 3319 sky2_write32(hw, B2_I2C_IRQ, 1); 3320 3321 /* turn off hardware timer (unused) */ 3322 sky2_write8(hw, B2_TI_CTRL, TIM_STOP); 3323 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ); 3324 3325 /* Turn off descriptor polling */ 3326 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP); 3327 3328 /* Turn off receive timestamp */ 3329 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP); 3330 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); 3331 3332 /* enable the Tx Arbiters */ 3333 for (i = 0; i < hw->ports; i++) 3334 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB); 3335 3336 /* Initialize ram interface */ 3337 for (i = 0; i < hw->ports; i++) { 3338 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR); 3339 3340 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53); 3341 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53); 3342 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53); 3343 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53); 3344 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53); 3345 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53); 3346 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53); 3347 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53); 3348 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53); 3349 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53); 3350 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53); 3351 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53); 3352 } 3353 3354 sky2_write32(hw, B0_HWE_IMSK, hwe_mask); 3355 3356 for (i = 0; i < hw->ports; i++) 3357 sky2_gmac_reset(hw, i); 3358 3359 memset(hw->st_le, 0, hw->st_size * sizeof(struct sky2_status_le)); 3360 hw->st_idx = 0; 3361 3362 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET); 3363 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR); 3364 3365 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma); 3366 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32); 3367 3368 /* Set the list last index */ 3369 sky2_write16(hw, STAT_LAST_IDX, hw->st_size - 1); 3370 3371 sky2_write16(hw, STAT_TX_IDX_TH, 10); 3372 sky2_write8(hw, STAT_FIFO_WM, 16); 3373 3374 /* set Status-FIFO ISR watermark */ 3375 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0) 3376 sky2_write8(hw, STAT_FIFO_ISR_WM, 4); 3377 else 3378 sky2_write8(hw, STAT_FIFO_ISR_WM, 16); 3379 3380 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000)); 3381 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20)); 3382 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100)); 3383 3384 /* enable status unit */ 3385 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON); 3386 3387 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START); 3388 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START); 3389 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START); 3390 } 3391 3392 /* Take device down (offline). 3393 * Equivalent to doing dev_stop() but this does not 3394 * inform upper layers of the transition. 3395 */ 3396 static void sky2_detach(struct net_device *dev) 3397 { 3398 if (netif_running(dev)) { 3399 netif_tx_lock(dev); 3400 netif_device_detach(dev); /* stop txq */ 3401 netif_tx_unlock(dev); 3402 sky2_close(dev); 3403 } 3404 } 3405 3406 /* Bring device back after doing sky2_detach */ 3407 static int sky2_reattach(struct net_device *dev) 3408 { 3409 int err = 0; 3410 3411 if (netif_running(dev)) { 3412 err = sky2_open(dev); 3413 if (err) { 3414 netdev_info(dev, "could not restart %d\n", err); 3415 dev_close(dev); 3416 } else { 3417 netif_device_attach(dev); 3418 sky2_set_multicast(dev); 3419 } 3420 } 3421 3422 return err; 3423 } 3424 3425 static void sky2_all_down(struct sky2_hw *hw) 3426 { 3427 int i; 3428 3429 if (hw->flags & SKY2_HW_IRQ_SETUP) { 3430 sky2_read32(hw, B0_IMSK); 3431 sky2_write32(hw, B0_IMSK, 0); 3432 3433 synchronize_irq(hw->pdev->irq); 3434 napi_disable(&hw->napi); 3435 } 3436 3437 for (i = 0; i < hw->ports; i++) { 3438 struct net_device *dev = hw->dev[i]; 3439 struct sky2_port *sky2 = netdev_priv(dev); 3440 3441 if (!netif_running(dev)) 3442 continue; 3443 3444 netif_carrier_off(dev); 3445 netif_tx_disable(dev); 3446 sky2_hw_down(sky2); 3447 } 3448 } 3449 3450 static void sky2_all_up(struct sky2_hw *hw) 3451 { 3452 u32 imask = Y2_IS_BASE; 3453 int i; 3454 3455 for (i = 0; i < hw->ports; i++) { 3456 struct net_device *dev = hw->dev[i]; 3457 struct sky2_port *sky2 = netdev_priv(dev); 3458 3459 if (!netif_running(dev)) 3460 continue; 3461 3462 sky2_hw_up(sky2); 3463 sky2_set_multicast(dev); 3464 imask |= portirq_msk[i]; 3465 netif_wake_queue(dev); 3466 } 3467 3468 if (hw->flags & SKY2_HW_IRQ_SETUP) { 3469 sky2_write32(hw, B0_IMSK, imask); 3470 sky2_read32(hw, B0_IMSK); 3471 sky2_read32(hw, B0_Y2_SP_LISR); 3472 napi_enable(&hw->napi); 3473 } 3474 } 3475 3476 static void sky2_restart(struct work_struct *work) 3477 { 3478 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work); 3479 3480 rtnl_lock(); 3481 3482 sky2_all_down(hw); 3483 sky2_reset(hw); 3484 sky2_all_up(hw); 3485 3486 rtnl_unlock(); 3487 } 3488 3489 static inline u8 sky2_wol_supported(const struct sky2_hw *hw) 3490 { 3491 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0; 3492 } 3493 3494 static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 3495 { 3496 const struct sky2_port *sky2 = netdev_priv(dev); 3497 3498 wol->supported = sky2_wol_supported(sky2->hw); 3499 wol->wolopts = sky2->wol; 3500 } 3501 3502 static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 3503 { 3504 struct sky2_port *sky2 = netdev_priv(dev); 3505 struct sky2_hw *hw = sky2->hw; 3506 bool enable_wakeup = false; 3507 int i; 3508 3509 if ((wol->wolopts & ~sky2_wol_supported(sky2->hw)) || 3510 !device_can_wakeup(&hw->pdev->dev)) 3511 return -EOPNOTSUPP; 3512 3513 sky2->wol = wol->wolopts; 3514 3515 for (i = 0; i < hw->ports; i++) { 3516 struct net_device *dev = hw->dev[i]; 3517 struct sky2_port *sky2 = netdev_priv(dev); 3518 3519 if (sky2->wol) 3520 enable_wakeup = true; 3521 } 3522 device_set_wakeup_enable(&hw->pdev->dev, enable_wakeup); 3523 3524 return 0; 3525 } 3526 3527 static u32 sky2_supported_modes(const struct sky2_hw *hw) 3528 { 3529 if (sky2_is_copper(hw)) { 3530 u32 modes = SUPPORTED_10baseT_Half 3531 | SUPPORTED_10baseT_Full 3532 | SUPPORTED_100baseT_Half 3533 | SUPPORTED_100baseT_Full; 3534 3535 if (hw->flags & SKY2_HW_GIGABIT) 3536 modes |= SUPPORTED_1000baseT_Half 3537 | SUPPORTED_1000baseT_Full; 3538 return modes; 3539 } else 3540 return SUPPORTED_1000baseT_Half 3541 | SUPPORTED_1000baseT_Full; 3542 } 3543 3544 static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd) 3545 { 3546 struct sky2_port *sky2 = netdev_priv(dev); 3547 struct sky2_hw *hw = sky2->hw; 3548 3549 ecmd->transceiver = XCVR_INTERNAL; 3550 ecmd->supported = sky2_supported_modes(hw); 3551 ecmd->phy_address = PHY_ADDR_MARV; 3552 if (sky2_is_copper(hw)) { 3553 ecmd->port = PORT_TP; 3554 ethtool_cmd_speed_set(ecmd, sky2->speed); 3555 ecmd->supported |= SUPPORTED_Autoneg | SUPPORTED_TP; 3556 } else { 3557 ethtool_cmd_speed_set(ecmd, SPEED_1000); 3558 ecmd->port = PORT_FIBRE; 3559 ecmd->supported |= SUPPORTED_Autoneg | SUPPORTED_FIBRE; 3560 } 3561 3562 ecmd->advertising = sky2->advertising; 3563 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_SPEED) 3564 ? AUTONEG_ENABLE : AUTONEG_DISABLE; 3565 ecmd->duplex = sky2->duplex; 3566 return 0; 3567 } 3568 3569 static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd) 3570 { 3571 struct sky2_port *sky2 = netdev_priv(dev); 3572 const struct sky2_hw *hw = sky2->hw; 3573 u32 supported = sky2_supported_modes(hw); 3574 3575 if (ecmd->autoneg == AUTONEG_ENABLE) { 3576 if (ecmd->advertising & ~supported) 3577 return -EINVAL; 3578 3579 if (sky2_is_copper(hw)) 3580 sky2->advertising = ecmd->advertising | 3581 ADVERTISED_TP | 3582 ADVERTISED_Autoneg; 3583 else 3584 sky2->advertising = ecmd->advertising | 3585 ADVERTISED_FIBRE | 3586 ADVERTISED_Autoneg; 3587 3588 sky2->flags |= SKY2_FLAG_AUTO_SPEED; 3589 sky2->duplex = -1; 3590 sky2->speed = -1; 3591 } else { 3592 u32 setting; 3593 u32 speed = ethtool_cmd_speed(ecmd); 3594 3595 switch (speed) { 3596 case SPEED_1000: 3597 if (ecmd->duplex == DUPLEX_FULL) 3598 setting = SUPPORTED_1000baseT_Full; 3599 else if (ecmd->duplex == DUPLEX_HALF) 3600 setting = SUPPORTED_1000baseT_Half; 3601 else 3602 return -EINVAL; 3603 break; 3604 case SPEED_100: 3605 if (ecmd->duplex == DUPLEX_FULL) 3606 setting = SUPPORTED_100baseT_Full; 3607 else if (ecmd->duplex == DUPLEX_HALF) 3608 setting = SUPPORTED_100baseT_Half; 3609 else 3610 return -EINVAL; 3611 break; 3612 3613 case SPEED_10: 3614 if (ecmd->duplex == DUPLEX_FULL) 3615 setting = SUPPORTED_10baseT_Full; 3616 else if (ecmd->duplex == DUPLEX_HALF) 3617 setting = SUPPORTED_10baseT_Half; 3618 else 3619 return -EINVAL; 3620 break; 3621 default: 3622 return -EINVAL; 3623 } 3624 3625 if ((setting & supported) == 0) 3626 return -EINVAL; 3627 3628 sky2->speed = speed; 3629 sky2->duplex = ecmd->duplex; 3630 sky2->flags &= ~SKY2_FLAG_AUTO_SPEED; 3631 } 3632 3633 if (netif_running(dev)) { 3634 sky2_phy_reinit(sky2); 3635 sky2_set_multicast(dev); 3636 } 3637 3638 return 0; 3639 } 3640 3641 static void sky2_get_drvinfo(struct net_device *dev, 3642 struct ethtool_drvinfo *info) 3643 { 3644 struct sky2_port *sky2 = netdev_priv(dev); 3645 3646 strcpy(info->driver, DRV_NAME); 3647 strcpy(info->version, DRV_VERSION); 3648 strcpy(info->fw_version, "N/A"); 3649 strcpy(info->bus_info, pci_name(sky2->hw->pdev)); 3650 } 3651 3652 static const struct sky2_stat { 3653 char name[ETH_GSTRING_LEN]; 3654 u16 offset; 3655 } sky2_stats[] = { 3656 { "tx_bytes", GM_TXO_OK_HI }, 3657 { "rx_bytes", GM_RXO_OK_HI }, 3658 { "tx_broadcast", GM_TXF_BC_OK }, 3659 { "rx_broadcast", GM_RXF_BC_OK }, 3660 { "tx_multicast", GM_TXF_MC_OK }, 3661 { "rx_multicast", GM_RXF_MC_OK }, 3662 { "tx_unicast", GM_TXF_UC_OK }, 3663 { "rx_unicast", GM_RXF_UC_OK }, 3664 { "tx_mac_pause", GM_TXF_MPAUSE }, 3665 { "rx_mac_pause", GM_RXF_MPAUSE }, 3666 { "collisions", GM_TXF_COL }, 3667 { "late_collision",GM_TXF_LAT_COL }, 3668 { "aborted", GM_TXF_ABO_COL }, 3669 { "single_collisions", GM_TXF_SNG_COL }, 3670 { "multi_collisions", GM_TXF_MUL_COL }, 3671 3672 { "rx_short", GM_RXF_SHT }, 3673 { "rx_runt", GM_RXE_FRAG }, 3674 { "rx_64_byte_packets", GM_RXF_64B }, 3675 { "rx_65_to_127_byte_packets", GM_RXF_127B }, 3676 { "rx_128_to_255_byte_packets", GM_RXF_255B }, 3677 { "rx_256_to_511_byte_packets", GM_RXF_511B }, 3678 { "rx_512_to_1023_byte_packets", GM_RXF_1023B }, 3679 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B }, 3680 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ }, 3681 { "rx_too_long", GM_RXF_LNG_ERR }, 3682 { "rx_fifo_overflow", GM_RXE_FIFO_OV }, 3683 { "rx_jabber", GM_RXF_JAB_PKT }, 3684 { "rx_fcs_error", GM_RXF_FCS_ERR }, 3685 3686 { "tx_64_byte_packets", GM_TXF_64B }, 3687 { "tx_65_to_127_byte_packets", GM_TXF_127B }, 3688 { "tx_128_to_255_byte_packets", GM_TXF_255B }, 3689 { "tx_256_to_511_byte_packets", GM_TXF_511B }, 3690 { "tx_512_to_1023_byte_packets", GM_TXF_1023B }, 3691 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B }, 3692 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ }, 3693 { "tx_fifo_underrun", GM_TXE_FIFO_UR }, 3694 }; 3695 3696 static u32 sky2_get_msglevel(struct net_device *netdev) 3697 { 3698 struct sky2_port *sky2 = netdev_priv(netdev); 3699 return sky2->msg_enable; 3700 } 3701 3702 static int sky2_nway_reset(struct net_device *dev) 3703 { 3704 struct sky2_port *sky2 = netdev_priv(dev); 3705 3706 if (!netif_running(dev) || !(sky2->flags & SKY2_FLAG_AUTO_SPEED)) 3707 return -EINVAL; 3708 3709 sky2_phy_reinit(sky2); 3710 sky2_set_multicast(dev); 3711 3712 return 0; 3713 } 3714 3715 static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count) 3716 { 3717 struct sky2_hw *hw = sky2->hw; 3718 unsigned port = sky2->port; 3719 int i; 3720 3721 data[0] = get_stats64(hw, port, GM_TXO_OK_LO); 3722 data[1] = get_stats64(hw, port, GM_RXO_OK_LO); 3723 3724 for (i = 2; i < count; i++) 3725 data[i] = get_stats32(hw, port, sky2_stats[i].offset); 3726 } 3727 3728 static void sky2_set_msglevel(struct net_device *netdev, u32 value) 3729 { 3730 struct sky2_port *sky2 = netdev_priv(netdev); 3731 sky2->msg_enable = value; 3732 } 3733 3734 static int sky2_get_sset_count(struct net_device *dev, int sset) 3735 { 3736 switch (sset) { 3737 case ETH_SS_STATS: 3738 return ARRAY_SIZE(sky2_stats); 3739 default: 3740 return -EOPNOTSUPP; 3741 } 3742 } 3743 3744 static void sky2_get_ethtool_stats(struct net_device *dev, 3745 struct ethtool_stats *stats, u64 * data) 3746 { 3747 struct sky2_port *sky2 = netdev_priv(dev); 3748 3749 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats)); 3750 } 3751 3752 static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data) 3753 { 3754 int i; 3755 3756 switch (stringset) { 3757 case ETH_SS_STATS: 3758 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++) 3759 memcpy(data + i * ETH_GSTRING_LEN, 3760 sky2_stats[i].name, ETH_GSTRING_LEN); 3761 break; 3762 } 3763 } 3764 3765 static int sky2_set_mac_address(struct net_device *dev, void *p) 3766 { 3767 struct sky2_port *sky2 = netdev_priv(dev); 3768 struct sky2_hw *hw = sky2->hw; 3769 unsigned port = sky2->port; 3770 const struct sockaddr *addr = p; 3771 3772 if (!is_valid_ether_addr(addr->sa_data)) 3773 return -EADDRNOTAVAIL; 3774 3775 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN); 3776 memcpy_toio(hw->regs + B2_MAC_1 + port * 8, 3777 dev->dev_addr, ETH_ALEN); 3778 memcpy_toio(hw->regs + B2_MAC_2 + port * 8, 3779 dev->dev_addr, ETH_ALEN); 3780 3781 /* virtual address for data */ 3782 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr); 3783 3784 /* physical address: used for pause frames */ 3785 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr); 3786 3787 return 0; 3788 } 3789 3790 static inline void sky2_add_filter(u8 filter[8], const u8 *addr) 3791 { 3792 u32 bit; 3793 3794 bit = ether_crc(ETH_ALEN, addr) & 63; 3795 filter[bit >> 3] |= 1 << (bit & 7); 3796 } 3797 3798 static void sky2_set_multicast(struct net_device *dev) 3799 { 3800 struct sky2_port *sky2 = netdev_priv(dev); 3801 struct sky2_hw *hw = sky2->hw; 3802 unsigned port = sky2->port; 3803 struct netdev_hw_addr *ha; 3804 u16 reg; 3805 u8 filter[8]; 3806 int rx_pause; 3807 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 }; 3808 3809 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH); 3810 memset(filter, 0, sizeof(filter)); 3811 3812 reg = gma_read16(hw, port, GM_RX_CTRL); 3813 reg |= GM_RXCR_UCF_ENA; 3814 3815 if (dev->flags & IFF_PROMISC) /* promiscuous */ 3816 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA); 3817 else if (dev->flags & IFF_ALLMULTI) 3818 memset(filter, 0xff, sizeof(filter)); 3819 else if (netdev_mc_empty(dev) && !rx_pause) 3820 reg &= ~GM_RXCR_MCF_ENA; 3821 else { 3822 reg |= GM_RXCR_MCF_ENA; 3823 3824 if (rx_pause) 3825 sky2_add_filter(filter, pause_mc_addr); 3826 3827 netdev_for_each_mc_addr(ha, dev) 3828 sky2_add_filter(filter, ha->addr); 3829 } 3830 3831 gma_write16(hw, port, GM_MC_ADDR_H1, 3832 (u16) filter[0] | ((u16) filter[1] << 8)); 3833 gma_write16(hw, port, GM_MC_ADDR_H2, 3834 (u16) filter[2] | ((u16) filter[3] << 8)); 3835 gma_write16(hw, port, GM_MC_ADDR_H3, 3836 (u16) filter[4] | ((u16) filter[5] << 8)); 3837 gma_write16(hw, port, GM_MC_ADDR_H4, 3838 (u16) filter[6] | ((u16) filter[7] << 8)); 3839 3840 gma_write16(hw, port, GM_RX_CTRL, reg); 3841 } 3842 3843 static struct rtnl_link_stats64 *sky2_get_stats(struct net_device *dev, 3844 struct rtnl_link_stats64 *stats) 3845 { 3846 struct sky2_port *sky2 = netdev_priv(dev); 3847 struct sky2_hw *hw = sky2->hw; 3848 unsigned port = sky2->port; 3849 unsigned int start; 3850 u64 _bytes, _packets; 3851 3852 do { 3853 start = u64_stats_fetch_begin_bh(&sky2->rx_stats.syncp); 3854 _bytes = sky2->rx_stats.bytes; 3855 _packets = sky2->rx_stats.packets; 3856 } while (u64_stats_fetch_retry_bh(&sky2->rx_stats.syncp, start)); 3857 3858 stats->rx_packets = _packets; 3859 stats->rx_bytes = _bytes; 3860 3861 do { 3862 start = u64_stats_fetch_begin_bh(&sky2->tx_stats.syncp); 3863 _bytes = sky2->tx_stats.bytes; 3864 _packets = sky2->tx_stats.packets; 3865 } while (u64_stats_fetch_retry_bh(&sky2->tx_stats.syncp, start)); 3866 3867 stats->tx_packets = _packets; 3868 stats->tx_bytes = _bytes; 3869 3870 stats->multicast = get_stats32(hw, port, GM_RXF_MC_OK) 3871 + get_stats32(hw, port, GM_RXF_BC_OK); 3872 3873 stats->collisions = get_stats32(hw, port, GM_TXF_COL); 3874 3875 stats->rx_length_errors = get_stats32(hw, port, GM_RXF_LNG_ERR); 3876 stats->rx_crc_errors = get_stats32(hw, port, GM_RXF_FCS_ERR); 3877 stats->rx_frame_errors = get_stats32(hw, port, GM_RXF_SHT) 3878 + get_stats32(hw, port, GM_RXE_FRAG); 3879 stats->rx_over_errors = get_stats32(hw, port, GM_RXE_FIFO_OV); 3880 3881 stats->rx_dropped = dev->stats.rx_dropped; 3882 stats->rx_fifo_errors = dev->stats.rx_fifo_errors; 3883 stats->tx_fifo_errors = dev->stats.tx_fifo_errors; 3884 3885 return stats; 3886 } 3887 3888 /* Can have one global because blinking is controlled by 3889 * ethtool and that is always under RTNL mutex 3890 */ 3891 static void sky2_led(struct sky2_port *sky2, enum led_mode mode) 3892 { 3893 struct sky2_hw *hw = sky2->hw; 3894 unsigned port = sky2->port; 3895 3896 spin_lock_bh(&sky2->phy_lock); 3897 if (hw->chip_id == CHIP_ID_YUKON_EC_U || 3898 hw->chip_id == CHIP_ID_YUKON_EX || 3899 hw->chip_id == CHIP_ID_YUKON_SUPR) { 3900 u16 pg; 3901 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); 3902 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); 3903 3904 switch (mode) { 3905 case MO_LED_OFF: 3906 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, 3907 PHY_M_LEDC_LOS_CTRL(8) | 3908 PHY_M_LEDC_INIT_CTRL(8) | 3909 PHY_M_LEDC_STA1_CTRL(8) | 3910 PHY_M_LEDC_STA0_CTRL(8)); 3911 break; 3912 case MO_LED_ON: 3913 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, 3914 PHY_M_LEDC_LOS_CTRL(9) | 3915 PHY_M_LEDC_INIT_CTRL(9) | 3916 PHY_M_LEDC_STA1_CTRL(9) | 3917 PHY_M_LEDC_STA0_CTRL(9)); 3918 break; 3919 case MO_LED_BLINK: 3920 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, 3921 PHY_M_LEDC_LOS_CTRL(0xa) | 3922 PHY_M_LEDC_INIT_CTRL(0xa) | 3923 PHY_M_LEDC_STA1_CTRL(0xa) | 3924 PHY_M_LEDC_STA0_CTRL(0xa)); 3925 break; 3926 case MO_LED_NORM: 3927 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, 3928 PHY_M_LEDC_LOS_CTRL(1) | 3929 PHY_M_LEDC_INIT_CTRL(8) | 3930 PHY_M_LEDC_STA1_CTRL(7) | 3931 PHY_M_LEDC_STA0_CTRL(7)); 3932 } 3933 3934 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); 3935 } else 3936 gm_phy_write(hw, port, PHY_MARV_LED_OVER, 3937 PHY_M_LED_MO_DUP(mode) | 3938 PHY_M_LED_MO_10(mode) | 3939 PHY_M_LED_MO_100(mode) | 3940 PHY_M_LED_MO_1000(mode) | 3941 PHY_M_LED_MO_RX(mode) | 3942 PHY_M_LED_MO_TX(mode)); 3943 3944 spin_unlock_bh(&sky2->phy_lock); 3945 } 3946 3947 /* blink LED's for finding board */ 3948 static int sky2_set_phys_id(struct net_device *dev, 3949 enum ethtool_phys_id_state state) 3950 { 3951 struct sky2_port *sky2 = netdev_priv(dev); 3952 3953 switch (state) { 3954 case ETHTOOL_ID_ACTIVE: 3955 return 1; /* cycle on/off once per second */ 3956 case ETHTOOL_ID_INACTIVE: 3957 sky2_led(sky2, MO_LED_NORM); 3958 break; 3959 case ETHTOOL_ID_ON: 3960 sky2_led(sky2, MO_LED_ON); 3961 break; 3962 case ETHTOOL_ID_OFF: 3963 sky2_led(sky2, MO_LED_OFF); 3964 break; 3965 } 3966 3967 return 0; 3968 } 3969 3970 static void sky2_get_pauseparam(struct net_device *dev, 3971 struct ethtool_pauseparam *ecmd) 3972 { 3973 struct sky2_port *sky2 = netdev_priv(dev); 3974 3975 switch (sky2->flow_mode) { 3976 case FC_NONE: 3977 ecmd->tx_pause = ecmd->rx_pause = 0; 3978 break; 3979 case FC_TX: 3980 ecmd->tx_pause = 1, ecmd->rx_pause = 0; 3981 break; 3982 case FC_RX: 3983 ecmd->tx_pause = 0, ecmd->rx_pause = 1; 3984 break; 3985 case FC_BOTH: 3986 ecmd->tx_pause = ecmd->rx_pause = 1; 3987 } 3988 3989 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_PAUSE) 3990 ? AUTONEG_ENABLE : AUTONEG_DISABLE; 3991 } 3992 3993 static int sky2_set_pauseparam(struct net_device *dev, 3994 struct ethtool_pauseparam *ecmd) 3995 { 3996 struct sky2_port *sky2 = netdev_priv(dev); 3997 3998 if (ecmd->autoneg == AUTONEG_ENABLE) 3999 sky2->flags |= SKY2_FLAG_AUTO_PAUSE; 4000 else 4001 sky2->flags &= ~SKY2_FLAG_AUTO_PAUSE; 4002 4003 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause); 4004 4005 if (netif_running(dev)) 4006 sky2_phy_reinit(sky2); 4007 4008 return 0; 4009 } 4010 4011 static int sky2_get_coalesce(struct net_device *dev, 4012 struct ethtool_coalesce *ecmd) 4013 { 4014 struct sky2_port *sky2 = netdev_priv(dev); 4015 struct sky2_hw *hw = sky2->hw; 4016 4017 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP) 4018 ecmd->tx_coalesce_usecs = 0; 4019 else { 4020 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI); 4021 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks); 4022 } 4023 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH); 4024 4025 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP) 4026 ecmd->rx_coalesce_usecs = 0; 4027 else { 4028 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI); 4029 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks); 4030 } 4031 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM); 4032 4033 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP) 4034 ecmd->rx_coalesce_usecs_irq = 0; 4035 else { 4036 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI); 4037 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks); 4038 } 4039 4040 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM); 4041 4042 return 0; 4043 } 4044 4045 /* Note: this affect both ports */ 4046 static int sky2_set_coalesce(struct net_device *dev, 4047 struct ethtool_coalesce *ecmd) 4048 { 4049 struct sky2_port *sky2 = netdev_priv(dev); 4050 struct sky2_hw *hw = sky2->hw; 4051 const u32 tmax = sky2_clk2us(hw, 0x0ffffff); 4052 4053 if (ecmd->tx_coalesce_usecs > tmax || 4054 ecmd->rx_coalesce_usecs > tmax || 4055 ecmd->rx_coalesce_usecs_irq > tmax) 4056 return -EINVAL; 4057 4058 if (ecmd->tx_max_coalesced_frames >= sky2->tx_ring_size-1) 4059 return -EINVAL; 4060 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING) 4061 return -EINVAL; 4062 if (ecmd->rx_max_coalesced_frames_irq > RX_MAX_PENDING) 4063 return -EINVAL; 4064 4065 if (ecmd->tx_coalesce_usecs == 0) 4066 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP); 4067 else { 4068 sky2_write32(hw, STAT_TX_TIMER_INI, 4069 sky2_us2clk(hw, ecmd->tx_coalesce_usecs)); 4070 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START); 4071 } 4072 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames); 4073 4074 if (ecmd->rx_coalesce_usecs == 0) 4075 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP); 4076 else { 4077 sky2_write32(hw, STAT_LEV_TIMER_INI, 4078 sky2_us2clk(hw, ecmd->rx_coalesce_usecs)); 4079 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START); 4080 } 4081 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames); 4082 4083 if (ecmd->rx_coalesce_usecs_irq == 0) 4084 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP); 4085 else { 4086 sky2_write32(hw, STAT_ISR_TIMER_INI, 4087 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq)); 4088 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START); 4089 } 4090 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq); 4091 return 0; 4092 } 4093 4094 /* 4095 * Hardware is limited to min of 128 and max of 2048 for ring size 4096 * and rounded up to next power of two 4097 * to avoid division in modulus calclation 4098 */ 4099 static unsigned long roundup_ring_size(unsigned long pending) 4100 { 4101 return max(128ul, roundup_pow_of_two(pending+1)); 4102 } 4103 4104 static void sky2_get_ringparam(struct net_device *dev, 4105 struct ethtool_ringparam *ering) 4106 { 4107 struct sky2_port *sky2 = netdev_priv(dev); 4108 4109 ering->rx_max_pending = RX_MAX_PENDING; 4110 ering->tx_max_pending = TX_MAX_PENDING; 4111 4112 ering->rx_pending = sky2->rx_pending; 4113 ering->tx_pending = sky2->tx_pending; 4114 } 4115 4116 static int sky2_set_ringparam(struct net_device *dev, 4117 struct ethtool_ringparam *ering) 4118 { 4119 struct sky2_port *sky2 = netdev_priv(dev); 4120 4121 if (ering->rx_pending > RX_MAX_PENDING || 4122 ering->rx_pending < 8 || 4123 ering->tx_pending < TX_MIN_PENDING || 4124 ering->tx_pending > TX_MAX_PENDING) 4125 return -EINVAL; 4126 4127 sky2_detach(dev); 4128 4129 sky2->rx_pending = ering->rx_pending; 4130 sky2->tx_pending = ering->tx_pending; 4131 sky2->tx_ring_size = roundup_ring_size(sky2->tx_pending); 4132 4133 return sky2_reattach(dev); 4134 } 4135 4136 static int sky2_get_regs_len(struct net_device *dev) 4137 { 4138 return 0x4000; 4139 } 4140 4141 static int sky2_reg_access_ok(struct sky2_hw *hw, unsigned int b) 4142 { 4143 /* This complicated switch statement is to make sure and 4144 * only access regions that are unreserved. 4145 * Some blocks are only valid on dual port cards. 4146 */ 4147 switch (b) { 4148 /* second port */ 4149 case 5: /* Tx Arbiter 2 */ 4150 case 9: /* RX2 */ 4151 case 14 ... 15: /* TX2 */ 4152 case 17: case 19: /* Ram Buffer 2 */ 4153 case 22 ... 23: /* Tx Ram Buffer 2 */ 4154 case 25: /* Rx MAC Fifo 1 */ 4155 case 27: /* Tx MAC Fifo 2 */ 4156 case 31: /* GPHY 2 */ 4157 case 40 ... 47: /* Pattern Ram 2 */ 4158 case 52: case 54: /* TCP Segmentation 2 */ 4159 case 112 ... 116: /* GMAC 2 */ 4160 return hw->ports > 1; 4161 4162 case 0: /* Control */ 4163 case 2: /* Mac address */ 4164 case 4: /* Tx Arbiter 1 */ 4165 case 7: /* PCI express reg */ 4166 case 8: /* RX1 */ 4167 case 12 ... 13: /* TX1 */ 4168 case 16: case 18:/* Rx Ram Buffer 1 */ 4169 case 20 ... 21: /* Tx Ram Buffer 1 */ 4170 case 24: /* Rx MAC Fifo 1 */ 4171 case 26: /* Tx MAC Fifo 1 */ 4172 case 28 ... 29: /* Descriptor and status unit */ 4173 case 30: /* GPHY 1*/ 4174 case 32 ... 39: /* Pattern Ram 1 */ 4175 case 48: case 50: /* TCP Segmentation 1 */ 4176 case 56 ... 60: /* PCI space */ 4177 case 80 ... 84: /* GMAC 1 */ 4178 return 1; 4179 4180 default: 4181 return 0; 4182 } 4183 } 4184 4185 /* 4186 * Returns copy of control register region 4187 * Note: ethtool_get_regs always provides full size (16k) buffer 4188 */ 4189 static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs, 4190 void *p) 4191 { 4192 const struct sky2_port *sky2 = netdev_priv(dev); 4193 const void __iomem *io = sky2->hw->regs; 4194 unsigned int b; 4195 4196 regs->version = 1; 4197 4198 for (b = 0; b < 128; b++) { 4199 /* skip poisonous diagnostic ram region in block 3 */ 4200 if (b == 3) 4201 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10); 4202 else if (sky2_reg_access_ok(sky2->hw, b)) 4203 memcpy_fromio(p, io, 128); 4204 else 4205 memset(p, 0, 128); 4206 4207 p += 128; 4208 io += 128; 4209 } 4210 } 4211 4212 static int sky2_get_eeprom_len(struct net_device *dev) 4213 { 4214 struct sky2_port *sky2 = netdev_priv(dev); 4215 struct sky2_hw *hw = sky2->hw; 4216 u16 reg2; 4217 4218 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2); 4219 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8); 4220 } 4221 4222 static int sky2_vpd_wait(const struct sky2_hw *hw, int cap, u16 busy) 4223 { 4224 unsigned long start = jiffies; 4225 4226 while ( (sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F) == busy) { 4227 /* Can take up to 10.6 ms for write */ 4228 if (time_after(jiffies, start + HZ/4)) { 4229 dev_err(&hw->pdev->dev, "VPD cycle timed out\n"); 4230 return -ETIMEDOUT; 4231 } 4232 mdelay(1); 4233 } 4234 4235 return 0; 4236 } 4237 4238 static int sky2_vpd_read(struct sky2_hw *hw, int cap, void *data, 4239 u16 offset, size_t length) 4240 { 4241 int rc = 0; 4242 4243 while (length > 0) { 4244 u32 val; 4245 4246 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset); 4247 rc = sky2_vpd_wait(hw, cap, 0); 4248 if (rc) 4249 break; 4250 4251 val = sky2_pci_read32(hw, cap + PCI_VPD_DATA); 4252 4253 memcpy(data, &val, min(sizeof(val), length)); 4254 offset += sizeof(u32); 4255 data += sizeof(u32); 4256 length -= sizeof(u32); 4257 } 4258 4259 return rc; 4260 } 4261 4262 static int sky2_vpd_write(struct sky2_hw *hw, int cap, const void *data, 4263 u16 offset, unsigned int length) 4264 { 4265 unsigned int i; 4266 int rc = 0; 4267 4268 for (i = 0; i < length; i += sizeof(u32)) { 4269 u32 val = *(u32 *)(data + i); 4270 4271 sky2_pci_write32(hw, cap + PCI_VPD_DATA, val); 4272 sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F); 4273 4274 rc = sky2_vpd_wait(hw, cap, PCI_VPD_ADDR_F); 4275 if (rc) 4276 break; 4277 } 4278 return rc; 4279 } 4280 4281 static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, 4282 u8 *data) 4283 { 4284 struct sky2_port *sky2 = netdev_priv(dev); 4285 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD); 4286 4287 if (!cap) 4288 return -EINVAL; 4289 4290 eeprom->magic = SKY2_EEPROM_MAGIC; 4291 4292 return sky2_vpd_read(sky2->hw, cap, data, eeprom->offset, eeprom->len); 4293 } 4294 4295 static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, 4296 u8 *data) 4297 { 4298 struct sky2_port *sky2 = netdev_priv(dev); 4299 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD); 4300 4301 if (!cap) 4302 return -EINVAL; 4303 4304 if (eeprom->magic != SKY2_EEPROM_MAGIC) 4305 return -EINVAL; 4306 4307 /* Partial writes not supported */ 4308 if ((eeprom->offset & 3) || (eeprom->len & 3)) 4309 return -EINVAL; 4310 4311 return sky2_vpd_write(sky2->hw, cap, data, eeprom->offset, eeprom->len); 4312 } 4313 4314 static u32 sky2_fix_features(struct net_device *dev, u32 features) 4315 { 4316 const struct sky2_port *sky2 = netdev_priv(dev); 4317 const struct sky2_hw *hw = sky2->hw; 4318 4319 /* In order to do Jumbo packets on these chips, need to turn off the 4320 * transmit store/forward. Therefore checksum offload won't work. 4321 */ 4322 if (dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U) { 4323 netdev_info(dev, "checksum offload not possible with jumbo frames\n"); 4324 features &= ~(NETIF_F_TSO|NETIF_F_SG|NETIF_F_ALL_CSUM); 4325 } 4326 4327 /* Some hardware requires receive checksum for RSS to work. */ 4328 if ( (features & NETIF_F_RXHASH) && 4329 !(features & NETIF_F_RXCSUM) && 4330 (sky2->hw->flags & SKY2_HW_RSS_CHKSUM)) { 4331 netdev_info(dev, "receive hashing forces receive checksum\n"); 4332 features |= NETIF_F_RXCSUM; 4333 } 4334 4335 return features; 4336 } 4337 4338 static int sky2_set_features(struct net_device *dev, u32 features) 4339 { 4340 struct sky2_port *sky2 = netdev_priv(dev); 4341 u32 changed = dev->features ^ features; 4342 4343 if (changed & NETIF_F_RXCSUM) { 4344 u32 on = features & NETIF_F_RXCSUM; 4345 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR), 4346 on ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM); 4347 } 4348 4349 if (changed & NETIF_F_RXHASH) 4350 rx_set_rss(dev, features); 4351 4352 if (changed & (NETIF_F_HW_VLAN_TX|NETIF_F_HW_VLAN_RX)) 4353 sky2_vlan_mode(dev, features); 4354 4355 return 0; 4356 } 4357 4358 static const struct ethtool_ops sky2_ethtool_ops = { 4359 .get_settings = sky2_get_settings, 4360 .set_settings = sky2_set_settings, 4361 .get_drvinfo = sky2_get_drvinfo, 4362 .get_wol = sky2_get_wol, 4363 .set_wol = sky2_set_wol, 4364 .get_msglevel = sky2_get_msglevel, 4365 .set_msglevel = sky2_set_msglevel, 4366 .nway_reset = sky2_nway_reset, 4367 .get_regs_len = sky2_get_regs_len, 4368 .get_regs = sky2_get_regs, 4369 .get_link = ethtool_op_get_link, 4370 .get_eeprom_len = sky2_get_eeprom_len, 4371 .get_eeprom = sky2_get_eeprom, 4372 .set_eeprom = sky2_set_eeprom, 4373 .get_strings = sky2_get_strings, 4374 .get_coalesce = sky2_get_coalesce, 4375 .set_coalesce = sky2_set_coalesce, 4376 .get_ringparam = sky2_get_ringparam, 4377 .set_ringparam = sky2_set_ringparam, 4378 .get_pauseparam = sky2_get_pauseparam, 4379 .set_pauseparam = sky2_set_pauseparam, 4380 .set_phys_id = sky2_set_phys_id, 4381 .get_sset_count = sky2_get_sset_count, 4382 .get_ethtool_stats = sky2_get_ethtool_stats, 4383 }; 4384 4385 #ifdef CONFIG_SKY2_DEBUG 4386 4387 static struct dentry *sky2_debug; 4388 4389 4390 /* 4391 * Read and parse the first part of Vital Product Data 4392 */ 4393 #define VPD_SIZE 128 4394 #define VPD_MAGIC 0x82 4395 4396 static const struct vpd_tag { 4397 char tag[2]; 4398 char *label; 4399 } vpd_tags[] = { 4400 { "PN", "Part Number" }, 4401 { "EC", "Engineering Level" }, 4402 { "MN", "Manufacturer" }, 4403 { "SN", "Serial Number" }, 4404 { "YA", "Asset Tag" }, 4405 { "VL", "First Error Log Message" }, 4406 { "VF", "Second Error Log Message" }, 4407 { "VB", "Boot Agent ROM Configuration" }, 4408 { "VE", "EFI UNDI Configuration" }, 4409 }; 4410 4411 static void sky2_show_vpd(struct seq_file *seq, struct sky2_hw *hw) 4412 { 4413 size_t vpd_size; 4414 loff_t offs; 4415 u8 len; 4416 unsigned char *buf; 4417 u16 reg2; 4418 4419 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2); 4420 vpd_size = 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8); 4421 4422 seq_printf(seq, "%s Product Data\n", pci_name(hw->pdev)); 4423 buf = kmalloc(vpd_size, GFP_KERNEL); 4424 if (!buf) { 4425 seq_puts(seq, "no memory!\n"); 4426 return; 4427 } 4428 4429 if (pci_read_vpd(hw->pdev, 0, vpd_size, buf) < 0) { 4430 seq_puts(seq, "VPD read failed\n"); 4431 goto out; 4432 } 4433 4434 if (buf[0] != VPD_MAGIC) { 4435 seq_printf(seq, "VPD tag mismatch: %#x\n", buf[0]); 4436 goto out; 4437 } 4438 len = buf[1]; 4439 if (len == 0 || len > vpd_size - 4) { 4440 seq_printf(seq, "Invalid id length: %d\n", len); 4441 goto out; 4442 } 4443 4444 seq_printf(seq, "%.*s\n", len, buf + 3); 4445 offs = len + 3; 4446 4447 while (offs < vpd_size - 4) { 4448 int i; 4449 4450 if (!memcmp("RW", buf + offs, 2)) /* end marker */ 4451 break; 4452 len = buf[offs + 2]; 4453 if (offs + len + 3 >= vpd_size) 4454 break; 4455 4456 for (i = 0; i < ARRAY_SIZE(vpd_tags); i++) { 4457 if (!memcmp(vpd_tags[i].tag, buf + offs, 2)) { 4458 seq_printf(seq, " %s: %.*s\n", 4459 vpd_tags[i].label, len, buf + offs + 3); 4460 break; 4461 } 4462 } 4463 offs += len + 3; 4464 } 4465 out: 4466 kfree(buf); 4467 } 4468 4469 static int sky2_debug_show(struct seq_file *seq, void *v) 4470 { 4471 struct net_device *dev = seq->private; 4472 const struct sky2_port *sky2 = netdev_priv(dev); 4473 struct sky2_hw *hw = sky2->hw; 4474 unsigned port = sky2->port; 4475 unsigned idx, last; 4476 int sop; 4477 4478 sky2_show_vpd(seq, hw); 4479 4480 seq_printf(seq, "\nIRQ src=%x mask=%x control=%x\n", 4481 sky2_read32(hw, B0_ISRC), 4482 sky2_read32(hw, B0_IMSK), 4483 sky2_read32(hw, B0_Y2_SP_ICR)); 4484 4485 if (!netif_running(dev)) { 4486 seq_printf(seq, "network not running\n"); 4487 return 0; 4488 } 4489 4490 napi_disable(&hw->napi); 4491 last = sky2_read16(hw, STAT_PUT_IDX); 4492 4493 seq_printf(seq, "Status ring %u\n", hw->st_size); 4494 if (hw->st_idx == last) 4495 seq_puts(seq, "Status ring (empty)\n"); 4496 else { 4497 seq_puts(seq, "Status ring\n"); 4498 for (idx = hw->st_idx; idx != last && idx < hw->st_size; 4499 idx = RING_NEXT(idx, hw->st_size)) { 4500 const struct sky2_status_le *le = hw->st_le + idx; 4501 seq_printf(seq, "[%d] %#x %d %#x\n", 4502 idx, le->opcode, le->length, le->status); 4503 } 4504 seq_puts(seq, "\n"); 4505 } 4506 4507 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n", 4508 sky2->tx_cons, sky2->tx_prod, 4509 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX), 4510 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE))); 4511 4512 /* Dump contents of tx ring */ 4513 sop = 1; 4514 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < sky2->tx_ring_size; 4515 idx = RING_NEXT(idx, sky2->tx_ring_size)) { 4516 const struct sky2_tx_le *le = sky2->tx_le + idx; 4517 u32 a = le32_to_cpu(le->addr); 4518 4519 if (sop) 4520 seq_printf(seq, "%u:", idx); 4521 sop = 0; 4522 4523 switch (le->opcode & ~HW_OWNER) { 4524 case OP_ADDR64: 4525 seq_printf(seq, " %#x:", a); 4526 break; 4527 case OP_LRGLEN: 4528 seq_printf(seq, " mtu=%d", a); 4529 break; 4530 case OP_VLAN: 4531 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length)); 4532 break; 4533 case OP_TCPLISW: 4534 seq_printf(seq, " csum=%#x", a); 4535 break; 4536 case OP_LARGESEND: 4537 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length)); 4538 break; 4539 case OP_PACKET: 4540 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length)); 4541 break; 4542 case OP_BUFFER: 4543 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length)); 4544 break; 4545 default: 4546 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode, 4547 a, le16_to_cpu(le->length)); 4548 } 4549 4550 if (le->ctrl & EOP) { 4551 seq_putc(seq, '\n'); 4552 sop = 1; 4553 } 4554 } 4555 4556 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n", 4557 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)), 4558 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)), 4559 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX))); 4560 4561 sky2_read32(hw, B0_Y2_SP_LISR); 4562 napi_enable(&hw->napi); 4563 return 0; 4564 } 4565 4566 static int sky2_debug_open(struct inode *inode, struct file *file) 4567 { 4568 return single_open(file, sky2_debug_show, inode->i_private); 4569 } 4570 4571 static const struct file_operations sky2_debug_fops = { 4572 .owner = THIS_MODULE, 4573 .open = sky2_debug_open, 4574 .read = seq_read, 4575 .llseek = seq_lseek, 4576 .release = single_release, 4577 }; 4578 4579 /* 4580 * Use network device events to create/remove/rename 4581 * debugfs file entries 4582 */ 4583 static int sky2_device_event(struct notifier_block *unused, 4584 unsigned long event, void *ptr) 4585 { 4586 struct net_device *dev = ptr; 4587 struct sky2_port *sky2 = netdev_priv(dev); 4588 4589 if (dev->netdev_ops->ndo_open != sky2_open || !sky2_debug) 4590 return NOTIFY_DONE; 4591 4592 switch (event) { 4593 case NETDEV_CHANGENAME: 4594 if (sky2->debugfs) { 4595 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs, 4596 sky2_debug, dev->name); 4597 } 4598 break; 4599 4600 case NETDEV_GOING_DOWN: 4601 if (sky2->debugfs) { 4602 netdev_printk(KERN_DEBUG, dev, "remove debugfs\n"); 4603 debugfs_remove(sky2->debugfs); 4604 sky2->debugfs = NULL; 4605 } 4606 break; 4607 4608 case NETDEV_UP: 4609 sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO, 4610 sky2_debug, dev, 4611 &sky2_debug_fops); 4612 if (IS_ERR(sky2->debugfs)) 4613 sky2->debugfs = NULL; 4614 } 4615 4616 return NOTIFY_DONE; 4617 } 4618 4619 static struct notifier_block sky2_notifier = { 4620 .notifier_call = sky2_device_event, 4621 }; 4622 4623 4624 static __init void sky2_debug_init(void) 4625 { 4626 struct dentry *ent; 4627 4628 ent = debugfs_create_dir("sky2", NULL); 4629 if (!ent || IS_ERR(ent)) 4630 return; 4631 4632 sky2_debug = ent; 4633 register_netdevice_notifier(&sky2_notifier); 4634 } 4635 4636 static __exit void sky2_debug_cleanup(void) 4637 { 4638 if (sky2_debug) { 4639 unregister_netdevice_notifier(&sky2_notifier); 4640 debugfs_remove(sky2_debug); 4641 sky2_debug = NULL; 4642 } 4643 } 4644 4645 #else 4646 #define sky2_debug_init() 4647 #define sky2_debug_cleanup() 4648 #endif 4649 4650 /* Two copies of network device operations to handle special case of 4651 not allowing netpoll on second port */ 4652 static const struct net_device_ops sky2_netdev_ops[2] = { 4653 { 4654 .ndo_open = sky2_open, 4655 .ndo_stop = sky2_close, 4656 .ndo_start_xmit = sky2_xmit_frame, 4657 .ndo_do_ioctl = sky2_ioctl, 4658 .ndo_validate_addr = eth_validate_addr, 4659 .ndo_set_mac_address = sky2_set_mac_address, 4660 .ndo_set_rx_mode = sky2_set_multicast, 4661 .ndo_change_mtu = sky2_change_mtu, 4662 .ndo_fix_features = sky2_fix_features, 4663 .ndo_set_features = sky2_set_features, 4664 .ndo_tx_timeout = sky2_tx_timeout, 4665 .ndo_get_stats64 = sky2_get_stats, 4666 #ifdef CONFIG_NET_POLL_CONTROLLER 4667 .ndo_poll_controller = sky2_netpoll, 4668 #endif 4669 }, 4670 { 4671 .ndo_open = sky2_open, 4672 .ndo_stop = sky2_close, 4673 .ndo_start_xmit = sky2_xmit_frame, 4674 .ndo_do_ioctl = sky2_ioctl, 4675 .ndo_validate_addr = eth_validate_addr, 4676 .ndo_set_mac_address = sky2_set_mac_address, 4677 .ndo_set_rx_mode = sky2_set_multicast, 4678 .ndo_change_mtu = sky2_change_mtu, 4679 .ndo_fix_features = sky2_fix_features, 4680 .ndo_set_features = sky2_set_features, 4681 .ndo_tx_timeout = sky2_tx_timeout, 4682 .ndo_get_stats64 = sky2_get_stats, 4683 }, 4684 }; 4685 4686 /* Initialize network device */ 4687 static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw, 4688 unsigned port, 4689 int highmem, int wol) 4690 { 4691 struct sky2_port *sky2; 4692 struct net_device *dev = alloc_etherdev(sizeof(*sky2)); 4693 4694 if (!dev) { 4695 dev_err(&hw->pdev->dev, "etherdev alloc failed\n"); 4696 return NULL; 4697 } 4698 4699 SET_NETDEV_DEV(dev, &hw->pdev->dev); 4700 dev->irq = hw->pdev->irq; 4701 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops); 4702 dev->watchdog_timeo = TX_WATCHDOG; 4703 dev->netdev_ops = &sky2_netdev_ops[port]; 4704 4705 sky2 = netdev_priv(dev); 4706 sky2->netdev = dev; 4707 sky2->hw = hw; 4708 sky2->msg_enable = netif_msg_init(debug, default_msg); 4709 4710 /* Auto speed and flow control */ 4711 sky2->flags = SKY2_FLAG_AUTO_SPEED | SKY2_FLAG_AUTO_PAUSE; 4712 if (hw->chip_id != CHIP_ID_YUKON_XL) 4713 dev->hw_features |= NETIF_F_RXCSUM; 4714 4715 sky2->flow_mode = FC_BOTH; 4716 4717 sky2->duplex = -1; 4718 sky2->speed = -1; 4719 sky2->advertising = sky2_supported_modes(hw); 4720 sky2->wol = wol; 4721 4722 spin_lock_init(&sky2->phy_lock); 4723 4724 sky2->tx_pending = TX_DEF_PENDING; 4725 sky2->tx_ring_size = roundup_ring_size(TX_DEF_PENDING); 4726 sky2->rx_pending = RX_DEF_PENDING; 4727 4728 hw->dev[port] = dev; 4729 4730 sky2->port = port; 4731 4732 dev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_TSO; 4733 4734 if (highmem) 4735 dev->features |= NETIF_F_HIGHDMA; 4736 4737 /* Enable receive hashing unless hardware is known broken */ 4738 if (!(hw->flags & SKY2_HW_RSS_BROKEN)) 4739 dev->hw_features |= NETIF_F_RXHASH; 4740 4741 if (!(hw->flags & SKY2_HW_VLAN_BROKEN)) { 4742 dev->hw_features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; 4743 dev->vlan_features |= SKY2_VLAN_OFFLOADS; 4744 } 4745 4746 dev->features |= dev->hw_features; 4747 4748 /* read the mac address */ 4749 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN); 4750 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); 4751 4752 return dev; 4753 } 4754 4755 static void __devinit sky2_show_addr(struct net_device *dev) 4756 { 4757 const struct sky2_port *sky2 = netdev_priv(dev); 4758 4759 netif_info(sky2, probe, dev, "addr %pM\n", dev->dev_addr); 4760 } 4761 4762 /* Handle software interrupt used during MSI test */ 4763 static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id) 4764 { 4765 struct sky2_hw *hw = dev_id; 4766 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2); 4767 4768 if (status == 0) 4769 return IRQ_NONE; 4770 4771 if (status & Y2_IS_IRQ_SW) { 4772 hw->flags |= SKY2_HW_USE_MSI; 4773 wake_up(&hw->msi_wait); 4774 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ); 4775 } 4776 sky2_write32(hw, B0_Y2_SP_ICR, 2); 4777 4778 return IRQ_HANDLED; 4779 } 4780 4781 /* Test interrupt path by forcing a a software IRQ */ 4782 static int __devinit sky2_test_msi(struct sky2_hw *hw) 4783 { 4784 struct pci_dev *pdev = hw->pdev; 4785 int err; 4786 4787 init_waitqueue_head(&hw->msi_wait); 4788 4789 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW); 4790 4791 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw); 4792 if (err) { 4793 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq); 4794 return err; 4795 } 4796 4797 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ); 4798 sky2_read8(hw, B0_CTST); 4799 4800 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10); 4801 4802 if (!(hw->flags & SKY2_HW_USE_MSI)) { 4803 /* MSI test failed, go back to INTx mode */ 4804 dev_info(&pdev->dev, "No interrupt generated using MSI, " 4805 "switching to INTx mode.\n"); 4806 4807 err = -EOPNOTSUPP; 4808 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ); 4809 } 4810 4811 sky2_write32(hw, B0_IMSK, 0); 4812 sky2_read32(hw, B0_IMSK); 4813 4814 free_irq(pdev->irq, hw); 4815 4816 return err; 4817 } 4818 4819 /* This driver supports yukon2 chipset only */ 4820 static const char *sky2_name(u8 chipid, char *buf, int sz) 4821 { 4822 const char *name[] = { 4823 "XL", /* 0xb3 */ 4824 "EC Ultra", /* 0xb4 */ 4825 "Extreme", /* 0xb5 */ 4826 "EC", /* 0xb6 */ 4827 "FE", /* 0xb7 */ 4828 "FE+", /* 0xb8 */ 4829 "Supreme", /* 0xb9 */ 4830 "UL 2", /* 0xba */ 4831 "Unknown", /* 0xbb */ 4832 "Optima", /* 0xbc */ 4833 "Optima Prime", /* 0xbd */ 4834 "Optima 2", /* 0xbe */ 4835 }; 4836 4837 if (chipid >= CHIP_ID_YUKON_XL && chipid <= CHIP_ID_YUKON_OP_2) 4838 strncpy(buf, name[chipid - CHIP_ID_YUKON_XL], sz); 4839 else 4840 snprintf(buf, sz, "(chip %#x)", chipid); 4841 return buf; 4842 } 4843 4844 static int __devinit sky2_probe(struct pci_dev *pdev, 4845 const struct pci_device_id *ent) 4846 { 4847 struct net_device *dev, *dev1; 4848 struct sky2_hw *hw; 4849 int err, using_dac = 0, wol_default; 4850 u32 reg; 4851 char buf1[16]; 4852 4853 err = pci_enable_device(pdev); 4854 if (err) { 4855 dev_err(&pdev->dev, "cannot enable PCI device\n"); 4856 goto err_out; 4857 } 4858 4859 /* Get configuration information 4860 * Note: only regular PCI config access once to test for HW issues 4861 * other PCI access through shared memory for speed and to 4862 * avoid MMCONFIG problems. 4863 */ 4864 err = pci_read_config_dword(pdev, PCI_DEV_REG2, ®); 4865 if (err) { 4866 dev_err(&pdev->dev, "PCI read config failed\n"); 4867 goto err_out; 4868 } 4869 4870 if (~reg == 0) { 4871 dev_err(&pdev->dev, "PCI configuration read error\n"); 4872 goto err_out; 4873 } 4874 4875 err = pci_request_regions(pdev, DRV_NAME); 4876 if (err) { 4877 dev_err(&pdev->dev, "cannot obtain PCI resources\n"); 4878 goto err_out_disable; 4879 } 4880 4881 pci_set_master(pdev); 4882 4883 if (sizeof(dma_addr_t) > sizeof(u32) && 4884 !(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))) { 4885 using_dac = 1; 4886 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); 4887 if (err < 0) { 4888 dev_err(&pdev->dev, "unable to obtain 64 bit DMA " 4889 "for consistent allocations\n"); 4890 goto err_out_free_regions; 4891 } 4892 } else { 4893 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 4894 if (err) { 4895 dev_err(&pdev->dev, "no usable DMA configuration\n"); 4896 goto err_out_free_regions; 4897 } 4898 } 4899 4900 4901 #ifdef __BIG_ENDIAN 4902 /* The sk98lin vendor driver uses hardware byte swapping but 4903 * this driver uses software swapping. 4904 */ 4905 reg &= ~PCI_REV_DESC; 4906 err = pci_write_config_dword(pdev, PCI_DEV_REG2, reg); 4907 if (err) { 4908 dev_err(&pdev->dev, "PCI write config failed\n"); 4909 goto err_out_free_regions; 4910 } 4911 #endif 4912 4913 wol_default = device_may_wakeup(&pdev->dev) ? WAKE_MAGIC : 0; 4914 4915 err = -ENOMEM; 4916 4917 hw = kzalloc(sizeof(*hw) + strlen(DRV_NAME "@pci:") 4918 + strlen(pci_name(pdev)) + 1, GFP_KERNEL); 4919 if (!hw) { 4920 dev_err(&pdev->dev, "cannot allocate hardware struct\n"); 4921 goto err_out_free_regions; 4922 } 4923 4924 hw->pdev = pdev; 4925 sprintf(hw->irq_name, DRV_NAME "@pci:%s", pci_name(pdev)); 4926 4927 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000); 4928 if (!hw->regs) { 4929 dev_err(&pdev->dev, "cannot map device registers\n"); 4930 goto err_out_free_hw; 4931 } 4932 4933 err = sky2_init(hw); 4934 if (err) 4935 goto err_out_iounmap; 4936 4937 /* ring for status responses */ 4938 hw->st_size = hw->ports * roundup_pow_of_two(3*RX_MAX_PENDING + TX_MAX_PENDING); 4939 hw->st_le = pci_alloc_consistent(pdev, hw->st_size * sizeof(struct sky2_status_le), 4940 &hw->st_dma); 4941 if (!hw->st_le) 4942 goto err_out_reset; 4943 4944 dev_info(&pdev->dev, "Yukon-2 %s chip revision %d\n", 4945 sky2_name(hw->chip_id, buf1, sizeof(buf1)), hw->chip_rev); 4946 4947 sky2_reset(hw); 4948 4949 dev = sky2_init_netdev(hw, 0, using_dac, wol_default); 4950 if (!dev) { 4951 err = -ENOMEM; 4952 goto err_out_free_pci; 4953 } 4954 4955 if (!disable_msi && pci_enable_msi(pdev) == 0) { 4956 err = sky2_test_msi(hw); 4957 if (err == -EOPNOTSUPP) 4958 pci_disable_msi(pdev); 4959 else if (err) 4960 goto err_out_free_netdev; 4961 } 4962 4963 err = register_netdev(dev); 4964 if (err) { 4965 dev_err(&pdev->dev, "cannot register net device\n"); 4966 goto err_out_free_netdev; 4967 } 4968 4969 netif_carrier_off(dev); 4970 4971 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT); 4972 4973 sky2_show_addr(dev); 4974 4975 if (hw->ports > 1) { 4976 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default); 4977 if (!dev1) { 4978 err = -ENOMEM; 4979 goto err_out_unregister; 4980 } 4981 4982 err = register_netdev(dev1); 4983 if (err) { 4984 dev_err(&pdev->dev, "cannot register second net device\n"); 4985 goto err_out_free_dev1; 4986 } 4987 4988 err = sky2_setup_irq(hw, hw->irq_name); 4989 if (err) 4990 goto err_out_unregister_dev1; 4991 4992 sky2_show_addr(dev1); 4993 } 4994 4995 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw); 4996 INIT_WORK(&hw->restart_work, sky2_restart); 4997 4998 pci_set_drvdata(pdev, hw); 4999 pdev->d3_delay = 150; 5000 5001 return 0; 5002 5003 err_out_unregister_dev1: 5004 unregister_netdev(dev1); 5005 err_out_free_dev1: 5006 free_netdev(dev1); 5007 err_out_unregister: 5008 if (hw->flags & SKY2_HW_USE_MSI) 5009 pci_disable_msi(pdev); 5010 unregister_netdev(dev); 5011 err_out_free_netdev: 5012 free_netdev(dev); 5013 err_out_free_pci: 5014 pci_free_consistent(pdev, hw->st_size * sizeof(struct sky2_status_le), 5015 hw->st_le, hw->st_dma); 5016 err_out_reset: 5017 sky2_write8(hw, B0_CTST, CS_RST_SET); 5018 err_out_iounmap: 5019 iounmap(hw->regs); 5020 err_out_free_hw: 5021 kfree(hw); 5022 err_out_free_regions: 5023 pci_release_regions(pdev); 5024 err_out_disable: 5025 pci_disable_device(pdev); 5026 err_out: 5027 pci_set_drvdata(pdev, NULL); 5028 return err; 5029 } 5030 5031 static void __devexit sky2_remove(struct pci_dev *pdev) 5032 { 5033 struct sky2_hw *hw = pci_get_drvdata(pdev); 5034 int i; 5035 5036 if (!hw) 5037 return; 5038 5039 del_timer_sync(&hw->watchdog_timer); 5040 cancel_work_sync(&hw->restart_work); 5041 5042 for (i = hw->ports-1; i >= 0; --i) 5043 unregister_netdev(hw->dev[i]); 5044 5045 sky2_write32(hw, B0_IMSK, 0); 5046 sky2_read32(hw, B0_IMSK); 5047 5048 sky2_power_aux(hw); 5049 5050 sky2_write8(hw, B0_CTST, CS_RST_SET); 5051 sky2_read8(hw, B0_CTST); 5052 5053 if (hw->ports > 1) { 5054 napi_disable(&hw->napi); 5055 free_irq(pdev->irq, hw); 5056 } 5057 5058 if (hw->flags & SKY2_HW_USE_MSI) 5059 pci_disable_msi(pdev); 5060 pci_free_consistent(pdev, hw->st_size * sizeof(struct sky2_status_le), 5061 hw->st_le, hw->st_dma); 5062 pci_release_regions(pdev); 5063 pci_disable_device(pdev); 5064 5065 for (i = hw->ports-1; i >= 0; --i) 5066 free_netdev(hw->dev[i]); 5067 5068 iounmap(hw->regs); 5069 kfree(hw); 5070 5071 pci_set_drvdata(pdev, NULL); 5072 } 5073 5074 static int sky2_suspend(struct device *dev) 5075 { 5076 struct pci_dev *pdev = to_pci_dev(dev); 5077 struct sky2_hw *hw = pci_get_drvdata(pdev); 5078 int i; 5079 5080 if (!hw) 5081 return 0; 5082 5083 del_timer_sync(&hw->watchdog_timer); 5084 cancel_work_sync(&hw->restart_work); 5085 5086 rtnl_lock(); 5087 5088 sky2_all_down(hw); 5089 for (i = 0; i < hw->ports; i++) { 5090 struct net_device *dev = hw->dev[i]; 5091 struct sky2_port *sky2 = netdev_priv(dev); 5092 5093 if (sky2->wol) 5094 sky2_wol_init(sky2); 5095 } 5096 5097 sky2_power_aux(hw); 5098 rtnl_unlock(); 5099 5100 return 0; 5101 } 5102 5103 #ifdef CONFIG_PM_SLEEP 5104 static int sky2_resume(struct device *dev) 5105 { 5106 struct pci_dev *pdev = to_pci_dev(dev); 5107 struct sky2_hw *hw = pci_get_drvdata(pdev); 5108 int err; 5109 5110 if (!hw) 5111 return 0; 5112 5113 /* Re-enable all clocks */ 5114 err = pci_write_config_dword(pdev, PCI_DEV_REG3, 0); 5115 if (err) { 5116 dev_err(&pdev->dev, "PCI write config failed\n"); 5117 goto out; 5118 } 5119 5120 rtnl_lock(); 5121 sky2_reset(hw); 5122 sky2_all_up(hw); 5123 rtnl_unlock(); 5124 5125 return 0; 5126 out: 5127 5128 dev_err(&pdev->dev, "resume failed (%d)\n", err); 5129 pci_disable_device(pdev); 5130 return err; 5131 } 5132 5133 static SIMPLE_DEV_PM_OPS(sky2_pm_ops, sky2_suspend, sky2_resume); 5134 #define SKY2_PM_OPS (&sky2_pm_ops) 5135 5136 #else 5137 5138 #define SKY2_PM_OPS NULL 5139 #endif 5140 5141 static void sky2_shutdown(struct pci_dev *pdev) 5142 { 5143 sky2_suspend(&pdev->dev); 5144 pci_wake_from_d3(pdev, device_may_wakeup(&pdev->dev)); 5145 pci_set_power_state(pdev, PCI_D3hot); 5146 } 5147 5148 static struct pci_driver sky2_driver = { 5149 .name = DRV_NAME, 5150 .id_table = sky2_id_table, 5151 .probe = sky2_probe, 5152 .remove = __devexit_p(sky2_remove), 5153 .shutdown = sky2_shutdown, 5154 .driver.pm = SKY2_PM_OPS, 5155 }; 5156 5157 static int __init sky2_init_module(void) 5158 { 5159 pr_info("driver version " DRV_VERSION "\n"); 5160 5161 sky2_debug_init(); 5162 return pci_register_driver(&sky2_driver); 5163 } 5164 5165 static void __exit sky2_cleanup_module(void) 5166 { 5167 pci_unregister_driver(&sky2_driver); 5168 sky2_debug_cleanup(); 5169 } 5170 5171 module_init(sky2_init_module); 5172 module_exit(sky2_cleanup_module); 5173 5174 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver"); 5175 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>"); 5176 MODULE_LICENSE("GPL"); 5177 MODULE_VERSION(DRV_VERSION); 5178