1ae06c70bSJeff Kirsher /* SPDX-License-Identifier: GPL-2.0 */ 2*51dce24bSJeff Kirsher /* Copyright(c) 1999 - 2018 Intel Corporation. */ 3dee1ad47SJeff Kirsher 4dee1ad47SJeff Kirsher #ifndef _DCB_CONFIG_H_ 5dee1ad47SJeff Kirsher #define _DCB_CONFIG_H_ 6dee1ad47SJeff Kirsher 74c09f3a0SJohn Fastabend #include <linux/dcbnl.h> 8dee1ad47SJeff Kirsher #include "ixgbe_type.h" 9dee1ad47SJeff Kirsher 10dee1ad47SJeff Kirsher /* DCB data structures */ 11dee1ad47SJeff Kirsher 12dee1ad47SJeff Kirsher #define IXGBE_MAX_PACKET_BUFFERS 8 13dee1ad47SJeff Kirsher #define MAX_USER_PRIORITY 8 14dee1ad47SJeff Kirsher #define MAX_BW_GROUP 8 15dee1ad47SJeff Kirsher #define BW_PERCENT 100 16dee1ad47SJeff Kirsher 17dee1ad47SJeff Kirsher #define DCB_TX_CONFIG 0 18dee1ad47SJeff Kirsher #define DCB_RX_CONFIG 1 19dee1ad47SJeff Kirsher 20dee1ad47SJeff Kirsher /* DCB error Codes */ 21dee1ad47SJeff Kirsher #define DCB_SUCCESS 0 22dee1ad47SJeff Kirsher #define DCB_ERR_CONFIG -1 23dee1ad47SJeff Kirsher #define DCB_ERR_PARAM -2 24dee1ad47SJeff Kirsher 25dee1ad47SJeff Kirsher /* Transmit and receive Errors */ 26dee1ad47SJeff Kirsher /* Error in bandwidth group allocation */ 27dee1ad47SJeff Kirsher #define DCB_ERR_BW_GROUP -3 28dee1ad47SJeff Kirsher /* Error in traffic class bandwidth allocation */ 29dee1ad47SJeff Kirsher #define DCB_ERR_TC_BW -4 30dee1ad47SJeff Kirsher /* Traffic class has both link strict and group strict enabled */ 31dee1ad47SJeff Kirsher #define DCB_ERR_LS_GS -5 32dee1ad47SJeff Kirsher /* Link strict traffic class has non zero bandwidth */ 33dee1ad47SJeff Kirsher #define DCB_ERR_LS_BW_NONZERO -6 34dee1ad47SJeff Kirsher /* Link strict bandwidth group has non zero bandwidth */ 35dee1ad47SJeff Kirsher #define DCB_ERR_LS_BWG_NONZERO -7 36dee1ad47SJeff Kirsher /* Traffic class has zero bandwidth */ 37dee1ad47SJeff Kirsher #define DCB_ERR_TC_BW_ZERO -8 38dee1ad47SJeff Kirsher 39dee1ad47SJeff Kirsher #define DCB_NOT_IMPLEMENTED 0x7FFFFFFF 40dee1ad47SJeff Kirsher 41dee1ad47SJeff Kirsher struct dcb_pfc_tc_debug { 42dee1ad47SJeff Kirsher u8 tc; 43dee1ad47SJeff Kirsher u8 pause_status; 44dee1ad47SJeff Kirsher u64 pause_quanta; 45dee1ad47SJeff Kirsher }; 46dee1ad47SJeff Kirsher 47dee1ad47SJeff Kirsher enum strict_prio_type { 48dee1ad47SJeff Kirsher prio_none = 0, 49dee1ad47SJeff Kirsher prio_group, 50dee1ad47SJeff Kirsher prio_link 51dee1ad47SJeff Kirsher }; 52dee1ad47SJeff Kirsher 53dee1ad47SJeff Kirsher /* DCB capability definitions */ 54dee1ad47SJeff Kirsher #define IXGBE_DCB_PG_SUPPORT 0x00000001 55dee1ad47SJeff Kirsher #define IXGBE_DCB_PFC_SUPPORT 0x00000002 56dee1ad47SJeff Kirsher #define IXGBE_DCB_BCN_SUPPORT 0x00000004 57dee1ad47SJeff Kirsher #define IXGBE_DCB_UP2TC_SUPPORT 0x00000008 58dee1ad47SJeff Kirsher #define IXGBE_DCB_GSP_SUPPORT 0x00000010 59dee1ad47SJeff Kirsher 60dee1ad47SJeff Kirsher #define IXGBE_DCB_8_TC_SUPPORT 0x80 61dee1ad47SJeff Kirsher 62dee1ad47SJeff Kirsher struct dcb_support { 63dee1ad47SJeff Kirsher /* DCB capabilities */ 64dee1ad47SJeff Kirsher u32 capabilities; 65dee1ad47SJeff Kirsher 66dee1ad47SJeff Kirsher /* Each bit represents a number of TCs configurable in the hw. 67dee1ad47SJeff Kirsher * If 8 traffic classes can be configured, the value is 0x80. 68dee1ad47SJeff Kirsher */ 69dee1ad47SJeff Kirsher u8 traffic_classes; 70dee1ad47SJeff Kirsher u8 pfc_traffic_classes; 71dee1ad47SJeff Kirsher }; 72dee1ad47SJeff Kirsher 73dee1ad47SJeff Kirsher /* Traffic class bandwidth allocation per direction */ 74dee1ad47SJeff Kirsher struct tc_bw_alloc { 75dee1ad47SJeff Kirsher u8 bwg_id; /* Bandwidth Group (BWG) ID */ 76dee1ad47SJeff Kirsher u8 bwg_percent; /* % of BWG's bandwidth */ 77dee1ad47SJeff Kirsher u8 link_percent; /* % of link bandwidth */ 78dee1ad47SJeff Kirsher u8 up_to_tc_bitmap; /* User Priority to Traffic Class mapping */ 79dee1ad47SJeff Kirsher u16 data_credits_refill; /* Credit refill amount in 64B granularity */ 80dee1ad47SJeff Kirsher u16 data_credits_max; /* Max credits for a configured packet buffer 81dee1ad47SJeff Kirsher * in 64B granularity.*/ 82dee1ad47SJeff Kirsher enum strict_prio_type prio_type; /* Link or Group Strict Priority */ 83dee1ad47SJeff Kirsher }; 84dee1ad47SJeff Kirsher 85dee1ad47SJeff Kirsher enum dcb_pfc_type { 86dee1ad47SJeff Kirsher pfc_disabled = 0, 87dee1ad47SJeff Kirsher pfc_enabled_full, 88dee1ad47SJeff Kirsher pfc_enabled_tx, 89dee1ad47SJeff Kirsher pfc_enabled_rx 90dee1ad47SJeff Kirsher }; 91dee1ad47SJeff Kirsher 92dee1ad47SJeff Kirsher /* Traffic class configuration */ 93dee1ad47SJeff Kirsher struct tc_configuration { 94dee1ad47SJeff Kirsher struct tc_bw_alloc path[2]; /* One each for Tx/Rx */ 95dee1ad47SJeff Kirsher enum dcb_pfc_type dcb_pfc; /* Class based flow control setting */ 96dee1ad47SJeff Kirsher 97dee1ad47SJeff Kirsher u16 desc_credits_max; /* For Tx Descriptor arbitration */ 98dee1ad47SJeff Kirsher u8 tc; /* Traffic class (TC) */ 99dee1ad47SJeff Kirsher }; 100dee1ad47SJeff Kirsher 101dee1ad47SJeff Kirsher struct dcb_num_tcs { 102dee1ad47SJeff Kirsher u8 pg_tcs; 103dee1ad47SJeff Kirsher u8 pfc_tcs; 104dee1ad47SJeff Kirsher }; 105dee1ad47SJeff Kirsher 106dee1ad47SJeff Kirsher struct ixgbe_dcb_config { 107dee1ad47SJeff Kirsher struct dcb_support support; 108dee1ad47SJeff Kirsher struct dcb_num_tcs num_tcs; 109dee1ad47SJeff Kirsher struct tc_configuration tc_config[MAX_TRAFFIC_CLASS]; 110dee1ad47SJeff Kirsher u8 bw_percentage[2][MAX_BW_GROUP]; /* One each for Tx/Rx */ 111dee1ad47SJeff Kirsher bool pfc_mode_enable; 112dee1ad47SJeff Kirsher 113dee1ad47SJeff Kirsher u32 dcb_cfg_version; /* Not used...OS-specific? */ 114dee1ad47SJeff Kirsher u32 link_speed; /* For bandwidth allocation validation purpose */ 115dee1ad47SJeff Kirsher }; 116dee1ad47SJeff Kirsher 117dee1ad47SJeff Kirsher /* DCB driver APIs */ 118dee1ad47SJeff Kirsher void ixgbe_dcb_unpack_pfc(struct ixgbe_dcb_config *cfg, u8 *pfc_en); 119dee1ad47SJeff Kirsher void ixgbe_dcb_unpack_refill(struct ixgbe_dcb_config *, int, u16 *); 120dee1ad47SJeff Kirsher void ixgbe_dcb_unpack_max(struct ixgbe_dcb_config *, u16 *); 121dee1ad47SJeff Kirsher void ixgbe_dcb_unpack_bwgid(struct ixgbe_dcb_config *, int, u8 *); 122dee1ad47SJeff Kirsher void ixgbe_dcb_unpack_prio(struct ixgbe_dcb_config *, int, u8 *); 12332701dc2SJohn Fastabend void ixgbe_dcb_unpack_map(struct ixgbe_dcb_config *, int, u8 *); 12402debdc9SAlexander Duyck u8 ixgbe_dcb_get_tc_from_up(struct ixgbe_dcb_config *, int, u8); 125dee1ad47SJeff Kirsher 126dee1ad47SJeff Kirsher /* DCB credits calculation */ 127dee1ad47SJeff Kirsher s32 ixgbe_dcb_calculate_tc_credits(struct ixgbe_hw *, 128dee1ad47SJeff Kirsher struct ixgbe_dcb_config *, int, u8); 129dee1ad47SJeff Kirsher 130dee1ad47SJeff Kirsher /* DCB hw initialization */ 1314c09f3a0SJohn Fastabend s32 ixgbe_dcb_hw_ets(struct ixgbe_hw *hw, struct ieee_ets *ets, int max); 132dee1ad47SJeff Kirsher s32 ixgbe_dcb_hw_ets_config(struct ixgbe_hw *hw, u16 *refill, u16 *max, 133dee1ad47SJeff Kirsher u8 *bwg_id, u8 *prio_type, u8 *tc_prio); 13432701dc2SJohn Fastabend s32 ixgbe_dcb_hw_pfc_config(struct ixgbe_hw *hw, u8 pfc_en, u8 *tc_prio); 135dee1ad47SJeff Kirsher s32 ixgbe_dcb_hw_config(struct ixgbe_hw *, struct ixgbe_dcb_config *); 136dee1ad47SJeff Kirsher 137e8915bebSAmir Hanania void ixgbe_dcb_read_rtrup2tc(struct ixgbe_hw *hw, u8 *map); 138e8915bebSAmir Hanania 139dee1ad47SJeff Kirsher /* DCB definitions for credit calculation */ 140dee1ad47SJeff Kirsher #define DCB_CREDIT_QUANTUM 64 /* DCB Quantum */ 141dee1ad47SJeff Kirsher #define MAX_CREDIT_REFILL 511 /* 0x1FF * 64B = 32704B */ 142dee1ad47SJeff Kirsher #define DCB_MAX_TSO_SIZE (32*1024) /* MAX TSO packet size supported in DCB mode */ 143dee1ad47SJeff Kirsher #define MINIMUM_CREDIT_FOR_TSO (DCB_MAX_TSO_SIZE/64 + 1) /* 513 for 32KB TSO packet */ 144dee1ad47SJeff Kirsher #define MAX_CREDIT 4095 /* Maximum credit supported: 256KB * 1204 / 64B */ 145dee1ad47SJeff Kirsher 146dee1ad47SJeff Kirsher #endif /* _DCB_CONFIG_H */ 147