1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2018 Intel Corporation */ 3 4 #ifndef _IGC_H_ 5 #define _IGC_H_ 6 7 #include <linux/kobject.h> 8 #include <linux/pci.h> 9 #include <linux/netdevice.h> 10 #include <linux/vmalloc.h> 11 #include <linux/ethtool.h> 12 #include <linux/sctp.h> 13 #include <linux/ptp_clock_kernel.h> 14 #include <linux/timecounter.h> 15 #include <linux/net_tstamp.h> 16 #include <linux/bitfield.h> 17 #include <linux/hrtimer.h> 18 #include <net/xdp.h> 19 20 #include "igc_hw.h" 21 22 void igc_ethtool_set_ops(struct net_device *); 23 24 /* Transmit and receive queues */ 25 #define IGC_MAX_RX_QUEUES 4 26 #define IGC_MAX_TX_QUEUES 4 27 28 #define MAX_Q_VECTORS 8 29 #define MAX_STD_JUMBO_FRAME_SIZE 9216 30 31 #define MAX_ETYPE_FILTER 8 32 #define IGC_RETA_SIZE 128 33 34 /* SDP support */ 35 #define IGC_N_EXTTS 2 36 #define IGC_N_PEROUT 2 37 #define IGC_N_SDP 4 38 39 #define MAX_FLEX_FILTER 32 40 41 enum igc_mac_filter_type { 42 IGC_MAC_FILTER_TYPE_DST = 0, 43 IGC_MAC_FILTER_TYPE_SRC 44 }; 45 46 struct igc_tx_queue_stats { 47 u64 packets; 48 u64 bytes; 49 u64 restart_queue; 50 u64 restart_queue2; 51 }; 52 53 struct igc_rx_queue_stats { 54 u64 packets; 55 u64 bytes; 56 u64 drops; 57 u64 csum_err; 58 u64 alloc_failed; 59 }; 60 61 struct igc_rx_packet_stats { 62 u64 ipv4_packets; /* IPv4 headers processed */ 63 u64 ipv4e_packets; /* IPv4E headers with extensions processed */ 64 u64 ipv6_packets; /* IPv6 headers processed */ 65 u64 ipv6e_packets; /* IPv6E headers with extensions processed */ 66 u64 tcp_packets; /* TCP headers processed */ 67 u64 udp_packets; /* UDP headers processed */ 68 u64 sctp_packets; /* SCTP headers processed */ 69 u64 nfs_packets; /* NFS headers processe */ 70 u64 other_packets; 71 }; 72 73 struct igc_ring_container { 74 struct igc_ring *ring; /* pointer to linked list of rings */ 75 unsigned int total_bytes; /* total bytes processed this int */ 76 unsigned int total_packets; /* total packets processed this int */ 77 u16 work_limit; /* total work allowed per interrupt */ 78 u8 count; /* total number of rings in vector */ 79 u8 itr; /* current ITR setting for ring */ 80 }; 81 82 struct igc_ring { 83 struct igc_q_vector *q_vector; /* backlink to q_vector */ 84 struct net_device *netdev; /* back pointer to net_device */ 85 struct device *dev; /* device for dma mapping */ 86 union { /* array of buffer info structs */ 87 struct igc_tx_buffer *tx_buffer_info; 88 struct igc_rx_buffer *rx_buffer_info; 89 }; 90 void *desc; /* descriptor ring memory */ 91 unsigned long flags; /* ring specific flags */ 92 void __iomem *tail; /* pointer to ring tail register */ 93 dma_addr_t dma; /* phys address of the ring */ 94 unsigned int size; /* length of desc. ring in bytes */ 95 96 u16 count; /* number of desc. in the ring */ 97 u8 queue_index; /* logical index of the ring*/ 98 u8 reg_idx; /* physical index of the ring */ 99 bool launchtime_enable; /* true if LaunchTime is enabled */ 100 ktime_t last_tx_cycle; /* end of the cycle with a launchtime transmission */ 101 ktime_t last_ff_cycle; /* Last cycle with an active first flag */ 102 103 u32 start_time; 104 u32 end_time; 105 u32 max_sdu; 106 bool oper_gate_closed; /* Operating gate. True if the TX Queue is closed */ 107 bool admin_gate_closed; /* Future gate. True if the TX Queue will be closed */ 108 109 /* CBS parameters */ 110 bool cbs_enable; /* indicates if CBS is enabled */ 111 s32 idleslope; /* idleSlope in kbps */ 112 s32 sendslope; /* sendSlope in kbps */ 113 s32 hicredit; /* hiCredit in bytes */ 114 s32 locredit; /* loCredit in bytes */ 115 116 /* everything past this point are written often */ 117 u16 next_to_clean; 118 u16 next_to_use; 119 u16 next_to_alloc; 120 121 union { 122 /* TX */ 123 struct { 124 struct igc_tx_queue_stats tx_stats; 125 struct u64_stats_sync tx_syncp; 126 struct u64_stats_sync tx_syncp2; 127 }; 128 /* RX */ 129 struct { 130 struct igc_rx_queue_stats rx_stats; 131 struct igc_rx_packet_stats pkt_stats; 132 struct u64_stats_sync rx_syncp; 133 struct sk_buff *skb; 134 }; 135 }; 136 137 struct xdp_rxq_info xdp_rxq; 138 struct xsk_buff_pool *xsk_pool; 139 } ____cacheline_internodealigned_in_smp; 140 141 /* Board specific private data structure */ 142 struct igc_adapter { 143 struct net_device *netdev; 144 145 struct ethtool_eee eee; 146 u16 eee_advert; 147 148 unsigned long state; 149 unsigned int flags; 150 unsigned int num_q_vectors; 151 152 struct msix_entry *msix_entries; 153 154 /* TX */ 155 u16 tx_work_limit; 156 u32 tx_timeout_count; 157 int num_tx_queues; 158 struct igc_ring *tx_ring[IGC_MAX_TX_QUEUES]; 159 160 /* RX */ 161 int num_rx_queues; 162 struct igc_ring *rx_ring[IGC_MAX_RX_QUEUES]; 163 164 struct timer_list watchdog_timer; 165 struct timer_list dma_err_timer; 166 struct timer_list phy_info_timer; 167 struct hrtimer hrtimer; 168 169 u32 wol; 170 u32 en_mng_pt; 171 u16 link_speed; 172 u16 link_duplex; 173 174 u8 port_num; 175 176 u8 __iomem *io_addr; 177 /* Interrupt Throttle Rate */ 178 u32 rx_itr_setting; 179 u32 tx_itr_setting; 180 181 struct work_struct reset_task; 182 struct work_struct watchdog_task; 183 struct work_struct dma_err_task; 184 bool fc_autoneg; 185 186 u8 tx_timeout_factor; 187 188 int msg_enable; 189 u32 max_frame_size; 190 u32 min_frame_size; 191 192 int tc_setup_type; 193 ktime_t base_time; 194 ktime_t cycle_time; 195 bool taprio_offload_enable; 196 u32 qbv_config_change_errors; 197 bool qbv_transition; 198 unsigned int qbv_count; 199 200 /* OS defined structs */ 201 struct pci_dev *pdev; 202 /* lock for statistics */ 203 spinlock_t stats64_lock; 204 struct rtnl_link_stats64 stats64; 205 206 /* structs defined in igc_hw.h */ 207 struct igc_hw hw; 208 struct igc_hw_stats stats; 209 210 struct igc_q_vector *q_vector[MAX_Q_VECTORS]; 211 u32 eims_enable_mask; 212 u32 eims_other; 213 214 u16 tx_ring_count; 215 u16 rx_ring_count; 216 217 u32 tx_hwtstamp_timeouts; 218 u32 tx_hwtstamp_skipped; 219 u32 rx_hwtstamp_cleared; 220 221 u32 rss_queues; 222 u32 rss_indir_tbl_init; 223 224 /* Any access to elements in nfc_rule_list is protected by the 225 * nfc_rule_lock. 226 */ 227 struct mutex nfc_rule_lock; 228 struct list_head nfc_rule_list; 229 unsigned int nfc_rule_count; 230 231 u8 rss_indir_tbl[IGC_RETA_SIZE]; 232 233 unsigned long link_check_timeout; 234 struct igc_info ei; 235 236 u32 test_icr; 237 238 struct ptp_clock *ptp_clock; 239 struct ptp_clock_info ptp_caps; 240 /* Access to ptp_tx_skb and ptp_tx_start are protected by the 241 * ptp_tx_lock. 242 */ 243 spinlock_t ptp_tx_lock; 244 struct sk_buff *ptp_tx_skb; 245 struct hwtstamp_config tstamp_config; 246 unsigned long ptp_tx_start; 247 unsigned int ptp_flags; 248 /* System time value lock */ 249 spinlock_t tmreg_lock; 250 struct cyclecounter cc; 251 struct timecounter tc; 252 struct timespec64 prev_ptp_time; /* Pre-reset PTP clock */ 253 ktime_t ptp_reset_start; /* Reset time in clock mono */ 254 struct system_time_snapshot snapshot; 255 256 char fw_version[32]; 257 258 struct bpf_prog *xdp_prog; 259 260 bool pps_sys_wrap_on; 261 262 struct ptp_pin_desc sdp_config[IGC_N_SDP]; 263 struct { 264 struct timespec64 start; 265 struct timespec64 period; 266 } perout[IGC_N_PEROUT]; 267 }; 268 269 void igc_up(struct igc_adapter *adapter); 270 void igc_down(struct igc_adapter *adapter); 271 int igc_open(struct net_device *netdev); 272 int igc_close(struct net_device *netdev); 273 int igc_setup_tx_resources(struct igc_ring *ring); 274 int igc_setup_rx_resources(struct igc_ring *ring); 275 void igc_free_tx_resources(struct igc_ring *ring); 276 void igc_free_rx_resources(struct igc_ring *ring); 277 unsigned int igc_get_max_rss_queues(struct igc_adapter *adapter); 278 void igc_set_flag_queue_pairs(struct igc_adapter *adapter, 279 const u32 max_rss_queues); 280 int igc_reinit_queues(struct igc_adapter *adapter); 281 void igc_write_rss_indir_tbl(struct igc_adapter *adapter); 282 bool igc_has_link(struct igc_adapter *adapter); 283 void igc_reset(struct igc_adapter *adapter); 284 void igc_update_stats(struct igc_adapter *adapter); 285 void igc_disable_rx_ring(struct igc_ring *ring); 286 void igc_enable_rx_ring(struct igc_ring *ring); 287 void igc_disable_tx_ring(struct igc_ring *ring); 288 void igc_enable_tx_ring(struct igc_ring *ring); 289 int igc_xsk_wakeup(struct net_device *dev, u32 queue_id, u32 flags); 290 291 /* igc_dump declarations */ 292 void igc_rings_dump(struct igc_adapter *adapter); 293 void igc_regs_dump(struct igc_adapter *adapter); 294 295 extern char igc_driver_name[]; 296 297 #define IGC_REGS_LEN 740 298 299 /* flags controlling PTP/1588 function */ 300 #define IGC_PTP_ENABLED BIT(0) 301 302 /* Flags definitions */ 303 #define IGC_FLAG_HAS_MSI BIT(0) 304 #define IGC_FLAG_QUEUE_PAIRS BIT(3) 305 #define IGC_FLAG_DMAC BIT(4) 306 #define IGC_FLAG_PTP BIT(8) 307 #define IGC_FLAG_WOL_SUPPORTED BIT(8) 308 #define IGC_FLAG_NEED_LINK_UPDATE BIT(9) 309 #define IGC_FLAG_HAS_MSIX BIT(13) 310 #define IGC_FLAG_EEE BIT(14) 311 #define IGC_FLAG_VLAN_PROMISC BIT(15) 312 #define IGC_FLAG_RX_LEGACY BIT(16) 313 #define IGC_FLAG_TSN_QBV_ENABLED BIT(17) 314 #define IGC_FLAG_TSN_QAV_ENABLED BIT(18) 315 316 #define IGC_FLAG_TSN_ANY_ENABLED \ 317 (IGC_FLAG_TSN_QBV_ENABLED | IGC_FLAG_TSN_QAV_ENABLED) 318 319 #define IGC_FLAG_RSS_FIELD_IPV4_UDP BIT(6) 320 #define IGC_FLAG_RSS_FIELD_IPV6_UDP BIT(7) 321 322 #define IGC_MRQC_ENABLE_RSS_MQ 0x00000002 323 #define IGC_MRQC_RSS_FIELD_IPV4_UDP 0x00400000 324 #define IGC_MRQC_RSS_FIELD_IPV6_UDP 0x00800000 325 326 /* RX-desc Write-Back format RSS Type's */ 327 enum igc_rss_type_num { 328 IGC_RSS_TYPE_NO_HASH = 0, 329 IGC_RSS_TYPE_HASH_TCP_IPV4 = 1, 330 IGC_RSS_TYPE_HASH_IPV4 = 2, 331 IGC_RSS_TYPE_HASH_TCP_IPV6 = 3, 332 IGC_RSS_TYPE_HASH_IPV6_EX = 4, 333 IGC_RSS_TYPE_HASH_IPV6 = 5, 334 IGC_RSS_TYPE_HASH_TCP_IPV6_EX = 6, 335 IGC_RSS_TYPE_HASH_UDP_IPV4 = 7, 336 IGC_RSS_TYPE_HASH_UDP_IPV6 = 8, 337 IGC_RSS_TYPE_HASH_UDP_IPV6_EX = 9, 338 IGC_RSS_TYPE_MAX = 10, 339 }; 340 #define IGC_RSS_TYPE_MAX_TABLE 16 341 #define IGC_RSS_TYPE_MASK GENMASK(3,0) /* 4-bits (3:0) = mask 0x0F */ 342 343 /* igc_rss_type - Rx descriptor RSS type field */ 344 static inline u32 igc_rss_type(const union igc_adv_rx_desc *rx_desc) 345 { 346 /* RSS Type 4-bits (3:0) number: 0-9 (above 9 is reserved) 347 * Accessing the same bits via u16 (wb.lower.lo_dword.hs_rss.pkt_info) 348 * is slightly slower than via u32 (wb.lower.lo_dword.data) 349 */ 350 return le32_get_bits(rx_desc->wb.lower.lo_dword.data, IGC_RSS_TYPE_MASK); 351 } 352 353 /* Interrupt defines */ 354 #define IGC_START_ITR 648 /* ~6000 ints/sec */ 355 #define IGC_4K_ITR 980 356 #define IGC_20K_ITR 196 357 #define IGC_70K_ITR 56 358 359 #define IGC_DEFAULT_ITR 3 /* dynamic */ 360 #define IGC_MAX_ITR_USECS 10000 361 #define IGC_MIN_ITR_USECS 10 362 #define NON_Q_VECTORS 1 363 #define MAX_MSIX_ENTRIES 10 364 365 /* TX/RX descriptor defines */ 366 #define IGC_DEFAULT_TXD 256 367 #define IGC_DEFAULT_TX_WORK 128 368 #define IGC_MIN_TXD 80 369 #define IGC_MAX_TXD 4096 370 371 #define IGC_DEFAULT_RXD 256 372 #define IGC_MIN_RXD 80 373 #define IGC_MAX_RXD 4096 374 375 /* Supported Rx Buffer Sizes */ 376 #define IGC_RXBUFFER_256 256 377 #define IGC_RXBUFFER_2048 2048 378 #define IGC_RXBUFFER_3072 3072 379 380 #define AUTO_ALL_MODES 0 381 #define IGC_RX_HDR_LEN IGC_RXBUFFER_256 382 383 /* Transmit and receive latency (for PTP timestamps) */ 384 #define IGC_I225_TX_LATENCY_10 240 385 #define IGC_I225_TX_LATENCY_100 58 386 #define IGC_I225_TX_LATENCY_1000 80 387 #define IGC_I225_TX_LATENCY_2500 1325 388 #define IGC_I225_RX_LATENCY_10 6450 389 #define IGC_I225_RX_LATENCY_100 185 390 #define IGC_I225_RX_LATENCY_1000 300 391 #define IGC_I225_RX_LATENCY_2500 1485 392 393 /* RX and TX descriptor control thresholds. 394 * PTHRESH - MAC will consider prefetch if it has fewer than this number of 395 * descriptors available in its onboard memory. 396 * Setting this to 0 disables RX descriptor prefetch. 397 * HTHRESH - MAC will only prefetch if there are at least this many descriptors 398 * available in host memory. 399 * If PTHRESH is 0, this should also be 0. 400 * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back 401 * descriptors until either it has this many to write back, or the 402 * ITR timer expires. 403 */ 404 #define IGC_RX_PTHRESH 8 405 #define IGC_RX_HTHRESH 8 406 #define IGC_TX_PTHRESH 8 407 #define IGC_TX_HTHRESH 1 408 #define IGC_RX_WTHRESH 4 409 #define IGC_TX_WTHRESH 16 410 411 #define IGC_RX_DMA_ATTR \ 412 (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING) 413 414 #define IGC_TS_HDR_LEN 16 415 416 #define IGC_SKB_PAD (NET_SKB_PAD + NET_IP_ALIGN) 417 418 #if (PAGE_SIZE < 8192) 419 #define IGC_MAX_FRAME_BUILD_SKB \ 420 (SKB_WITH_OVERHEAD(IGC_RXBUFFER_2048) - IGC_SKB_PAD - IGC_TS_HDR_LEN) 421 #else 422 #define IGC_MAX_FRAME_BUILD_SKB (IGC_RXBUFFER_2048 - IGC_TS_HDR_LEN) 423 #endif 424 425 /* How many Rx Buffers do we bundle into one write to the hardware ? */ 426 #define IGC_RX_BUFFER_WRITE 16 /* Must be power of 2 */ 427 428 /* VLAN info */ 429 #define IGC_TX_FLAGS_VLAN_MASK 0xffff0000 430 #define IGC_TX_FLAGS_VLAN_SHIFT 16 431 432 /* igc_test_staterr - tests bits within Rx descriptor status and error fields */ 433 static inline __le32 igc_test_staterr(union igc_adv_rx_desc *rx_desc, 434 const u32 stat_err_bits) 435 { 436 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits); 437 } 438 439 enum igc_state_t { 440 __IGC_TESTING, 441 __IGC_RESETTING, 442 __IGC_DOWN, 443 }; 444 445 enum igc_tx_flags { 446 /* cmd_type flags */ 447 IGC_TX_FLAGS_VLAN = 0x01, 448 IGC_TX_FLAGS_TSO = 0x02, 449 IGC_TX_FLAGS_TSTAMP = 0x04, 450 451 /* olinfo flags */ 452 IGC_TX_FLAGS_IPV4 = 0x10, 453 IGC_TX_FLAGS_CSUM = 0x20, 454 }; 455 456 enum igc_boards { 457 board_base, 458 }; 459 460 /* The largest size we can write to the descriptor is 65535. In order to 461 * maintain a power of two alignment we have to limit ourselves to 32K. 462 */ 463 #define IGC_MAX_TXD_PWR 15 464 #define IGC_MAX_DATA_PER_TXD BIT(IGC_MAX_TXD_PWR) 465 466 /* Tx Descriptors needed, worst case */ 467 #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IGC_MAX_DATA_PER_TXD) 468 #define DESC_NEEDED (MAX_SKB_FRAGS + 4) 469 470 enum igc_tx_buffer_type { 471 IGC_TX_BUFFER_TYPE_SKB, 472 IGC_TX_BUFFER_TYPE_XDP, 473 IGC_TX_BUFFER_TYPE_XSK, 474 }; 475 476 /* wrapper around a pointer to a socket buffer, 477 * so a DMA handle can be stored along with the buffer 478 */ 479 struct igc_tx_buffer { 480 union igc_adv_tx_desc *next_to_watch; 481 unsigned long time_stamp; 482 enum igc_tx_buffer_type type; 483 union { 484 struct sk_buff *skb; 485 struct xdp_frame *xdpf; 486 }; 487 unsigned int bytecount; 488 u16 gso_segs; 489 __be16 protocol; 490 491 DEFINE_DMA_UNMAP_ADDR(dma); 492 DEFINE_DMA_UNMAP_LEN(len); 493 u32 tx_flags; 494 }; 495 496 struct igc_rx_buffer { 497 union { 498 struct { 499 dma_addr_t dma; 500 struct page *page; 501 #if (BITS_PER_LONG > 32) || (PAGE_SIZE >= 65536) 502 __u32 page_offset; 503 #else 504 __u16 page_offset; 505 #endif 506 __u16 pagecnt_bias; 507 }; 508 struct xdp_buff *xdp; 509 }; 510 }; 511 512 /* context wrapper around xdp_buff to provide access to descriptor metadata */ 513 struct igc_xdp_buff { 514 struct xdp_buff xdp; 515 union igc_adv_rx_desc *rx_desc; 516 ktime_t rx_ts; /* data indication bit IGC_RXDADV_STAT_TSIP */ 517 }; 518 519 struct igc_q_vector { 520 struct igc_adapter *adapter; /* backlink */ 521 void __iomem *itr_register; 522 u32 eims_value; /* EIMS mask value */ 523 524 u16 itr_val; 525 u8 set_itr; 526 527 struct igc_ring_container rx, tx; 528 529 struct napi_struct napi; 530 531 struct rcu_head rcu; /* to avoid race with update stats on free */ 532 char name[IFNAMSIZ + 9]; 533 struct net_device poll_dev; 534 535 /* for dynamic allocation of rings associated with this q_vector */ 536 struct igc_ring ring[] ____cacheline_internodealigned_in_smp; 537 }; 538 539 enum igc_filter_match_flags { 540 IGC_FILTER_FLAG_ETHER_TYPE = BIT(0), 541 IGC_FILTER_FLAG_VLAN_TCI = BIT(1), 542 IGC_FILTER_FLAG_SRC_MAC_ADDR = BIT(2), 543 IGC_FILTER_FLAG_DST_MAC_ADDR = BIT(3), 544 IGC_FILTER_FLAG_USER_DATA = BIT(4), 545 IGC_FILTER_FLAG_VLAN_ETYPE = BIT(5), 546 }; 547 548 struct igc_nfc_filter { 549 u8 match_flags; 550 u16 etype; 551 __be16 vlan_etype; 552 u16 vlan_tci; 553 u8 src_addr[ETH_ALEN]; 554 u8 dst_addr[ETH_ALEN]; 555 u8 user_data[8]; 556 u8 user_mask[8]; 557 u8 flex_index; 558 u8 rx_queue; 559 u8 prio; 560 u8 immediate_irq; 561 u8 drop; 562 }; 563 564 struct igc_nfc_rule { 565 struct list_head list; 566 struct igc_nfc_filter filter; 567 u32 location; 568 u16 action; 569 bool flex; 570 }; 571 572 /* IGC supports a total of 32 NFC rules: 16 MAC address based, 8 VLAN priority 573 * based, 8 ethertype based and 32 Flex filter based rules. 574 */ 575 #define IGC_MAX_RXNFC_RULES 64 576 577 struct igc_flex_filter { 578 u8 index; 579 u8 data[128]; 580 u8 mask[16]; 581 u8 length; 582 u8 rx_queue; 583 u8 prio; 584 u8 immediate_irq; 585 u8 drop; 586 }; 587 588 /* igc_desc_unused - calculate if we have unused descriptors */ 589 static inline u16 igc_desc_unused(const struct igc_ring *ring) 590 { 591 u16 ntc = ring->next_to_clean; 592 u16 ntu = ring->next_to_use; 593 594 return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1; 595 } 596 597 static inline s32 igc_get_phy_info(struct igc_hw *hw) 598 { 599 if (hw->phy.ops.get_phy_info) 600 return hw->phy.ops.get_phy_info(hw); 601 602 return 0; 603 } 604 605 static inline s32 igc_reset_phy(struct igc_hw *hw) 606 { 607 if (hw->phy.ops.reset) 608 return hw->phy.ops.reset(hw); 609 610 return 0; 611 } 612 613 static inline struct netdev_queue *txring_txq(const struct igc_ring *tx_ring) 614 { 615 return netdev_get_tx_queue(tx_ring->netdev, tx_ring->queue_index); 616 } 617 618 enum igc_ring_flags_t { 619 IGC_RING_FLAG_RX_3K_BUFFER, 620 IGC_RING_FLAG_RX_BUILD_SKB_ENABLED, 621 IGC_RING_FLAG_RX_SCTP_CSUM, 622 IGC_RING_FLAG_RX_LB_VLAN_BSWAP, 623 IGC_RING_FLAG_TX_CTX_IDX, 624 IGC_RING_FLAG_TX_DETECT_HANG, 625 IGC_RING_FLAG_AF_XDP_ZC, 626 IGC_RING_FLAG_TX_HWTSTAMP, 627 }; 628 629 #define ring_uses_large_buffer(ring) \ 630 test_bit(IGC_RING_FLAG_RX_3K_BUFFER, &(ring)->flags) 631 #define set_ring_uses_large_buffer(ring) \ 632 set_bit(IGC_RING_FLAG_RX_3K_BUFFER, &(ring)->flags) 633 #define clear_ring_uses_large_buffer(ring) \ 634 clear_bit(IGC_RING_FLAG_RX_3K_BUFFER, &(ring)->flags) 635 636 #define ring_uses_build_skb(ring) \ 637 test_bit(IGC_RING_FLAG_RX_BUILD_SKB_ENABLED, &(ring)->flags) 638 639 static inline unsigned int igc_rx_bufsz(struct igc_ring *ring) 640 { 641 #if (PAGE_SIZE < 8192) 642 if (ring_uses_large_buffer(ring)) 643 return IGC_RXBUFFER_3072; 644 645 if (ring_uses_build_skb(ring)) 646 return IGC_MAX_FRAME_BUILD_SKB + IGC_TS_HDR_LEN; 647 #endif 648 return IGC_RXBUFFER_2048; 649 } 650 651 static inline unsigned int igc_rx_pg_order(struct igc_ring *ring) 652 { 653 #if (PAGE_SIZE < 8192) 654 if (ring_uses_large_buffer(ring)) 655 return 1; 656 #endif 657 return 0; 658 } 659 660 static inline s32 igc_read_phy_reg(struct igc_hw *hw, u32 offset, u16 *data) 661 { 662 if (hw->phy.ops.read_reg) 663 return hw->phy.ops.read_reg(hw, offset, data); 664 665 return -EOPNOTSUPP; 666 } 667 668 void igc_reinit_locked(struct igc_adapter *); 669 struct igc_nfc_rule *igc_get_nfc_rule(struct igc_adapter *adapter, 670 u32 location); 671 int igc_add_nfc_rule(struct igc_adapter *adapter, struct igc_nfc_rule *rule); 672 void igc_del_nfc_rule(struct igc_adapter *adapter, struct igc_nfc_rule *rule); 673 674 void igc_ptp_init(struct igc_adapter *adapter); 675 void igc_ptp_reset(struct igc_adapter *adapter); 676 void igc_ptp_suspend(struct igc_adapter *adapter); 677 void igc_ptp_stop(struct igc_adapter *adapter); 678 ktime_t igc_ptp_rx_pktstamp(struct igc_adapter *adapter, __le32 *buf); 679 int igc_ptp_set_ts_config(struct net_device *netdev, struct ifreq *ifr); 680 int igc_ptp_get_ts_config(struct net_device *netdev, struct ifreq *ifr); 681 void igc_ptp_tx_hang(struct igc_adapter *adapter); 682 void igc_ptp_read(struct igc_adapter *adapter, struct timespec64 *ts); 683 void igc_ptp_tx_tstamp_event(struct igc_adapter *adapter); 684 685 #define igc_rx_pg_size(_ring) (PAGE_SIZE << igc_rx_pg_order(_ring)) 686 687 #define IGC_TXD_DCMD (IGC_ADVTXD_DCMD_EOP | IGC_ADVTXD_DCMD_RS) 688 689 #define IGC_RX_DESC(R, i) \ 690 (&(((union igc_adv_rx_desc *)((R)->desc))[i])) 691 #define IGC_TX_DESC(R, i) \ 692 (&(((union igc_adv_tx_desc *)((R)->desc))[i])) 693 #define IGC_TX_CTXTDESC(R, i) \ 694 (&(((struct igc_adv_tx_context_desc *)((R)->desc))[i])) 695 696 #endif /* _IGC_H_ */ 697