1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (C) 2018-2021, Intel Corporation. */ 3 4 #ifndef _ICE_PTP_CONSTS_H_ 5 #define _ICE_PTP_CONSTS_H_ 6 7 /* Constant definitions related to the hardware clock used for PTP 1588 8 * features and functionality. 9 */ 10 /* Constants defined for the PTP 1588 clock hardware. */ 11 12 /* struct ice_time_ref_info_e822 13 * 14 * E822 hardware can use different sources as the reference for the PTP 15 * hardware clock. Each clock has different characteristics such as a slightly 16 * different frequency, etc. 17 * 18 * This lookup table defines several constants that depend on the current time 19 * reference. See the struct ice_time_ref_info_e822 for information about the 20 * meaning of each constant. 21 */ 22 const struct ice_time_ref_info_e822 e822_time_ref[NUM_ICE_TIME_REF_FREQ] = { 23 /* ICE_TIME_REF_FREQ_25_000 -> 25 MHz */ 24 { 25 /* pll_freq */ 26 823437500, /* 823.4375 MHz PLL */ 27 /* nominal_incval */ 28 0x136e44fabULL, 29 /* pps_delay */ 30 11, 31 }, 32 33 /* ICE_TIME_REF_FREQ_122_880 -> 122.88 MHz */ 34 { 35 /* pll_freq */ 36 783360000, /* 783.36 MHz */ 37 /* nominal_incval */ 38 0x146cc2177ULL, 39 /* pps_delay */ 40 12, 41 }, 42 43 /* ICE_TIME_REF_FREQ_125_000 -> 125 MHz */ 44 { 45 /* pll_freq */ 46 796875000, /* 796.875 MHz */ 47 /* nominal_incval */ 48 0x141414141ULL, 49 /* pps_delay */ 50 12, 51 }, 52 53 /* ICE_TIME_REF_FREQ_153_600 -> 153.6 MHz */ 54 { 55 /* pll_freq */ 56 816000000, /* 816 MHz */ 57 /* nominal_incval */ 58 0x139b9b9baULL, 59 /* pps_delay */ 60 12, 61 }, 62 63 /* ICE_TIME_REF_FREQ_156_250 -> 156.25 MHz */ 64 { 65 /* pll_freq */ 66 830078125, /* 830.78125 MHz */ 67 /* nominal_incval */ 68 0x134679aceULL, 69 /* pps_delay */ 70 11, 71 }, 72 73 /* ICE_TIME_REF_FREQ_245_760 -> 245.76 MHz */ 74 { 75 /* pll_freq */ 76 783360000, /* 783.36 MHz */ 77 /* nominal_incval */ 78 0x146cc2177ULL, 79 /* pps_delay */ 80 12, 81 }, 82 }; 83 84 /* struct ice_vernier_info_e822 85 * 86 * E822 hardware calibrates the delay of the timestamp indication from the 87 * actual packet transmission or reception during the initialization of the 88 * PHY. To do this, the hardware mechanism uses some conversions between the 89 * various clocks within the PHY block. This table defines constants used to 90 * calculate the correct conversion ratios in the PHY registers. 91 * 92 * Many of the values relate to the PAR/PCS clock conversion registers. For 93 * these registers, a value of 0 means that the associated register is not 94 * used by this link speed, and that the register should be cleared by writing 95 * 0. Other values specify the clock frequency in Hz. 96 */ 97 const struct ice_vernier_info_e822 e822_vernier[NUM_ICE_PTP_LNK_SPD] = { 98 /* ICE_PTP_LNK_SPD_1G */ 99 { 100 /* tx_par_clk */ 101 31250000, /* 31.25 MHz */ 102 /* rx_par_clk */ 103 31250000, /* 31.25 MHz */ 104 /* tx_pcs_clk */ 105 125000000, /* 125 MHz */ 106 /* rx_pcs_clk */ 107 125000000, /* 125 MHz */ 108 /* tx_desk_rsgb_par */ 109 0, /* unused */ 110 /* rx_desk_rsgb_par */ 111 0, /* unused */ 112 /* tx_desk_rsgb_pcs */ 113 0, /* unused */ 114 /* rx_desk_rsgb_pcs */ 115 0, /* unused */ 116 /* tx_fixed_delay */ 117 25140, 118 /* pmd_adj_divisor */ 119 10000000, 120 /* rx_fixed_delay */ 121 17372, 122 }, 123 /* ICE_PTP_LNK_SPD_10G */ 124 { 125 /* tx_par_clk */ 126 257812500, /* 257.8125 MHz */ 127 /* rx_par_clk */ 128 257812500, /* 257.8125 MHz */ 129 /* tx_pcs_clk */ 130 156250000, /* 156.25 MHz */ 131 /* rx_pcs_clk */ 132 156250000, /* 156.25 MHz */ 133 /* tx_desk_rsgb_par */ 134 0, /* unused */ 135 /* rx_desk_rsgb_par */ 136 0, /* unused */ 137 /* tx_desk_rsgb_pcs */ 138 0, /* unused */ 139 /* rx_desk_rsgb_pcs */ 140 0, /* unused */ 141 /* tx_fixed_delay */ 142 6938, 143 /* pmd_adj_divisor */ 144 82500000, 145 /* rx_fixed_delay */ 146 6212, 147 }, 148 /* ICE_PTP_LNK_SPD_25G */ 149 { 150 /* tx_par_clk */ 151 644531250, /* 644.53125 MHZ */ 152 /* rx_par_clk */ 153 644531250, /* 644.53125 MHz */ 154 /* tx_pcs_clk */ 155 390625000, /* 390.625 MHz */ 156 /* rx_pcs_clk */ 157 390625000, /* 390.625 MHz */ 158 /* tx_desk_rsgb_par */ 159 0, /* unused */ 160 /* rx_desk_rsgb_par */ 161 0, /* unused */ 162 /* tx_desk_rsgb_pcs */ 163 0, /* unused */ 164 /* rx_desk_rsgb_pcs */ 165 0, /* unused */ 166 /* tx_fixed_delay */ 167 2778, 168 /* pmd_adj_divisor */ 169 206250000, 170 /* rx_fixed_delay */ 171 2491, 172 }, 173 /* ICE_PTP_LNK_SPD_25G_RS */ 174 { 175 /* tx_par_clk */ 176 0, /* unused */ 177 /* rx_par_clk */ 178 0, /* unused */ 179 /* tx_pcs_clk */ 180 0, /* unused */ 181 /* rx_pcs_clk */ 182 0, /* unused */ 183 /* tx_desk_rsgb_par */ 184 161132812, /* 162.1328125 MHz Reed Solomon gearbox */ 185 /* rx_desk_rsgb_par */ 186 161132812, /* 162.1328125 MHz Reed Solomon gearbox */ 187 /* tx_desk_rsgb_pcs */ 188 97656250, /* 97.62625 MHz Reed Solomon gearbox */ 189 /* rx_desk_rsgb_pcs */ 190 97656250, /* 97.62625 MHz Reed Solomon gearbox */ 191 /* tx_fixed_delay */ 192 3928, 193 /* pmd_adj_divisor */ 194 206250000, 195 /* rx_fixed_delay */ 196 29535, 197 }, 198 /* ICE_PTP_LNK_SPD_40G */ 199 { 200 /* tx_par_clk */ 201 257812500, 202 /* rx_par_clk */ 203 257812500, 204 /* tx_pcs_clk */ 205 156250000, /* 156.25 MHz */ 206 /* rx_pcs_clk */ 207 156250000, /* 156.25 MHz */ 208 /* tx_desk_rsgb_par */ 209 0, /* unused */ 210 /* rx_desk_rsgb_par */ 211 156250000, /* 156.25 MHz deskew clock */ 212 /* tx_desk_rsgb_pcs */ 213 0, /* unused */ 214 /* rx_desk_rsgb_pcs */ 215 156250000, /* 156.25 MHz deskew clock */ 216 /* tx_fixed_delay */ 217 5666, 218 /* pmd_adj_divisor */ 219 82500000, 220 /* rx_fixed_delay */ 221 4244, 222 }, 223 /* ICE_PTP_LNK_SPD_50G */ 224 { 225 /* tx_par_clk */ 226 644531250, /* 644.53125 MHZ */ 227 /* rx_par_clk */ 228 644531250, /* 644.53125 MHZ */ 229 /* tx_pcs_clk */ 230 390625000, /* 390.625 MHz */ 231 /* rx_pcs_clk */ 232 390625000, /* 390.625 MHz */ 233 /* tx_desk_rsgb_par */ 234 0, /* unused */ 235 /* rx_desk_rsgb_par */ 236 195312500, /* 193.3125 MHz deskew clock */ 237 /* tx_desk_rsgb_pcs */ 238 0, /* unused */ 239 /* rx_desk_rsgb_pcs */ 240 195312500, /* 193.3125 MHz deskew clock */ 241 /* tx_fixed_delay */ 242 2778, 243 /* pmd_adj_divisor */ 244 206250000, 245 /* rx_fixed_delay */ 246 2868, 247 }, 248 /* ICE_PTP_LNK_SPD_50G_RS */ 249 { 250 /* tx_par_clk */ 251 0, /* unused */ 252 /* rx_par_clk */ 253 644531250, /* 644.53125 MHz */ 254 /* tx_pcs_clk */ 255 0, /* unused */ 256 /* rx_pcs_clk */ 257 644531250, /* 644.53125 MHz */ 258 /* tx_desk_rsgb_par */ 259 322265625, /* 322.265625 MHz Reed Solomon gearbox */ 260 /* rx_desk_rsgb_par */ 261 322265625, /* 322.265625 MHz Reed Solomon gearbox */ 262 /* tx_desk_rsgb_pcs */ 263 644531250, /* 644.53125 MHz Reed Solomon gearbox */ 264 /* rx_desk_rsgb_pcs */ 265 644531250, /* 644.53125 MHz Reed Solomon gearbox */ 266 /* tx_fixed_delay */ 267 2095, 268 /* pmd_adj_divisor */ 269 206250000, 270 /* rx_fixed_delay */ 271 14524, 272 }, 273 /* ICE_PTP_LNK_SPD_100G_RS */ 274 { 275 /* tx_par_clk */ 276 0, /* unused */ 277 /* rx_par_clk */ 278 644531250, /* 644.53125 MHz */ 279 /* tx_pcs_clk */ 280 0, /* unused */ 281 /* rx_pcs_clk */ 282 644531250, /* 644.53125 MHz */ 283 /* tx_desk_rsgb_par */ 284 644531250, /* 644.53125 MHz Reed Solomon gearbox */ 285 /* rx_desk_rsgb_par */ 286 644531250, /* 644.53125 MHz Reed Solomon gearbox */ 287 /* tx_desk_rsgb_pcs */ 288 644531250, /* 644.53125 MHz Reed Solomon gearbox */ 289 /* rx_desk_rsgb_pcs */ 290 644531250, /* 644.53125 MHz Reed Solomon gearbox */ 291 /* tx_fixed_delay */ 292 1620, 293 /* pmd_adj_divisor */ 294 206250000, 295 /* rx_fixed_delay */ 296 7775, 297 }, 298 }; 299 300 #endif /* _ICE_PTP_CONSTS_H_ */ 301